1 //===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RAGreedy function pass for register allocation in
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "llvm/CodeGen/Passes.h"
17 #include "AllocationOrder.h"
18 #include "InterferenceCache.h"
19 #include "LiveDebugVariables.h"
20 #include "RegAllocBase.h"
21 #include "SpillPlacement.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/CodeGen/CalcSpillWeights.h"
27 #include "llvm/CodeGen/EdgeBundles.h"
28 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
29 #include "llvm/CodeGen/LiveRangeEdit.h"
30 #include "llvm/CodeGen/LiveRegMatrix.h"
31 #include "llvm/CodeGen/LiveStackAnalysis.h"
32 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
33 #include "llvm/CodeGen/MachineDominators.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineLoopInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/RegAllocRegistry.h"
38 #include "llvm/CodeGen/RegisterClassInfo.h"
39 #include "llvm/CodeGen/VirtRegMap.h"
40 #include "llvm/PassAnalysisSupport.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/Timer.h"
45 #include "llvm/Support/raw_ostream.h"
50 STATISTIC(NumGlobalSplits, "Number of split global live ranges");
51 STATISTIC(NumLocalSplits, "Number of split local live ranges");
52 STATISTIC(NumEvicted, "Number of interferences evicted");
54 static cl::opt<SplitEditor::ComplementSpillMode>
55 SplitSpillMode("split-spill-mode", cl::Hidden,
56 cl::desc("Spill mode for splitting live ranges"),
57 cl::values(clEnumValN(SplitEditor::SM_Partition, "default", "Default"),
58 clEnumValN(SplitEditor::SM_Size, "size", "Optimize for size"),
59 clEnumValN(SplitEditor::SM_Speed, "speed", "Optimize for speed"),
61 cl::init(SplitEditor::SM_Partition));
63 static cl::opt<unsigned>
64 LastChanceRecoloringMaxDepth("lcr-max-depth", cl::Hidden,
65 cl::desc("Last chance recoloring max depth"),
68 static cl::opt<unsigned> LastChanceRecoloringMaxInterference(
69 "lcr-max-interf", cl::Hidden,
70 cl::desc("Last chance recoloring maximum number of considered"
71 " interference at a time"),
74 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
75 createGreedyRegisterAllocator);
78 class RAGreedy : public MachineFunctionPass,
80 private LiveRangeEdit::Delegate {
81 // Convenient shortcuts.
82 typedef std::priority_queue<std::pair<unsigned, unsigned> > PQueue;
83 typedef SmallPtrSet<LiveInterval *, 4> SmallLISet;
84 typedef SmallSet<unsigned, 16> SmallVirtRegSet;
89 // Shortcuts to some useful interface.
90 const TargetInstrInfo *TII;
91 const TargetRegisterInfo *TRI;
92 RegisterClassInfo RCI;
96 MachineBlockFrequencyInfo *MBFI;
97 MachineDominatorTree *DomTree;
98 MachineLoopInfo *Loops;
100 SpillPlacement *SpillPlacer;
101 LiveDebugVariables *DebugVars;
104 OwningPtr<Spiller> SpillerInstance;
106 unsigned NextCascade;
108 // Live ranges pass through a number of stages as we try to allocate them.
109 // Some of the stages may also create new live ranges:
111 // - Region splitting.
112 // - Per-block splitting.
113 // - Local splitting.
116 // Ranges produced by one of the stages skip the previous stages when they are
117 // dequeued. This improves performance because we can skip interference checks
118 // that are unlikely to give any results. It also guarantees that the live
119 // range splitting algorithm terminates, something that is otherwise hard to
121 enum LiveRangeStage {
122 /// Newly created live range that has never been queued.
125 /// Only attempt assignment and eviction. Then requeue as RS_Split.
128 /// Attempt live range splitting if assignment is impossible.
131 /// Attempt more aggressive live range splitting that is guaranteed to make
132 /// progress. This is used for split products that may not be making
136 /// Live range will be spilled. No more splitting will be attempted.
139 /// There is nothing more we can do to this live range. Abort compilation
140 /// if it can't be assigned.
145 static const char *const StageName[];
148 // RegInfo - Keep additional information about each live range.
150 LiveRangeStage Stage;
152 // Cascade - Eviction loop prevention. See canEvictInterference().
155 RegInfo() : Stage(RS_New), Cascade(0) {}
158 IndexedMap<RegInfo, VirtReg2IndexFunctor> ExtraRegInfo;
160 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
161 return ExtraRegInfo[VirtReg.reg].Stage;
164 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) {
165 ExtraRegInfo.resize(MRI->getNumVirtRegs());
166 ExtraRegInfo[VirtReg.reg].Stage = Stage;
169 template<typename Iterator>
170 void setStage(Iterator Begin, Iterator End, LiveRangeStage NewStage) {
171 ExtraRegInfo.resize(MRI->getNumVirtRegs());
172 for (;Begin != End; ++Begin) {
173 unsigned Reg = *Begin;
174 if (ExtraRegInfo[Reg].Stage == RS_New)
175 ExtraRegInfo[Reg].Stage = NewStage;
179 /// Cost of evicting interference.
180 struct EvictionCost {
181 unsigned BrokenHints; ///< Total number of broken hints.
182 float MaxWeight; ///< Maximum spill weight evicted.
184 EvictionCost(): BrokenHints(0), MaxWeight(0) {}
186 bool isMax() const { return BrokenHints == ~0u; }
188 void setMax() { BrokenHints = ~0u; }
190 void setBrokenHints(unsigned NHints) { BrokenHints = NHints; }
192 bool operator<(const EvictionCost &O) const {
193 if (BrokenHints != O.BrokenHints)
194 return BrokenHints < O.BrokenHints;
195 return MaxWeight < O.MaxWeight;
200 OwningPtr<SplitAnalysis> SA;
201 OwningPtr<SplitEditor> SE;
203 /// Cached per-block interference maps
204 InterferenceCache IntfCache;
206 /// All basic blocks where the current register has uses.
207 SmallVector<SpillPlacement::BlockConstraint, 8> SplitConstraints;
209 /// Global live range splitting candidate info.
210 struct GlobalSplitCandidate {
211 // Register intended for assignment, or 0.
214 // SplitKit interval index for this candidate.
217 // Interference for PhysReg.
218 InterferenceCache::Cursor Intf;
220 // Bundles where this candidate should be live.
221 BitVector LiveBundles;
222 SmallVector<unsigned, 8> ActiveBlocks;
224 void reset(InterferenceCache &Cache, unsigned Reg) {
227 Intf.setPhysReg(Cache, Reg);
229 ActiveBlocks.clear();
232 // Set B[i] = C for every live bundle where B[i] was NoCand.
233 unsigned getBundles(SmallVectorImpl<unsigned> &B, unsigned C) {
235 for (int i = LiveBundles.find_first(); i >= 0;
236 i = LiveBundles.find_next(i))
237 if (B[i] == NoCand) {
245 /// Candidate info for each PhysReg in AllocationOrder.
246 /// This vector never shrinks, but grows to the size of the largest register
248 SmallVector<GlobalSplitCandidate, 32> GlobalCand;
250 enum LLVM_ENUM_INT_TYPE(unsigned) { NoCand = ~0u };
252 /// Candidate map. Each edge bundle is assigned to a GlobalCand entry, or to
253 /// NoCand which indicates the stack interval.
254 SmallVector<unsigned, 32> BundleCand;
259 /// Return the pass name.
260 virtual const char* getPassName() const {
261 return "Greedy Register Allocator";
264 /// RAGreedy analysis usage.
265 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
266 virtual void releaseMemory();
267 virtual Spiller &spiller() { return *SpillerInstance; }
268 virtual void enqueue(LiveInterval *LI);
269 virtual LiveInterval *dequeue();
270 virtual unsigned selectOrSplit(LiveInterval&,
271 SmallVectorImpl<unsigned>&);
273 /// Perform register allocation.
274 virtual bool runOnMachineFunction(MachineFunction &mf);
279 unsigned selectOrSplitImpl(LiveInterval &, SmallVectorImpl<unsigned> &,
280 SmallVirtRegSet &, unsigned = 0);
282 bool LRE_CanEraseVirtReg(unsigned);
283 void LRE_WillShrinkVirtReg(unsigned);
284 void LRE_DidCloneVirtReg(unsigned, unsigned);
285 void enqueue(PQueue &CurQueue, LiveInterval *LI);
286 LiveInterval *dequeue(PQueue &CurQueue);
288 BlockFrequency calcSpillCost();
289 bool addSplitConstraints(InterferenceCache::Cursor, BlockFrequency&);
290 void addThroughConstraints(InterferenceCache::Cursor, ArrayRef<unsigned>);
291 void growRegion(GlobalSplitCandidate &Cand);
292 BlockFrequency calcGlobalSplitCost(GlobalSplitCandidate&);
293 bool calcCompactRegion(GlobalSplitCandidate&);
294 void splitAroundRegion(LiveRangeEdit&, ArrayRef<unsigned>);
295 void calcGapWeights(unsigned, SmallVectorImpl<float>&);
296 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
297 bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool);
298 bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&);
299 void evictInterference(LiveInterval&, unsigned,
300 SmallVectorImpl<unsigned>&);
301 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
302 SmallLISet &RecoloringCandidates,
303 const SmallVirtRegSet &FixedRegisters);
305 unsigned tryAssign(LiveInterval&, AllocationOrder&,
306 SmallVectorImpl<unsigned>&);
307 unsigned tryEvict(LiveInterval&, AllocationOrder&,
308 SmallVectorImpl<unsigned>&, unsigned = ~0u);
309 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
310 SmallVectorImpl<unsigned>&);
311 unsigned tryBlockSplit(LiveInterval&, AllocationOrder&,
312 SmallVectorImpl<unsigned>&);
313 unsigned tryInstructionSplit(LiveInterval&, AllocationOrder&,
314 SmallVectorImpl<unsigned>&);
315 unsigned tryLocalSplit(LiveInterval&, AllocationOrder&,
316 SmallVectorImpl<unsigned>&);
317 unsigned trySplit(LiveInterval&, AllocationOrder&,
318 SmallVectorImpl<unsigned>&);
319 unsigned tryLastChanceRecoloring(LiveInterval &, AllocationOrder &,
320 SmallVectorImpl<unsigned> &,
321 SmallVirtRegSet &, unsigned);
322 bool tryRecoloringCandidates(PQueue &, SmallVectorImpl<unsigned> &,
323 SmallVirtRegSet &, unsigned);
325 } // end anonymous namespace
327 char RAGreedy::ID = 0;
330 const char *const RAGreedy::StageName[] = {
340 // Hysteresis to use when comparing floats.
341 // This helps stabilize decisions based on float comparisons.
342 const float Hysteresis = (2007 / 2048.0f); // 0.97998046875
345 FunctionPass* llvm::createGreedyRegisterAllocator() {
346 return new RAGreedy();
349 RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
350 initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
351 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
352 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
353 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
354 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
355 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
356 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
357 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
358 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
359 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
360 initializeLiveRegMatrixPass(*PassRegistry::getPassRegistry());
361 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
362 initializeSpillPlacementPass(*PassRegistry::getPassRegistry());
365 void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
366 AU.setPreservesCFG();
367 AU.addRequired<MachineBlockFrequencyInfo>();
368 AU.addPreserved<MachineBlockFrequencyInfo>();
369 AU.addRequired<AliasAnalysis>();
370 AU.addPreserved<AliasAnalysis>();
371 AU.addRequired<LiveIntervals>();
372 AU.addPreserved<LiveIntervals>();
373 AU.addRequired<SlotIndexes>();
374 AU.addPreserved<SlotIndexes>();
375 AU.addRequired<LiveDebugVariables>();
376 AU.addPreserved<LiveDebugVariables>();
377 AU.addRequired<LiveStacks>();
378 AU.addPreserved<LiveStacks>();
379 AU.addRequired<MachineDominatorTree>();
380 AU.addPreserved<MachineDominatorTree>();
381 AU.addRequired<MachineLoopInfo>();
382 AU.addPreserved<MachineLoopInfo>();
383 AU.addRequired<VirtRegMap>();
384 AU.addPreserved<VirtRegMap>();
385 AU.addRequired<LiveRegMatrix>();
386 AU.addPreserved<LiveRegMatrix>();
387 AU.addRequired<EdgeBundles>();
388 AU.addRequired<SpillPlacement>();
389 MachineFunctionPass::getAnalysisUsage(AU);
393 //===----------------------------------------------------------------------===//
394 // LiveRangeEdit delegate methods
395 //===----------------------------------------------------------------------===//
397 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
398 if (VRM->hasPhys(VirtReg)) {
399 Matrix->unassign(LIS->getInterval(VirtReg));
402 // Unassigned virtreg is probably in the priority queue.
403 // RegAllocBase will erase it after dequeueing.
407 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) {
408 if (!VRM->hasPhys(VirtReg))
411 // Register is assigned, put it back on the queue for reassignment.
412 LiveInterval &LI = LIS->getInterval(VirtReg);
413 Matrix->unassign(LI);
417 void RAGreedy::LRE_DidCloneVirtReg(unsigned New, unsigned Old) {
418 // Cloning a register we haven't even heard about yet? Just ignore it.
419 if (!ExtraRegInfo.inBounds(Old))
422 // LRE may clone a virtual register because dead code elimination causes it to
423 // be split into connected components. The new components are much smaller
424 // than the original, so they should get a new chance at being assigned.
425 // same stage as the parent.
426 ExtraRegInfo[Old].Stage = RS_Assign;
427 ExtraRegInfo.grow(New);
428 ExtraRegInfo[New] = ExtraRegInfo[Old];
431 void RAGreedy::releaseMemory() {
432 SpillerInstance.reset(0);
433 ExtraRegInfo.clear();
437 void RAGreedy::enqueue(LiveInterval *LI) { enqueue(Queue, LI); }
439 void RAGreedy::enqueue(PQueue &CurQueue, LiveInterval *LI) {
440 // Prioritize live ranges by size, assigning larger ranges first.
441 // The queue holds (size, reg) pairs.
442 const unsigned Size = LI->getSize();
443 const unsigned Reg = LI->reg;
444 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
445 "Can only enqueue virtual registers");
448 ExtraRegInfo.grow(Reg);
449 if (ExtraRegInfo[Reg].Stage == RS_New)
450 ExtraRegInfo[Reg].Stage = RS_Assign;
452 if (ExtraRegInfo[Reg].Stage == RS_Split) {
453 // Unsplit ranges that couldn't be allocated immediately are deferred until
454 // everything else has been allocated.
457 // Giant live ranges fall back to the global assignment heuristic, which
458 // prevents excessive spilling in pathological cases.
459 bool ReverseLocal = TRI->reverseLocalAssignment();
460 bool ForceGlobal = !ReverseLocal && TRI->mayOverrideLocalAssignment() &&
461 (Size / SlotIndex::InstrDist) > (2 * MRI->getRegClass(Reg)->getNumRegs());
463 if (ExtraRegInfo[Reg].Stage == RS_Assign && !ForceGlobal && !LI->empty() &&
464 LIS->intervalIsInOneMBB(*LI)) {
465 // Allocate original local ranges in linear instruction order. Since they
466 // are singly defined, this produces optimal coloring in the absence of
467 // global interference and other constraints.
469 Prio = LI->beginIndex().getInstrDistance(Indexes->getLastIndex());
471 // Allocating bottom up may allow many short LRGs to be assigned first
472 // to one of the cheap registers. This could be much faster for very
473 // large blocks on targets with many physical registers.
474 Prio = Indexes->getZeroIndex().getInstrDistance(LI->beginIndex());
478 // Allocate global and split ranges in long->short order. Long ranges that
479 // don't fit should be spilled (or split) ASAP so they don't create
480 // interference. Mark a bit to prioritize global above local ranges.
481 Prio = (1u << 29) + Size;
483 // Mark a higher bit to prioritize global and local above RS_Split.
486 // Boost ranges that have a physical register hint.
487 if (VRM->hasKnownPreference(Reg))
490 // The virtual register number is a tie breaker for same-sized ranges.
491 // Give lower vreg numbers higher priority to assign them first.
492 CurQueue.push(std::make_pair(Prio, ~Reg));
495 LiveInterval *RAGreedy::dequeue() { return dequeue(Queue); }
497 LiveInterval *RAGreedy::dequeue(PQueue &CurQueue) {
498 if (CurQueue.empty())
500 LiveInterval *LI = &LIS->getInterval(~CurQueue.top().second);
506 //===----------------------------------------------------------------------===//
508 //===----------------------------------------------------------------------===//
510 /// tryAssign - Try to assign VirtReg to an available register.
511 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg,
512 AllocationOrder &Order,
513 SmallVectorImpl<unsigned> &NewVRegs) {
516 while ((PhysReg = Order.next()))
517 if (!Matrix->checkInterference(VirtReg, PhysReg))
519 if (!PhysReg || Order.isHint())
522 // PhysReg is available, but there may be a better choice.
524 // If we missed a simple hint, try to cheaply evict interference from the
525 // preferred register.
526 if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg))
527 if (Order.isHint(Hint)) {
528 DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n');
529 EvictionCost MaxCost;
530 MaxCost.setBrokenHints(1);
531 if (canEvictInterference(VirtReg, Hint, true, MaxCost)) {
532 evictInterference(VirtReg, Hint, NewVRegs);
537 // Try to evict interference from a cheaper alternative.
538 unsigned Cost = TRI->getCostPerUse(PhysReg);
540 // Most registers have 0 additional cost.
544 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost
546 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
547 return CheapReg ? CheapReg : PhysReg;
551 //===----------------------------------------------------------------------===//
552 // Interference eviction
553 //===----------------------------------------------------------------------===//
555 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) {
556 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
558 while ((PhysReg = Order.next())) {
559 if (PhysReg == PrevReg)
562 MCRegUnitIterator Units(PhysReg, TRI);
563 for (; Units.isValid(); ++Units) {
564 // Instantiate a "subquery", not to be confused with the Queries array.
565 LiveIntervalUnion::Query subQ(&VirtReg, &Matrix->getLiveUnions()[*Units]);
566 if (subQ.checkInterference())
569 // If no units have interference, break out with the current PhysReg.
570 if (!Units.isValid())
574 DEBUG(dbgs() << "can reassign: " << VirtReg << " from "
575 << PrintReg(PrevReg, TRI) << " to " << PrintReg(PhysReg, TRI)
580 /// shouldEvict - determine if A should evict the assigned live range B. The
581 /// eviction policy defined by this function together with the allocation order
582 /// defined by enqueue() decides which registers ultimately end up being split
585 /// Cascade numbers are used to prevent infinite loops if this function is a
588 /// @param A The live range to be assigned.
589 /// @param IsHint True when A is about to be assigned to its preferred
591 /// @param B The live range to be evicted.
592 /// @param BreaksHint True when B is already assigned to its preferred register.
593 bool RAGreedy::shouldEvict(LiveInterval &A, bool IsHint,
594 LiveInterval &B, bool BreaksHint) {
595 bool CanSplit = getStage(B) < RS_Spill;
597 // Be fairly aggressive about following hints as long as the evictee can be
599 if (CanSplit && IsHint && !BreaksHint)
602 if (A.weight > B.weight) {
603 DEBUG(dbgs() << "should evict: " << B << " w= " << B.weight << '\n');
609 /// canEvictInterference - Return true if all interferences between VirtReg and
610 /// PhysReg can be evicted.
612 /// @param VirtReg Live range that is about to be assigned.
613 /// @param PhysReg Desired register for assignment.
614 /// @param IsHint True when PhysReg is VirtReg's preferred register.
615 /// @param MaxCost Only look for cheaper candidates and update with new cost
616 /// when returning true.
617 /// @returns True when interference can be evicted cheaper than MaxCost.
618 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
619 bool IsHint, EvictionCost &MaxCost) {
620 // It is only possible to evict virtual register interference.
621 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg)
624 bool IsLocal = LIS->intervalIsInOneMBB(VirtReg);
626 // Find VirtReg's cascade number. This will be unassigned if VirtReg was never
627 // involved in an eviction before. If a cascade number was assigned, deny
628 // evicting anything with the same or a newer cascade number. This prevents
629 // infinite eviction loops.
631 // This works out so a register without a cascade number is allowed to evict
632 // anything, and it can be evicted by anything.
633 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
635 Cascade = NextCascade;
638 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
639 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
640 // If there is 10 or more interferences, chances are one is heavier.
641 if (Q.collectInterferingVRegs(10) >= 10)
644 // Check if any interfering live range is heavier than MaxWeight.
645 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
646 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
647 assert(TargetRegisterInfo::isVirtualRegister(Intf->reg) &&
648 "Only expecting virtual register interference from query");
649 // Never evict spill products. They cannot split or spill.
650 if (getStage(*Intf) == RS_Done)
652 // Once a live range becomes small enough, it is urgent that we find a
653 // register for it. This is indicated by an infinite spill weight. These
654 // urgent live ranges get to evict almost anything.
656 // Also allow urgent evictions of unspillable ranges from a strictly
657 // larger allocation order.
658 bool Urgent = !VirtReg.isSpillable() &&
659 (Intf->isSpillable() ||
660 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) <
661 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg)));
662 // Only evict older cascades or live ranges without a cascade.
663 unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;
664 if (Cascade <= IntfCascade) {
667 // We permit breaking cascades for urgent evictions. It should be the
668 // last resort, though, so make it really expensive.
669 Cost.BrokenHints += 10;
671 // Would this break a satisfied hint?
672 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg);
673 // Update eviction cost.
674 Cost.BrokenHints += BreaksHint;
675 Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight);
676 // Abort if this would be too expensive.
677 if (!(Cost < MaxCost))
681 // Apply the eviction policy for non-urgent evictions.
682 if (!shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
684 // If !MaxCost.isMax(), then we're just looking for a cheap register.
685 // Evicting another local live range in this case could lead to suboptimal
687 if (!MaxCost.isMax() && IsLocal && LIS->intervalIsInOneMBB(*Intf) &&
688 !canReassign(*Intf, PhysReg)) {
697 /// evictInterference - Evict any interferring registers that prevent VirtReg
698 /// from being assigned to Physreg. This assumes that canEvictInterference
700 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg,
701 SmallVectorImpl<unsigned> &NewVRegs) {
702 // Make sure that VirtReg has a cascade number, and assign that cascade
703 // number to every evicted register. These live ranges than then only be
704 // evicted by a newer cascade, preventing infinite loops.
705 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
707 Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;
709 DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI)
710 << " interference: Cascade " << Cascade << '\n');
712 // Collect all interfering virtregs first.
713 SmallVector<LiveInterval*, 8> Intfs;
714 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
715 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
716 assert(Q.seenAllInterferences() && "Didn't check all interfererences.");
717 ArrayRef<LiveInterval*> IVR = Q.interferingVRegs();
718 Intfs.append(IVR.begin(), IVR.end());
721 // Evict them second. This will invalidate the queries.
722 for (unsigned i = 0, e = Intfs.size(); i != e; ++i) {
723 LiveInterval *Intf = Intfs[i];
724 // The same VirtReg may be present in multiple RegUnits. Skip duplicates.
725 if (!VRM->hasPhys(Intf->reg))
727 Matrix->unassign(*Intf);
728 assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||
729 VirtReg.isSpillable() < Intf->isSpillable()) &&
730 "Cannot decrease cascade number, illegal eviction");
731 ExtraRegInfo[Intf->reg].Cascade = Cascade;
733 NewVRegs.push_back(Intf->reg);
737 /// tryEvict - Try to evict all interferences for a physreg.
738 /// @param VirtReg Currently unassigned virtual register.
739 /// @param Order Physregs to try.
740 /// @return Physreg to assign VirtReg, or 0.
741 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
742 AllocationOrder &Order,
743 SmallVectorImpl<unsigned> &NewVRegs,
744 unsigned CostPerUseLimit) {
745 NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled);
747 // Keep track of the cheapest interference seen so far.
748 EvictionCost BestCost;
750 unsigned BestPhys = 0;
751 unsigned OrderLimit = Order.getOrder().size();
753 // When we are just looking for a reduced cost per use, don't break any
754 // hints, and only evict smaller spill weights.
755 if (CostPerUseLimit < ~0u) {
756 BestCost.BrokenHints = 0;
757 BestCost.MaxWeight = VirtReg.weight;
759 // Check of any registers in RC are below CostPerUseLimit.
760 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg);
761 unsigned MinCost = RegClassInfo.getMinCost(RC);
762 if (MinCost >= CostPerUseLimit) {
763 DEBUG(dbgs() << RC->getName() << " minimum cost = " << MinCost
764 << ", no cheaper registers to be found.\n");
768 // It is normal for register classes to have a long tail of registers with
769 // the same cost. We don't need to look at them if they're too expensive.
770 if (TRI->getCostPerUse(Order.getOrder().back()) >= CostPerUseLimit) {
771 OrderLimit = RegClassInfo.getLastCostChange(RC);
772 DEBUG(dbgs() << "Only trying the first " << OrderLimit << " regs.\n");
777 while (unsigned PhysReg = Order.next(OrderLimit)) {
778 if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit)
780 // The first use of a callee-saved register in a function has cost 1.
781 // Don't start using a CSR when the CostPerUseLimit is low.
782 if (CostPerUseLimit == 1)
783 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
784 if (!MRI->isPhysRegUsed(CSR)) {
785 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR "
786 << PrintReg(CSR, TRI) << '\n');
790 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost))
796 // Stop if the hint can be used.
804 evictInterference(VirtReg, BestPhys, NewVRegs);
809 //===----------------------------------------------------------------------===//
811 //===----------------------------------------------------------------------===//
813 /// addSplitConstraints - Fill out the SplitConstraints vector based on the
814 /// interference pattern in Physreg and its aliases. Add the constraints to
815 /// SpillPlacement and return the static cost of this split in Cost, assuming
816 /// that all preferences in SplitConstraints are met.
817 /// Return false if there are no bundles with positive bias.
818 bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
819 BlockFrequency &Cost) {
820 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
822 // Reset interference dependent info.
823 SplitConstraints.resize(UseBlocks.size());
824 BlockFrequency StaticCost = 0;
825 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
826 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
827 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
829 BC.Number = BI.MBB->getNumber();
830 Intf.moveToBlock(BC.Number);
831 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
832 BC.Exit = BI.LiveOut ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
833 BC.ChangesValue = BI.FirstDef.isValid();
835 if (!Intf.hasInterference())
838 // Number of spill code instructions to insert.
841 // Interference for the live-in value.
843 if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number))
844 BC.Entry = SpillPlacement::MustSpill, ++Ins;
845 else if (Intf.first() < BI.FirstInstr)
846 BC.Entry = SpillPlacement::PrefSpill, ++Ins;
847 else if (Intf.first() < BI.LastInstr)
851 // Interference for the live-out value.
853 if (Intf.last() >= SA->getLastSplitPoint(BC.Number))
854 BC.Exit = SpillPlacement::MustSpill, ++Ins;
855 else if (Intf.last() > BI.LastInstr)
856 BC.Exit = SpillPlacement::PrefSpill, ++Ins;
857 else if (Intf.last() > BI.FirstInstr)
861 // Accumulate the total frequency of inserted spill code.
863 StaticCost += SpillPlacer->getBlockFrequency(BC.Number);
867 // Add constraints for use-blocks. Note that these are the only constraints
868 // that may add a positive bias, it is downhill from here.
869 SpillPlacer->addConstraints(SplitConstraints);
870 return SpillPlacer->scanActiveBundles();
874 /// addThroughConstraints - Add constraints and links to SpillPlacer from the
875 /// live-through blocks in Blocks.
876 void RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
877 ArrayRef<unsigned> Blocks) {
878 const unsigned GroupSize = 8;
879 SpillPlacement::BlockConstraint BCS[GroupSize];
880 unsigned TBS[GroupSize];
881 unsigned B = 0, T = 0;
883 for (unsigned i = 0; i != Blocks.size(); ++i) {
884 unsigned Number = Blocks[i];
885 Intf.moveToBlock(Number);
887 if (!Intf.hasInterference()) {
888 assert(T < GroupSize && "Array overflow");
890 if (++T == GroupSize) {
891 SpillPlacer->addLinks(makeArrayRef(TBS, T));
897 assert(B < GroupSize && "Array overflow");
898 BCS[B].Number = Number;
900 // Interference for the live-in value.
901 if (Intf.first() <= Indexes->getMBBStartIdx(Number))
902 BCS[B].Entry = SpillPlacement::MustSpill;
904 BCS[B].Entry = SpillPlacement::PrefSpill;
906 // Interference for the live-out value.
907 if (Intf.last() >= SA->getLastSplitPoint(Number))
908 BCS[B].Exit = SpillPlacement::MustSpill;
910 BCS[B].Exit = SpillPlacement::PrefSpill;
912 if (++B == GroupSize) {
913 ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B);
914 SpillPlacer->addConstraints(Array);
919 ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B);
920 SpillPlacer->addConstraints(Array);
921 SpillPlacer->addLinks(makeArrayRef(TBS, T));
924 void RAGreedy::growRegion(GlobalSplitCandidate &Cand) {
925 // Keep track of through blocks that have not been added to SpillPlacer.
926 BitVector Todo = SA->getThroughBlocks();
927 SmallVectorImpl<unsigned> &ActiveBlocks = Cand.ActiveBlocks;
928 unsigned AddedTo = 0;
930 unsigned Visited = 0;
934 ArrayRef<unsigned> NewBundles = SpillPlacer->getRecentPositive();
935 // Find new through blocks in the periphery of PrefRegBundles.
936 for (int i = 0, e = NewBundles.size(); i != e; ++i) {
937 unsigned Bundle = NewBundles[i];
938 // Look at all blocks connected to Bundle in the full graph.
939 ArrayRef<unsigned> Blocks = Bundles->getBlocks(Bundle);
940 for (ArrayRef<unsigned>::iterator I = Blocks.begin(), E = Blocks.end();
943 if (!Todo.test(Block))
946 // This is a new through block. Add it to SpillPlacer later.
947 ActiveBlocks.push_back(Block);
953 // Any new blocks to add?
954 if (ActiveBlocks.size() == AddedTo)
957 // Compute through constraints from the interference, or assume that all
958 // through blocks prefer spilling when forming compact regions.
959 ArrayRef<unsigned> NewBlocks = makeArrayRef(ActiveBlocks).slice(AddedTo);
961 addThroughConstraints(Cand.Intf, NewBlocks);
963 // Provide a strong negative bias on through blocks to prevent unwanted
964 // liveness on loop backedges.
965 SpillPlacer->addPrefSpill(NewBlocks, /* Strong= */ true);
966 AddedTo = ActiveBlocks.size();
968 // Perhaps iterating can enable more bundles?
969 SpillPlacer->iterate();
971 DEBUG(dbgs() << ", v=" << Visited);
974 /// calcCompactRegion - Compute the set of edge bundles that should be live
975 /// when splitting the current live range into compact regions. Compact
976 /// regions can be computed without looking at interference. They are the
977 /// regions formed by removing all the live-through blocks from the live range.
979 /// Returns false if the current live range is already compact, or if the
980 /// compact regions would form single block regions anyway.
981 bool RAGreedy::calcCompactRegion(GlobalSplitCandidate &Cand) {
982 // Without any through blocks, the live range is already compact.
983 if (!SA->getNumThroughBlocks())
986 // Compact regions don't correspond to any physreg.
987 Cand.reset(IntfCache, 0);
989 DEBUG(dbgs() << "Compact region bundles");
991 // Use the spill placer to determine the live bundles. GrowRegion pretends
992 // that all the through blocks have interference when PhysReg is unset.
993 SpillPlacer->prepare(Cand.LiveBundles);
995 // The static split cost will be zero since Cand.Intf reports no interference.
997 if (!addSplitConstraints(Cand.Intf, Cost)) {
998 DEBUG(dbgs() << ", none.\n");
1003 SpillPlacer->finish();
1005 if (!Cand.LiveBundles.any()) {
1006 DEBUG(dbgs() << ", none.\n");
1011 for (int i = Cand.LiveBundles.find_first(); i>=0;
1012 i = Cand.LiveBundles.find_next(i))
1013 dbgs() << " EB#" << i;
1019 /// calcSpillCost - Compute how expensive it would be to split the live range in
1020 /// SA around all use blocks instead of forming bundle regions.
1021 BlockFrequency RAGreedy::calcSpillCost() {
1022 BlockFrequency Cost = 0;
1023 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1024 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1025 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1026 unsigned Number = BI.MBB->getNumber();
1027 // We normally only need one spill instruction - a load or a store.
1028 Cost += SpillPlacer->getBlockFrequency(Number);
1030 // Unless the value is redefined in the block.
1031 if (BI.LiveIn && BI.LiveOut && BI.FirstDef)
1032 Cost += SpillPlacer->getBlockFrequency(Number);
1037 /// calcGlobalSplitCost - Return the global split cost of following the split
1038 /// pattern in LiveBundles. This cost should be added to the local cost of the
1039 /// interference pattern in SplitConstraints.
1041 BlockFrequency RAGreedy::calcGlobalSplitCost(GlobalSplitCandidate &Cand) {
1042 BlockFrequency GlobalCost = 0;
1043 const BitVector &LiveBundles = Cand.LiveBundles;
1044 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1045 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1046 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1047 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
1048 bool RegIn = LiveBundles[Bundles->getBundle(BC.Number, 0)];
1049 bool RegOut = LiveBundles[Bundles->getBundle(BC.Number, 1)];
1053 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg);
1055 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg);
1057 GlobalCost += SpillPlacer->getBlockFrequency(BC.Number);
1060 for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) {
1061 unsigned Number = Cand.ActiveBlocks[i];
1062 bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)];
1063 bool RegOut = LiveBundles[Bundles->getBundle(Number, 1)];
1064 if (!RegIn && !RegOut)
1066 if (RegIn && RegOut) {
1067 // We need double spill code if this block has interference.
1068 Cand.Intf.moveToBlock(Number);
1069 if (Cand.Intf.hasInterference()) {
1070 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1071 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1075 // live-in / stack-out or stack-in live-out.
1076 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1081 /// splitAroundRegion - Split the current live range around the regions
1082 /// determined by BundleCand and GlobalCand.
1084 /// Before calling this function, GlobalCand and BundleCand must be initialized
1085 /// so each bundle is assigned to a valid candidate, or NoCand for the
1086 /// stack-bound bundles. The shared SA/SE SplitAnalysis and SplitEditor
1087 /// objects must be initialized for the current live range, and intervals
1088 /// created for the used candidates.
1090 /// @param LREdit The LiveRangeEdit object handling the current split.
1091 /// @param UsedCands List of used GlobalCand entries. Every BundleCand value
1092 /// must appear in this list.
1093 void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit,
1094 ArrayRef<unsigned> UsedCands) {
1095 // These are the intervals created for new global ranges. We may create more
1096 // intervals for local ranges.
1097 const unsigned NumGlobalIntvs = LREdit.size();
1098 DEBUG(dbgs() << "splitAroundRegion with " << NumGlobalIntvs << " globals.\n");
1099 assert(NumGlobalIntvs && "No global intervals configured");
1101 // Isolate even single instructions when dealing with a proper sub-class.
1102 // That guarantees register class inflation for the stack interval because it
1104 unsigned Reg = SA->getParent().reg;
1105 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1107 // First handle all the blocks with uses.
1108 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1109 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1110 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1111 unsigned Number = BI.MBB->getNumber();
1112 unsigned IntvIn = 0, IntvOut = 0;
1113 SlotIndex IntfIn, IntfOut;
1115 unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)];
1116 if (CandIn != NoCand) {
1117 GlobalSplitCandidate &Cand = GlobalCand[CandIn];
1118 IntvIn = Cand.IntvIdx;
1119 Cand.Intf.moveToBlock(Number);
1120 IntfIn = Cand.Intf.first();
1124 unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)];
1125 if (CandOut != NoCand) {
1126 GlobalSplitCandidate &Cand = GlobalCand[CandOut];
1127 IntvOut = Cand.IntvIdx;
1128 Cand.Intf.moveToBlock(Number);
1129 IntfOut = Cand.Intf.last();
1133 // Create separate intervals for isolated blocks with multiple uses.
1134 if (!IntvIn && !IntvOut) {
1135 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n");
1136 if (SA->shouldSplitSingleBlock(BI, SingleInstrs))
1137 SE->splitSingleBlock(BI);
1141 if (IntvIn && IntvOut)
1142 SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut);
1144 SE->splitRegInBlock(BI, IntvIn, IntfIn);
1146 SE->splitRegOutBlock(BI, IntvOut, IntfOut);
1149 // Handle live-through blocks. The relevant live-through blocks are stored in
1150 // the ActiveBlocks list with each candidate. We need to filter out
1152 BitVector Todo = SA->getThroughBlocks();
1153 for (unsigned c = 0; c != UsedCands.size(); ++c) {
1154 ArrayRef<unsigned> Blocks = GlobalCand[UsedCands[c]].ActiveBlocks;
1155 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
1156 unsigned Number = Blocks[i];
1157 if (!Todo.test(Number))
1161 unsigned IntvIn = 0, IntvOut = 0;
1162 SlotIndex IntfIn, IntfOut;
1164 unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)];
1165 if (CandIn != NoCand) {
1166 GlobalSplitCandidate &Cand = GlobalCand[CandIn];
1167 IntvIn = Cand.IntvIdx;
1168 Cand.Intf.moveToBlock(Number);
1169 IntfIn = Cand.Intf.first();
1172 unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)];
1173 if (CandOut != NoCand) {
1174 GlobalSplitCandidate &Cand = GlobalCand[CandOut];
1175 IntvOut = Cand.IntvIdx;
1176 Cand.Intf.moveToBlock(Number);
1177 IntfOut = Cand.Intf.last();
1179 if (!IntvIn && !IntvOut)
1181 SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut);
1187 SmallVector<unsigned, 8> IntvMap;
1188 SE->finish(&IntvMap);
1189 DebugVars->splitRegister(Reg, LREdit.regs(), *LIS);
1191 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1192 unsigned OrigBlocks = SA->getNumLiveBlocks();
1194 // Sort out the new intervals created by splitting. We get four kinds:
1195 // - Remainder intervals should not be split again.
1196 // - Candidate intervals can be assigned to Cand.PhysReg.
1197 // - Block-local splits are candidates for local splitting.
1198 // - DCE leftovers should go back on the queue.
1199 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) {
1200 LiveInterval &Reg = LIS->getInterval(LREdit.get(i));
1202 // Ignore old intervals from DCE.
1203 if (getStage(Reg) != RS_New)
1206 // Remainder interval. Don't try splitting again, spill if it doesn't
1208 if (IntvMap[i] == 0) {
1209 setStage(Reg, RS_Spill);
1213 // Global intervals. Allow repeated splitting as long as the number of live
1214 // blocks is strictly decreasing.
1215 if (IntvMap[i] < NumGlobalIntvs) {
1216 if (SA->countLiveBlocks(&Reg) >= OrigBlocks) {
1217 DEBUG(dbgs() << "Main interval covers the same " << OrigBlocks
1218 << " blocks as original.\n");
1219 // Don't allow repeated splitting as a safe guard against looping.
1220 setStage(Reg, RS_Split2);
1225 // Other intervals are treated as new. This includes local intervals created
1226 // for blocks with multiple uses, and anything created by DCE.
1230 MF->verify(this, "After splitting live range around region");
1233 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1234 SmallVectorImpl<unsigned> &NewVRegs) {
1235 unsigned NumCands = 0;
1236 unsigned BestCand = NoCand;
1237 BlockFrequency BestCost;
1238 SmallVector<unsigned, 8> UsedCands;
1240 // Check if we can split this live range around a compact region.
1241 bool HasCompact = calcCompactRegion(GlobalCand.front());
1243 // Yes, keep GlobalCand[0] as the compact region candidate.
1245 BestCost = BlockFrequency::getMaxFrequency();
1247 // No benefit from the compact region, our fallback will be per-block
1248 // splitting. Make sure we find a solution that is cheaper than spilling.
1249 BestCost = calcSpillCost();
1250 DEBUG(dbgs() << "Cost of isolating all blocks = ";
1251 MBFI->printBlockFreq(dbgs(), BestCost) << '\n');
1255 while (unsigned PhysReg = Order.next()) {
1256 // Discard bad candidates before we run out of interference cache cursors.
1257 // This will only affect register classes with a lot of registers (>32).
1258 if (NumCands == IntfCache.getMaxCursors()) {
1259 unsigned WorstCount = ~0u;
1261 for (unsigned i = 0; i != NumCands; ++i) {
1262 if (i == BestCand || !GlobalCand[i].PhysReg)
1264 unsigned Count = GlobalCand[i].LiveBundles.count();
1265 if (Count < WorstCount)
1266 Worst = i, WorstCount = Count;
1269 GlobalCand[Worst] = GlobalCand[NumCands];
1270 if (BestCand == NumCands)
1274 if (GlobalCand.size() <= NumCands)
1275 GlobalCand.resize(NumCands+1);
1276 GlobalSplitCandidate &Cand = GlobalCand[NumCands];
1277 Cand.reset(IntfCache, PhysReg);
1279 SpillPlacer->prepare(Cand.LiveBundles);
1280 BlockFrequency Cost;
1281 if (!addSplitConstraints(Cand.Intf, Cost)) {
1282 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n");
1285 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = ";
1286 MBFI->printBlockFreq(dbgs(), Cost));
1287 if (Cost >= BestCost) {
1289 if (BestCand == NoCand)
1290 dbgs() << " worse than no bundles\n";
1292 dbgs() << " worse than "
1293 << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
1299 SpillPlacer->finish();
1301 // No live bundles, defer to splitSingleBlocks().
1302 if (!Cand.LiveBundles.any()) {
1303 DEBUG(dbgs() << " no bundles.\n");
1307 Cost += calcGlobalSplitCost(Cand);
1309 dbgs() << ", total = "; MBFI->printBlockFreq(dbgs(), Cost)
1311 for (int i = Cand.LiveBundles.find_first(); i>=0;
1312 i = Cand.LiveBundles.find_next(i))
1313 dbgs() << " EB#" << i;
1316 if (Cost < BestCost) {
1317 BestCand = NumCands;
1323 // No solutions found, fall back to single block splitting.
1324 if (!HasCompact && BestCand == NoCand)
1327 // Prepare split editor.
1328 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1329 SE->reset(LREdit, SplitSpillMode);
1331 // Assign all edge bundles to the preferred candidate, or NoCand.
1332 BundleCand.assign(Bundles->getNumBundles(), NoCand);
1334 // Assign bundles for the best candidate region.
1335 if (BestCand != NoCand) {
1336 GlobalSplitCandidate &Cand = GlobalCand[BestCand];
1337 if (unsigned B = Cand.getBundles(BundleCand, BestCand)) {
1338 UsedCands.push_back(BestCand);
1339 Cand.IntvIdx = SE->openIntv();
1340 DEBUG(dbgs() << "Split for " << PrintReg(Cand.PhysReg, TRI) << " in "
1341 << B << " bundles, intv " << Cand.IntvIdx << ".\n");
1346 // Assign bundles for the compact region.
1348 GlobalSplitCandidate &Cand = GlobalCand.front();
1349 assert(!Cand.PhysReg && "Compact region has no physreg");
1350 if (unsigned B = Cand.getBundles(BundleCand, 0)) {
1351 UsedCands.push_back(0);
1352 Cand.IntvIdx = SE->openIntv();
1353 DEBUG(dbgs() << "Split for compact region in " << B << " bundles, intv "
1354 << Cand.IntvIdx << ".\n");
1359 splitAroundRegion(LREdit, UsedCands);
1364 //===----------------------------------------------------------------------===//
1365 // Per-Block Splitting
1366 //===----------------------------------------------------------------------===//
1368 /// tryBlockSplit - Split a global live range around every block with uses. This
1369 /// creates a lot of local live ranges, that will be split by tryLocalSplit if
1370 /// they don't allocate.
1371 unsigned RAGreedy::tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1372 SmallVectorImpl<unsigned> &NewVRegs) {
1373 assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed");
1374 unsigned Reg = VirtReg.reg;
1375 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1376 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1377 SE->reset(LREdit, SplitSpillMode);
1378 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1379 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1380 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1381 if (SA->shouldSplitSingleBlock(BI, SingleInstrs))
1382 SE->splitSingleBlock(BI);
1384 // No blocks were split.
1388 // We did split for some blocks.
1389 SmallVector<unsigned, 8> IntvMap;
1390 SE->finish(&IntvMap);
1392 // Tell LiveDebugVariables about the new ranges.
1393 DebugVars->splitRegister(Reg, LREdit.regs(), *LIS);
1395 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1397 // Sort out the new intervals created by splitting. The remainder interval
1398 // goes straight to spilling, the new local ranges get to stay RS_New.
1399 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) {
1400 LiveInterval &LI = LIS->getInterval(LREdit.get(i));
1401 if (getStage(LI) == RS_New && IntvMap[i] == 0)
1402 setStage(LI, RS_Spill);
1406 MF->verify(this, "After splitting live range around basic blocks");
1411 //===----------------------------------------------------------------------===//
1412 // Per-Instruction Splitting
1413 //===----------------------------------------------------------------------===//
1415 /// Get the number of allocatable registers that match the constraints of \p Reg
1416 /// on \p MI and that are also in \p SuperRC.
1417 static unsigned getNumAllocatableRegsForConstraints(
1418 const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC,
1419 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1420 const RegisterClassInfo &RCI) {
1421 assert(SuperRC && "Invalid register class");
1423 const TargetRegisterClass *ConstrainedRC =
1424 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI,
1425 /* ExploreBundle */ true);
1428 return RCI.getNumAllocatableRegs(ConstrainedRC);
1431 /// tryInstructionSplit - Split a live range around individual instructions.
1432 /// This is normally not worthwhile since the spiller is doing essentially the
1433 /// same thing. However, when the live range is in a constrained register
1434 /// class, it may help to insert copies such that parts of the live range can
1435 /// be moved to a larger register class.
1437 /// This is similar to spilling to a larger register class.
1439 RAGreedy::tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1440 SmallVectorImpl<unsigned> &NewVRegs) {
1441 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg);
1442 // There is no point to this if there are no larger sub-classes.
1443 if (!RegClassInfo.isProperSubClass(CurRC))
1446 // Always enable split spill mode, since we're effectively spilling to a
1448 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1449 SE->reset(LREdit, SplitEditor::SM_Size);
1451 ArrayRef<SlotIndex> Uses = SA->getUseSlots();
1452 if (Uses.size() <= 1)
1455 DEBUG(dbgs() << "Split around " << Uses.size() << " individual instrs.\n");
1457 const TargetRegisterClass *SuperRC = TRI->getLargestLegalSuperClass(CurRC);
1458 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC);
1459 // Split around every non-copy instruction if this split will relax
1460 // the constraints on the virtual register.
1461 // Otherwise, splitting just inserts uncoalescable copies that do not help
1463 for (unsigned i = 0; i != Uses.size(); ++i) {
1464 if (const MachineInstr *MI = Indexes->getInstructionFromIndex(Uses[i]))
1465 if (MI->isFullCopy() ||
1466 SuperRCNumAllocatableRegs ==
1467 getNumAllocatableRegsForConstraints(MI, VirtReg.reg, SuperRC, TII,
1469 DEBUG(dbgs() << " skip:\t" << Uses[i] << '\t' << *MI);
1473 SlotIndex SegStart = SE->enterIntvBefore(Uses[i]);
1474 SlotIndex SegStop = SE->leaveIntvAfter(Uses[i]);
1475 SE->useIntv(SegStart, SegStop);
1478 if (LREdit.empty()) {
1479 DEBUG(dbgs() << "All uses were copies.\n");
1483 SmallVector<unsigned, 8> IntvMap;
1484 SE->finish(&IntvMap);
1485 DebugVars->splitRegister(VirtReg.reg, LREdit.regs(), *LIS);
1486 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1488 // Assign all new registers to RS_Spill. This was the last chance.
1489 setStage(LREdit.begin(), LREdit.end(), RS_Spill);
1494 //===----------------------------------------------------------------------===//
1496 //===----------------------------------------------------------------------===//
1499 /// calcGapWeights - Compute the maximum spill weight that needs to be evicted
1500 /// in order to use PhysReg between two entries in SA->UseSlots.
1502 /// GapWeight[i] represents the gap between UseSlots[i] and UseSlots[i+1].
1504 void RAGreedy::calcGapWeights(unsigned PhysReg,
1505 SmallVectorImpl<float> &GapWeight) {
1506 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
1507 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
1508 ArrayRef<SlotIndex> Uses = SA->getUseSlots();
1509 const unsigned NumGaps = Uses.size()-1;
1511 // Start and end points for the interference check.
1512 SlotIndex StartIdx =
1513 BI.LiveIn ? BI.FirstInstr.getBaseIndex() : BI.FirstInstr;
1515 BI.LiveOut ? BI.LastInstr.getBoundaryIndex() : BI.LastInstr;
1517 GapWeight.assign(NumGaps, 0.0f);
1519 // Add interference from each overlapping register.
1520 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1521 if (!Matrix->query(const_cast<LiveInterval&>(SA->getParent()), *Units)
1522 .checkInterference())
1525 // We know that VirtReg is a continuous interval from FirstInstr to
1526 // LastInstr, so we don't need InterferenceQuery.
1528 // Interference that overlaps an instruction is counted in both gaps
1529 // surrounding the instruction. The exception is interference before
1530 // StartIdx and after StopIdx.
1532 LiveIntervalUnion::SegmentIter IntI =
1533 Matrix->getLiveUnions()[*Units] .find(StartIdx);
1534 for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) {
1535 // Skip the gaps before IntI.
1536 while (Uses[Gap+1].getBoundaryIndex() < IntI.start())
1537 if (++Gap == NumGaps)
1542 // Update the gaps covered by IntI.
1543 const float weight = IntI.value()->weight;
1544 for (; Gap != NumGaps; ++Gap) {
1545 GapWeight[Gap] = std::max(GapWeight[Gap], weight);
1546 if (Uses[Gap+1].getBaseIndex() >= IntI.stop())
1554 // Add fixed interference.
1555 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1556 const LiveRange &LR = LIS->getRegUnit(*Units);
1557 LiveRange::const_iterator I = LR.find(StartIdx);
1558 LiveRange::const_iterator E = LR.end();
1560 // Same loop as above. Mark any overlapped gaps as HUGE_VALF.
1561 for (unsigned Gap = 0; I != E && I->start < StopIdx; ++I) {
1562 while (Uses[Gap+1].getBoundaryIndex() < I->start)
1563 if (++Gap == NumGaps)
1568 for (; Gap != NumGaps; ++Gap) {
1569 GapWeight[Gap] = llvm::huge_valf;
1570 if (Uses[Gap+1].getBaseIndex() >= I->end)
1579 /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
1582 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1583 SmallVectorImpl<unsigned> &NewVRegs) {
1584 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
1585 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
1587 // Note that it is possible to have an interval that is live-in or live-out
1588 // while only covering a single block - A phi-def can use undef values from
1589 // predecessors, and the block could be a single-block loop.
1590 // We don't bother doing anything clever about such a case, we simply assume
1591 // that the interval is continuous from FirstInstr to LastInstr. We should
1592 // make sure that we don't do anything illegal to such an interval, though.
1594 ArrayRef<SlotIndex> Uses = SA->getUseSlots();
1595 if (Uses.size() <= 2)
1597 const unsigned NumGaps = Uses.size()-1;
1600 dbgs() << "tryLocalSplit: ";
1601 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
1602 dbgs() << ' ' << Uses[i];
1606 // If VirtReg is live across any register mask operands, compute a list of
1607 // gaps with register masks.
1608 SmallVector<unsigned, 8> RegMaskGaps;
1609 if (Matrix->checkRegMaskInterference(VirtReg)) {
1610 // Get regmask slots for the whole block.
1611 ArrayRef<SlotIndex> RMS = LIS->getRegMaskSlotsInBlock(BI.MBB->getNumber());
1612 DEBUG(dbgs() << RMS.size() << " regmasks in block:");
1613 // Constrain to VirtReg's live range.
1614 unsigned ri = std::lower_bound(RMS.begin(), RMS.end(),
1615 Uses.front().getRegSlot()) - RMS.begin();
1616 unsigned re = RMS.size();
1617 for (unsigned i = 0; i != NumGaps && ri != re; ++i) {
1618 // Look for Uses[i] <= RMS <= Uses[i+1].
1619 assert(!SlotIndex::isEarlierInstr(RMS[ri], Uses[i]));
1620 if (SlotIndex::isEarlierInstr(Uses[i+1], RMS[ri]))
1622 // Skip a regmask on the same instruction as the last use. It doesn't
1623 // overlap the live range.
1624 if (SlotIndex::isSameInstr(Uses[i+1], RMS[ri]) && i+1 == NumGaps)
1626 DEBUG(dbgs() << ' ' << RMS[ri] << ':' << Uses[i] << '-' << Uses[i+1]);
1627 RegMaskGaps.push_back(i);
1628 // Advance ri to the next gap. A regmask on one of the uses counts in
1630 while (ri != re && SlotIndex::isEarlierInstr(RMS[ri], Uses[i+1]))
1633 DEBUG(dbgs() << '\n');
1636 // Since we allow local split results to be split again, there is a risk of
1637 // creating infinite loops. It is tempting to require that the new live
1638 // ranges have less instructions than the original. That would guarantee
1639 // convergence, but it is too strict. A live range with 3 instructions can be
1640 // split 2+3 (including the COPY), and we want to allow that.
1642 // Instead we use these rules:
1644 // 1. Allow any split for ranges with getStage() < RS_Split2. (Except for the
1645 // noop split, of course).
1646 // 2. Require progress be made for ranges with getStage() == RS_Split2. All
1647 // the new ranges must have fewer instructions than before the split.
1648 // 3. New ranges with the same number of instructions are marked RS_Split2,
1649 // smaller ranges are marked RS_New.
1651 // These rules allow a 3 -> 2+3 split once, which we need. They also prevent
1652 // excessive splitting and infinite loops.
1654 bool ProgressRequired = getStage(VirtReg) >= RS_Split2;
1656 // Best split candidate.
1657 unsigned BestBefore = NumGaps;
1658 unsigned BestAfter = 0;
1661 const float blockFreq =
1662 SpillPlacer->getBlockFrequency(BI.MBB->getNumber()).getFrequency() *
1663 (1.0f / MBFI->getEntryFreq());
1664 SmallVector<float, 8> GapWeight;
1667 while (unsigned PhysReg = Order.next()) {
1668 // Keep track of the largest spill weight that would need to be evicted in
1669 // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1].
1670 calcGapWeights(PhysReg, GapWeight);
1672 // Remove any gaps with regmask clobbers.
1673 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg))
1674 for (unsigned i = 0, e = RegMaskGaps.size(); i != e; ++i)
1675 GapWeight[RegMaskGaps[i]] = llvm::huge_valf;
1677 // Try to find the best sequence of gaps to close.
1678 // The new spill weight must be larger than any gap interference.
1680 // We will split before Uses[SplitBefore] and after Uses[SplitAfter].
1681 unsigned SplitBefore = 0, SplitAfter = 1;
1683 // MaxGap should always be max(GapWeight[SplitBefore..SplitAfter-1]).
1684 // It is the spill weight that needs to be evicted.
1685 float MaxGap = GapWeight[0];
1688 // Live before/after split?
1689 const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
1690 const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut;
1692 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' '
1693 << Uses[SplitBefore] << '-' << Uses[SplitAfter]
1694 << " i=" << MaxGap);
1696 // Stop before the interval gets so big we wouldn't be making progress.
1697 if (!LiveBefore && !LiveAfter) {
1698 DEBUG(dbgs() << " all\n");
1701 // Should the interval be extended or shrunk?
1704 // How many gaps would the new range have?
1705 unsigned NewGaps = LiveBefore + SplitAfter - SplitBefore + LiveAfter;
1707 // Legally, without causing looping?
1708 bool Legal = !ProgressRequired || NewGaps < NumGaps;
1710 if (Legal && MaxGap < llvm::huge_valf) {
1711 // Estimate the new spill weight. Each instruction reads or writes the
1712 // register. Conservatively assume there are no read-modify-write
1715 // Try to guess the size of the new interval.
1716 const float EstWeight = normalizeSpillWeight(blockFreq * (NewGaps + 1),
1717 Uses[SplitBefore].distance(Uses[SplitAfter]) +
1718 (LiveBefore + LiveAfter)*SlotIndex::InstrDist);
1719 // Would this split be possible to allocate?
1720 // Never allocate all gaps, we wouldn't be making progress.
1721 DEBUG(dbgs() << " w=" << EstWeight);
1722 if (EstWeight * Hysteresis >= MaxGap) {
1724 float Diff = EstWeight - MaxGap;
1725 if (Diff > BestDiff) {
1726 DEBUG(dbgs() << " (best)");
1727 BestDiff = Hysteresis * Diff;
1728 BestBefore = SplitBefore;
1729 BestAfter = SplitAfter;
1736 if (++SplitBefore < SplitAfter) {
1737 DEBUG(dbgs() << " shrink\n");
1738 // Recompute the max when necessary.
1739 if (GapWeight[SplitBefore - 1] >= MaxGap) {
1740 MaxGap = GapWeight[SplitBefore];
1741 for (unsigned i = SplitBefore + 1; i != SplitAfter; ++i)
1742 MaxGap = std::max(MaxGap, GapWeight[i]);
1749 // Try to extend the interval.
1750 if (SplitAfter >= NumGaps) {
1751 DEBUG(dbgs() << " end\n");
1755 DEBUG(dbgs() << " extend\n");
1756 MaxGap = std::max(MaxGap, GapWeight[SplitAfter++]);
1760 // Didn't find any candidates?
1761 if (BestBefore == NumGaps)
1764 DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore]
1765 << '-' << Uses[BestAfter] << ", " << BestDiff
1766 << ", " << (BestAfter - BestBefore + 1) << " instrs\n");
1768 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1772 SlotIndex SegStart = SE->enterIntvBefore(Uses[BestBefore]);
1773 SlotIndex SegStop = SE->leaveIntvAfter(Uses[BestAfter]);
1774 SE->useIntv(SegStart, SegStop);
1775 SmallVector<unsigned, 8> IntvMap;
1776 SE->finish(&IntvMap);
1777 DebugVars->splitRegister(VirtReg.reg, LREdit.regs(), *LIS);
1779 // If the new range has the same number of instructions as before, mark it as
1780 // RS_Split2 so the next split will be forced to make progress. Otherwise,
1781 // leave the new intervals as RS_New so they can compete.
1782 bool LiveBefore = BestBefore != 0 || BI.LiveIn;
1783 bool LiveAfter = BestAfter != NumGaps || BI.LiveOut;
1784 unsigned NewGaps = LiveBefore + BestAfter - BestBefore + LiveAfter;
1785 if (NewGaps >= NumGaps) {
1786 DEBUG(dbgs() << "Tagging non-progress ranges: ");
1787 assert(!ProgressRequired && "Didn't make progress when it was required.");
1788 for (unsigned i = 0, e = IntvMap.size(); i != e; ++i)
1789 if (IntvMap[i] == 1) {
1790 setStage(LIS->getInterval(LREdit.get(i)), RS_Split2);
1791 DEBUG(dbgs() << PrintReg(LREdit.get(i)));
1793 DEBUG(dbgs() << '\n');
1800 //===----------------------------------------------------------------------===//
1801 // Live Range Splitting
1802 //===----------------------------------------------------------------------===//
1804 /// trySplit - Try to split VirtReg or one of its interferences, making it
1806 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
1807 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
1808 SmallVectorImpl<unsigned>&NewVRegs) {
1809 // Ranges must be Split2 or less.
1810 if (getStage(VirtReg) >= RS_Spill)
1813 // Local intervals are handled separately.
1814 if (LIS->intervalIsInOneMBB(VirtReg)) {
1815 NamedRegionTimer T("Local Splitting", TimerGroupName, TimePassesIsEnabled);
1816 SA->analyze(&VirtReg);
1817 unsigned PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs);
1818 if (PhysReg || !NewVRegs.empty())
1820 return tryInstructionSplit(VirtReg, Order, NewVRegs);
1823 NamedRegionTimer T("Global Splitting", TimerGroupName, TimePassesIsEnabled);
1825 SA->analyze(&VirtReg);
1827 // FIXME: SplitAnalysis may repair broken live ranges coming from the
1828 // coalescer. That may cause the range to become allocatable which means that
1829 // tryRegionSplit won't be making progress. This check should be replaced with
1830 // an assertion when the coalescer is fixed.
1831 if (SA->didRepairRange()) {
1832 // VirtReg has changed, so all cached queries are invalid.
1833 Matrix->invalidateVirtRegs();
1834 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
1838 // First try to split around a region spanning multiple blocks. RS_Split2
1839 // ranges already made dubious progress with region splitting, so they go
1840 // straight to single block splitting.
1841 if (getStage(VirtReg) < RS_Split2) {
1842 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1843 if (PhysReg || !NewVRegs.empty())
1847 // Then isolate blocks.
1848 return tryBlockSplit(VirtReg, Order, NewVRegs);
1851 //===----------------------------------------------------------------------===//
1852 // Last Chance Recoloring
1853 //===----------------------------------------------------------------------===//
1855 /// mayRecolorAllInterferences - Check if the virtual registers that
1856 /// interfere with \p VirtReg on \p PhysReg (or one of its aliases) may be
1857 /// recolored to free \p PhysReg.
1858 /// When true is returned, \p RecoloringCandidates has been augmented with all
1859 /// the live intervals that need to be recolored in order to free \p PhysReg
1861 /// \p FixedRegisters contains all the virtual registers that cannot be
1864 RAGreedy::mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
1865 SmallLISet &RecoloringCandidates,
1866 const SmallVirtRegSet &FixedRegisters) {
1867 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg);
1869 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1870 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
1871 // If there is LastChanceRecoloringMaxInterference or more interferences,
1872 // chances are one would not be recolorable.
1873 if (Q.collectInterferingVRegs(LastChanceRecoloringMaxInterference) >=
1874 LastChanceRecoloringMaxInterference) {
1875 DEBUG(dbgs() << "Early abort: too many interferences.\n");
1878 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
1879 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
1880 // If Intf is done and sit on the same register class as VirtReg,
1881 // it would not be recolorable as it is in the same state as VirtReg.
1882 if ((getStage(*Intf) == RS_Done &&
1883 MRI->getRegClass(Intf->reg) == CurRC) ||
1884 FixedRegisters.count(Intf->reg)) {
1885 DEBUG(dbgs() << "Early abort: the inteference is not recolorable.\n");
1888 RecoloringCandidates.insert(Intf);
1894 /// tryLastChanceRecoloring - Try to assign a color to \p VirtReg by recoloring
1895 /// its interferences.
1896 /// Last chance recoloring chooses a color for \p VirtReg and recolors every
1897 /// virtual register that was using it. The recoloring process may recursively
1898 /// use the last chance recoloring. Therefore, when a virtual register has been
1899 /// assigned a color by this mechanism, it is marked as Fixed, i.e., it cannot
1900 /// be last-chance-recolored again during this recoloring "session".
1903 /// vA can use {R1, R2 }
1904 /// vB can use { R2, R3}
1905 /// vC can use {R1 }
1906 /// Where vA, vB, and vC cannot be split anymore (they are reloads for
1907 /// instance) and they all interfere.
1909 /// vA is assigned R1
1910 /// vB is assigned R2
1911 /// vC tries to evict vA but vA is already done.
1912 /// Regular register allocation fails.
1914 /// Last chance recoloring kicks in:
1915 /// vC does as if vA was evicted => vC uses R1.
1916 /// vC is marked as fixed.
1917 /// vA needs to find a color.
1918 /// None are available.
1919 /// vA cannot evict vC: vC is a fixed virtual register now.
1920 /// vA does as if vB was evicted => vA uses R2.
1921 /// vB needs to find a color.
1922 /// R3 is available.
1923 /// Recoloring => vC = R1, vA = R2, vB = R3
1925 /// \p Order defines the preferred allocation order for \p VirtReg.
1926 /// \p NewRegs will contain any new virtual register that have been created
1927 /// (split, spill) during the process and that must be assigned.
1928 /// \p FixedRegisters contains all the virtual registers that cannot be
1930 /// \p Depth gives the current depth of the last chance recoloring.
1931 /// \return a physical register that can be used for VirtReg or ~0u if none
1933 unsigned RAGreedy::tryLastChanceRecoloring(LiveInterval &VirtReg,
1934 AllocationOrder &Order,
1935 SmallVectorImpl<unsigned> &NewVRegs,
1936 SmallVirtRegSet &FixedRegisters,
1938 DEBUG(dbgs() << "Try last chance recoloring for " << VirtReg << '\n');
1939 // Ranges must be Done.
1940 assert((getStage(VirtReg) >= RS_Done || !VirtReg.isSpillable()) &&
1941 "Last chance recoloring should really be last chance");
1942 // Set the max depth to LastChanceRecoloringMaxDepth.
1943 // We may want to reconsider that if we end up with a too large search space
1944 // for target with hundreds of registers.
1945 // Indeed, in that case we may want to cut the search space earlier.
1946 if (Depth >= LastChanceRecoloringMaxDepth) {
1947 DEBUG(dbgs() << "Abort because max depth has been reached.\n");
1951 // Set of Live intervals that will need to be recolored.
1952 SmallLISet RecoloringCandidates;
1953 // Record the original mapping virtual register to physical register in case
1954 // the recoloring fails.
1955 DenseMap<unsigned, unsigned> VirtRegToPhysReg;
1956 // Mark VirtReg as fixed, i.e., it will not be recolored pass this point in
1957 // this recoloring "session".
1958 FixedRegisters.insert(VirtReg.reg);
1961 while (unsigned PhysReg = Order.next()) {
1962 DEBUG(dbgs() << "Try to assign: " << VirtReg << " to "
1963 << PrintReg(PhysReg, TRI) << '\n');
1964 RecoloringCandidates.clear();
1965 VirtRegToPhysReg.clear();
1967 // It is only possible to recolor virtual register interference.
1968 if (Matrix->checkInterference(VirtReg, PhysReg) >
1969 LiveRegMatrix::IK_VirtReg) {
1970 DEBUG(dbgs() << "Some inteferences are not with virtual registers.\n");
1975 // Early give up on this PhysReg if it is obvious we cannot recolor all
1976 // the interferences.
1977 if (!mayRecolorAllInterferences(PhysReg, VirtReg, RecoloringCandidates,
1979 DEBUG(dbgs() << "Some inteferences cannot be recolored.\n");
1983 // RecoloringCandidates contains all the virtual registers that interfer
1984 // with VirtReg on PhysReg (or one of its aliases).
1985 // Enqueue them for recoloring and perform the actual recoloring.
1986 PQueue RecoloringQueue;
1987 for (SmallLISet::iterator It = RecoloringCandidates.begin(),
1988 EndIt = RecoloringCandidates.end();
1989 It != EndIt; ++It) {
1990 unsigned ItVirtReg = (*It)->reg;
1991 enqueue(RecoloringQueue, *It);
1992 assert(VRM->hasPhys(ItVirtReg) &&
1993 "Interferences are supposed to be with allocated vairables");
1995 // Record the current allocation.
1996 VirtRegToPhysReg[ItVirtReg] = VRM->getPhys(ItVirtReg);
1997 // unset the related struct.
1998 Matrix->unassign(**It);
2001 // Do as if VirtReg was assigned to PhysReg so that the underlying
2002 // recoloring has the right information about the interferes and
2003 // available colors.
2004 Matrix->assign(VirtReg, PhysReg);
2006 // Save the current recoloring state.
2007 // If we cannot recolor all the interferences, we will have to start again
2008 // at this point for the next physical register.
2009 SmallVirtRegSet SaveFixedRegisters(FixedRegisters);
2010 if (tryRecoloringCandidates(RecoloringQueue, NewVRegs, FixedRegisters,
2012 // Do not mess up with the global assignment process.
2013 // I.e., VirtReg must be unassigned.
2014 Matrix->unassign(VirtReg);
2018 DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to "
2019 << PrintReg(PhysReg, TRI) << '\n');
2021 // The recoloring attempt failed, undo the changes.
2022 FixedRegisters = SaveFixedRegisters;
2023 Matrix->unassign(VirtReg);
2025 for (SmallLISet::iterator It = RecoloringCandidates.begin(),
2026 EndIt = RecoloringCandidates.end();
2027 It != EndIt; ++It) {
2028 unsigned ItVirtReg = (*It)->reg;
2029 if (VRM->hasPhys(ItVirtReg))
2030 Matrix->unassign(**It);
2031 Matrix->assign(**It, VirtRegToPhysReg[ItVirtReg]);
2035 // Last chance recoloring did not worked either, give up.
2039 /// tryRecoloringCandidates - Try to assign a new color to every register
2040 /// in \RecoloringQueue.
2041 /// \p NewRegs will contain any new virtual register created during the
2042 /// recoloring process.
2043 /// \p FixedRegisters[in/out] contains all the registers that have been
2045 /// \return true if all virtual registers in RecoloringQueue were successfully
2046 /// recolored, false otherwise.
2047 bool RAGreedy::tryRecoloringCandidates(PQueue &RecoloringQueue,
2048 SmallVectorImpl<unsigned> &NewVRegs,
2049 SmallVirtRegSet &FixedRegisters,
2051 while (!RecoloringQueue.empty()) {
2052 LiveInterval *LI = dequeue(RecoloringQueue);
2053 DEBUG(dbgs() << "Try to recolor: " << *LI << '\n');
2055 PhysReg = selectOrSplitImpl(*LI, NewVRegs, FixedRegisters, Depth + 1);
2056 if (PhysReg == ~0u || !PhysReg)
2058 DEBUG(dbgs() << "Recoloring of " << *LI
2059 << " succeeded with: " << PrintReg(PhysReg, TRI) << '\n');
2060 Matrix->assign(*LI, PhysReg);
2061 FixedRegisters.insert(LI->reg);
2066 //===----------------------------------------------------------------------===//
2068 //===----------------------------------------------------------------------===//
2070 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
2071 SmallVectorImpl<unsigned> &NewVRegs) {
2072 SmallVirtRegSet FixedRegisters;
2073 return selectOrSplitImpl(VirtReg, NewVRegs, FixedRegisters);
2076 unsigned RAGreedy::selectOrSplitImpl(LiveInterval &VirtReg,
2077 SmallVectorImpl<unsigned> &NewVRegs,
2078 SmallVirtRegSet &FixedRegisters,
2080 // First try assigning a free register.
2081 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
2082 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
2085 LiveRangeStage Stage = getStage(VirtReg);
2086 DEBUG(dbgs() << StageName[Stage]
2087 << " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n');
2089 // Try to evict a less worthy live range, but only for ranges from the primary
2090 // queue. The RS_Split ranges already failed to do this, and they should not
2091 // get a second chance until they have been split.
2092 if (Stage != RS_Split)
2093 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs))
2096 assert(NewVRegs.empty() && "Cannot append to existing NewVRegs");
2098 // The first time we see a live range, don't try to split or spill.
2099 // Wait until the second time, when all smaller ranges have been allocated.
2100 // This gives a better picture of the interference to split around.
2101 if (Stage < RS_Split) {
2102 setStage(VirtReg, RS_Split);
2103 DEBUG(dbgs() << "wait for second round\n");
2104 NewVRegs.push_back(VirtReg.reg);
2108 // If we couldn't allocate a register from spilling, there is probably some
2109 // invalid inline assembly. The base class wil report it.
2110 if (Stage >= RS_Done || !VirtReg.isSpillable())
2111 return tryLastChanceRecoloring(VirtReg, Order, NewVRegs, FixedRegisters,
2114 // Try splitting VirtReg or interferences.
2115 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
2116 if (PhysReg || !NewVRegs.empty())
2119 // Finally spill VirtReg itself.
2120 NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
2121 LiveRangeEdit LRE(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
2122 spiller().spill(LRE);
2123 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Done);
2126 MF->verify(this, "After spilling");
2128 // The live virtual register requesting allocation was spilled, so tell
2129 // the caller not to allocate anything during this round.
2133 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
2134 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
2135 << "********** Function: " << mf.getName() << '\n');
2138 TRI = MF->getTarget().getRegisterInfo();
2139 TII = MF->getTarget().getInstrInfo();
2140 RCI.runOnMachineFunction(mf);
2142 MF->verify(this, "Before greedy register allocator");
2144 RegAllocBase::init(getAnalysis<VirtRegMap>(),
2145 getAnalysis<LiveIntervals>(),
2146 getAnalysis<LiveRegMatrix>());
2147 Indexes = &getAnalysis<SlotIndexes>();
2148 MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
2149 DomTree = &getAnalysis<MachineDominatorTree>();
2150 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
2151 Loops = &getAnalysis<MachineLoopInfo>();
2152 Bundles = &getAnalysis<EdgeBundles>();
2153 SpillPlacer = &getAnalysis<SpillPlacement>();
2154 DebugVars = &getAnalysis<LiveDebugVariables>();
2156 calculateSpillWeightsAndHints(*LIS, mf, *Loops, *MBFI);
2160 SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops));
2161 SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree, *MBFI));
2162 ExtraRegInfo.clear();
2163 ExtraRegInfo.resize(MRI->getNumVirtRegs());
2165 IntfCache.init(MF, Matrix->getLiveUnions(), Indexes, LIS, TRI);
2166 GlobalCand.resize(32); // This will grow as needed.