1 //===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RAGreedy function pass for register allocation in
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "llvm/CodeGen/Passes.h"
17 #include "AllocationOrder.h"
18 #include "InterferenceCache.h"
19 #include "LiveDebugVariables.h"
20 #include "RegAllocBase.h"
21 #include "SpillPlacement.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/CodeGen/CalcSpillWeights.h"
27 #include "llvm/CodeGen/EdgeBundles.h"
28 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
29 #include "llvm/CodeGen/LiveRangeEdit.h"
30 #include "llvm/CodeGen/LiveRegMatrix.h"
31 #include "llvm/CodeGen/LiveStackAnalysis.h"
32 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
33 #include "llvm/CodeGen/MachineDominators.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineLoopInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/RegAllocRegistry.h"
38 #include "llvm/CodeGen/RegisterClassInfo.h"
39 #include "llvm/CodeGen/VirtRegMap.h"
40 #include "llvm/PassAnalysisSupport.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/Timer.h"
45 #include "llvm/Support/raw_ostream.h"
50 STATISTIC(NumGlobalSplits, "Number of split global live ranges");
51 STATISTIC(NumLocalSplits, "Number of split local live ranges");
52 STATISTIC(NumEvicted, "Number of interferences evicted");
54 static cl::opt<SplitEditor::ComplementSpillMode>
55 SplitSpillMode("split-spill-mode", cl::Hidden,
56 cl::desc("Spill mode for splitting live ranges"),
57 cl::values(clEnumValN(SplitEditor::SM_Partition, "default", "Default"),
58 clEnumValN(SplitEditor::SM_Size, "size", "Optimize for size"),
59 clEnumValN(SplitEditor::SM_Speed, "speed", "Optimize for speed"),
61 cl::init(SplitEditor::SM_Partition));
63 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
64 createGreedyRegisterAllocator);
67 class RAGreedy : public MachineFunctionPass,
69 private LiveRangeEdit::Delegate {
74 // Shortcuts to some useful interface.
75 const TargetInstrInfo *TII;
76 const TargetRegisterInfo *TRI;
77 RegisterClassInfo RCI;
81 MachineBlockFrequencyInfo *MBFI;
82 MachineDominatorTree *DomTree;
83 MachineLoopInfo *Loops;
85 SpillPlacement *SpillPlacer;
86 LiveDebugVariables *DebugVars;
89 OwningPtr<Spiller> SpillerInstance;
90 std::priority_queue<std::pair<unsigned, unsigned> > Queue;
93 // Live ranges pass through a number of stages as we try to allocate them.
94 // Some of the stages may also create new live ranges:
96 // - Region splitting.
97 // - Per-block splitting.
101 // Ranges produced by one of the stages skip the previous stages when they are
102 // dequeued. This improves performance because we can skip interference checks
103 // that are unlikely to give any results. It also guarantees that the live
104 // range splitting algorithm terminates, something that is otherwise hard to
106 enum LiveRangeStage {
107 /// Newly created live range that has never been queued.
110 /// Only attempt assignment and eviction. Then requeue as RS_Split.
113 /// Attempt live range splitting if assignment is impossible.
116 /// Attempt more aggressive live range splitting that is guaranteed to make
117 /// progress. This is used for split products that may not be making
121 /// Live range will be spilled. No more splitting will be attempted.
124 /// There is nothing more we can do to this live range. Abort compilation
125 /// if it can't be assigned.
130 static const char *const StageName[];
133 // RegInfo - Keep additional information about each live range.
135 LiveRangeStage Stage;
137 // Cascade - Eviction loop prevention. See canEvictInterference().
140 RegInfo() : Stage(RS_New), Cascade(0) {}
143 IndexedMap<RegInfo, VirtReg2IndexFunctor> ExtraRegInfo;
145 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
146 return ExtraRegInfo[VirtReg.reg].Stage;
149 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) {
150 ExtraRegInfo.resize(MRI->getNumVirtRegs());
151 ExtraRegInfo[VirtReg.reg].Stage = Stage;
154 template<typename Iterator>
155 void setStage(Iterator Begin, Iterator End, LiveRangeStage NewStage) {
156 ExtraRegInfo.resize(MRI->getNumVirtRegs());
157 for (;Begin != End; ++Begin) {
158 unsigned Reg = *Begin;
159 if (ExtraRegInfo[Reg].Stage == RS_New)
160 ExtraRegInfo[Reg].Stage = NewStage;
164 /// Cost of evicting interference.
165 struct EvictionCost {
166 unsigned BrokenHints; ///< Total number of broken hints.
167 float MaxWeight; ///< Maximum spill weight evicted.
169 EvictionCost(): BrokenHints(0), MaxWeight(0) {}
171 bool isMax() const { return BrokenHints == ~0u; }
173 void setMax() { BrokenHints = ~0u; }
175 void setBrokenHints(unsigned NHints) { BrokenHints = NHints; }
177 bool operator<(const EvictionCost &O) const {
178 if (BrokenHints != O.BrokenHints)
179 return BrokenHints < O.BrokenHints;
180 return MaxWeight < O.MaxWeight;
185 OwningPtr<SplitAnalysis> SA;
186 OwningPtr<SplitEditor> SE;
188 /// Cached per-block interference maps
189 InterferenceCache IntfCache;
191 /// All basic blocks where the current register has uses.
192 SmallVector<SpillPlacement::BlockConstraint, 8> SplitConstraints;
194 /// Global live range splitting candidate info.
195 struct GlobalSplitCandidate {
196 // Register intended for assignment, or 0.
199 // SplitKit interval index for this candidate.
202 // Interference for PhysReg.
203 InterferenceCache::Cursor Intf;
205 // Bundles where this candidate should be live.
206 BitVector LiveBundles;
207 SmallVector<unsigned, 8> ActiveBlocks;
209 void reset(InterferenceCache &Cache, unsigned Reg) {
212 Intf.setPhysReg(Cache, Reg);
214 ActiveBlocks.clear();
217 // Set B[i] = C for every live bundle where B[i] was NoCand.
218 unsigned getBundles(SmallVectorImpl<unsigned> &B, unsigned C) {
220 for (int i = LiveBundles.find_first(); i >= 0;
221 i = LiveBundles.find_next(i))
222 if (B[i] == NoCand) {
230 /// Candidate info for each PhysReg in AllocationOrder.
231 /// This vector never shrinks, but grows to the size of the largest register
233 SmallVector<GlobalSplitCandidate, 32> GlobalCand;
235 enum LLVM_ENUM_INT_TYPE(unsigned) { NoCand = ~0u };
237 /// Candidate map. Each edge bundle is assigned to a GlobalCand entry, or to
238 /// NoCand which indicates the stack interval.
239 SmallVector<unsigned, 32> BundleCand;
244 /// Return the pass name.
245 virtual const char* getPassName() const {
246 return "Greedy Register Allocator";
249 /// RAGreedy analysis usage.
250 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
251 virtual void releaseMemory();
252 virtual Spiller &spiller() { return *SpillerInstance; }
253 virtual void enqueue(LiveInterval *LI);
254 virtual LiveInterval *dequeue();
255 virtual unsigned selectOrSplit(LiveInterval&,
256 SmallVectorImpl<unsigned>&);
258 /// Perform register allocation.
259 virtual bool runOnMachineFunction(MachineFunction &mf);
264 bool LRE_CanEraseVirtReg(unsigned);
265 void LRE_WillShrinkVirtReg(unsigned);
266 void LRE_DidCloneVirtReg(unsigned, unsigned);
268 BlockFrequency calcSpillCost();
269 bool addSplitConstraints(InterferenceCache::Cursor, BlockFrequency&);
270 void addThroughConstraints(InterferenceCache::Cursor, ArrayRef<unsigned>);
271 void growRegion(GlobalSplitCandidate &Cand);
272 BlockFrequency calcGlobalSplitCost(GlobalSplitCandidate&);
273 bool calcCompactRegion(GlobalSplitCandidate&);
274 void splitAroundRegion(LiveRangeEdit&, ArrayRef<unsigned>);
275 void calcGapWeights(unsigned, SmallVectorImpl<float>&);
276 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
277 bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool);
278 bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&);
279 void evictInterference(LiveInterval&, unsigned,
280 SmallVectorImpl<unsigned>&);
282 unsigned tryAssign(LiveInterval&, AllocationOrder&,
283 SmallVectorImpl<unsigned>&);
284 unsigned tryEvict(LiveInterval&, AllocationOrder&,
285 SmallVectorImpl<unsigned>&, unsigned = ~0u);
286 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
287 SmallVectorImpl<unsigned>&);
288 unsigned tryBlockSplit(LiveInterval&, AllocationOrder&,
289 SmallVectorImpl<unsigned>&);
290 unsigned tryInstructionSplit(LiveInterval&, AllocationOrder&,
291 SmallVectorImpl<unsigned>&);
292 unsigned tryLocalSplit(LiveInterval&, AllocationOrder&,
293 SmallVectorImpl<unsigned>&);
294 unsigned trySplit(LiveInterval&, AllocationOrder&,
295 SmallVectorImpl<unsigned>&);
297 } // end anonymous namespace
299 char RAGreedy::ID = 0;
302 const char *const RAGreedy::StageName[] = {
312 // Hysteresis to use when comparing floats.
313 // This helps stabilize decisions based on float comparisons.
314 const float Hysteresis = 0.98f;
317 FunctionPass* llvm::createGreedyRegisterAllocator() {
318 return new RAGreedy();
321 RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
322 initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
323 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
324 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
325 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
326 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
327 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
328 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
329 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
330 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
331 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
332 initializeLiveRegMatrixPass(*PassRegistry::getPassRegistry());
333 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
334 initializeSpillPlacementPass(*PassRegistry::getPassRegistry());
337 void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
338 AU.setPreservesCFG();
339 AU.addRequired<MachineBlockFrequencyInfo>();
340 AU.addPreserved<MachineBlockFrequencyInfo>();
341 AU.addRequired<AliasAnalysis>();
342 AU.addPreserved<AliasAnalysis>();
343 AU.addRequired<LiveIntervals>();
344 AU.addPreserved<LiveIntervals>();
345 AU.addRequired<SlotIndexes>();
346 AU.addPreserved<SlotIndexes>();
347 AU.addRequired<LiveDebugVariables>();
348 AU.addPreserved<LiveDebugVariables>();
349 AU.addRequired<LiveStacks>();
350 AU.addPreserved<LiveStacks>();
351 AU.addRequired<MachineDominatorTree>();
352 AU.addPreserved<MachineDominatorTree>();
353 AU.addRequired<MachineLoopInfo>();
354 AU.addPreserved<MachineLoopInfo>();
355 AU.addRequired<VirtRegMap>();
356 AU.addPreserved<VirtRegMap>();
357 AU.addRequired<LiveRegMatrix>();
358 AU.addPreserved<LiveRegMatrix>();
359 AU.addRequired<EdgeBundles>();
360 AU.addRequired<SpillPlacement>();
361 MachineFunctionPass::getAnalysisUsage(AU);
365 //===----------------------------------------------------------------------===//
366 // LiveRangeEdit delegate methods
367 //===----------------------------------------------------------------------===//
369 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
370 if (VRM->hasPhys(VirtReg)) {
371 Matrix->unassign(LIS->getInterval(VirtReg));
374 // Unassigned virtreg is probably in the priority queue.
375 // RegAllocBase will erase it after dequeueing.
379 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) {
380 if (!VRM->hasPhys(VirtReg))
383 // Register is assigned, put it back on the queue for reassignment.
384 LiveInterval &LI = LIS->getInterval(VirtReg);
385 Matrix->unassign(LI);
389 void RAGreedy::LRE_DidCloneVirtReg(unsigned New, unsigned Old) {
390 // Cloning a register we haven't even heard about yet? Just ignore it.
391 if (!ExtraRegInfo.inBounds(Old))
394 // LRE may clone a virtual register because dead code elimination causes it to
395 // be split into connected components. The new components are much smaller
396 // than the original, so they should get a new chance at being assigned.
397 // same stage as the parent.
398 ExtraRegInfo[Old].Stage = RS_Assign;
399 ExtraRegInfo.grow(New);
400 ExtraRegInfo[New] = ExtraRegInfo[Old];
403 void RAGreedy::releaseMemory() {
404 SpillerInstance.reset(0);
405 ExtraRegInfo.clear();
409 void RAGreedy::enqueue(LiveInterval *LI) {
410 // Prioritize live ranges by size, assigning larger ranges first.
411 // The queue holds (size, reg) pairs.
412 const unsigned Size = LI->getSize();
413 const unsigned Reg = LI->reg;
414 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
415 "Can only enqueue virtual registers");
418 ExtraRegInfo.grow(Reg);
419 if (ExtraRegInfo[Reg].Stage == RS_New)
420 ExtraRegInfo[Reg].Stage = RS_Assign;
422 if (ExtraRegInfo[Reg].Stage == RS_Split) {
423 // Unsplit ranges that couldn't be allocated immediately are deferred until
424 // everything else has been allocated.
427 if (ExtraRegInfo[Reg].Stage == RS_Assign && !LI->empty() &&
428 LIS->intervalIsInOneMBB(*LI)) {
429 // Allocate original local ranges in linear instruction order. Since they
430 // are singly defined, this produces optimal coloring in the absence of
431 // global interference and other constraints.
432 if (!TRI->reverseLocalAssignment())
433 Prio = LI->beginIndex().getInstrDistance(Indexes->getLastIndex());
435 // Allocating bottom up may allow many short LRGs to be assigned first
436 // to one of the cheap registers. This could be much faster for very
437 // large blocks on targets with many physical registers.
438 Prio = Indexes->getZeroIndex().getInstrDistance(LI->beginIndex());
442 // Allocate global and split ranges in long->short order. Long ranges that
443 // don't fit should be spilled (or split) ASAP so they don't create
444 // interference. Mark a bit to prioritize global above local ranges.
445 Prio = (1u << 29) + Size;
447 // Mark a higher bit to prioritize global and local above RS_Split.
450 // Boost ranges that have a physical register hint.
451 if (VRM->hasKnownPreference(Reg))
454 // The virtual register number is a tie breaker for same-sized ranges.
455 // Give lower vreg numbers higher priority to assign them first.
456 Queue.push(std::make_pair(Prio, ~Reg));
459 LiveInterval *RAGreedy::dequeue() {
462 LiveInterval *LI = &LIS->getInterval(~Queue.top().second);
468 //===----------------------------------------------------------------------===//
470 //===----------------------------------------------------------------------===//
472 /// tryAssign - Try to assign VirtReg to an available register.
473 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg,
474 AllocationOrder &Order,
475 SmallVectorImpl<unsigned> &NewVRegs) {
478 while ((PhysReg = Order.next()))
479 if (!Matrix->checkInterference(VirtReg, PhysReg))
481 if (!PhysReg || Order.isHint())
484 // PhysReg is available, but there may be a better choice.
486 // If we missed a simple hint, try to cheaply evict interference from the
487 // preferred register.
488 if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg))
489 if (Order.isHint(Hint)) {
490 DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n');
491 EvictionCost MaxCost;
492 MaxCost.setBrokenHints(1);
493 if (canEvictInterference(VirtReg, Hint, true, MaxCost)) {
494 evictInterference(VirtReg, Hint, NewVRegs);
499 // Try to evict interference from a cheaper alternative.
500 unsigned Cost = TRI->getCostPerUse(PhysReg);
502 // Most registers have 0 additional cost.
506 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost
508 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
509 return CheapReg ? CheapReg : PhysReg;
513 //===----------------------------------------------------------------------===//
514 // Interference eviction
515 //===----------------------------------------------------------------------===//
517 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) {
518 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
520 while ((PhysReg = Order.next())) {
521 if (PhysReg == PrevReg)
524 MCRegUnitIterator Units(PhysReg, TRI);
525 for (; Units.isValid(); ++Units) {
526 // Instantiate a "subquery", not to be confused with the Queries array.
527 LiveIntervalUnion::Query subQ(&VirtReg, &Matrix->getLiveUnions()[*Units]);
528 if (subQ.checkInterference())
531 // If no units have interference, break out with the current PhysReg.
532 if (!Units.isValid())
536 DEBUG(dbgs() << "can reassign: " << VirtReg << " from "
537 << PrintReg(PrevReg, TRI) << " to " << PrintReg(PhysReg, TRI)
542 /// shouldEvict - determine if A should evict the assigned live range B. The
543 /// eviction policy defined by this function together with the allocation order
544 /// defined by enqueue() decides which registers ultimately end up being split
547 /// Cascade numbers are used to prevent infinite loops if this function is a
550 /// @param A The live range to be assigned.
551 /// @param IsHint True when A is about to be assigned to its preferred
553 /// @param B The live range to be evicted.
554 /// @param BreaksHint True when B is already assigned to its preferred register.
555 bool RAGreedy::shouldEvict(LiveInterval &A, bool IsHint,
556 LiveInterval &B, bool BreaksHint) {
557 bool CanSplit = getStage(B) < RS_Spill;
559 // Be fairly aggressive about following hints as long as the evictee can be
561 if (CanSplit && IsHint && !BreaksHint)
564 if (A.weight > B.weight) {
565 DEBUG(dbgs() << "should evict: " << B << " w= " << B.weight << '\n');
571 /// canEvictInterference - Return true if all interferences between VirtReg and
572 /// PhysReg can be evicted. When OnlyCheap is set, don't do anything
574 /// @param VirtReg Live range that is about to be assigned.
575 /// @param PhysReg Desired register for assignment.
576 /// @param IsHint True when PhysReg is VirtReg's preferred register.
577 /// @param MaxCost Only look for cheaper candidates and update with new cost
578 /// when returning true.
579 /// @returns True when interference can be evicted cheaper than MaxCost.
580 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
581 bool IsHint, EvictionCost &MaxCost) {
582 // It is only possible to evict virtual register interference.
583 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg)
586 bool IsLocal = LIS->intervalIsInOneMBB(VirtReg);
588 // Find VirtReg's cascade number. This will be unassigned if VirtReg was never
589 // involved in an eviction before. If a cascade number was assigned, deny
590 // evicting anything with the same or a newer cascade number. This prevents
591 // infinite eviction loops.
593 // This works out so a register without a cascade number is allowed to evict
594 // anything, and it can be evicted by anything.
595 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
597 Cascade = NextCascade;
600 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
601 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
602 // If there is 10 or more interferences, chances are one is heavier.
603 if (Q.collectInterferingVRegs(10) >= 10)
606 // Check if any interfering live range is heavier than MaxWeight.
607 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
608 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
609 assert(TargetRegisterInfo::isVirtualRegister(Intf->reg) &&
610 "Only expecting virtual register interference from query");
611 // Never evict spill products. They cannot split or spill.
612 if (getStage(*Intf) == RS_Done)
614 // Once a live range becomes small enough, it is urgent that we find a
615 // register for it. This is indicated by an infinite spill weight. These
616 // urgent live ranges get to evict almost anything.
618 // Also allow urgent evictions of unspillable ranges from a strictly
619 // larger allocation order.
620 bool Urgent = !VirtReg.isSpillable() &&
621 (Intf->isSpillable() ||
622 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) <
623 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg)));
624 // Only evict older cascades or live ranges without a cascade.
625 unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;
626 if (Cascade <= IntfCascade) {
629 // We permit breaking cascades for urgent evictions. It should be the
630 // last resort, though, so make it really expensive.
631 Cost.BrokenHints += 10;
633 // Would this break a satisfied hint?
634 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg);
635 // Update eviction cost.
636 Cost.BrokenHints += BreaksHint;
637 Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight);
638 // Abort if this would be too expensive.
639 if (!(Cost < MaxCost))
643 // Apply the eviction policy for non-urgent evictions.
644 if (!shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
646 // If !MaxCost.isMax(), then we're just looking for a cheap register.
647 // Evicting another local live range in this case could lead to suboptimal
649 if (!MaxCost.isMax() && IsLocal && LIS->intervalIsInOneMBB(*Intf) &&
650 !canReassign(*Intf, PhysReg)) {
659 /// evictInterference - Evict any interferring registers that prevent VirtReg
660 /// from being assigned to Physreg. This assumes that canEvictInterference
662 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg,
663 SmallVectorImpl<unsigned> &NewVRegs) {
664 // Make sure that VirtReg has a cascade number, and assign that cascade
665 // number to every evicted register. These live ranges than then only be
666 // evicted by a newer cascade, preventing infinite loops.
667 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
669 Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;
671 DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI)
672 << " interference: Cascade " << Cascade << '\n');
674 // Collect all interfering virtregs first.
675 SmallVector<LiveInterval*, 8> Intfs;
676 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
677 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
678 assert(Q.seenAllInterferences() && "Didn't check all interfererences.");
679 ArrayRef<LiveInterval*> IVR = Q.interferingVRegs();
680 Intfs.append(IVR.begin(), IVR.end());
683 // Evict them second. This will invalidate the queries.
684 for (unsigned i = 0, e = Intfs.size(); i != e; ++i) {
685 LiveInterval *Intf = Intfs[i];
686 // The same VirtReg may be present in multiple RegUnits. Skip duplicates.
687 if (!VRM->hasPhys(Intf->reg))
689 Matrix->unassign(*Intf);
690 assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||
691 VirtReg.isSpillable() < Intf->isSpillable()) &&
692 "Cannot decrease cascade number, illegal eviction");
693 ExtraRegInfo[Intf->reg].Cascade = Cascade;
695 NewVRegs.push_back(Intf->reg);
699 /// tryEvict - Try to evict all interferences for a physreg.
700 /// @param VirtReg Currently unassigned virtual register.
701 /// @param Order Physregs to try.
702 /// @return Physreg to assign VirtReg, or 0.
703 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
704 AllocationOrder &Order,
705 SmallVectorImpl<unsigned> &NewVRegs,
706 unsigned CostPerUseLimit) {
707 NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled);
709 // Keep track of the cheapest interference seen so far.
710 EvictionCost BestCost;
712 unsigned BestPhys = 0;
713 unsigned OrderLimit = Order.getOrder().size();
715 // When we are just looking for a reduced cost per use, don't break any
716 // hints, and only evict smaller spill weights.
717 if (CostPerUseLimit < ~0u) {
718 BestCost.BrokenHints = 0;
719 BestCost.MaxWeight = VirtReg.weight;
721 // Check of any registers in RC are below CostPerUseLimit.
722 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg);
723 unsigned MinCost = RegClassInfo.getMinCost(RC);
724 if (MinCost >= CostPerUseLimit) {
725 DEBUG(dbgs() << RC->getName() << " minimum cost = " << MinCost
726 << ", no cheaper registers to be found.\n");
730 // It is normal for register classes to have a long tail of registers with
731 // the same cost. We don't need to look at them if they're too expensive.
732 if (TRI->getCostPerUse(Order.getOrder().back()) >= CostPerUseLimit) {
733 OrderLimit = RegClassInfo.getLastCostChange(RC);
734 DEBUG(dbgs() << "Only trying the first " << OrderLimit << " regs.\n");
739 while (unsigned PhysReg = Order.next(OrderLimit)) {
740 if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit)
742 // The first use of a callee-saved register in a function has cost 1.
743 // Don't start using a CSR when the CostPerUseLimit is low.
744 if (CostPerUseLimit == 1)
745 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
746 if (!MRI->isPhysRegUsed(CSR)) {
747 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR "
748 << PrintReg(CSR, TRI) << '\n');
752 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost))
758 // Stop if the hint can be used.
766 evictInterference(VirtReg, BestPhys, NewVRegs);
771 //===----------------------------------------------------------------------===//
773 //===----------------------------------------------------------------------===//
775 /// addSplitConstraints - Fill out the SplitConstraints vector based on the
776 /// interference pattern in Physreg and its aliases. Add the constraints to
777 /// SpillPlacement and return the static cost of this split in Cost, assuming
778 /// that all preferences in SplitConstraints are met.
779 /// Return false if there are no bundles with positive bias.
780 bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
781 BlockFrequency &Cost) {
782 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
784 // Reset interference dependent info.
785 SplitConstraints.resize(UseBlocks.size());
786 BlockFrequency StaticCost = 0;
787 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
788 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
789 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
791 BC.Number = BI.MBB->getNumber();
792 Intf.moveToBlock(BC.Number);
793 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
794 BC.Exit = BI.LiveOut ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
795 BC.ChangesValue = BI.FirstDef.isValid();
797 if (!Intf.hasInterference())
800 // Number of spill code instructions to insert.
803 // Interference for the live-in value.
805 if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number))
806 BC.Entry = SpillPlacement::MustSpill, ++Ins;
807 else if (Intf.first() < BI.FirstInstr)
808 BC.Entry = SpillPlacement::PrefSpill, ++Ins;
809 else if (Intf.first() < BI.LastInstr)
813 // Interference for the live-out value.
815 if (Intf.last() >= SA->getLastSplitPoint(BC.Number))
816 BC.Exit = SpillPlacement::MustSpill, ++Ins;
817 else if (Intf.last() > BI.LastInstr)
818 BC.Exit = SpillPlacement::PrefSpill, ++Ins;
819 else if (Intf.last() > BI.FirstInstr)
823 // Accumulate the total frequency of inserted spill code.
825 StaticCost += SpillPlacer->getBlockFrequency(BC.Number);
829 // Add constraints for use-blocks. Note that these are the only constraints
830 // that may add a positive bias, it is downhill from here.
831 SpillPlacer->addConstraints(SplitConstraints);
832 return SpillPlacer->scanActiveBundles();
836 /// addThroughConstraints - Add constraints and links to SpillPlacer from the
837 /// live-through blocks in Blocks.
838 void RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
839 ArrayRef<unsigned> Blocks) {
840 const unsigned GroupSize = 8;
841 SpillPlacement::BlockConstraint BCS[GroupSize];
842 unsigned TBS[GroupSize];
843 unsigned B = 0, T = 0;
845 for (unsigned i = 0; i != Blocks.size(); ++i) {
846 unsigned Number = Blocks[i];
847 Intf.moveToBlock(Number);
849 if (!Intf.hasInterference()) {
850 assert(T < GroupSize && "Array overflow");
852 if (++T == GroupSize) {
853 SpillPlacer->addLinks(makeArrayRef(TBS, T));
859 assert(B < GroupSize && "Array overflow");
860 BCS[B].Number = Number;
862 // Interference for the live-in value.
863 if (Intf.first() <= Indexes->getMBBStartIdx(Number))
864 BCS[B].Entry = SpillPlacement::MustSpill;
866 BCS[B].Entry = SpillPlacement::PrefSpill;
868 // Interference for the live-out value.
869 if (Intf.last() >= SA->getLastSplitPoint(Number))
870 BCS[B].Exit = SpillPlacement::MustSpill;
872 BCS[B].Exit = SpillPlacement::PrefSpill;
874 if (++B == GroupSize) {
875 ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B);
876 SpillPlacer->addConstraints(Array);
881 ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B);
882 SpillPlacer->addConstraints(Array);
883 SpillPlacer->addLinks(makeArrayRef(TBS, T));
886 void RAGreedy::growRegion(GlobalSplitCandidate &Cand) {
887 // Keep track of through blocks that have not been added to SpillPlacer.
888 BitVector Todo = SA->getThroughBlocks();
889 SmallVectorImpl<unsigned> &ActiveBlocks = Cand.ActiveBlocks;
890 unsigned AddedTo = 0;
892 unsigned Visited = 0;
896 ArrayRef<unsigned> NewBundles = SpillPlacer->getRecentPositive();
897 // Find new through blocks in the periphery of PrefRegBundles.
898 for (int i = 0, e = NewBundles.size(); i != e; ++i) {
899 unsigned Bundle = NewBundles[i];
900 // Look at all blocks connected to Bundle in the full graph.
901 ArrayRef<unsigned> Blocks = Bundles->getBlocks(Bundle);
902 for (ArrayRef<unsigned>::iterator I = Blocks.begin(), E = Blocks.end();
905 if (!Todo.test(Block))
908 // This is a new through block. Add it to SpillPlacer later.
909 ActiveBlocks.push_back(Block);
915 // Any new blocks to add?
916 if (ActiveBlocks.size() == AddedTo)
919 // Compute through constraints from the interference, or assume that all
920 // through blocks prefer spilling when forming compact regions.
921 ArrayRef<unsigned> NewBlocks = makeArrayRef(ActiveBlocks).slice(AddedTo);
923 addThroughConstraints(Cand.Intf, NewBlocks);
925 // Provide a strong negative bias on through blocks to prevent unwanted
926 // liveness on loop backedges.
927 SpillPlacer->addPrefSpill(NewBlocks, /* Strong= */ true);
928 AddedTo = ActiveBlocks.size();
930 // Perhaps iterating can enable more bundles?
931 SpillPlacer->iterate();
933 DEBUG(dbgs() << ", v=" << Visited);
936 /// calcCompactRegion - Compute the set of edge bundles that should be live
937 /// when splitting the current live range into compact regions. Compact
938 /// regions can be computed without looking at interference. They are the
939 /// regions formed by removing all the live-through blocks from the live range.
941 /// Returns false if the current live range is already compact, or if the
942 /// compact regions would form single block regions anyway.
943 bool RAGreedy::calcCompactRegion(GlobalSplitCandidate &Cand) {
944 // Without any through blocks, the live range is already compact.
945 if (!SA->getNumThroughBlocks())
948 // Compact regions don't correspond to any physreg.
949 Cand.reset(IntfCache, 0);
951 DEBUG(dbgs() << "Compact region bundles");
953 // Use the spill placer to determine the live bundles. GrowRegion pretends
954 // that all the through blocks have interference when PhysReg is unset.
955 SpillPlacer->prepare(Cand.LiveBundles);
957 // The static split cost will be zero since Cand.Intf reports no interference.
959 if (!addSplitConstraints(Cand.Intf, Cost)) {
960 DEBUG(dbgs() << ", none.\n");
965 SpillPlacer->finish();
967 if (!Cand.LiveBundles.any()) {
968 DEBUG(dbgs() << ", none.\n");
973 for (int i = Cand.LiveBundles.find_first(); i>=0;
974 i = Cand.LiveBundles.find_next(i))
975 dbgs() << " EB#" << i;
981 /// calcSpillCost - Compute how expensive it would be to split the live range in
982 /// SA around all use blocks instead of forming bundle regions.
983 BlockFrequency RAGreedy::calcSpillCost() {
984 BlockFrequency Cost = 0;
985 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
986 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
987 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
988 unsigned Number = BI.MBB->getNumber();
989 // We normally only need one spill instruction - a load or a store.
990 Cost += SpillPlacer->getBlockFrequency(Number);
992 // Unless the value is redefined in the block.
993 if (BI.LiveIn && BI.LiveOut && BI.FirstDef)
994 Cost += SpillPlacer->getBlockFrequency(Number);
999 /// calcGlobalSplitCost - Return the global split cost of following the split
1000 /// pattern in LiveBundles. This cost should be added to the local cost of the
1001 /// interference pattern in SplitConstraints.
1003 BlockFrequency RAGreedy::calcGlobalSplitCost(GlobalSplitCandidate &Cand) {
1004 BlockFrequency GlobalCost = 0;
1005 const BitVector &LiveBundles = Cand.LiveBundles;
1006 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1007 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1008 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1009 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
1010 bool RegIn = LiveBundles[Bundles->getBundle(BC.Number, 0)];
1011 bool RegOut = LiveBundles[Bundles->getBundle(BC.Number, 1)];
1015 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg);
1017 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg);
1019 GlobalCost += SpillPlacer->getBlockFrequency(BC.Number);
1022 for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) {
1023 unsigned Number = Cand.ActiveBlocks[i];
1024 bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)];
1025 bool RegOut = LiveBundles[Bundles->getBundle(Number, 1)];
1026 if (!RegIn && !RegOut)
1028 if (RegIn && RegOut) {
1029 // We need double spill code if this block has interference.
1030 Cand.Intf.moveToBlock(Number);
1031 if (Cand.Intf.hasInterference()) {
1032 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1033 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1037 // live-in / stack-out or stack-in live-out.
1038 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1043 /// splitAroundRegion - Split the current live range around the regions
1044 /// determined by BundleCand and GlobalCand.
1046 /// Before calling this function, GlobalCand and BundleCand must be initialized
1047 /// so each bundle is assigned to a valid candidate, or NoCand for the
1048 /// stack-bound bundles. The shared SA/SE SplitAnalysis and SplitEditor
1049 /// objects must be initialized for the current live range, and intervals
1050 /// created for the used candidates.
1052 /// @param LREdit The LiveRangeEdit object handling the current split.
1053 /// @param UsedCands List of used GlobalCand entries. Every BundleCand value
1054 /// must appear in this list.
1055 void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit,
1056 ArrayRef<unsigned> UsedCands) {
1057 // These are the intervals created for new global ranges. We may create more
1058 // intervals for local ranges.
1059 const unsigned NumGlobalIntvs = LREdit.size();
1060 DEBUG(dbgs() << "splitAroundRegion with " << NumGlobalIntvs << " globals.\n");
1061 assert(NumGlobalIntvs && "No global intervals configured");
1063 // Isolate even single instructions when dealing with a proper sub-class.
1064 // That guarantees register class inflation for the stack interval because it
1066 unsigned Reg = SA->getParent().reg;
1067 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1069 // First handle all the blocks with uses.
1070 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1071 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1072 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1073 unsigned Number = BI.MBB->getNumber();
1074 unsigned IntvIn = 0, IntvOut = 0;
1075 SlotIndex IntfIn, IntfOut;
1077 unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)];
1078 if (CandIn != NoCand) {
1079 GlobalSplitCandidate &Cand = GlobalCand[CandIn];
1080 IntvIn = Cand.IntvIdx;
1081 Cand.Intf.moveToBlock(Number);
1082 IntfIn = Cand.Intf.first();
1086 unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)];
1087 if (CandOut != NoCand) {
1088 GlobalSplitCandidate &Cand = GlobalCand[CandOut];
1089 IntvOut = Cand.IntvIdx;
1090 Cand.Intf.moveToBlock(Number);
1091 IntfOut = Cand.Intf.last();
1095 // Create separate intervals for isolated blocks with multiple uses.
1096 if (!IntvIn && !IntvOut) {
1097 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n");
1098 if (SA->shouldSplitSingleBlock(BI, SingleInstrs))
1099 SE->splitSingleBlock(BI);
1103 if (IntvIn && IntvOut)
1104 SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut);
1106 SE->splitRegInBlock(BI, IntvIn, IntfIn);
1108 SE->splitRegOutBlock(BI, IntvOut, IntfOut);
1111 // Handle live-through blocks. The relevant live-through blocks are stored in
1112 // the ActiveBlocks list with each candidate. We need to filter out
1114 BitVector Todo = SA->getThroughBlocks();
1115 for (unsigned c = 0; c != UsedCands.size(); ++c) {
1116 ArrayRef<unsigned> Blocks = GlobalCand[UsedCands[c]].ActiveBlocks;
1117 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
1118 unsigned Number = Blocks[i];
1119 if (!Todo.test(Number))
1123 unsigned IntvIn = 0, IntvOut = 0;
1124 SlotIndex IntfIn, IntfOut;
1126 unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)];
1127 if (CandIn != NoCand) {
1128 GlobalSplitCandidate &Cand = GlobalCand[CandIn];
1129 IntvIn = Cand.IntvIdx;
1130 Cand.Intf.moveToBlock(Number);
1131 IntfIn = Cand.Intf.first();
1134 unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)];
1135 if (CandOut != NoCand) {
1136 GlobalSplitCandidate &Cand = GlobalCand[CandOut];
1137 IntvOut = Cand.IntvIdx;
1138 Cand.Intf.moveToBlock(Number);
1139 IntfOut = Cand.Intf.last();
1141 if (!IntvIn && !IntvOut)
1143 SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut);
1149 SmallVector<unsigned, 8> IntvMap;
1150 SE->finish(&IntvMap);
1151 DebugVars->splitRegister(Reg, LREdit.regs(), *LIS);
1153 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1154 unsigned OrigBlocks = SA->getNumLiveBlocks();
1156 // Sort out the new intervals created by splitting. We get four kinds:
1157 // - Remainder intervals should not be split again.
1158 // - Candidate intervals can be assigned to Cand.PhysReg.
1159 // - Block-local splits are candidates for local splitting.
1160 // - DCE leftovers should go back on the queue.
1161 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) {
1162 LiveInterval &Reg = LIS->getInterval(LREdit.get(i));
1164 // Ignore old intervals from DCE.
1165 if (getStage(Reg) != RS_New)
1168 // Remainder interval. Don't try splitting again, spill if it doesn't
1170 if (IntvMap[i] == 0) {
1171 setStage(Reg, RS_Spill);
1175 // Global intervals. Allow repeated splitting as long as the number of live
1176 // blocks is strictly decreasing.
1177 if (IntvMap[i] < NumGlobalIntvs) {
1178 if (SA->countLiveBlocks(&Reg) >= OrigBlocks) {
1179 DEBUG(dbgs() << "Main interval covers the same " << OrigBlocks
1180 << " blocks as original.\n");
1181 // Don't allow repeated splitting as a safe guard against looping.
1182 setStage(Reg, RS_Split2);
1187 // Other intervals are treated as new. This includes local intervals created
1188 // for blocks with multiple uses, and anything created by DCE.
1192 MF->verify(this, "After splitting live range around region");
1195 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1196 SmallVectorImpl<unsigned> &NewVRegs) {
1197 unsigned NumCands = 0;
1198 unsigned BestCand = NoCand;
1199 BlockFrequency BestCost;
1200 SmallVector<unsigned, 8> UsedCands;
1202 // Check if we can split this live range around a compact region.
1203 bool HasCompact = calcCompactRegion(GlobalCand.front());
1205 // Yes, keep GlobalCand[0] as the compact region candidate.
1207 BestCost = BlockFrequency::getMaxFrequency();
1209 // No benefit from the compact region, our fallback will be per-block
1210 // splitting. Make sure we find a solution that is cheaper than spilling.
1211 BestCost = calcSpillCost();
1212 DEBUG(dbgs() << "Cost of isolating all blocks = ";
1213 MBFI->printBlockFreq(dbgs(), BestCost) << '\n');
1217 while (unsigned PhysReg = Order.next()) {
1218 // Discard bad candidates before we run out of interference cache cursors.
1219 // This will only affect register classes with a lot of registers (>32).
1220 if (NumCands == IntfCache.getMaxCursors()) {
1221 unsigned WorstCount = ~0u;
1223 for (unsigned i = 0; i != NumCands; ++i) {
1224 if (i == BestCand || !GlobalCand[i].PhysReg)
1226 unsigned Count = GlobalCand[i].LiveBundles.count();
1227 if (Count < WorstCount)
1228 Worst = i, WorstCount = Count;
1231 GlobalCand[Worst] = GlobalCand[NumCands];
1232 if (BestCand == NumCands)
1236 if (GlobalCand.size() <= NumCands)
1237 GlobalCand.resize(NumCands+1);
1238 GlobalSplitCandidate &Cand = GlobalCand[NumCands];
1239 Cand.reset(IntfCache, PhysReg);
1241 SpillPlacer->prepare(Cand.LiveBundles);
1242 BlockFrequency Cost;
1243 if (!addSplitConstraints(Cand.Intf, Cost)) {
1244 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n");
1247 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = ";
1248 MBFI->printBlockFreq(dbgs(), Cost));
1249 if (Cost >= BestCost) {
1251 if (BestCand == NoCand)
1252 dbgs() << " worse than no bundles\n";
1254 dbgs() << " worse than "
1255 << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
1261 SpillPlacer->finish();
1263 // No live bundles, defer to splitSingleBlocks().
1264 if (!Cand.LiveBundles.any()) {
1265 DEBUG(dbgs() << " no bundles.\n");
1269 Cost += calcGlobalSplitCost(Cand);
1271 dbgs() << ", total = "; MBFI->printBlockFreq(dbgs(), Cost)
1273 for (int i = Cand.LiveBundles.find_first(); i>=0;
1274 i = Cand.LiveBundles.find_next(i))
1275 dbgs() << " EB#" << i;
1278 if (Cost < BestCost) {
1279 BestCand = NumCands;
1285 // No solutions found, fall back to single block splitting.
1286 if (!HasCompact && BestCand == NoCand)
1289 // Prepare split editor.
1290 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1291 SE->reset(LREdit, SplitSpillMode);
1293 // Assign all edge bundles to the preferred candidate, or NoCand.
1294 BundleCand.assign(Bundles->getNumBundles(), NoCand);
1296 // Assign bundles for the best candidate region.
1297 if (BestCand != NoCand) {
1298 GlobalSplitCandidate &Cand = GlobalCand[BestCand];
1299 if (unsigned B = Cand.getBundles(BundleCand, BestCand)) {
1300 UsedCands.push_back(BestCand);
1301 Cand.IntvIdx = SE->openIntv();
1302 DEBUG(dbgs() << "Split for " << PrintReg(Cand.PhysReg, TRI) << " in "
1303 << B << " bundles, intv " << Cand.IntvIdx << ".\n");
1308 // Assign bundles for the compact region.
1310 GlobalSplitCandidate &Cand = GlobalCand.front();
1311 assert(!Cand.PhysReg && "Compact region has no physreg");
1312 if (unsigned B = Cand.getBundles(BundleCand, 0)) {
1313 UsedCands.push_back(0);
1314 Cand.IntvIdx = SE->openIntv();
1315 DEBUG(dbgs() << "Split for compact region in " << B << " bundles, intv "
1316 << Cand.IntvIdx << ".\n");
1321 splitAroundRegion(LREdit, UsedCands);
1326 //===----------------------------------------------------------------------===//
1327 // Per-Block Splitting
1328 //===----------------------------------------------------------------------===//
1330 /// tryBlockSplit - Split a global live range around every block with uses. This
1331 /// creates a lot of local live ranges, that will be split by tryLocalSplit if
1332 /// they don't allocate.
1333 unsigned RAGreedy::tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1334 SmallVectorImpl<unsigned> &NewVRegs) {
1335 assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed");
1336 unsigned Reg = VirtReg.reg;
1337 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1338 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1339 SE->reset(LREdit, SplitSpillMode);
1340 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1341 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1342 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1343 if (SA->shouldSplitSingleBlock(BI, SingleInstrs))
1344 SE->splitSingleBlock(BI);
1346 // No blocks were split.
1350 // We did split for some blocks.
1351 SmallVector<unsigned, 8> IntvMap;
1352 SE->finish(&IntvMap);
1354 // Tell LiveDebugVariables about the new ranges.
1355 DebugVars->splitRegister(Reg, LREdit.regs(), *LIS);
1357 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1359 // Sort out the new intervals created by splitting. The remainder interval
1360 // goes straight to spilling, the new local ranges get to stay RS_New.
1361 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) {
1362 LiveInterval &LI = LIS->getInterval(LREdit.get(i));
1363 if (getStage(LI) == RS_New && IntvMap[i] == 0)
1364 setStage(LI, RS_Spill);
1368 MF->verify(this, "After splitting live range around basic blocks");
1373 //===----------------------------------------------------------------------===//
1374 // Per-Instruction Splitting
1375 //===----------------------------------------------------------------------===//
1377 /// Get the number of allocatable registers that match the constraints of \p Reg
1378 /// on \p MI and that are also in \p SuperRC.
1379 static unsigned getNumAllocatableRegsForConstraints(
1380 const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC,
1381 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1382 const RegisterClassInfo &RCI) {
1383 assert(SuperRC && "Invalid register class");
1385 const TargetRegisterClass *ConstrainedRC =
1386 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI,
1387 /* ExploreBundle */ true);
1390 return RCI.getNumAllocatableRegs(ConstrainedRC);
1393 /// tryInstructionSplit - Split a live range around individual instructions.
1394 /// This is normally not worthwhile since the spiller is doing essentially the
1395 /// same thing. However, when the live range is in a constrained register
1396 /// class, it may help to insert copies such that parts of the live range can
1397 /// be moved to a larger register class.
1399 /// This is similar to spilling to a larger register class.
1401 RAGreedy::tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1402 SmallVectorImpl<unsigned> &NewVRegs) {
1403 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg);
1404 // There is no point to this if there are no larger sub-classes.
1405 if (!RegClassInfo.isProperSubClass(CurRC))
1408 // Always enable split spill mode, since we're effectively spilling to a
1410 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1411 SE->reset(LREdit, SplitEditor::SM_Size);
1413 ArrayRef<SlotIndex> Uses = SA->getUseSlots();
1414 if (Uses.size() <= 1)
1417 DEBUG(dbgs() << "Split around " << Uses.size() << " individual instrs.\n");
1419 const TargetRegisterClass *SuperRC = TRI->getLargestLegalSuperClass(CurRC);
1420 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC);
1421 // Split around every non-copy instruction if this split will relax
1422 // the constraints on the virtual register.
1423 // Otherwise, splitting just inserts uncoalescable copies that do not help
1425 for (unsigned i = 0; i != Uses.size(); ++i) {
1426 if (const MachineInstr *MI = Indexes->getInstructionFromIndex(Uses[i]))
1427 if (MI->isFullCopy() ||
1428 SuperRCNumAllocatableRegs ==
1429 getNumAllocatableRegsForConstraints(MI, VirtReg.reg, SuperRC, TII,
1431 DEBUG(dbgs() << " skip:\t" << Uses[i] << '\t' << *MI);
1435 SlotIndex SegStart = SE->enterIntvBefore(Uses[i]);
1436 SlotIndex SegStop = SE->leaveIntvAfter(Uses[i]);
1437 SE->useIntv(SegStart, SegStop);
1440 if (LREdit.empty()) {
1441 DEBUG(dbgs() << "All uses were copies.\n");
1445 SmallVector<unsigned, 8> IntvMap;
1446 SE->finish(&IntvMap);
1447 DebugVars->splitRegister(VirtReg.reg, LREdit.regs(), *LIS);
1448 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1450 // Assign all new registers to RS_Spill. This was the last chance.
1451 setStage(LREdit.begin(), LREdit.end(), RS_Spill);
1456 //===----------------------------------------------------------------------===//
1458 //===----------------------------------------------------------------------===//
1461 /// calcGapWeights - Compute the maximum spill weight that needs to be evicted
1462 /// in order to use PhysReg between two entries in SA->UseSlots.
1464 /// GapWeight[i] represents the gap between UseSlots[i] and UseSlots[i+1].
1466 void RAGreedy::calcGapWeights(unsigned PhysReg,
1467 SmallVectorImpl<float> &GapWeight) {
1468 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
1469 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
1470 ArrayRef<SlotIndex> Uses = SA->getUseSlots();
1471 const unsigned NumGaps = Uses.size()-1;
1473 // Start and end points for the interference check.
1474 SlotIndex StartIdx =
1475 BI.LiveIn ? BI.FirstInstr.getBaseIndex() : BI.FirstInstr;
1477 BI.LiveOut ? BI.LastInstr.getBoundaryIndex() : BI.LastInstr;
1479 GapWeight.assign(NumGaps, 0.0f);
1481 // Add interference from each overlapping register.
1482 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1483 if (!Matrix->query(const_cast<LiveInterval&>(SA->getParent()), *Units)
1484 .checkInterference())
1487 // We know that VirtReg is a continuous interval from FirstInstr to
1488 // LastInstr, so we don't need InterferenceQuery.
1490 // Interference that overlaps an instruction is counted in both gaps
1491 // surrounding the instruction. The exception is interference before
1492 // StartIdx and after StopIdx.
1494 LiveIntervalUnion::SegmentIter IntI =
1495 Matrix->getLiveUnions()[*Units] .find(StartIdx);
1496 for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) {
1497 // Skip the gaps before IntI.
1498 while (Uses[Gap+1].getBoundaryIndex() < IntI.start())
1499 if (++Gap == NumGaps)
1504 // Update the gaps covered by IntI.
1505 const float weight = IntI.value()->weight;
1506 for (; Gap != NumGaps; ++Gap) {
1507 GapWeight[Gap] = std::max(GapWeight[Gap], weight);
1508 if (Uses[Gap+1].getBaseIndex() >= IntI.stop())
1516 // Add fixed interference.
1517 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1518 const LiveRange &LR = LIS->getRegUnit(*Units);
1519 LiveRange::const_iterator I = LR.find(StartIdx);
1520 LiveRange::const_iterator E = LR.end();
1522 // Same loop as above. Mark any overlapped gaps as HUGE_VALF.
1523 for (unsigned Gap = 0; I != E && I->start < StopIdx; ++I) {
1524 while (Uses[Gap+1].getBoundaryIndex() < I->start)
1525 if (++Gap == NumGaps)
1530 for (; Gap != NumGaps; ++Gap) {
1531 GapWeight[Gap] = llvm::huge_valf;
1532 if (Uses[Gap+1].getBaseIndex() >= I->end)
1541 /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
1544 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1545 SmallVectorImpl<unsigned> &NewVRegs) {
1546 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
1547 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
1549 // Note that it is possible to have an interval that is live-in or live-out
1550 // while only covering a single block - A phi-def can use undef values from
1551 // predecessors, and the block could be a single-block loop.
1552 // We don't bother doing anything clever about such a case, we simply assume
1553 // that the interval is continuous from FirstInstr to LastInstr. We should
1554 // make sure that we don't do anything illegal to such an interval, though.
1556 ArrayRef<SlotIndex> Uses = SA->getUseSlots();
1557 if (Uses.size() <= 2)
1559 const unsigned NumGaps = Uses.size()-1;
1562 dbgs() << "tryLocalSplit: ";
1563 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
1564 dbgs() << ' ' << Uses[i];
1568 // If VirtReg is live across any register mask operands, compute a list of
1569 // gaps with register masks.
1570 SmallVector<unsigned, 8> RegMaskGaps;
1571 if (Matrix->checkRegMaskInterference(VirtReg)) {
1572 // Get regmask slots for the whole block.
1573 ArrayRef<SlotIndex> RMS = LIS->getRegMaskSlotsInBlock(BI.MBB->getNumber());
1574 DEBUG(dbgs() << RMS.size() << " regmasks in block:");
1575 // Constrain to VirtReg's live range.
1576 unsigned ri = std::lower_bound(RMS.begin(), RMS.end(),
1577 Uses.front().getRegSlot()) - RMS.begin();
1578 unsigned re = RMS.size();
1579 for (unsigned i = 0; i != NumGaps && ri != re; ++i) {
1580 // Look for Uses[i] <= RMS <= Uses[i+1].
1581 assert(!SlotIndex::isEarlierInstr(RMS[ri], Uses[i]));
1582 if (SlotIndex::isEarlierInstr(Uses[i+1], RMS[ri]))
1584 // Skip a regmask on the same instruction as the last use. It doesn't
1585 // overlap the live range.
1586 if (SlotIndex::isSameInstr(Uses[i+1], RMS[ri]) && i+1 == NumGaps)
1588 DEBUG(dbgs() << ' ' << RMS[ri] << ':' << Uses[i] << '-' << Uses[i+1]);
1589 RegMaskGaps.push_back(i);
1590 // Advance ri to the next gap. A regmask on one of the uses counts in
1592 while (ri != re && SlotIndex::isEarlierInstr(RMS[ri], Uses[i+1]))
1595 DEBUG(dbgs() << '\n');
1598 // Since we allow local split results to be split again, there is a risk of
1599 // creating infinite loops. It is tempting to require that the new live
1600 // ranges have less instructions than the original. That would guarantee
1601 // convergence, but it is too strict. A live range with 3 instructions can be
1602 // split 2+3 (including the COPY), and we want to allow that.
1604 // Instead we use these rules:
1606 // 1. Allow any split for ranges with getStage() < RS_Split2. (Except for the
1607 // noop split, of course).
1608 // 2. Require progress be made for ranges with getStage() == RS_Split2. All
1609 // the new ranges must have fewer instructions than before the split.
1610 // 3. New ranges with the same number of instructions are marked RS_Split2,
1611 // smaller ranges are marked RS_New.
1613 // These rules allow a 3 -> 2+3 split once, which we need. They also prevent
1614 // excessive splitting and infinite loops.
1616 bool ProgressRequired = getStage(VirtReg) >= RS_Split2;
1618 // Best split candidate.
1619 unsigned BestBefore = NumGaps;
1620 unsigned BestAfter = 0;
1623 const float blockFreq =
1624 SpillPlacer->getBlockFrequency(BI.MBB->getNumber()).getFrequency() *
1625 (1.0f / MBFI->getEntryFreq());
1626 SmallVector<float, 8> GapWeight;
1629 while (unsigned PhysReg = Order.next()) {
1630 // Keep track of the largest spill weight that would need to be evicted in
1631 // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1].
1632 calcGapWeights(PhysReg, GapWeight);
1634 // Remove any gaps with regmask clobbers.
1635 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg))
1636 for (unsigned i = 0, e = RegMaskGaps.size(); i != e; ++i)
1637 GapWeight[RegMaskGaps[i]] = llvm::huge_valf;
1639 // Try to find the best sequence of gaps to close.
1640 // The new spill weight must be larger than any gap interference.
1642 // We will split before Uses[SplitBefore] and after Uses[SplitAfter].
1643 unsigned SplitBefore = 0, SplitAfter = 1;
1645 // MaxGap should always be max(GapWeight[SplitBefore..SplitAfter-1]).
1646 // It is the spill weight that needs to be evicted.
1647 float MaxGap = GapWeight[0];
1650 // Live before/after split?
1651 const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
1652 const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut;
1654 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' '
1655 << Uses[SplitBefore] << '-' << Uses[SplitAfter]
1656 << " i=" << MaxGap);
1658 // Stop before the interval gets so big we wouldn't be making progress.
1659 if (!LiveBefore && !LiveAfter) {
1660 DEBUG(dbgs() << " all\n");
1663 // Should the interval be extended or shrunk?
1666 // How many gaps would the new range have?
1667 unsigned NewGaps = LiveBefore + SplitAfter - SplitBefore + LiveAfter;
1669 // Legally, without causing looping?
1670 bool Legal = !ProgressRequired || NewGaps < NumGaps;
1672 if (Legal && MaxGap < llvm::huge_valf) {
1673 // Estimate the new spill weight. Each instruction reads or writes the
1674 // register. Conservatively assume there are no read-modify-write
1677 // Try to guess the size of the new interval.
1678 const float EstWeight = normalizeSpillWeight(blockFreq * (NewGaps + 1),
1679 Uses[SplitBefore].distance(Uses[SplitAfter]) +
1680 (LiveBefore + LiveAfter)*SlotIndex::InstrDist);
1681 // Would this split be possible to allocate?
1682 // Never allocate all gaps, we wouldn't be making progress.
1683 DEBUG(dbgs() << " w=" << EstWeight);
1684 if (EstWeight * Hysteresis >= MaxGap) {
1686 float Diff = EstWeight - MaxGap;
1687 if (Diff > BestDiff) {
1688 DEBUG(dbgs() << " (best)");
1689 BestDiff = Hysteresis * Diff;
1690 BestBefore = SplitBefore;
1691 BestAfter = SplitAfter;
1698 if (++SplitBefore < SplitAfter) {
1699 DEBUG(dbgs() << " shrink\n");
1700 // Recompute the max when necessary.
1701 if (GapWeight[SplitBefore - 1] >= MaxGap) {
1702 MaxGap = GapWeight[SplitBefore];
1703 for (unsigned i = SplitBefore + 1; i != SplitAfter; ++i)
1704 MaxGap = std::max(MaxGap, GapWeight[i]);
1711 // Try to extend the interval.
1712 if (SplitAfter >= NumGaps) {
1713 DEBUG(dbgs() << " end\n");
1717 DEBUG(dbgs() << " extend\n");
1718 MaxGap = std::max(MaxGap, GapWeight[SplitAfter++]);
1722 // Didn't find any candidates?
1723 if (BestBefore == NumGaps)
1726 DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore]
1727 << '-' << Uses[BestAfter] << ", " << BestDiff
1728 << ", " << (BestAfter - BestBefore + 1) << " instrs\n");
1730 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1734 SlotIndex SegStart = SE->enterIntvBefore(Uses[BestBefore]);
1735 SlotIndex SegStop = SE->leaveIntvAfter(Uses[BestAfter]);
1736 SE->useIntv(SegStart, SegStop);
1737 SmallVector<unsigned, 8> IntvMap;
1738 SE->finish(&IntvMap);
1739 DebugVars->splitRegister(VirtReg.reg, LREdit.regs(), *LIS);
1741 // If the new range has the same number of instructions as before, mark it as
1742 // RS_Split2 so the next split will be forced to make progress. Otherwise,
1743 // leave the new intervals as RS_New so they can compete.
1744 bool LiveBefore = BestBefore != 0 || BI.LiveIn;
1745 bool LiveAfter = BestAfter != NumGaps || BI.LiveOut;
1746 unsigned NewGaps = LiveBefore + BestAfter - BestBefore + LiveAfter;
1747 if (NewGaps >= NumGaps) {
1748 DEBUG(dbgs() << "Tagging non-progress ranges: ");
1749 assert(!ProgressRequired && "Didn't make progress when it was required.");
1750 for (unsigned i = 0, e = IntvMap.size(); i != e; ++i)
1751 if (IntvMap[i] == 1) {
1752 setStage(LIS->getInterval(LREdit.get(i)), RS_Split2);
1753 DEBUG(dbgs() << PrintReg(LREdit.get(i)));
1755 DEBUG(dbgs() << '\n');
1762 //===----------------------------------------------------------------------===//
1763 // Live Range Splitting
1764 //===----------------------------------------------------------------------===//
1766 /// trySplit - Try to split VirtReg or one of its interferences, making it
1768 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
1769 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
1770 SmallVectorImpl<unsigned>&NewVRegs) {
1771 // Ranges must be Split2 or less.
1772 if (getStage(VirtReg) >= RS_Spill)
1775 // Local intervals are handled separately.
1776 if (LIS->intervalIsInOneMBB(VirtReg)) {
1777 NamedRegionTimer T("Local Splitting", TimerGroupName, TimePassesIsEnabled);
1778 SA->analyze(&VirtReg);
1779 unsigned PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs);
1780 if (PhysReg || !NewVRegs.empty())
1782 return tryInstructionSplit(VirtReg, Order, NewVRegs);
1785 NamedRegionTimer T("Global Splitting", TimerGroupName, TimePassesIsEnabled);
1787 SA->analyze(&VirtReg);
1789 // FIXME: SplitAnalysis may repair broken live ranges coming from the
1790 // coalescer. That may cause the range to become allocatable which means that
1791 // tryRegionSplit won't be making progress. This check should be replaced with
1792 // an assertion when the coalescer is fixed.
1793 if (SA->didRepairRange()) {
1794 // VirtReg has changed, so all cached queries are invalid.
1795 Matrix->invalidateVirtRegs();
1796 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
1800 // First try to split around a region spanning multiple blocks. RS_Split2
1801 // ranges already made dubious progress with region splitting, so they go
1802 // straight to single block splitting.
1803 if (getStage(VirtReg) < RS_Split2) {
1804 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1805 if (PhysReg || !NewVRegs.empty())
1809 // Then isolate blocks.
1810 return tryBlockSplit(VirtReg, Order, NewVRegs);
1814 //===----------------------------------------------------------------------===//
1816 //===----------------------------------------------------------------------===//
1818 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
1819 SmallVectorImpl<unsigned> &NewVRegs) {
1820 // First try assigning a free register.
1821 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
1822 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
1825 LiveRangeStage Stage = getStage(VirtReg);
1826 DEBUG(dbgs() << StageName[Stage]
1827 << " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n');
1829 // Try to evict a less worthy live range, but only for ranges from the primary
1830 // queue. The RS_Split ranges already failed to do this, and they should not
1831 // get a second chance until they have been split.
1832 if (Stage != RS_Split)
1833 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs))
1836 assert(NewVRegs.empty() && "Cannot append to existing NewVRegs");
1838 // The first time we see a live range, don't try to split or spill.
1839 // Wait until the second time, when all smaller ranges have been allocated.
1840 // This gives a better picture of the interference to split around.
1841 if (Stage < RS_Split) {
1842 setStage(VirtReg, RS_Split);
1843 DEBUG(dbgs() << "wait for second round\n");
1844 NewVRegs.push_back(VirtReg.reg);
1848 // If we couldn't allocate a register from spilling, there is probably some
1849 // invalid inline assembly. The base class wil report it.
1850 if (Stage >= RS_Done || !VirtReg.isSpillable())
1853 // Try splitting VirtReg or interferences.
1854 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
1855 if (PhysReg || !NewVRegs.empty())
1858 // Finally spill VirtReg itself.
1859 NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
1860 LiveRangeEdit LRE(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1861 spiller().spill(LRE);
1862 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Done);
1865 MF->verify(this, "After spilling");
1867 // The live virtual register requesting allocation was spilled, so tell
1868 // the caller not to allocate anything during this round.
1872 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
1873 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
1874 << "********** Function: " << mf.getName() << '\n');
1877 TRI = MF->getTarget().getRegisterInfo();
1878 TII = MF->getTarget().getInstrInfo();
1879 RCI.runOnMachineFunction(mf);
1881 MF->verify(this, "Before greedy register allocator");
1883 RegAllocBase::init(getAnalysis<VirtRegMap>(),
1884 getAnalysis<LiveIntervals>(),
1885 getAnalysis<LiveRegMatrix>());
1886 Indexes = &getAnalysis<SlotIndexes>();
1887 MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
1888 DomTree = &getAnalysis<MachineDominatorTree>();
1889 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
1890 Loops = &getAnalysis<MachineLoopInfo>();
1891 Bundles = &getAnalysis<EdgeBundles>();
1892 SpillPlacer = &getAnalysis<SpillPlacement>();
1893 DebugVars = &getAnalysis<LiveDebugVariables>();
1895 calculateSpillWeightsAndHints(*LIS, mf, *Loops, *MBFI);
1899 SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops));
1900 SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree, *MBFI));
1901 ExtraRegInfo.clear();
1902 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1904 IntfCache.init(MF, Matrix->getLiveUnions(), Indexes, LIS, TRI);
1905 GlobalCand.resize(32); // This will grow as needed.