1 //===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RAGreedy function pass for register allocation in
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "AllocationOrder.h"
17 #include "LiveIntervalUnion.h"
18 #include "LiveRangeEdit.h"
19 #include "RegAllocBase.h"
21 #include "SpillPlacement.h"
23 #include "VirtRegMap.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/Function.h"
27 #include "llvm/PassAnalysisSupport.h"
28 #include "llvm/CodeGen/CalcSpillWeights.h"
29 #include "llvm/CodeGen/EdgeBundles.h"
30 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
31 #include "llvm/CodeGen/LiveStackAnalysis.h"
32 #include "llvm/CodeGen/MachineDominators.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineLoopInfo.h"
35 #include "llvm/CodeGen/MachineLoopRanges.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/CodeGen/RegAllocRegistry.h"
39 #include "llvm/CodeGen/RegisterCoalescer.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/raw_ostream.h"
44 #include "llvm/Support/Timer.h"
50 STATISTIC(NumGlobalSplits, "Number of split global live ranges");
51 STATISTIC(NumLocalSplits, "Number of split local live ranges");
52 STATISTIC(NumReassigned, "Number of interferences reassigned");
53 STATISTIC(NumEvicted, "Number of interferences evicted");
55 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
56 createGreedyRegisterAllocator);
59 class RAGreedy : public MachineFunctionPass,
61 private LiveRangeEdit::Delegate {
65 BitVector ReservedRegs;
70 MachineDominatorTree *DomTree;
71 MachineLoopInfo *Loops;
72 MachineLoopRanges *LoopRanges;
74 SpillPlacement *SpillPlacer;
77 std::auto_ptr<Spiller> SpillerInstance;
78 std::priority_queue<std::pair<unsigned, unsigned> > Queue;
80 // Live ranges pass through a number of stages as we try to allocate them.
81 // Some of the stages may also create new live ranges:
83 // - Region splitting.
84 // - Per-block splitting.
88 // Ranges produced by one of the stages skip the previous stages when they are
89 // dequeued. This improves performance because we can skip interference checks
90 // that are unlikely to give any results. It also guarantees that the live
91 // range splitting algorithm terminates, something that is otherwise hard to
94 RS_Original, ///< Never seen before, never split.
95 RS_Second, ///< Second time in the queue.
96 RS_Region, ///< Produced by region splitting.
97 RS_Block, ///< Produced by per-block splitting.
98 RS_Local, ///< Produced by local splitting.
99 RS_Spill ///< Produced by spilling.
102 IndexedMap<unsigned char, VirtReg2IndexFunctor> LRStage;
104 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
105 return LiveRangeStage(LRStage[VirtReg.reg]);
108 template<typename Iterator>
109 void setStage(Iterator Begin, Iterator End, LiveRangeStage NewStage) {
110 LRStage.resize(MRI->getNumVirtRegs());
111 for (;Begin != End; ++Begin)
112 LRStage[(*Begin)->reg] = NewStage;
116 std::auto_ptr<SplitAnalysis> SA;
117 std::auto_ptr<SplitEditor> SE;
119 /// All basic blocks where the current register is live.
120 SmallVector<SpillPlacement::BlockConstraint, 8> SplitConstraints;
122 typedef std::pair<SlotIndex, SlotIndex> IndexPair;
124 /// Global live range splitting candidate info.
125 struct GlobalSplitCandidate {
127 SmallVector<IndexPair, 8> Interference;
128 BitVector LiveBundles;
131 /// Candidate info for for each PhysReg in AllocationOrder.
132 /// This vector never shrinks, but grows to the size of the largest register
134 SmallVector<GlobalSplitCandidate, 32> GlobalCand;
136 /// For every instruction in SA->UseSlots, store the previous non-copy
138 SmallVector<SlotIndex, 8> PrevSlot;
143 /// Return the pass name.
144 virtual const char* getPassName() const {
145 return "Greedy Register Allocator";
148 /// RAGreedy analysis usage.
149 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
150 virtual void releaseMemory();
151 virtual Spiller &spiller() { return *SpillerInstance; }
152 virtual void enqueue(LiveInterval *LI);
153 virtual LiveInterval *dequeue();
154 virtual unsigned selectOrSplit(LiveInterval&,
155 SmallVectorImpl<LiveInterval*>&);
157 /// Perform register allocation.
158 virtual bool runOnMachineFunction(MachineFunction &mf);
163 void LRE_WillEraseInstruction(MachineInstr*);
164 bool LRE_CanEraseVirtReg(unsigned);
166 bool checkUncachedInterference(LiveInterval&, unsigned);
167 LiveInterval *getSingleInterference(LiveInterval&, unsigned);
168 bool reassignVReg(LiveInterval &InterferingVReg, unsigned OldPhysReg);
170 void mapGlobalInterference(unsigned, SmallVectorImpl<IndexPair>&);
171 float calcSplitConstraints(const SmallVectorImpl<IndexPair>&);
173 float calcGlobalSplitCost(const BitVector&);
174 void splitAroundRegion(LiveInterval&, unsigned, const BitVector&,
175 SmallVectorImpl<LiveInterval*>&);
176 void calcGapWeights(unsigned, SmallVectorImpl<float>&);
177 SlotIndex getPrevMappedIndex(const MachineInstr*);
178 void calcPrevSlots();
179 unsigned nextSplitPoint(unsigned);
180 bool canEvictInterference(LiveInterval&, unsigned, float&);
182 unsigned tryReassign(LiveInterval&, AllocationOrder&,
183 SmallVectorImpl<LiveInterval*>&);
184 unsigned tryEvict(LiveInterval&, AllocationOrder&,
185 SmallVectorImpl<LiveInterval*>&);
186 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
187 SmallVectorImpl<LiveInterval*>&);
188 unsigned tryLocalSplit(LiveInterval&, AllocationOrder&,
189 SmallVectorImpl<LiveInterval*>&);
190 unsigned trySplit(LiveInterval&, AllocationOrder&,
191 SmallVectorImpl<LiveInterval*>&);
193 } // end anonymous namespace
195 char RAGreedy::ID = 0;
197 FunctionPass* llvm::createGreedyRegisterAllocator() {
198 return new RAGreedy();
201 RAGreedy::RAGreedy(): MachineFunctionPass(ID), LRStage(RS_Original) {
202 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
203 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
204 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
205 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
206 initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
207 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
208 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
209 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
210 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
211 initializeMachineLoopRangesPass(*PassRegistry::getPassRegistry());
212 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
213 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
214 initializeSpillPlacementPass(*PassRegistry::getPassRegistry());
217 void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
218 AU.setPreservesCFG();
219 AU.addRequired<AliasAnalysis>();
220 AU.addPreserved<AliasAnalysis>();
221 AU.addRequired<LiveIntervals>();
222 AU.addRequired<SlotIndexes>();
223 AU.addPreserved<SlotIndexes>();
225 AU.addRequiredID(StrongPHIEliminationID);
226 AU.addRequiredTransitive<RegisterCoalescer>();
227 AU.addRequired<CalculateSpillWeights>();
228 AU.addRequired<LiveStacks>();
229 AU.addPreserved<LiveStacks>();
230 AU.addRequired<MachineDominatorTree>();
231 AU.addPreserved<MachineDominatorTree>();
232 AU.addRequired<MachineLoopInfo>();
233 AU.addPreserved<MachineLoopInfo>();
234 AU.addRequired<MachineLoopRanges>();
235 AU.addPreserved<MachineLoopRanges>();
236 AU.addRequired<VirtRegMap>();
237 AU.addPreserved<VirtRegMap>();
238 AU.addRequired<EdgeBundles>();
239 AU.addRequired<SpillPlacement>();
240 MachineFunctionPass::getAnalysisUsage(AU);
244 //===----------------------------------------------------------------------===//
245 // LiveRangeEdit delegate methods
246 //===----------------------------------------------------------------------===//
248 void RAGreedy::LRE_WillEraseInstruction(MachineInstr *MI) {
249 // LRE itself will remove from SlotIndexes and parent basic block.
250 VRM->RemoveMachineInstrFromMaps(MI);
253 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
254 if (unsigned PhysReg = VRM->getPhys(VirtReg)) {
255 unassign(LIS->getInterval(VirtReg), PhysReg);
258 // Unassigned virtreg is probably in the priority queue.
259 // RegAllocBase will erase it after dequeueing.
263 void RAGreedy::releaseMemory() {
264 SpillerInstance.reset(0);
266 RegAllocBase::releaseMemory();
269 void RAGreedy::enqueue(LiveInterval *LI) {
270 // Prioritize live ranges by size, assigning larger ranges first.
271 // The queue holds (size, reg) pairs.
272 const unsigned Size = LI->getSize();
273 const unsigned Reg = LI->reg;
274 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
275 "Can only enqueue virtual registers");
279 if (LRStage[Reg] == RS_Original)
280 // 1st generation ranges are handled first, long -> short.
281 Prio = (1u << 31) + Size;
283 // Repeat offenders are handled second, short -> long
284 Prio = (1u << 30) - Size;
286 // Boost ranges that have a physical register hint.
287 const unsigned Hint = VRM->getRegAllocPref(Reg);
288 if (TargetRegisterInfo::isPhysicalRegister(Hint))
291 Queue.push(std::make_pair(Prio, Reg));
294 LiveInterval *RAGreedy::dequeue() {
297 LiveInterval *LI = &LIS->getInterval(Queue.top().second);
302 //===----------------------------------------------------------------------===//
303 // Register Reassignment
304 //===----------------------------------------------------------------------===//
306 // Check interference without using the cache.
307 bool RAGreedy::checkUncachedInterference(LiveInterval &VirtReg,
309 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
310 LiveIntervalUnion::Query subQ(&VirtReg, &PhysReg2LiveUnion[*AliasI]);
311 if (subQ.checkInterference())
317 /// getSingleInterference - Return the single interfering virtual register
318 /// assigned to PhysReg. Return 0 if more than one virtual register is
320 LiveInterval *RAGreedy::getSingleInterference(LiveInterval &VirtReg,
322 // Check physreg and aliases.
323 LiveInterval *Interference = 0;
324 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
325 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
326 if (Q.checkInterference()) {
329 if (Q.collectInterferingVRegs(2) > 1)
331 Interference = Q.interferingVRegs().front();
337 // Attempt to reassign this virtual register to a different physical register.
339 // FIXME: we are not yet caching these "second-level" interferences discovered
340 // in the sub-queries. These interferences can change with each call to
341 // selectOrSplit. However, we could implement a "may-interfere" cache that
342 // could be conservatively dirtied when we reassign or split.
344 // FIXME: This may result in a lot of alias queries. We could summarize alias
345 // live intervals in their parent register's live union, but it's messy.
346 bool RAGreedy::reassignVReg(LiveInterval &InterferingVReg,
347 unsigned WantedPhysReg) {
348 assert(TargetRegisterInfo::isVirtualRegister(InterferingVReg.reg) &&
349 "Can only reassign virtual registers");
350 assert(TRI->regsOverlap(WantedPhysReg, VRM->getPhys(InterferingVReg.reg)) &&
351 "inconsistent phys reg assigment");
353 AllocationOrder Order(InterferingVReg.reg, *VRM, ReservedRegs);
354 while (unsigned PhysReg = Order.next()) {
355 // Don't reassign to a WantedPhysReg alias.
356 if (TRI->regsOverlap(PhysReg, WantedPhysReg))
359 if (checkUncachedInterference(InterferingVReg, PhysReg))
362 // Reassign the interfering virtual reg to this physical reg.
363 unsigned OldAssign = VRM->getPhys(InterferingVReg.reg);
364 DEBUG(dbgs() << "reassigning: " << InterferingVReg << " from " <<
365 TRI->getName(OldAssign) << " to " << TRI->getName(PhysReg) << '\n');
366 unassign(InterferingVReg, OldAssign);
367 assign(InterferingVReg, PhysReg);
374 /// tryReassign - Try to reassign a single interference to a different physreg.
375 /// @param VirtReg Currently unassigned virtual register.
376 /// @param Order Physregs to try.
377 /// @return Physreg to assign VirtReg, or 0.
378 unsigned RAGreedy::tryReassign(LiveInterval &VirtReg, AllocationOrder &Order,
379 SmallVectorImpl<LiveInterval*> &NewVRegs){
380 NamedRegionTimer T("Reassign", TimerGroupName, TimePassesIsEnabled);
383 while (unsigned PhysReg = Order.next()) {
384 LiveInterval *InterferingVReg = getSingleInterference(VirtReg, PhysReg);
385 if (!InterferingVReg)
387 if (TargetRegisterInfo::isPhysicalRegister(InterferingVReg->reg))
389 if (reassignVReg(*InterferingVReg, PhysReg))
396 //===----------------------------------------------------------------------===//
397 // Interference eviction
398 //===----------------------------------------------------------------------===//
400 /// canEvict - Return true if all interferences between VirtReg and PhysReg can
401 /// be evicted. Set maxWeight to the maximal spill weight of an interference.
402 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
405 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
406 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
407 // If there is 10 or more interferences, chances are one is smaller.
408 if (Q.collectInterferingVRegs(10) >= 10)
411 // Check if any interfering live range is heavier than VirtReg.
412 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
413 LiveInterval *Intf = Q.interferingVRegs()[i];
414 if (TargetRegisterInfo::isPhysicalRegister(Intf->reg))
416 if (Intf->weight >= VirtReg.weight)
418 Weight = std::max(Weight, Intf->weight);
425 /// tryEvict - Try to evict all interferences for a physreg.
426 /// @param VirtReg Currently unassigned virtual register.
427 /// @param Order Physregs to try.
428 /// @return Physreg to assign VirtReg, or 0.
429 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
430 AllocationOrder &Order,
431 SmallVectorImpl<LiveInterval*> &NewVRegs){
432 NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled);
434 // Keep track of the lightest single interference seen so far.
435 float BestWeight = 0;
436 unsigned BestPhys = 0;
439 while (unsigned PhysReg = Order.next()) {
441 if (!canEvictInterference(VirtReg, PhysReg, Weight))
444 // This is an eviction candidate.
445 DEBUG(dbgs() << "max " << PrintReg(PhysReg, TRI) << " interference = "
447 if (BestPhys && Weight >= BestWeight)
453 // Stop if the hint can be used.
454 if (Order.isHint(PhysReg))
461 DEBUG(dbgs() << "evicting " << PrintReg(BestPhys, TRI) << " interference\n");
462 for (const unsigned *AliasI = TRI->getOverlaps(BestPhys); *AliasI; ++AliasI) {
463 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
464 assert(Q.seenAllInterferences() && "Didn't check all interfererences.");
465 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
466 LiveInterval *Intf = Q.interferingVRegs()[i];
467 unassign(*Intf, VRM->getPhys(Intf->reg));
469 NewVRegs.push_back(Intf);
476 //===----------------------------------------------------------------------===//
478 //===----------------------------------------------------------------------===//
480 /// mapGlobalInterference - Compute a map of the interference from PhysReg and
481 /// its aliases in each block in SA->LiveBlocks.
482 /// If LiveBlocks[i] is live-in, Ranges[i].first is the first interference.
483 /// If LiveBlocks[i] is live-out, Ranges[i].second is the last interference.
484 void RAGreedy::mapGlobalInterference(unsigned PhysReg,
485 SmallVectorImpl<IndexPair> &Ranges) {
486 Ranges.assign(SA->LiveBlocks.size(), IndexPair());
487 LiveInterval &VirtReg = const_cast<LiveInterval&>(SA->getParent());
488 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
489 if (!query(VirtReg, *AI).checkInterference())
491 LiveIntervalUnion::SegmentIter IntI =
492 PhysReg2LiveUnion[*AI].find(VirtReg.beginIndex());
495 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
496 const SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
497 IndexPair &IP = Ranges[i];
499 // Skip interference-free blocks.
500 if (IntI.start() >= BI.Stop)
503 // First interference in block.
505 IntI.advanceTo(BI.Start);
508 if (IntI.start() >= BI.Stop)
510 if (!IP.first.isValid() || IntI.start() < IP.first)
511 IP.first = IntI.start();
514 // Last interference in block.
516 IntI.advanceTo(BI.Stop);
517 if (!IntI.valid() || IntI.start() >= BI.Stop)
519 if (IntI.stop() <= BI.Start)
521 if (!IP.second.isValid() || IntI.stop() > IP.second)
522 IP.second = IntI.stop();
528 /// calcSplitConstraints - Fill out the SplitConstraints vector based on the
529 /// interference pattern in Intf. Return the static cost of this split,
530 /// assuming that all preferences in SplitConstraints are met.
531 float RAGreedy::calcSplitConstraints(const SmallVectorImpl<IndexPair> &Intf) {
532 // Reset interference dependent info.
533 SplitConstraints.resize(SA->LiveBlocks.size());
534 float StaticCost = 0;
535 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
536 SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
537 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
538 IndexPair IP = Intf[i];
540 BC.Number = BI.MBB->getNumber();
541 BC.Entry = (BI.Uses && BI.LiveIn) ?
542 SpillPlacement::PrefReg : SpillPlacement::DontCare;
543 BC.Exit = (BI.Uses && BI.LiveOut) ?
544 SpillPlacement::PrefReg : SpillPlacement::DontCare;
546 // Number of spill code instructions to insert.
549 // Interference for the live-in value.
550 if (IP.first.isValid()) {
551 if (IP.first <= BI.Start)
552 BC.Entry = SpillPlacement::MustSpill, Ins += BI.Uses;
554 BC.Entry = SpillPlacement::PrefSpill;
555 else if (IP.first < BI.FirstUse)
556 BC.Entry = SpillPlacement::PrefSpill, ++Ins;
557 else if (IP.first < (BI.LiveThrough ? BI.LastUse : BI.Kill))
561 // Interference for the live-out value.
562 if (IP.second.isValid()) {
563 if (IP.second >= BI.LastSplitPoint)
564 BC.Exit = SpillPlacement::MustSpill, Ins += BI.Uses;
566 BC.Exit = SpillPlacement::PrefSpill;
567 else if (IP.second > BI.LastUse)
568 BC.Exit = SpillPlacement::PrefSpill, ++Ins;
569 else if (IP.second > (BI.LiveThrough ? BI.FirstUse : BI.Def))
573 // Accumulate the total frequency of inserted spill code.
575 StaticCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
581 /// calcGlobalSplitCost - Return the global split cost of following the split
582 /// pattern in LiveBundles. This cost should be added to the local cost of the
583 /// interference pattern in SplitConstraints.
585 float RAGreedy::calcGlobalSplitCost(const BitVector &LiveBundles) {
586 float GlobalCost = 0;
587 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
588 SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
589 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
590 bool RegIn = LiveBundles[Bundles->getBundle(BC.Number, 0)];
591 bool RegOut = LiveBundles[Bundles->getBundle(BC.Number, 1)];
595 Ins += RegIn != RegOut;
598 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg);
600 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg);
603 GlobalCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
608 /// splitAroundRegion - Split VirtReg around the region determined by
609 /// LiveBundles. Make an effort to avoid interference from PhysReg.
611 /// The 'register' interval is going to contain as many uses as possible while
612 /// avoiding interference. The 'stack' interval is the complement constructed by
613 /// SplitEditor. It will contain the rest.
615 void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, unsigned PhysReg,
616 const BitVector &LiveBundles,
617 SmallVectorImpl<LiveInterval*> &NewVRegs) {
619 dbgs() << "Splitting around region for " << PrintReg(PhysReg, TRI)
621 for (int i = LiveBundles.find_first(); i>=0; i = LiveBundles.find_next(i))
622 dbgs() << " EB#" << i;
626 // First compute interference ranges in the live blocks.
627 SmallVector<IndexPair, 8> InterferenceRanges;
628 mapGlobalInterference(PhysReg, InterferenceRanges);
630 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
633 // Create the main cross-block interval.
636 // First add all defs that are live out of a block.
637 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
638 SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
639 bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)];
640 bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)];
642 // Should the register be live out?
643 if (!BI.LiveOut || !RegOut)
646 IndexPair &IP = InterferenceRanges[i];
647 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " -> EB#"
648 << Bundles->getBundle(BI.MBB->getNumber(), 1)
649 << " intf [" << IP.first << ';' << IP.second << ')');
651 // The interference interval should either be invalid or overlap MBB.
652 assert((!IP.first.isValid() || IP.first < BI.Stop) && "Bad interference");
653 assert((!IP.second.isValid() || IP.second > BI.Start)
654 && "Bad interference");
656 // Check interference leaving the block.
657 if (!IP.second.isValid()) {
658 // Block is interference-free.
659 DEBUG(dbgs() << ", no interference");
661 assert(BI.LiveThrough && "No uses, but not live through block?");
662 // Block is live-through without interference.
663 DEBUG(dbgs() << ", no uses"
664 << (RegIn ? ", live-through.\n" : ", stack in.\n"));
666 SE->enterIntvAtEnd(*BI.MBB);
669 if (!BI.LiveThrough) {
670 DEBUG(dbgs() << ", not live-through.\n");
671 SE->useIntv(SE->enterIntvBefore(BI.Def), BI.Stop);
675 // Block is live-through, but entry bundle is on the stack.
676 // Reload just before the first use.
677 DEBUG(dbgs() << ", not live-in, enter before first use.\n");
678 SE->useIntv(SE->enterIntvBefore(BI.FirstUse), BI.Stop);
681 DEBUG(dbgs() << ", live-through.\n");
685 // Block has interference.
686 DEBUG(dbgs() << ", interference to " << IP.second);
688 if (!BI.LiveThrough && IP.second <= BI.Def) {
689 // The interference doesn't reach the outgoing segment.
690 DEBUG(dbgs() << " doesn't affect def from " << BI.Def << '\n');
691 SE->useIntv(BI.Def, BI.Stop);
697 // No uses in block, avoid interference by reloading as late as possible.
698 DEBUG(dbgs() << ", no uses.\n");
699 SlotIndex SegStart = SE->enterIntvAtEnd(*BI.MBB);
700 assert(SegStart >= IP.second && "Couldn't avoid interference");
704 if (IP.second.getBoundaryIndex() < BI.LastUse) {
705 // There are interference-free uses at the end of the block.
706 // Find the first use that can get the live-out register.
707 SmallVectorImpl<SlotIndex>::const_iterator UI =
708 std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(),
709 IP.second.getBoundaryIndex());
710 assert(UI != SA->UseSlots.end() && "Couldn't find last use");
712 assert(Use <= BI.LastUse && "Couldn't find last use");
713 // Only attempt a split befroe the last split point.
714 if (Use.getBaseIndex() <= BI.LastSplitPoint) {
715 DEBUG(dbgs() << ", free use at " << Use << ".\n");
716 SlotIndex SegStart = SE->enterIntvBefore(Use);
717 assert(SegStart >= IP.second && "Couldn't avoid interference");
718 assert(SegStart < BI.LastSplitPoint && "Impossible split point");
719 SE->useIntv(SegStart, BI.Stop);
724 // Interference is after the last use.
725 DEBUG(dbgs() << " after last use.\n");
726 SlotIndex SegStart = SE->enterIntvAtEnd(*BI.MBB);
727 assert(SegStart >= IP.second && "Couldn't avoid interference");
730 // Now all defs leading to live bundles are handled, do everything else.
731 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
732 SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
733 bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)];
734 bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)];
736 // Is the register live-in?
737 if (!BI.LiveIn || !RegIn)
740 // We have an incoming register. Check for interference.
741 IndexPair &IP = InterferenceRanges[i];
743 DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0)
744 << " -> BB#" << BI.MBB->getNumber());
746 // Check interference entering the block.
747 if (!IP.first.isValid()) {
748 // Block is interference-free.
749 DEBUG(dbgs() << ", no interference");
751 assert(BI.LiveThrough && "No uses, but not live through block?");
752 // Block is live-through without interference.
754 DEBUG(dbgs() << ", no uses, live-through.\n");
755 SE->useIntv(BI.Start, BI.Stop);
757 DEBUG(dbgs() << ", no uses, stack-out.\n");
758 SE->leaveIntvAtTop(*BI.MBB);
762 if (!BI.LiveThrough) {
763 DEBUG(dbgs() << ", killed in block.\n");
764 SE->useIntv(BI.Start, SE->leaveIntvAfter(BI.Kill));
768 // Block is live-through, but exit bundle is on the stack.
769 // Spill immediately after the last use.
770 if (BI.LastUse < BI.LastSplitPoint) {
771 DEBUG(dbgs() << ", uses, stack-out.\n");
772 SE->useIntv(BI.Start, SE->leaveIntvAfter(BI.LastUse));
775 // The last use is after the last split point, it is probably an
777 DEBUG(dbgs() << ", uses at " << BI.LastUse << " after split point "
778 << BI.LastSplitPoint << ", stack-out.\n");
779 SlotIndex SegEnd = SE->leaveIntvBefore(BI.LastSplitPoint);
780 SE->useIntv(BI.Start, SegEnd);
781 // Run a double interval from the split to the last use.
782 // This makes it possible to spill the complement without affecting the
784 SE->overlapIntv(SegEnd, BI.LastUse);
787 // Register is live-through.
788 DEBUG(dbgs() << ", uses, live-through.\n");
789 SE->useIntv(BI.Start, BI.Stop);
793 // Block has interference.
794 DEBUG(dbgs() << ", interference from " << IP.first);
796 if (!BI.LiveThrough && IP.first >= BI.Kill) {
797 // The interference doesn't reach the outgoing segment.
798 DEBUG(dbgs() << " doesn't affect kill at " << BI.Kill << '\n');
799 SE->useIntv(BI.Start, BI.Kill);
804 // No uses in block, avoid interference by spilling as soon as possible.
805 DEBUG(dbgs() << ", no uses.\n");
806 SlotIndex SegEnd = SE->leaveIntvAtTop(*BI.MBB);
807 assert(SegEnd <= IP.first && "Couldn't avoid interference");
810 if (IP.first.getBaseIndex() > BI.FirstUse) {
811 // There are interference-free uses at the beginning of the block.
812 // Find the last use that can get the register.
813 SmallVectorImpl<SlotIndex>::const_iterator UI =
814 std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(),
815 IP.first.getBaseIndex());
816 assert(UI != SA->UseSlots.begin() && "Couldn't find first use");
817 SlotIndex Use = (--UI)->getBoundaryIndex();
818 DEBUG(dbgs() << ", free use at " << *UI << ".\n");
819 SlotIndex SegEnd = SE->leaveIntvAfter(Use);
820 assert(SegEnd <= IP.first && "Couldn't avoid interference");
821 SE->useIntv(BI.Start, SegEnd);
825 // Interference is before the first use.
826 DEBUG(dbgs() << " before first use.\n");
827 SlotIndex SegEnd = SE->leaveIntvAtTop(*BI.MBB);
828 assert(SegEnd <= IP.first && "Couldn't avoid interference");
833 // FIXME: Should we be more aggressive about splitting the stack region into
834 // per-block segments? The current approach allows the stack region to
835 // separate into connected components. Some components may be allocatable.
840 MF->verify(this, "After splitting live range around region");
843 // Make sure that at least one of the new intervals can allocate to PhysReg.
844 // That was the whole point of splitting the live range.
846 for (LiveRangeEdit::iterator I = LREdit.begin(), E = LREdit.end(); I != E;
848 if (!checkUncachedInterference(**I, PhysReg)) {
852 assert(found && "No allocatable intervals after pointless splitting");
857 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
858 SmallVectorImpl<LiveInterval*> &NewVRegs) {
859 BitVector LiveBundles, BestBundles;
861 unsigned BestReg = 0;
864 for (unsigned Cand = 0; unsigned PhysReg = Order.next(); ++Cand) {
865 if (GlobalCand.size() <= Cand)
866 GlobalCand.resize(Cand+1);
867 GlobalCand[Cand].PhysReg = PhysReg;
869 mapGlobalInterference(PhysReg, GlobalCand[Cand].Interference);
870 float Cost = calcSplitConstraints(GlobalCand[Cand].Interference);
871 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = " << Cost);
872 if (BestReg && Cost >= BestCost) {
873 DEBUG(dbgs() << " higher.\n");
877 SpillPlacer->placeSpills(SplitConstraints, LiveBundles);
878 // No live bundles, defer to splitSingleBlocks().
879 if (!LiveBundles.any()) {
880 DEBUG(dbgs() << " no bundles.\n");
884 Cost += calcGlobalSplitCost(LiveBundles);
886 dbgs() << ", total = " << Cost << " with bundles";
887 for (int i = LiveBundles.find_first(); i>=0; i = LiveBundles.find_next(i))
888 dbgs() << " EB#" << i;
891 if (!BestReg || Cost < BestCost) {
893 BestCost = 0.98f * Cost; // Prevent rounding effects.
894 BestBundles.swap(LiveBundles);
901 splitAroundRegion(VirtReg, BestReg, BestBundles, NewVRegs);
902 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Region);
907 //===----------------------------------------------------------------------===//
909 //===----------------------------------------------------------------------===//
912 /// calcGapWeights - Compute the maximum spill weight that needs to be evicted
913 /// in order to use PhysReg between two entries in SA->UseSlots.
915 /// GapWeight[i] represents the gap between UseSlots[i] and UseSlots[i+1].
917 void RAGreedy::calcGapWeights(unsigned PhysReg,
918 SmallVectorImpl<float> &GapWeight) {
919 assert(SA->LiveBlocks.size() == 1 && "Not a local interval");
920 const SplitAnalysis::BlockInfo &BI = SA->LiveBlocks.front();
921 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
922 const unsigned NumGaps = Uses.size()-1;
924 // Start and end points for the interference check.
925 SlotIndex StartIdx = BI.LiveIn ? BI.FirstUse.getBaseIndex() : BI.FirstUse;
926 SlotIndex StopIdx = BI.LiveOut ? BI.LastUse.getBoundaryIndex() : BI.LastUse;
928 GapWeight.assign(NumGaps, 0.0f);
930 // Add interference from each overlapping register.
931 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
932 if (!query(const_cast<LiveInterval&>(SA->getParent()), *AI)
933 .checkInterference())
936 // We know that VirtReg is a continuous interval from FirstUse to LastUse,
937 // so we don't need InterferenceQuery.
939 // Interference that overlaps an instruction is counted in both gaps
940 // surrounding the instruction. The exception is interference before
941 // StartIdx and after StopIdx.
943 LiveIntervalUnion::SegmentIter IntI = PhysReg2LiveUnion[*AI].find(StartIdx);
944 for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) {
945 // Skip the gaps before IntI.
946 while (Uses[Gap+1].getBoundaryIndex() < IntI.start())
947 if (++Gap == NumGaps)
952 // Update the gaps covered by IntI.
953 const float weight = IntI.value()->weight;
954 for (; Gap != NumGaps; ++Gap) {
955 GapWeight[Gap] = std::max(GapWeight[Gap], weight);
956 if (Uses[Gap+1].getBaseIndex() >= IntI.stop())
965 /// getPrevMappedIndex - Return the slot index of the last non-copy instruction
966 /// before MI that has a slot index. If MI is the first mapped instruction in
967 /// its block, return the block start index instead.
969 SlotIndex RAGreedy::getPrevMappedIndex(const MachineInstr *MI) {
970 assert(MI && "Missing MachineInstr");
971 const MachineBasicBlock *MBB = MI->getParent();
972 MachineBasicBlock::const_iterator B = MBB->begin(), I = MI;
974 if (!(--I)->isDebugValue() && !I->isCopy())
975 return Indexes->getInstructionIndex(I);
976 return Indexes->getMBBStartIdx(MBB);
979 /// calcPrevSlots - Fill in the PrevSlot array with the index of the previous
980 /// real non-copy instruction for each instruction in SA->UseSlots.
982 void RAGreedy::calcPrevSlots() {
983 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
985 PrevSlot.reserve(Uses.size());
986 for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
987 const MachineInstr *MI = Indexes->getInstructionFromIndex(Uses[i]);
988 PrevSlot.push_back(getPrevMappedIndex(MI).getDefIndex());
992 /// nextSplitPoint - Find the next index into SA->UseSlots > i such that it may
993 /// be beneficial to split before UseSlots[i].
995 /// 0 is always a valid split point
996 unsigned RAGreedy::nextSplitPoint(unsigned i) {
997 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
998 const unsigned Size = Uses.size();
999 assert(i != Size && "No split points after the end");
1000 // Allow split before i when Uses[i] is not adjacent to the previous use.
1001 while (++i != Size && PrevSlot[i].getBaseIndex() <= Uses[i-1].getBaseIndex())
1006 /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
1009 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1010 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1011 assert(SA->LiveBlocks.size() == 1 && "Not a local interval");
1012 const SplitAnalysis::BlockInfo &BI = SA->LiveBlocks.front();
1014 // Note that it is possible to have an interval that is live-in or live-out
1015 // while only covering a single block - A phi-def can use undef values from
1016 // predecessors, and the block could be a single-block loop.
1017 // We don't bother doing anything clever about such a case, we simply assume
1018 // that the interval is continuous from FirstUse to LastUse. We should make
1019 // sure that we don't do anything illegal to such an interval, though.
1021 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
1022 if (Uses.size() <= 2)
1024 const unsigned NumGaps = Uses.size()-1;
1027 dbgs() << "tryLocalSplit: ";
1028 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
1029 dbgs() << ' ' << SA->UseSlots[i];
1033 // For every use, find the previous mapped non-copy instruction.
1034 // We use this to detect valid split points, and to estimate new interval
1038 unsigned BestBefore = NumGaps;
1039 unsigned BestAfter = 0;
1042 const float blockFreq = SpillPlacer->getBlockFrequency(BI.MBB->getNumber());
1043 SmallVector<float, 8> GapWeight;
1046 while (unsigned PhysReg = Order.next()) {
1047 // Keep track of the largest spill weight that would need to be evicted in
1048 // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1].
1049 calcGapWeights(PhysReg, GapWeight);
1051 // Try to find the best sequence of gaps to close.
1052 // The new spill weight must be larger than any gap interference.
1054 // We will split before Uses[SplitBefore] and after Uses[SplitAfter].
1055 unsigned SplitBefore = 0, SplitAfter = nextSplitPoint(1) - 1;
1057 // MaxGap should always be max(GapWeight[SplitBefore..SplitAfter-1]).
1058 // It is the spill weight that needs to be evicted.
1059 float MaxGap = GapWeight[0];
1060 for (unsigned i = 1; i != SplitAfter; ++i)
1061 MaxGap = std::max(MaxGap, GapWeight[i]);
1064 // Live before/after split?
1065 const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
1066 const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut;
1068 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' '
1069 << Uses[SplitBefore] << '-' << Uses[SplitAfter]
1070 << " i=" << MaxGap);
1072 // Stop before the interval gets so big we wouldn't be making progress.
1073 if (!LiveBefore && !LiveAfter) {
1074 DEBUG(dbgs() << " all\n");
1077 // Should the interval be extended or shrunk?
1079 if (MaxGap < HUGE_VALF) {
1080 // Estimate the new spill weight.
1082 // Each instruction reads and writes the register, except the first
1083 // instr doesn't read when !FirstLive, and the last instr doesn't write
1086 // We will be inserting copies before and after, so the total number of
1087 // reads and writes is 2 * EstUses.
1089 const unsigned EstUses = 2*(SplitAfter - SplitBefore) +
1090 2*(LiveBefore + LiveAfter);
1092 // Try to guess the size of the new interval. This should be trivial,
1093 // but the slot index of an inserted copy can be a lot smaller than the
1094 // instruction it is inserted before if there are many dead indexes
1097 // We measure the distance from the instruction before SplitBefore to
1098 // get a conservative estimate.
1100 // The final distance can still be different if inserting copies
1101 // triggers a slot index renumbering.
1103 const float EstWeight = normalizeSpillWeight(blockFreq * EstUses,
1104 PrevSlot[SplitBefore].distance(Uses[SplitAfter]));
1105 // Would this split be possible to allocate?
1106 // Never allocate all gaps, we wouldn't be making progress.
1107 float Diff = EstWeight - MaxGap;
1108 DEBUG(dbgs() << " w=" << EstWeight << " d=" << Diff);
1111 if (Diff > BestDiff) {
1112 DEBUG(dbgs() << " (best)");
1114 BestBefore = SplitBefore;
1115 BestAfter = SplitAfter;
1122 SplitBefore = nextSplitPoint(SplitBefore);
1123 if (SplitBefore < SplitAfter) {
1124 DEBUG(dbgs() << " shrink\n");
1125 // Recompute the max when necessary.
1126 if (GapWeight[SplitBefore - 1] >= MaxGap) {
1127 MaxGap = GapWeight[SplitBefore];
1128 for (unsigned i = SplitBefore + 1; i != SplitAfter; ++i)
1129 MaxGap = std::max(MaxGap, GapWeight[i]);
1136 // Try to extend the interval.
1137 if (SplitAfter >= NumGaps) {
1138 DEBUG(dbgs() << " end\n");
1142 DEBUG(dbgs() << " extend\n");
1143 for (unsigned e = nextSplitPoint(SplitAfter + 1) - 1;
1144 SplitAfter != e; ++SplitAfter)
1145 MaxGap = std::max(MaxGap, GapWeight[SplitAfter]);
1150 // Didn't find any candidates?
1151 if (BestBefore == NumGaps)
1154 DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore]
1155 << '-' << Uses[BestAfter] << ", " << BestDiff
1156 << ", " << (BestAfter - BestBefore + 1) << " instrs\n");
1158 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
1162 SlotIndex SegStart = SE->enterIntvBefore(Uses[BestBefore]);
1163 SlotIndex SegStop = SE->leaveIntvAfter(Uses[BestAfter]);
1164 SE->useIntv(SegStart, SegStop);
1167 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Local);
1173 //===----------------------------------------------------------------------===//
1174 // Live Range Splitting
1175 //===----------------------------------------------------------------------===//
1177 /// trySplit - Try to split VirtReg or one of its interferences, making it
1179 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
1180 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
1181 SmallVectorImpl<LiveInterval*>&NewVRegs) {
1182 // Local intervals are handled separately.
1183 if (LIS->intervalIsInOneMBB(VirtReg)) {
1184 NamedRegionTimer T("Local Splitting", TimerGroupName, TimePassesIsEnabled);
1185 SA->analyze(&VirtReg);
1186 return tryLocalSplit(VirtReg, Order, NewVRegs);
1189 NamedRegionTimer T("Global Splitting", TimerGroupName, TimePassesIsEnabled);
1191 // Don't iterate global splitting.
1192 // Move straight to spilling if this range was produced by a global split.
1193 LiveRangeStage Stage = getStage(VirtReg);
1194 if (Stage >= RS_Block)
1197 SA->analyze(&VirtReg);
1199 // First try to split around a region spanning multiple blocks.
1200 if (Stage < RS_Region) {
1201 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1202 if (PhysReg || !NewVRegs.empty())
1206 // Then isolate blocks with multiple uses.
1207 if (Stage < RS_Block) {
1208 SplitAnalysis::BlockPtrSet Blocks;
1209 if (SA->getMultiUseBlocks(Blocks)) {
1210 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
1212 SE->splitSingleBlocks(Blocks);
1213 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Block);
1215 MF->verify(this, "After splitting live range around basic blocks");
1219 // Don't assign any physregs.
1224 //===----------------------------------------------------------------------===//
1226 //===----------------------------------------------------------------------===//
1228 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
1229 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1230 LiveRangeStage Stage = getStage(VirtReg);
1231 if (Stage == RS_Original)
1232 LRStage[VirtReg.reg] = RS_Second;
1234 // First try assigning a free register.
1235 AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);
1236 while (unsigned PhysReg = Order.next()) {
1237 if (!checkPhysRegInterference(VirtReg, PhysReg))
1241 if (unsigned PhysReg = tryReassign(VirtReg, Order, NewVRegs))
1244 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs))
1247 assert(NewVRegs.empty() && "Cannot append to existing NewVRegs");
1249 // The first time we see a live range, don't try to split or spill.
1250 // Wait until the second time, when all smaller ranges have been allocated.
1251 // This gives a better picture of the interference to split around.
1252 if (Stage == RS_Original) {
1253 NewVRegs.push_back(&VirtReg);
1257 assert(Stage < RS_Spill && "Cannot allocate after spilling");
1259 // Try splitting VirtReg or interferences.
1260 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
1261 if (PhysReg || !NewVRegs.empty())
1264 // Finally spill VirtReg itself.
1265 NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
1266 LiveRangeEdit LRE(VirtReg, NewVRegs, this);
1267 spiller().spill(LRE);
1269 // The live virtual register requesting allocation was spilled, so tell
1270 // the caller not to allocate anything during this round.
1274 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
1275 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
1276 << "********** Function: "
1277 << ((Value*)mf.getFunction())->getName() << '\n');
1281 MF->verify(this, "Before greedy register allocator");
1283 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
1284 Indexes = &getAnalysis<SlotIndexes>();
1285 DomTree = &getAnalysis<MachineDominatorTree>();
1286 ReservedRegs = TRI->getReservedRegs(*MF);
1287 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
1288 Loops = &getAnalysis<MachineLoopInfo>();
1289 LoopRanges = &getAnalysis<MachineLoopRanges>();
1290 Bundles = &getAnalysis<EdgeBundles>();
1291 SpillPlacer = &getAnalysis<SpillPlacement>();
1293 SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops));
1294 SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree));
1296 LRStage.resize(MRI->getNumVirtRegs());
1300 LIS->addKillFlags();
1304 NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled);
1305 VRM->rewrite(Indexes);
1308 // The pass output is in VirtRegMap. Release all the transient data.