1 //===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RAGreedy function pass for register allocation in
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "AllocationOrder.h"
17 #include "InterferenceCache.h"
18 #include "LiveDebugVariables.h"
19 #include "LiveRangeEdit.h"
20 #include "RegAllocBase.h"
22 #include "SpillPlacement.h"
24 #include "VirtRegMap.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/Function.h"
28 #include "llvm/PassAnalysisSupport.h"
29 #include "llvm/CodeGen/CalcSpillWeights.h"
30 #include "llvm/CodeGen/EdgeBundles.h"
31 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
32 #include "llvm/CodeGen/LiveStackAnalysis.h"
33 #include "llvm/CodeGen/MachineDominators.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineLoopInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/CodeGen/RegAllocRegistry.h"
39 #include "llvm/Target/TargetOptions.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/raw_ostream.h"
44 #include "llvm/Support/Timer.h"
50 STATISTIC(NumGlobalSplits, "Number of split global live ranges");
51 STATISTIC(NumLocalSplits, "Number of split local live ranges");
52 STATISTIC(NumEvicted, "Number of interferences evicted");
54 cl::opt<bool> CompactRegions("compact-regions", cl::init(true));
56 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
57 createGreedyRegisterAllocator);
60 class RAGreedy : public MachineFunctionPass,
62 private LiveRangeEdit::Delegate {
70 MachineDominatorTree *DomTree;
71 MachineLoopInfo *Loops;
73 SpillPlacement *SpillPlacer;
74 LiveDebugVariables *DebugVars;
77 std::auto_ptr<Spiller> SpillerInstance;
78 std::priority_queue<std::pair<unsigned, unsigned> > Queue;
81 // Live ranges pass through a number of stages as we try to allocate them.
82 // Some of the stages may also create new live ranges:
84 // - Region splitting.
85 // - Per-block splitting.
89 // Ranges produced by one of the stages skip the previous stages when they are
90 // dequeued. This improves performance because we can skip interference checks
91 // that are unlikely to give any results. It also guarantees that the live
92 // range splitting algorithm terminates, something that is otherwise hard to
95 /// Newly created live range that has never been queued.
98 /// Only attempt assignment and eviction. Then requeue as RS_Split.
101 /// Attempt live range splitting if assignment is impossible.
104 /// Attempt more aggressive live range splitting that is guaranteed to make
105 /// progress. This is used for split products that may not be making
109 /// Live range will be spilled. No more splitting will be attempted.
112 /// There is nothing more we can do to this live range. Abort compilation
113 /// if it can't be assigned.
117 static const char *const StageName[];
119 // RegInfo - Keep additional information about each live range.
121 LiveRangeStage Stage;
123 // Cascade - Eviction loop prevention. See canEvictInterference().
126 RegInfo() : Stage(RS_New), Cascade(0) {}
129 IndexedMap<RegInfo, VirtReg2IndexFunctor> ExtraRegInfo;
131 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
132 return ExtraRegInfo[VirtReg.reg].Stage;
135 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) {
136 ExtraRegInfo.resize(MRI->getNumVirtRegs());
137 ExtraRegInfo[VirtReg.reg].Stage = Stage;
140 template<typename Iterator>
141 void setStage(Iterator Begin, Iterator End, LiveRangeStage NewStage) {
142 ExtraRegInfo.resize(MRI->getNumVirtRegs());
143 for (;Begin != End; ++Begin) {
144 unsigned Reg = (*Begin)->reg;
145 if (ExtraRegInfo[Reg].Stage == RS_New)
146 ExtraRegInfo[Reg].Stage = NewStage;
150 /// Cost of evicting interference.
151 struct EvictionCost {
152 unsigned BrokenHints; ///< Total number of broken hints.
153 float MaxWeight; ///< Maximum spill weight evicted.
155 EvictionCost(unsigned B = 0) : BrokenHints(B), MaxWeight(0) {}
157 bool operator<(const EvictionCost &O) const {
158 if (BrokenHints != O.BrokenHints)
159 return BrokenHints < O.BrokenHints;
160 return MaxWeight < O.MaxWeight;
165 std::auto_ptr<SplitAnalysis> SA;
166 std::auto_ptr<SplitEditor> SE;
168 /// Cached per-block interference maps
169 InterferenceCache IntfCache;
171 /// All basic blocks where the current register has uses.
172 SmallVector<SpillPlacement::BlockConstraint, 8> SplitConstraints;
174 /// Global live range splitting candidate info.
175 struct GlobalSplitCandidate {
176 // Register intended for assignment, or 0.
179 // SplitKit interval index for this candidate.
182 // Interference for PhysReg.
183 InterferenceCache::Cursor Intf;
185 // Bundles where this candidate should be live.
186 BitVector LiveBundles;
187 SmallVector<unsigned, 8> ActiveBlocks;
189 void reset(InterferenceCache &Cache, unsigned Reg) {
192 Intf.setPhysReg(Cache, Reg);
194 ActiveBlocks.clear();
197 // Set B[i] = C for every live bundle where B[i] was NoCand.
198 unsigned getBundles(SmallVectorImpl<unsigned> &B, unsigned C) {
200 for (int i = LiveBundles.find_first(); i >= 0;
201 i = LiveBundles.find_next(i))
202 if (B[i] == NoCand) {
210 /// Candidate info for for each PhysReg in AllocationOrder.
211 /// This vector never shrinks, but grows to the size of the largest register
213 SmallVector<GlobalSplitCandidate, 32> GlobalCand;
215 enum { NoCand = ~0u };
217 /// Candidate map. Each edge bundle is assigned to a GlobalCand entry, or to
218 /// NoCand which indicates the stack interval.
219 SmallVector<unsigned, 32> BundleCand;
224 /// Return the pass name.
225 virtual const char* getPassName() const {
226 return "Greedy Register Allocator";
229 /// RAGreedy analysis usage.
230 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
231 virtual void releaseMemory();
232 virtual Spiller &spiller() { return *SpillerInstance; }
233 virtual void enqueue(LiveInterval *LI);
234 virtual LiveInterval *dequeue();
235 virtual unsigned selectOrSplit(LiveInterval&,
236 SmallVectorImpl<LiveInterval*>&);
238 /// Perform register allocation.
239 virtual bool runOnMachineFunction(MachineFunction &mf);
244 void LRE_WillEraseInstruction(MachineInstr*);
245 bool LRE_CanEraseVirtReg(unsigned);
246 void LRE_WillShrinkVirtReg(unsigned);
247 void LRE_DidCloneVirtReg(unsigned, unsigned);
249 float calcSpillCost();
250 bool addSplitConstraints(InterferenceCache::Cursor, float&);
251 void addThroughConstraints(InterferenceCache::Cursor, ArrayRef<unsigned>);
252 void growRegion(GlobalSplitCandidate &Cand);
253 float calcGlobalSplitCost(GlobalSplitCandidate&);
254 bool calcCompactRegion(GlobalSplitCandidate&);
255 void splitAroundRegion(LiveRangeEdit&, ArrayRef<unsigned>);
256 void calcGapWeights(unsigned, SmallVectorImpl<float>&);
257 bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool);
258 bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&);
259 void evictInterference(LiveInterval&, unsigned,
260 SmallVectorImpl<LiveInterval*>&);
262 unsigned tryAssign(LiveInterval&, AllocationOrder&,
263 SmallVectorImpl<LiveInterval*>&);
264 unsigned tryEvict(LiveInterval&, AllocationOrder&,
265 SmallVectorImpl<LiveInterval*>&, unsigned = ~0u);
266 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
267 SmallVectorImpl<LiveInterval*>&);
268 unsigned tryBlockSplit(LiveInterval&, AllocationOrder&,
269 SmallVectorImpl<LiveInterval*>&);
270 unsigned tryLocalSplit(LiveInterval&, AllocationOrder&,
271 SmallVectorImpl<LiveInterval*>&);
272 unsigned trySplit(LiveInterval&, AllocationOrder&,
273 SmallVectorImpl<LiveInterval*>&);
275 } // end anonymous namespace
277 char RAGreedy::ID = 0;
280 const char *const RAGreedy::StageName[] = {
290 // Hysteresis to use when comparing floats.
291 // This helps stabilize decisions based on float comparisons.
292 const float Hysteresis = 0.98f;
295 FunctionPass* llvm::createGreedyRegisterAllocator() {
296 return new RAGreedy();
299 RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
300 initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
301 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
302 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
303 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
304 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
305 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
306 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
307 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
308 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
309 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
310 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
311 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
312 initializeSpillPlacementPass(*PassRegistry::getPassRegistry());
315 void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
316 AU.setPreservesCFG();
317 AU.addRequired<AliasAnalysis>();
318 AU.addPreserved<AliasAnalysis>();
319 AU.addRequired<LiveIntervals>();
320 AU.addRequired<SlotIndexes>();
321 AU.addPreserved<SlotIndexes>();
322 AU.addRequired<LiveDebugVariables>();
323 AU.addPreserved<LiveDebugVariables>();
325 AU.addRequiredID(StrongPHIEliminationID);
326 AU.addRequiredTransitiveID(RegisterCoalescerPassID);
327 AU.addRequired<CalculateSpillWeights>();
328 AU.addRequired<LiveStacks>();
329 AU.addPreserved<LiveStacks>();
330 AU.addRequired<MachineDominatorTree>();
331 AU.addPreserved<MachineDominatorTree>();
332 AU.addRequired<MachineLoopInfo>();
333 AU.addPreserved<MachineLoopInfo>();
334 AU.addRequired<VirtRegMap>();
335 AU.addPreserved<VirtRegMap>();
336 AU.addRequired<EdgeBundles>();
337 AU.addRequired<SpillPlacement>();
338 MachineFunctionPass::getAnalysisUsage(AU);
342 //===----------------------------------------------------------------------===//
343 // LiveRangeEdit delegate methods
344 //===----------------------------------------------------------------------===//
346 void RAGreedy::LRE_WillEraseInstruction(MachineInstr *MI) {
347 // LRE itself will remove from SlotIndexes and parent basic block.
348 VRM->RemoveMachineInstrFromMaps(MI);
351 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
352 if (unsigned PhysReg = VRM->getPhys(VirtReg)) {
353 unassign(LIS->getInterval(VirtReg), PhysReg);
356 // Unassigned virtreg is probably in the priority queue.
357 // RegAllocBase will erase it after dequeueing.
361 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) {
362 unsigned PhysReg = VRM->getPhys(VirtReg);
366 // Register is assigned, put it back on the queue for reassignment.
367 LiveInterval &LI = LIS->getInterval(VirtReg);
368 unassign(LI, PhysReg);
372 void RAGreedy::LRE_DidCloneVirtReg(unsigned New, unsigned Old) {
373 // LRE may clone a virtual register because dead code elimination causes it to
374 // be split into connected components. The new components are much smaller
375 // than the original, so they should get a new chance at being assigned.
376 // same stage as the parent.
377 ExtraRegInfo[Old].Stage = RS_Assign;
378 ExtraRegInfo.grow(New);
379 ExtraRegInfo[New] = ExtraRegInfo[Old];
382 void RAGreedy::releaseMemory() {
383 SpillerInstance.reset(0);
384 ExtraRegInfo.clear();
386 RegAllocBase::releaseMemory();
389 void RAGreedy::enqueue(LiveInterval *LI) {
390 // Prioritize live ranges by size, assigning larger ranges first.
391 // The queue holds (size, reg) pairs.
392 const unsigned Size = LI->getSize();
393 const unsigned Reg = LI->reg;
394 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
395 "Can only enqueue virtual registers");
398 ExtraRegInfo.grow(Reg);
399 if (ExtraRegInfo[Reg].Stage == RS_New)
400 ExtraRegInfo[Reg].Stage = RS_Assign;
402 if (ExtraRegInfo[Reg].Stage == RS_Split) {
403 // Unsplit ranges that couldn't be allocated immediately are deferred until
404 // everything else has been allocated. Long ranges are allocated last so
405 // they are split against realistic interference.
409 Prio = (1u << 31) - Size;
411 // Everything else is allocated in long->short order. Long ranges that don't
412 // fit should be spilled ASAP so they don't create interference.
413 Prio = (1u << 31) + Size;
415 // Boost ranges that have a physical register hint.
416 if (TargetRegisterInfo::isPhysicalRegister(VRM->getRegAllocPref(Reg)))
420 Queue.push(std::make_pair(Prio, Reg));
423 LiveInterval *RAGreedy::dequeue() {
426 LiveInterval *LI = &LIS->getInterval(Queue.top().second);
432 //===----------------------------------------------------------------------===//
434 //===----------------------------------------------------------------------===//
436 /// tryAssign - Try to assign VirtReg to an available register.
437 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg,
438 AllocationOrder &Order,
439 SmallVectorImpl<LiveInterval*> &NewVRegs) {
442 while ((PhysReg = Order.next()))
443 if (!checkPhysRegInterference(VirtReg, PhysReg))
445 if (!PhysReg || Order.isHint(PhysReg))
448 // PhysReg is available, but there may be a better choice.
450 // If we missed a simple hint, try to cheaply evict interference from the
451 // preferred register.
452 if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg))
453 if (Order.isHint(Hint)) {
454 DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n');
455 EvictionCost MaxCost(1);
456 if (canEvictInterference(VirtReg, Hint, true, MaxCost)) {
457 evictInterference(VirtReg, Hint, NewVRegs);
462 // Try to evict interference from a cheaper alternative.
463 unsigned Cost = TRI->getCostPerUse(PhysReg);
465 // Most registers have 0 additional cost.
469 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost
471 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
472 return CheapReg ? CheapReg : PhysReg;
476 //===----------------------------------------------------------------------===//
477 // Interference eviction
478 //===----------------------------------------------------------------------===//
480 /// shouldEvict - determine if A should evict the assigned live range B. The
481 /// eviction policy defined by this function together with the allocation order
482 /// defined by enqueue() decides which registers ultimately end up being split
485 /// Cascade numbers are used to prevent infinite loops if this function is a
488 /// @param A The live range to be assigned.
489 /// @param IsHint True when A is about to be assigned to its preferred
491 /// @param B The live range to be evicted.
492 /// @param BreaksHint True when B is already assigned to its preferred register.
493 bool RAGreedy::shouldEvict(LiveInterval &A, bool IsHint,
494 LiveInterval &B, bool BreaksHint) {
495 bool CanSplit = getStage(B) < RS_Spill;
497 // Be fairly aggressive about following hints as long as the evictee can be
499 if (CanSplit && IsHint && !BreaksHint)
502 return A.weight > B.weight;
505 /// canEvictInterference - Return true if all interferences between VirtReg and
506 /// PhysReg can be evicted. When OnlyCheap is set, don't do anything
508 /// @param VirtReg Live range that is about to be assigned.
509 /// @param PhysReg Desired register for assignment.
510 /// @prarm IsHint True when PhysReg is VirtReg's preferred register.
511 /// @param MaxCost Only look for cheaper candidates and update with new cost
512 /// when returning true.
513 /// @returns True when interference can be evicted cheaper than MaxCost.
514 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
515 bool IsHint, EvictionCost &MaxCost) {
516 // Find VirtReg's cascade number. This will be unassigned if VirtReg was never
517 // involved in an eviction before. If a cascade number was assigned, deny
518 // evicting anything with the same or a newer cascade number. This prevents
519 // infinite eviction loops.
521 // This works out so a register without a cascade number is allowed to evict
522 // anything, and it can be evicted by anything.
523 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
525 Cascade = NextCascade;
528 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
529 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
530 // If there is 10 or more interferences, chances are one is heavier.
531 if (Q.collectInterferingVRegs(10) >= 10)
534 // Check if any interfering live range is heavier than MaxWeight.
535 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
536 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
537 if (TargetRegisterInfo::isPhysicalRegister(Intf->reg))
539 // Never evict spill products. They cannot split or spill.
540 if (getStage(*Intf) == RS_Done)
542 // Once a live range becomes small enough, it is urgent that we find a
543 // register for it. This is indicated by an infinite spill weight. These
544 // urgent live ranges get to evict almost anything.
545 bool Urgent = !VirtReg.isSpillable() && Intf->isSpillable();
546 // Only evict older cascades or live ranges without a cascade.
547 unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;
548 if (Cascade <= IntfCascade) {
551 // We permit breaking cascades for urgent evictions. It should be the
552 // last resort, though, so make it really expensive.
553 Cost.BrokenHints += 10;
555 // Would this break a satisfied hint?
556 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg);
557 // Update eviction cost.
558 Cost.BrokenHints += BreaksHint;
559 Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight);
560 // Abort if this would be too expensive.
561 if (!(Cost < MaxCost))
563 // Finally, apply the eviction policy for non-urgent evictions.
564 if (!Urgent && !shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
572 /// evictInterference - Evict any interferring registers that prevent VirtReg
573 /// from being assigned to Physreg. This assumes that canEvictInterference
575 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg,
576 SmallVectorImpl<LiveInterval*> &NewVRegs) {
577 // Make sure that VirtReg has a cascade number, and assign that cascade
578 // number to every evicted register. These live ranges than then only be
579 // evicted by a newer cascade, preventing infinite loops.
580 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
582 Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;
584 DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI)
585 << " interference: Cascade " << Cascade << '\n');
586 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
587 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
588 assert(Q.seenAllInterferences() && "Didn't check all interfererences.");
589 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
590 LiveInterval *Intf = Q.interferingVRegs()[i];
591 unassign(*Intf, VRM->getPhys(Intf->reg));
592 assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||
593 VirtReg.isSpillable() < Intf->isSpillable()) &&
594 "Cannot decrease cascade number, illegal eviction");
595 ExtraRegInfo[Intf->reg].Cascade = Cascade;
597 NewVRegs.push_back(Intf);
602 /// tryEvict - Try to evict all interferences for a physreg.
603 /// @param VirtReg Currently unassigned virtual register.
604 /// @param Order Physregs to try.
605 /// @return Physreg to assign VirtReg, or 0.
606 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
607 AllocationOrder &Order,
608 SmallVectorImpl<LiveInterval*> &NewVRegs,
609 unsigned CostPerUseLimit) {
610 NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled);
612 // Keep track of the cheapest interference seen so far.
613 EvictionCost BestCost(~0u);
614 unsigned BestPhys = 0;
616 // When we are just looking for a reduced cost per use, don't break any
617 // hints, and only evict smaller spill weights.
618 if (CostPerUseLimit < ~0u) {
619 BestCost.BrokenHints = 0;
620 BestCost.MaxWeight = VirtReg.weight;
624 while (unsigned PhysReg = Order.next()) {
625 if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit)
627 // The first use of a callee-saved register in a function has cost 1.
628 // Don't start using a CSR when the CostPerUseLimit is low.
629 if (CostPerUseLimit == 1)
630 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
631 if (!MRI->isPhysRegUsed(CSR)) {
632 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR "
633 << PrintReg(CSR, TRI) << '\n');
637 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost))
643 // Stop if the hint can be used.
644 if (Order.isHint(PhysReg))
651 evictInterference(VirtReg, BestPhys, NewVRegs);
656 //===----------------------------------------------------------------------===//
658 //===----------------------------------------------------------------------===//
660 /// addSplitConstraints - Fill out the SplitConstraints vector based on the
661 /// interference pattern in Physreg and its aliases. Add the constraints to
662 /// SpillPlacement and return the static cost of this split in Cost, assuming
663 /// that all preferences in SplitConstraints are met.
664 /// Return false if there are no bundles with positive bias.
665 bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
667 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
669 // Reset interference dependent info.
670 SplitConstraints.resize(UseBlocks.size());
671 float StaticCost = 0;
672 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
673 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
674 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
676 BC.Number = BI.MBB->getNumber();
677 Intf.moveToBlock(BC.Number);
678 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
679 BC.Exit = BI.LiveOut ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
680 BC.ChangesValue = BI.FirstDef;
682 if (!Intf.hasInterference())
685 // Number of spill code instructions to insert.
688 // Interference for the live-in value.
690 if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number))
691 BC.Entry = SpillPlacement::MustSpill, ++Ins;
692 else if (Intf.first() < BI.FirstInstr)
693 BC.Entry = SpillPlacement::PrefSpill, ++Ins;
694 else if (Intf.first() < BI.LastInstr)
698 // Interference for the live-out value.
700 if (Intf.last() >= SA->getLastSplitPoint(BC.Number))
701 BC.Exit = SpillPlacement::MustSpill, ++Ins;
702 else if (Intf.last() > BI.LastInstr)
703 BC.Exit = SpillPlacement::PrefSpill, ++Ins;
704 else if (Intf.last() > BI.FirstInstr)
708 // Accumulate the total frequency of inserted spill code.
710 StaticCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
714 // Add constraints for use-blocks. Note that these are the only constraints
715 // that may add a positive bias, it is downhill from here.
716 SpillPlacer->addConstraints(SplitConstraints);
717 return SpillPlacer->scanActiveBundles();
721 /// addThroughConstraints - Add constraints and links to SpillPlacer from the
722 /// live-through blocks in Blocks.
723 void RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
724 ArrayRef<unsigned> Blocks) {
725 const unsigned GroupSize = 8;
726 SpillPlacement::BlockConstraint BCS[GroupSize];
727 unsigned TBS[GroupSize];
728 unsigned B = 0, T = 0;
730 for (unsigned i = 0; i != Blocks.size(); ++i) {
731 unsigned Number = Blocks[i];
732 Intf.moveToBlock(Number);
734 if (!Intf.hasInterference()) {
735 assert(T < GroupSize && "Array overflow");
737 if (++T == GroupSize) {
738 SpillPlacer->addLinks(makeArrayRef(TBS, T));
744 assert(B < GroupSize && "Array overflow");
745 BCS[B].Number = Number;
747 // Interference for the live-in value.
748 if (Intf.first() <= Indexes->getMBBStartIdx(Number))
749 BCS[B].Entry = SpillPlacement::MustSpill;
751 BCS[B].Entry = SpillPlacement::PrefSpill;
753 // Interference for the live-out value.
754 if (Intf.last() >= SA->getLastSplitPoint(Number))
755 BCS[B].Exit = SpillPlacement::MustSpill;
757 BCS[B].Exit = SpillPlacement::PrefSpill;
759 if (++B == GroupSize) {
760 ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B);
761 SpillPlacer->addConstraints(Array);
766 ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B);
767 SpillPlacer->addConstraints(Array);
768 SpillPlacer->addLinks(makeArrayRef(TBS, T));
771 void RAGreedy::growRegion(GlobalSplitCandidate &Cand) {
772 // Keep track of through blocks that have not been added to SpillPlacer.
773 BitVector Todo = SA->getThroughBlocks();
774 SmallVectorImpl<unsigned> &ActiveBlocks = Cand.ActiveBlocks;
775 unsigned AddedTo = 0;
777 unsigned Visited = 0;
781 ArrayRef<unsigned> NewBundles = SpillPlacer->getRecentPositive();
782 // Find new through blocks in the periphery of PrefRegBundles.
783 for (int i = 0, e = NewBundles.size(); i != e; ++i) {
784 unsigned Bundle = NewBundles[i];
785 // Look at all blocks connected to Bundle in the full graph.
786 ArrayRef<unsigned> Blocks = Bundles->getBlocks(Bundle);
787 for (ArrayRef<unsigned>::iterator I = Blocks.begin(), E = Blocks.end();
790 if (!Todo.test(Block))
793 // This is a new through block. Add it to SpillPlacer later.
794 ActiveBlocks.push_back(Block);
800 // Any new blocks to add?
801 if (ActiveBlocks.size() == AddedTo)
804 // Compute through constraints from the interference, or assume that all
805 // through blocks prefer spilling when forming compact regions.
806 ArrayRef<unsigned> NewBlocks = makeArrayRef(ActiveBlocks).slice(AddedTo);
808 addThroughConstraints(Cand.Intf, NewBlocks);
810 // Provide a strong negative bias on through blocks to prevent unwanted
811 // liveness on loop backedges.
812 SpillPlacer->addPrefSpill(NewBlocks, /* Strong= */ true);
813 AddedTo = ActiveBlocks.size();
815 // Perhaps iterating can enable more bundles?
816 SpillPlacer->iterate();
818 DEBUG(dbgs() << ", v=" << Visited);
821 /// calcCompactRegion - Compute the set of edge bundles that should be live
822 /// when splitting the current live range into compact regions. Compact
823 /// regions can be computed without looking at interference. They are the
824 /// regions formed by removing all the live-through blocks from the live range.
826 /// Returns false if the current live range is already compact, or if the
827 /// compact regions would form single block regions anyway.
828 bool RAGreedy::calcCompactRegion(GlobalSplitCandidate &Cand) {
829 // Without any through blocks, the live range is already compact.
830 if (!SA->getNumThroughBlocks())
833 // Compact regions don't correspond to any physreg.
834 Cand.reset(IntfCache, 0);
836 DEBUG(dbgs() << "Compact region bundles");
838 // Use the spill placer to determine the live bundles. GrowRegion pretends
839 // that all the through blocks have interference when PhysReg is unset.
840 SpillPlacer->prepare(Cand.LiveBundles);
842 // The static split cost will be zero since Cand.Intf reports no interference.
844 if (!addSplitConstraints(Cand.Intf, Cost)) {
845 DEBUG(dbgs() << ", none.\n");
850 SpillPlacer->finish();
852 if (!Cand.LiveBundles.any()) {
853 DEBUG(dbgs() << ", none.\n");
858 for (int i = Cand.LiveBundles.find_first(); i>=0;
859 i = Cand.LiveBundles.find_next(i))
860 dbgs() << " EB#" << i;
866 /// calcSpillCost - Compute how expensive it would be to split the live range in
867 /// SA around all use blocks instead of forming bundle regions.
868 float RAGreedy::calcSpillCost() {
870 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
871 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
872 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
873 unsigned Number = BI.MBB->getNumber();
874 // We normally only need one spill instruction - a load or a store.
875 Cost += SpillPlacer->getBlockFrequency(Number);
877 // Unless the value is redefined in the block.
878 if (BI.LiveIn && BI.LiveOut && BI.FirstDef)
879 Cost += SpillPlacer->getBlockFrequency(Number);
884 /// calcGlobalSplitCost - Return the global split cost of following the split
885 /// pattern in LiveBundles. This cost should be added to the local cost of the
886 /// interference pattern in SplitConstraints.
888 float RAGreedy::calcGlobalSplitCost(GlobalSplitCandidate &Cand) {
889 float GlobalCost = 0;
890 const BitVector &LiveBundles = Cand.LiveBundles;
891 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
892 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
893 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
894 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
895 bool RegIn = LiveBundles[Bundles->getBundle(BC.Number, 0)];
896 bool RegOut = LiveBundles[Bundles->getBundle(BC.Number, 1)];
900 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg);
902 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg);
904 GlobalCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
907 for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) {
908 unsigned Number = Cand.ActiveBlocks[i];
909 bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)];
910 bool RegOut = LiveBundles[Bundles->getBundle(Number, 1)];
911 if (!RegIn && !RegOut)
913 if (RegIn && RegOut) {
914 // We need double spill code if this block has interference.
915 Cand.Intf.moveToBlock(Number);
916 if (Cand.Intf.hasInterference())
917 GlobalCost += 2*SpillPlacer->getBlockFrequency(Number);
920 // live-in / stack-out or stack-in live-out.
921 GlobalCost += SpillPlacer->getBlockFrequency(Number);
926 /// splitAroundRegion - Split the current live range around the regions
927 /// determined by BundleCand and GlobalCand.
929 /// Before calling this function, GlobalCand and BundleCand must be initialized
930 /// so each bundle is assigned to a valid candidate, or NoCand for the
931 /// stack-bound bundles. The shared SA/SE SplitAnalysis and SplitEditor
932 /// objects must be initialized for the current live range, and intervals
933 /// created for the used candidates.
935 /// @param LREdit The LiveRangeEdit object handling the current split.
936 /// @param UsedCands List of used GlobalCand entries. Every BundleCand value
937 /// must appear in this list.
938 void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit,
939 ArrayRef<unsigned> UsedCands) {
940 // These are the intervals created for new global ranges. We may create more
941 // intervals for local ranges.
942 const unsigned NumGlobalIntvs = LREdit.size();
943 DEBUG(dbgs() << "splitAroundRegion with " << NumGlobalIntvs << " globals.\n");
944 assert(NumGlobalIntvs && "No global intervals configured");
946 // Isolate even single instructions when dealing with a proper sub-class.
947 // That guarantees register class inflation for the stack interval because it
949 unsigned Reg = SA->getParent().reg;
950 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
952 // First handle all the blocks with uses.
953 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
954 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
955 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
956 unsigned Number = BI.MBB->getNumber();
957 unsigned IntvIn = 0, IntvOut = 0;
958 SlotIndex IntfIn, IntfOut;
960 unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)];
961 if (CandIn != NoCand) {
962 GlobalSplitCandidate &Cand = GlobalCand[CandIn];
963 IntvIn = Cand.IntvIdx;
964 Cand.Intf.moveToBlock(Number);
965 IntfIn = Cand.Intf.first();
969 unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)];
970 if (CandOut != NoCand) {
971 GlobalSplitCandidate &Cand = GlobalCand[CandOut];
972 IntvOut = Cand.IntvIdx;
973 Cand.Intf.moveToBlock(Number);
974 IntfOut = Cand.Intf.last();
978 // Create separate intervals for isolated blocks with multiple uses.
979 if (!IntvIn && !IntvOut) {
980 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n");
981 if (SA->shouldSplitSingleBlock(BI, SingleInstrs))
982 SE->splitSingleBlock(BI);
986 if (IntvIn && IntvOut)
987 SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut);
989 SE->splitRegInBlock(BI, IntvIn, IntfIn);
991 SE->splitRegOutBlock(BI, IntvOut, IntfOut);
994 // Handle live-through blocks. The relevant live-through blocks are stored in
995 // the ActiveBlocks list with each candidate. We need to filter out
997 BitVector Todo = SA->getThroughBlocks();
998 for (unsigned c = 0; c != UsedCands.size(); ++c) {
999 ArrayRef<unsigned> Blocks = GlobalCand[UsedCands[c]].ActiveBlocks;
1000 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
1001 unsigned Number = Blocks[i];
1002 if (!Todo.test(Number))
1006 unsigned IntvIn = 0, IntvOut = 0;
1007 SlotIndex IntfIn, IntfOut;
1009 unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)];
1010 if (CandIn != NoCand) {
1011 GlobalSplitCandidate &Cand = GlobalCand[CandIn];
1012 IntvIn = Cand.IntvIdx;
1013 Cand.Intf.moveToBlock(Number);
1014 IntfIn = Cand.Intf.first();
1017 unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)];
1018 if (CandOut != NoCand) {
1019 GlobalSplitCandidate &Cand = GlobalCand[CandOut];
1020 IntvOut = Cand.IntvIdx;
1021 Cand.Intf.moveToBlock(Number);
1022 IntfOut = Cand.Intf.last();
1024 if (!IntvIn && !IntvOut)
1026 SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut);
1032 SmallVector<unsigned, 8> IntvMap;
1033 SE->finish(&IntvMap);
1034 DebugVars->splitRegister(Reg, LREdit.regs());
1036 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1037 unsigned OrigBlocks = SA->getNumLiveBlocks();
1039 // Sort out the new intervals created by splitting. We get four kinds:
1040 // - Remainder intervals should not be split again.
1041 // - Candidate intervals can be assigned to Cand.PhysReg.
1042 // - Block-local splits are candidates for local splitting.
1043 // - DCE leftovers should go back on the queue.
1044 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) {
1045 LiveInterval &Reg = *LREdit.get(i);
1047 // Ignore old intervals from DCE.
1048 if (getStage(Reg) != RS_New)
1051 // Remainder interval. Don't try splitting again, spill if it doesn't
1053 if (IntvMap[i] == 0) {
1054 setStage(Reg, RS_Spill);
1058 // Global intervals. Allow repeated splitting as long as the number of live
1059 // blocks is strictly decreasing.
1060 if (IntvMap[i] < NumGlobalIntvs) {
1061 if (SA->countLiveBlocks(&Reg) >= OrigBlocks) {
1062 DEBUG(dbgs() << "Main interval covers the same " << OrigBlocks
1063 << " blocks as original.\n");
1064 // Don't allow repeated splitting as a safe guard against looping.
1065 setStage(Reg, RS_Split2);
1070 // Other intervals are treated as new. This includes local intervals created
1071 // for blocks with multiple uses, and anything created by DCE.
1075 MF->verify(this, "After splitting live range around region");
1078 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1079 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1080 unsigned NumCands = 0;
1081 unsigned BestCand = NoCand;
1083 SmallVector<unsigned, 8> UsedCands;
1085 // Check if we can split this live range around a compact region.
1086 bool HasCompact = CompactRegions && calcCompactRegion(GlobalCand.front());
1088 // Yes, keep GlobalCand[0] as the compact region candidate.
1090 BestCost = HUGE_VALF;
1092 // No benefit from the compact region, our fallback will be per-block
1093 // splitting. Make sure we find a solution that is cheaper than spilling.
1094 BestCost = Hysteresis * calcSpillCost();
1095 DEBUG(dbgs() << "Cost of isolating all blocks = " << BestCost << '\n');
1099 while (unsigned PhysReg = Order.next()) {
1100 // Discard bad candidates before we run out of interference cache cursors.
1101 // This will only affect register classes with a lot of registers (>32).
1102 if (NumCands == IntfCache.getMaxCursors()) {
1103 unsigned WorstCount = ~0u;
1105 for (unsigned i = 0; i != NumCands; ++i) {
1106 if (i == BestCand || !GlobalCand[i].PhysReg)
1108 unsigned Count = GlobalCand[i].LiveBundles.count();
1109 if (Count < WorstCount)
1110 Worst = i, WorstCount = Count;
1113 GlobalCand[Worst] = GlobalCand[NumCands];
1116 if (GlobalCand.size() <= NumCands)
1117 GlobalCand.resize(NumCands+1);
1118 GlobalSplitCandidate &Cand = GlobalCand[NumCands];
1119 Cand.reset(IntfCache, PhysReg);
1121 SpillPlacer->prepare(Cand.LiveBundles);
1123 if (!addSplitConstraints(Cand.Intf, Cost)) {
1124 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n");
1127 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = " << Cost);
1128 if (Cost >= BestCost) {
1130 if (BestCand == NoCand)
1131 dbgs() << " worse than no bundles\n";
1133 dbgs() << " worse than "
1134 << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
1140 SpillPlacer->finish();
1142 // No live bundles, defer to splitSingleBlocks().
1143 if (!Cand.LiveBundles.any()) {
1144 DEBUG(dbgs() << " no bundles.\n");
1148 Cost += calcGlobalSplitCost(Cand);
1150 dbgs() << ", total = " << Cost << " with bundles";
1151 for (int i = Cand.LiveBundles.find_first(); i>=0;
1152 i = Cand.LiveBundles.find_next(i))
1153 dbgs() << " EB#" << i;
1156 if (Cost < BestCost) {
1157 BestCand = NumCands;
1158 BestCost = Hysteresis * Cost; // Prevent rounding effects.
1163 // No solutions found, fall back to single block splitting.
1164 if (!HasCompact && BestCand == NoCand)
1167 // Prepare split editor.
1168 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
1171 // Assign all edge bundles to the preferred candidate, or NoCand.
1172 BundleCand.assign(Bundles->getNumBundles(), NoCand);
1174 // Assign bundles for the best candidate region.
1175 if (BestCand != NoCand) {
1176 GlobalSplitCandidate &Cand = GlobalCand[BestCand];
1177 if (unsigned B = Cand.getBundles(BundleCand, BestCand)) {
1178 UsedCands.push_back(BestCand);
1179 Cand.IntvIdx = SE->openIntv();
1180 DEBUG(dbgs() << "Split for " << PrintReg(Cand.PhysReg, TRI) << " in "
1181 << B << " bundles, intv " << Cand.IntvIdx << ".\n");
1186 // Assign bundles for the compact region.
1188 GlobalSplitCandidate &Cand = GlobalCand.front();
1189 assert(!Cand.PhysReg && "Compact region has no physreg");
1190 if (unsigned B = Cand.getBundles(BundleCand, 0)) {
1191 UsedCands.push_back(0);
1192 Cand.IntvIdx = SE->openIntv();
1193 DEBUG(dbgs() << "Split for compact region in " << B << " bundles, intv "
1194 << Cand.IntvIdx << ".\n");
1199 splitAroundRegion(LREdit, UsedCands);
1204 //===----------------------------------------------------------------------===//
1205 // Per-Block Splitting
1206 //===----------------------------------------------------------------------===//
1208 /// tryBlockSplit - Split a global live range around every block with uses. This
1209 /// creates a lot of local live ranges, that will be split by tryLocalSplit if
1210 /// they don't allocate.
1211 unsigned RAGreedy::tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1212 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1213 assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed");
1214 unsigned Reg = VirtReg.reg;
1215 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1216 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
1218 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1219 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1220 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1221 if (SA->shouldSplitSingleBlock(BI, SingleInstrs))
1222 SE->splitSingleBlock(BI);
1224 // No blocks were split.
1228 // We did split for some blocks.
1229 SmallVector<unsigned, 8> IntvMap;
1230 SE->finish(&IntvMap);
1232 // Tell LiveDebugVariables about the new ranges.
1233 DebugVars->splitRegister(Reg, LREdit.regs());
1235 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1237 // Sort out the new intervals created by splitting. The remainder interval
1238 // goes straight to spilling, the new local ranges get to stay RS_New.
1239 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) {
1240 LiveInterval &LI = *LREdit.get(i);
1241 if (getStage(LI) == RS_New && IntvMap[i] == 0)
1242 setStage(LI, RS_Spill);
1246 MF->verify(this, "After splitting live range around basic blocks");
1250 //===----------------------------------------------------------------------===//
1252 //===----------------------------------------------------------------------===//
1255 /// calcGapWeights - Compute the maximum spill weight that needs to be evicted
1256 /// in order to use PhysReg between two entries in SA->UseSlots.
1258 /// GapWeight[i] represents the gap between UseSlots[i] and UseSlots[i+1].
1260 void RAGreedy::calcGapWeights(unsigned PhysReg,
1261 SmallVectorImpl<float> &GapWeight) {
1262 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
1263 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
1264 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
1265 const unsigned NumGaps = Uses.size()-1;
1267 // Start and end points for the interference check.
1268 SlotIndex StartIdx =
1269 BI.LiveIn ? BI.FirstInstr.getBaseIndex() : BI.FirstInstr;
1271 BI.LiveOut ? BI.LastInstr.getBoundaryIndex() : BI.LastInstr;
1273 GapWeight.assign(NumGaps, 0.0f);
1275 // Add interference from each overlapping register.
1276 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
1277 if (!query(const_cast<LiveInterval&>(SA->getParent()), *AI)
1278 .checkInterference())
1281 // We know that VirtReg is a continuous interval from FirstInstr to
1282 // LastInstr, so we don't need InterferenceQuery.
1284 // Interference that overlaps an instruction is counted in both gaps
1285 // surrounding the instruction. The exception is interference before
1286 // StartIdx and after StopIdx.
1288 LiveIntervalUnion::SegmentIter IntI = PhysReg2LiveUnion[*AI].find(StartIdx);
1289 for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) {
1290 // Skip the gaps before IntI.
1291 while (Uses[Gap+1].getBoundaryIndex() < IntI.start())
1292 if (++Gap == NumGaps)
1297 // Update the gaps covered by IntI.
1298 const float weight = IntI.value()->weight;
1299 for (; Gap != NumGaps; ++Gap) {
1300 GapWeight[Gap] = std::max(GapWeight[Gap], weight);
1301 if (Uses[Gap+1].getBaseIndex() >= IntI.stop())
1310 /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
1313 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1314 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1315 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
1316 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
1318 // Note that it is possible to have an interval that is live-in or live-out
1319 // while only covering a single block - A phi-def can use undef values from
1320 // predecessors, and the block could be a single-block loop.
1321 // We don't bother doing anything clever about such a case, we simply assume
1322 // that the interval is continuous from FirstInstr to LastInstr. We should
1323 // make sure that we don't do anything illegal to such an interval, though.
1325 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
1326 if (Uses.size() <= 2)
1328 const unsigned NumGaps = Uses.size()-1;
1331 dbgs() << "tryLocalSplit: ";
1332 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
1333 dbgs() << ' ' << SA->UseSlots[i];
1337 // Since we allow local split results to be split again, there is a risk of
1338 // creating infinite loops. It is tempting to require that the new live
1339 // ranges have less instructions than the original. That would guarantee
1340 // convergence, but it is too strict. A live range with 3 instructions can be
1341 // split 2+3 (including the COPY), and we want to allow that.
1343 // Instead we use these rules:
1345 // 1. Allow any split for ranges with getStage() < RS_Split2. (Except for the
1346 // noop split, of course).
1347 // 2. Require progress be made for ranges with getStage() == RS_Split2. All
1348 // the new ranges must have fewer instructions than before the split.
1349 // 3. New ranges with the same number of instructions are marked RS_Split2,
1350 // smaller ranges are marked RS_New.
1352 // These rules allow a 3 -> 2+3 split once, which we need. They also prevent
1353 // excessive splitting and infinite loops.
1355 bool ProgressRequired = getStage(VirtReg) >= RS_Split2;
1357 // Best split candidate.
1358 unsigned BestBefore = NumGaps;
1359 unsigned BestAfter = 0;
1362 const float blockFreq = SpillPlacer->getBlockFrequency(BI.MBB->getNumber());
1363 SmallVector<float, 8> GapWeight;
1366 while (unsigned PhysReg = Order.next()) {
1367 // Keep track of the largest spill weight that would need to be evicted in
1368 // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1].
1369 calcGapWeights(PhysReg, GapWeight);
1371 // Try to find the best sequence of gaps to close.
1372 // The new spill weight must be larger than any gap interference.
1374 // We will split before Uses[SplitBefore] and after Uses[SplitAfter].
1375 unsigned SplitBefore = 0, SplitAfter = 1;
1377 // MaxGap should always be max(GapWeight[SplitBefore..SplitAfter-1]).
1378 // It is the spill weight that needs to be evicted.
1379 float MaxGap = GapWeight[0];
1382 // Live before/after split?
1383 const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
1384 const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut;
1386 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' '
1387 << Uses[SplitBefore] << '-' << Uses[SplitAfter]
1388 << " i=" << MaxGap);
1390 // Stop before the interval gets so big we wouldn't be making progress.
1391 if (!LiveBefore && !LiveAfter) {
1392 DEBUG(dbgs() << " all\n");
1395 // Should the interval be extended or shrunk?
1398 // How many gaps would the new range have?
1399 unsigned NewGaps = LiveBefore + SplitAfter - SplitBefore + LiveAfter;
1401 // Legally, without causing looping?
1402 bool Legal = !ProgressRequired || NewGaps < NumGaps;
1404 if (Legal && MaxGap < HUGE_VALF) {
1405 // Estimate the new spill weight. Each instruction reads or writes the
1406 // register. Conservatively assume there are no read-modify-write
1409 // Try to guess the size of the new interval.
1410 const float EstWeight = normalizeSpillWeight(blockFreq * (NewGaps + 1),
1411 Uses[SplitBefore].distance(Uses[SplitAfter]) +
1412 (LiveBefore + LiveAfter)*SlotIndex::InstrDist);
1413 // Would this split be possible to allocate?
1414 // Never allocate all gaps, we wouldn't be making progress.
1415 DEBUG(dbgs() << " w=" << EstWeight);
1416 if (EstWeight * Hysteresis >= MaxGap) {
1418 float Diff = EstWeight - MaxGap;
1419 if (Diff > BestDiff) {
1420 DEBUG(dbgs() << " (best)");
1421 BestDiff = Hysteresis * Diff;
1422 BestBefore = SplitBefore;
1423 BestAfter = SplitAfter;
1430 if (++SplitBefore < SplitAfter) {
1431 DEBUG(dbgs() << " shrink\n");
1432 // Recompute the max when necessary.
1433 if (GapWeight[SplitBefore - 1] >= MaxGap) {
1434 MaxGap = GapWeight[SplitBefore];
1435 for (unsigned i = SplitBefore + 1; i != SplitAfter; ++i)
1436 MaxGap = std::max(MaxGap, GapWeight[i]);
1443 // Try to extend the interval.
1444 if (SplitAfter >= NumGaps) {
1445 DEBUG(dbgs() << " end\n");
1449 DEBUG(dbgs() << " extend\n");
1450 MaxGap = std::max(MaxGap, GapWeight[SplitAfter++]);
1454 // Didn't find any candidates?
1455 if (BestBefore == NumGaps)
1458 DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore]
1459 << '-' << Uses[BestAfter] << ", " << BestDiff
1460 << ", " << (BestAfter - BestBefore + 1) << " instrs\n");
1462 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
1466 SlotIndex SegStart = SE->enterIntvBefore(Uses[BestBefore]);
1467 SlotIndex SegStop = SE->leaveIntvAfter(Uses[BestAfter]);
1468 SE->useIntv(SegStart, SegStop);
1469 SmallVector<unsigned, 8> IntvMap;
1470 SE->finish(&IntvMap);
1471 DebugVars->splitRegister(VirtReg.reg, LREdit.regs());
1473 // If the new range has the same number of instructions as before, mark it as
1474 // RS_Split2 so the next split will be forced to make progress. Otherwise,
1475 // leave the new intervals as RS_New so they can compete.
1476 bool LiveBefore = BestBefore != 0 || BI.LiveIn;
1477 bool LiveAfter = BestAfter != NumGaps || BI.LiveOut;
1478 unsigned NewGaps = LiveBefore + BestAfter - BestBefore + LiveAfter;
1479 if (NewGaps >= NumGaps) {
1480 DEBUG(dbgs() << "Tagging non-progress ranges: ");
1481 assert(!ProgressRequired && "Didn't make progress when it was required.");
1482 for (unsigned i = 0, e = IntvMap.size(); i != e; ++i)
1483 if (IntvMap[i] == 1) {
1484 setStage(*LREdit.get(i), RS_Split2);
1485 DEBUG(dbgs() << PrintReg(LREdit.get(i)->reg));
1487 DEBUG(dbgs() << '\n');
1494 //===----------------------------------------------------------------------===//
1495 // Live Range Splitting
1496 //===----------------------------------------------------------------------===//
1498 /// trySplit - Try to split VirtReg or one of its interferences, making it
1500 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
1501 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
1502 SmallVectorImpl<LiveInterval*>&NewVRegs) {
1503 // Ranges must be Split2 or less.
1504 if (getStage(VirtReg) >= RS_Spill)
1507 // Local intervals are handled separately.
1508 if (LIS->intervalIsInOneMBB(VirtReg)) {
1509 NamedRegionTimer T("Local Splitting", TimerGroupName, TimePassesIsEnabled);
1510 SA->analyze(&VirtReg);
1511 return tryLocalSplit(VirtReg, Order, NewVRegs);
1514 NamedRegionTimer T("Global Splitting", TimerGroupName, TimePassesIsEnabled);
1516 SA->analyze(&VirtReg);
1518 // FIXME: SplitAnalysis may repair broken live ranges coming from the
1519 // coalescer. That may cause the range to become allocatable which means that
1520 // tryRegionSplit won't be making progress. This check should be replaced with
1521 // an assertion when the coalescer is fixed.
1522 if (SA->didRepairRange()) {
1523 // VirtReg has changed, so all cached queries are invalid.
1524 invalidateVirtRegs();
1525 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
1529 // First try to split around a region spanning multiple blocks. RS_Split2
1530 // ranges already made dubious progress with region splitting, so they go
1531 // straight to single block splitting.
1532 if (getStage(VirtReg) < RS_Split2) {
1533 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1534 if (PhysReg || !NewVRegs.empty())
1538 // Then isolate blocks.
1539 return tryBlockSplit(VirtReg, Order, NewVRegs);
1543 //===----------------------------------------------------------------------===//
1545 //===----------------------------------------------------------------------===//
1547 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
1548 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1549 // First try assigning a free register.
1550 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
1551 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
1554 LiveRangeStage Stage = getStage(VirtReg);
1555 DEBUG(dbgs() << StageName[Stage]
1556 << " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n');
1558 // Try to evict a less worthy live range, but only for ranges from the primary
1559 // queue. The RS_Split ranges already failed to do this, and they should not
1560 // get a second chance until they have been split.
1561 if (Stage != RS_Split)
1562 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs))
1565 assert(NewVRegs.empty() && "Cannot append to existing NewVRegs");
1567 // The first time we see a live range, don't try to split or spill.
1568 // Wait until the second time, when all smaller ranges have been allocated.
1569 // This gives a better picture of the interference to split around.
1570 if (Stage < RS_Split) {
1571 setStage(VirtReg, RS_Split);
1572 DEBUG(dbgs() << "wait for second round\n");
1573 NewVRegs.push_back(&VirtReg);
1577 // If we couldn't allocate a register from spilling, there is probably some
1578 // invalid inline assembly. The base class wil report it.
1579 if (Stage >= RS_Done || !VirtReg.isSpillable())
1582 // Try splitting VirtReg or interferences.
1583 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
1584 if (PhysReg || !NewVRegs.empty())
1587 // Finally spill VirtReg itself.
1588 NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
1589 LiveRangeEdit LRE(VirtReg, NewVRegs, this);
1590 spiller().spill(LRE);
1591 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Done);
1594 MF->verify(this, "After spilling");
1596 // The live virtual register requesting allocation was spilled, so tell
1597 // the caller not to allocate anything during this round.
1601 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
1602 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
1603 << "********** Function: "
1604 << ((Value*)mf.getFunction())->getName() << '\n');
1608 MF->verify(this, "Before greedy register allocator");
1610 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
1611 Indexes = &getAnalysis<SlotIndexes>();
1612 DomTree = &getAnalysis<MachineDominatorTree>();
1613 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
1614 Loops = &getAnalysis<MachineLoopInfo>();
1615 Bundles = &getAnalysis<EdgeBundles>();
1616 SpillPlacer = &getAnalysis<SpillPlacement>();
1617 DebugVars = &getAnalysis<LiveDebugVariables>();
1619 SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops));
1620 SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree));
1621 ExtraRegInfo.clear();
1622 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1624 IntfCache.init(MF, &PhysReg2LiveUnion[0], Indexes, TRI);
1625 GlobalCand.resize(32); // This will grow as needed.
1629 LIS->addKillFlags();
1633 NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled);
1634 VRM->rewrite(Indexes);
1637 // Write out new DBG_VALUE instructions.
1639 NamedRegionTimer T("Emit Debug Info", TimerGroupName, TimePassesIsEnabled);
1640 DebugVars->emitDebugValues(VRM);
1643 // The pass output is in VirtRegMap. Release all the transient data.