1 //===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RAGreedy function pass for register allocation in
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/Passes.h"
16 #include "AllocationOrder.h"
17 #include "InterferenceCache.h"
18 #include "LiveDebugVariables.h"
19 #include "RegAllocBase.h"
20 #include "SpillPlacement.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/Analysis/AliasAnalysis.h"
25 #include "llvm/CodeGen/CalcSpillWeights.h"
26 #include "llvm/CodeGen/EdgeBundles.h"
27 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
28 #include "llvm/CodeGen/LiveRangeEdit.h"
29 #include "llvm/CodeGen/LiveRegMatrix.h"
30 #include "llvm/CodeGen/LiveStackAnalysis.h"
31 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
32 #include "llvm/CodeGen/MachineDominators.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineLoopInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/RegAllocRegistry.h"
37 #include "llvm/CodeGen/RegisterClassInfo.h"
38 #include "llvm/CodeGen/VirtRegMap.h"
39 #include "llvm/IR/LLVMContext.h"
40 #include "llvm/PassAnalysisSupport.h"
41 #include "llvm/Support/BranchProbability.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/Timer.h"
46 #include "llvm/Support/raw_ostream.h"
47 #include "llvm/Target/TargetSubtargetInfo.h"
52 #define DEBUG_TYPE "regalloc"
54 STATISTIC(NumGlobalSplits, "Number of split global live ranges");
55 STATISTIC(NumLocalSplits, "Number of split local live ranges");
56 STATISTIC(NumEvicted, "Number of interferences evicted");
58 static cl::opt<SplitEditor::ComplementSpillMode>
59 SplitSpillMode("split-spill-mode", cl::Hidden,
60 cl::desc("Spill mode for splitting live ranges"),
61 cl::values(clEnumValN(SplitEditor::SM_Partition, "default", "Default"),
62 clEnumValN(SplitEditor::SM_Size, "size", "Optimize for size"),
63 clEnumValN(SplitEditor::SM_Speed, "speed", "Optimize for speed"),
65 cl::init(SplitEditor::SM_Partition));
67 static cl::opt<unsigned>
68 LastChanceRecoloringMaxDepth("lcr-max-depth", cl::Hidden,
69 cl::desc("Last chance recoloring max depth"),
72 static cl::opt<unsigned> LastChanceRecoloringMaxInterference(
73 "lcr-max-interf", cl::Hidden,
74 cl::desc("Last chance recoloring maximum number of considered"
75 " interference at a time"),
79 ExhaustiveSearch("exhaustive-register-search", cl::NotHidden,
80 cl::desc("Exhaustive Search for registers bypassing the depth "
81 "and interference cutoffs of last chance recoloring"));
83 static cl::opt<bool> EnableLocalReassignment(
84 "enable-local-reassign", cl::Hidden,
85 cl::desc("Local reassignment can yield better allocation decisions, but "
86 "may be compile time intensive"),
89 // FIXME: Find a good default for this flag and remove the flag.
90 static cl::opt<unsigned>
91 CSRFirstTimeCost("regalloc-csr-first-time-cost",
92 cl::desc("Cost for first time use of callee-saved register."),
93 cl::init(0), cl::Hidden);
95 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
96 createGreedyRegisterAllocator);
99 class RAGreedy : public MachineFunctionPass,
101 private LiveRangeEdit::Delegate {
102 // Convenient shortcuts.
103 typedef std::priority_queue<std::pair<unsigned, unsigned> > PQueue;
104 typedef SmallPtrSet<LiveInterval *, 4> SmallLISet;
105 typedef SmallSet<unsigned, 16> SmallVirtRegSet;
110 // Shortcuts to some useful interface.
111 const TargetInstrInfo *TII;
112 const TargetRegisterInfo *TRI;
113 RegisterClassInfo RCI;
116 SlotIndexes *Indexes;
117 MachineBlockFrequencyInfo *MBFI;
118 MachineDominatorTree *DomTree;
119 MachineLoopInfo *Loops;
120 EdgeBundles *Bundles;
121 SpillPlacement *SpillPlacer;
122 LiveDebugVariables *DebugVars;
125 std::unique_ptr<Spiller> SpillerInstance;
127 unsigned NextCascade;
129 // Live ranges pass through a number of stages as we try to allocate them.
130 // Some of the stages may also create new live ranges:
132 // - Region splitting.
133 // - Per-block splitting.
134 // - Local splitting.
137 // Ranges produced by one of the stages skip the previous stages when they are
138 // dequeued. This improves performance because we can skip interference checks
139 // that are unlikely to give any results. It also guarantees that the live
140 // range splitting algorithm terminates, something that is otherwise hard to
142 enum LiveRangeStage {
143 /// Newly created live range that has never been queued.
146 /// Only attempt assignment and eviction. Then requeue as RS_Split.
149 /// Attempt live range splitting if assignment is impossible.
152 /// Attempt more aggressive live range splitting that is guaranteed to make
153 /// progress. This is used for split products that may not be making
157 /// Live range will be spilled. No more splitting will be attempted.
160 /// There is nothing more we can do to this live range. Abort compilation
161 /// if it can't be assigned.
165 // Enum CutOffStage to keep a track whether the register allocation failed
166 // because of the cutoffs encountered in last chance recoloring.
167 // Note: This is used as bitmask. New value should be next power of 2.
169 // No cutoffs encountered
172 // lcr-max-depth cutoff encountered
175 // lcr-max-interf cutoff encountered
182 static const char *const StageName[];
185 // RegInfo - Keep additional information about each live range.
187 LiveRangeStage Stage;
189 // Cascade - Eviction loop prevention. See canEvictInterference().
192 RegInfo() : Stage(RS_New), Cascade(0) {}
195 IndexedMap<RegInfo, VirtReg2IndexFunctor> ExtraRegInfo;
197 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
198 return ExtraRegInfo[VirtReg.reg].Stage;
201 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) {
202 ExtraRegInfo.resize(MRI->getNumVirtRegs());
203 ExtraRegInfo[VirtReg.reg].Stage = Stage;
206 template<typename Iterator>
207 void setStage(Iterator Begin, Iterator End, LiveRangeStage NewStage) {
208 ExtraRegInfo.resize(MRI->getNumVirtRegs());
209 for (;Begin != End; ++Begin) {
210 unsigned Reg = *Begin;
211 if (ExtraRegInfo[Reg].Stage == RS_New)
212 ExtraRegInfo[Reg].Stage = NewStage;
216 /// Cost of evicting interference.
217 struct EvictionCost {
218 unsigned BrokenHints; ///< Total number of broken hints.
219 float MaxWeight; ///< Maximum spill weight evicted.
221 EvictionCost(): BrokenHints(0), MaxWeight(0) {}
223 bool isMax() const { return BrokenHints == ~0u; }
225 void setMax() { BrokenHints = ~0u; }
227 void setBrokenHints(unsigned NHints) { BrokenHints = NHints; }
229 bool operator<(const EvictionCost &O) const {
230 return std::tie(BrokenHints, MaxWeight) <
231 std::tie(O.BrokenHints, O.MaxWeight);
236 std::unique_ptr<SplitAnalysis> SA;
237 std::unique_ptr<SplitEditor> SE;
239 /// Cached per-block interference maps
240 InterferenceCache IntfCache;
242 /// All basic blocks where the current register has uses.
243 SmallVector<SpillPlacement::BlockConstraint, 8> SplitConstraints;
245 /// Global live range splitting candidate info.
246 struct GlobalSplitCandidate {
247 // Register intended for assignment, or 0.
250 // SplitKit interval index for this candidate.
253 // Interference for PhysReg.
254 InterferenceCache::Cursor Intf;
256 // Bundles where this candidate should be live.
257 BitVector LiveBundles;
258 SmallVector<unsigned, 8> ActiveBlocks;
260 void reset(InterferenceCache &Cache, unsigned Reg) {
263 Intf.setPhysReg(Cache, Reg);
265 ActiveBlocks.clear();
268 // Set B[i] = C for every live bundle where B[i] was NoCand.
269 unsigned getBundles(SmallVectorImpl<unsigned> &B, unsigned C) {
271 for (int i = LiveBundles.find_first(); i >= 0;
272 i = LiveBundles.find_next(i))
273 if (B[i] == NoCand) {
281 /// Candidate info for each PhysReg in AllocationOrder.
282 /// This vector never shrinks, but grows to the size of the largest register
284 SmallVector<GlobalSplitCandidate, 32> GlobalCand;
286 enum : unsigned { NoCand = ~0u };
288 /// Candidate map. Each edge bundle is assigned to a GlobalCand entry, or to
289 /// NoCand which indicates the stack interval.
290 SmallVector<unsigned, 32> BundleCand;
292 /// Callee-save register cost, calculated once per machine function.
293 BlockFrequency CSRCost;
295 /// Run or not the local reassignment heuristic. This information is
296 /// obtained from the TargetSubtargetInfo.
297 bool EnableLocalReassign;
302 /// Return the pass name.
303 const char* getPassName() const override {
304 return "Greedy Register Allocator";
307 /// RAGreedy analysis usage.
308 void getAnalysisUsage(AnalysisUsage &AU) const override;
309 void releaseMemory() override;
310 Spiller &spiller() override { return *SpillerInstance; }
311 void enqueue(LiveInterval *LI) override;
312 LiveInterval *dequeue() override;
313 unsigned selectOrSplit(LiveInterval&, SmallVectorImpl<unsigned>&) override;
315 /// Perform register allocation.
316 bool runOnMachineFunction(MachineFunction &mf) override;
321 unsigned selectOrSplitImpl(LiveInterval &, SmallVectorImpl<unsigned> &,
322 SmallVirtRegSet &, unsigned = 0);
324 bool LRE_CanEraseVirtReg(unsigned) override;
325 void LRE_WillShrinkVirtReg(unsigned) override;
326 void LRE_DidCloneVirtReg(unsigned, unsigned) override;
327 void enqueue(PQueue &CurQueue, LiveInterval *LI);
328 LiveInterval *dequeue(PQueue &CurQueue);
330 BlockFrequency calcSpillCost();
331 bool addSplitConstraints(InterferenceCache::Cursor, BlockFrequency&);
332 void addThroughConstraints(InterferenceCache::Cursor, ArrayRef<unsigned>);
333 void growRegion(GlobalSplitCandidate &Cand);
334 BlockFrequency calcGlobalSplitCost(GlobalSplitCandidate&);
335 bool calcCompactRegion(GlobalSplitCandidate&);
336 void splitAroundRegion(LiveRangeEdit&, ArrayRef<unsigned>);
337 void calcGapWeights(unsigned, SmallVectorImpl<float>&);
338 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
339 bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool);
340 bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&);
341 void evictInterference(LiveInterval&, unsigned,
342 SmallVectorImpl<unsigned>&);
343 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
344 SmallLISet &RecoloringCandidates,
345 const SmallVirtRegSet &FixedRegisters);
347 unsigned tryAssign(LiveInterval&, AllocationOrder&,
348 SmallVectorImpl<unsigned>&);
349 unsigned tryEvict(LiveInterval&, AllocationOrder&,
350 SmallVectorImpl<unsigned>&, unsigned = ~0u);
351 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
352 SmallVectorImpl<unsigned>&);
353 /// Calculate cost of region splitting.
354 unsigned calculateRegionSplitCost(LiveInterval &VirtReg,
355 AllocationOrder &Order,
356 BlockFrequency &BestCost,
357 unsigned &NumCands, bool IgnoreCSR);
358 /// Perform region splitting.
359 unsigned doRegionSplit(LiveInterval &VirtReg, unsigned BestCand,
361 SmallVectorImpl<unsigned> &NewVRegs);
362 /// Check other options before using a callee-saved register for the first
364 unsigned tryAssignCSRFirstTime(LiveInterval &VirtReg, AllocationOrder &Order,
365 unsigned PhysReg, unsigned &CostPerUseLimit,
366 SmallVectorImpl<unsigned> &NewVRegs);
367 void initializeCSRCost();
368 unsigned tryBlockSplit(LiveInterval&, AllocationOrder&,
369 SmallVectorImpl<unsigned>&);
370 unsigned tryInstructionSplit(LiveInterval&, AllocationOrder&,
371 SmallVectorImpl<unsigned>&);
372 unsigned tryLocalSplit(LiveInterval&, AllocationOrder&,
373 SmallVectorImpl<unsigned>&);
374 unsigned trySplit(LiveInterval&, AllocationOrder&,
375 SmallVectorImpl<unsigned>&);
376 unsigned tryLastChanceRecoloring(LiveInterval &, AllocationOrder &,
377 SmallVectorImpl<unsigned> &,
378 SmallVirtRegSet &, unsigned);
379 bool tryRecoloringCandidates(PQueue &, SmallVectorImpl<unsigned> &,
380 SmallVirtRegSet &, unsigned);
382 } // end anonymous namespace
384 char RAGreedy::ID = 0;
387 const char *const RAGreedy::StageName[] = {
397 // Hysteresis to use when comparing floats.
398 // This helps stabilize decisions based on float comparisons.
399 const float Hysteresis = (2007 / 2048.0f); // 0.97998046875
402 FunctionPass* llvm::createGreedyRegisterAllocator() {
403 return new RAGreedy();
406 RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
407 initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
408 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
409 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
410 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
411 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
412 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
413 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
414 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
415 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
416 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
417 initializeLiveRegMatrixPass(*PassRegistry::getPassRegistry());
418 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
419 initializeSpillPlacementPass(*PassRegistry::getPassRegistry());
422 void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
423 AU.setPreservesCFG();
424 AU.addRequired<MachineBlockFrequencyInfo>();
425 AU.addPreserved<MachineBlockFrequencyInfo>();
426 AU.addRequired<AliasAnalysis>();
427 AU.addPreserved<AliasAnalysis>();
428 AU.addRequired<LiveIntervals>();
429 AU.addPreserved<LiveIntervals>();
430 AU.addRequired<SlotIndexes>();
431 AU.addPreserved<SlotIndexes>();
432 AU.addRequired<LiveDebugVariables>();
433 AU.addPreserved<LiveDebugVariables>();
434 AU.addRequired<LiveStacks>();
435 AU.addPreserved<LiveStacks>();
436 AU.addRequired<MachineDominatorTree>();
437 AU.addPreserved<MachineDominatorTree>();
438 AU.addRequired<MachineLoopInfo>();
439 AU.addPreserved<MachineLoopInfo>();
440 AU.addRequired<VirtRegMap>();
441 AU.addPreserved<VirtRegMap>();
442 AU.addRequired<LiveRegMatrix>();
443 AU.addPreserved<LiveRegMatrix>();
444 AU.addRequired<EdgeBundles>();
445 AU.addRequired<SpillPlacement>();
446 MachineFunctionPass::getAnalysisUsage(AU);
450 //===----------------------------------------------------------------------===//
451 // LiveRangeEdit delegate methods
452 //===----------------------------------------------------------------------===//
454 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
455 if (VRM->hasPhys(VirtReg)) {
456 Matrix->unassign(LIS->getInterval(VirtReg));
459 // Unassigned virtreg is probably in the priority queue.
460 // RegAllocBase will erase it after dequeueing.
464 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) {
465 if (!VRM->hasPhys(VirtReg))
468 // Register is assigned, put it back on the queue for reassignment.
469 LiveInterval &LI = LIS->getInterval(VirtReg);
470 Matrix->unassign(LI);
474 void RAGreedy::LRE_DidCloneVirtReg(unsigned New, unsigned Old) {
475 // Cloning a register we haven't even heard about yet? Just ignore it.
476 if (!ExtraRegInfo.inBounds(Old))
479 // LRE may clone a virtual register because dead code elimination causes it to
480 // be split into connected components. The new components are much smaller
481 // than the original, so they should get a new chance at being assigned.
482 // same stage as the parent.
483 ExtraRegInfo[Old].Stage = RS_Assign;
484 ExtraRegInfo.grow(New);
485 ExtraRegInfo[New] = ExtraRegInfo[Old];
488 void RAGreedy::releaseMemory() {
489 SpillerInstance.reset();
490 ExtraRegInfo.clear();
494 void RAGreedy::enqueue(LiveInterval *LI) { enqueue(Queue, LI); }
496 void RAGreedy::enqueue(PQueue &CurQueue, LiveInterval *LI) {
497 // Prioritize live ranges by size, assigning larger ranges first.
498 // The queue holds (size, reg) pairs.
499 const unsigned Size = LI->getSize();
500 const unsigned Reg = LI->reg;
501 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
502 "Can only enqueue virtual registers");
505 ExtraRegInfo.grow(Reg);
506 if (ExtraRegInfo[Reg].Stage == RS_New)
507 ExtraRegInfo[Reg].Stage = RS_Assign;
509 if (ExtraRegInfo[Reg].Stage == RS_Split) {
510 // Unsplit ranges that couldn't be allocated immediately are deferred until
511 // everything else has been allocated.
514 // Giant live ranges fall back to the global assignment heuristic, which
515 // prevents excessive spilling in pathological cases.
516 bool ReverseLocal = TRI->reverseLocalAssignment();
517 bool ForceGlobal = !ReverseLocal && TRI->mayOverrideLocalAssignment() &&
518 (Size / SlotIndex::InstrDist) > (2 * MRI->getRegClass(Reg)->getNumRegs());
520 if (ExtraRegInfo[Reg].Stage == RS_Assign && !ForceGlobal && !LI->empty() &&
521 LIS->intervalIsInOneMBB(*LI)) {
522 // Allocate original local ranges in linear instruction order. Since they
523 // are singly defined, this produces optimal coloring in the absence of
524 // global interference and other constraints.
526 Prio = LI->beginIndex().getInstrDistance(Indexes->getLastIndex());
528 // Allocating bottom up may allow many short LRGs to be assigned first
529 // to one of the cheap registers. This could be much faster for very
530 // large blocks on targets with many physical registers.
531 Prio = Indexes->getZeroIndex().getInstrDistance(LI->beginIndex());
535 // Allocate global and split ranges in long->short order. Long ranges that
536 // don't fit should be spilled (or split) ASAP so they don't create
537 // interference. Mark a bit to prioritize global above local ranges.
538 Prio = (1u << 29) + Size;
540 // Mark a higher bit to prioritize global and local above RS_Split.
543 // Boost ranges that have a physical register hint.
544 if (VRM->hasKnownPreference(Reg))
547 // The virtual register number is a tie breaker for same-sized ranges.
548 // Give lower vreg numbers higher priority to assign them first.
549 CurQueue.push(std::make_pair(Prio, ~Reg));
552 LiveInterval *RAGreedy::dequeue() { return dequeue(Queue); }
554 LiveInterval *RAGreedy::dequeue(PQueue &CurQueue) {
555 if (CurQueue.empty())
557 LiveInterval *LI = &LIS->getInterval(~CurQueue.top().second);
563 //===----------------------------------------------------------------------===//
565 //===----------------------------------------------------------------------===//
567 /// tryAssign - Try to assign VirtReg to an available register.
568 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg,
569 AllocationOrder &Order,
570 SmallVectorImpl<unsigned> &NewVRegs) {
573 while ((PhysReg = Order.next()))
574 if (!Matrix->checkInterference(VirtReg, PhysReg))
576 if (!PhysReg || Order.isHint())
579 // PhysReg is available, but there may be a better choice.
581 // If we missed a simple hint, try to cheaply evict interference from the
582 // preferred register.
583 if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg))
584 if (Order.isHint(Hint)) {
585 DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n');
586 EvictionCost MaxCost;
587 MaxCost.setBrokenHints(1);
588 if (canEvictInterference(VirtReg, Hint, true, MaxCost)) {
589 evictInterference(VirtReg, Hint, NewVRegs);
594 // Try to evict interference from a cheaper alternative.
595 unsigned Cost = TRI->getCostPerUse(PhysReg);
597 // Most registers have 0 additional cost.
601 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost
603 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
604 return CheapReg ? CheapReg : PhysReg;
608 //===----------------------------------------------------------------------===//
609 // Interference eviction
610 //===----------------------------------------------------------------------===//
612 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) {
613 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
615 while ((PhysReg = Order.next())) {
616 if (PhysReg == PrevReg)
619 MCRegUnitIterator Units(PhysReg, TRI);
620 for (; Units.isValid(); ++Units) {
621 // Instantiate a "subquery", not to be confused with the Queries array.
622 LiveIntervalUnion::Query subQ(&VirtReg, &Matrix->getLiveUnions()[*Units]);
623 if (subQ.checkInterference())
626 // If no units have interference, break out with the current PhysReg.
627 if (!Units.isValid())
631 DEBUG(dbgs() << "can reassign: " << VirtReg << " from "
632 << PrintReg(PrevReg, TRI) << " to " << PrintReg(PhysReg, TRI)
637 /// shouldEvict - determine if A should evict the assigned live range B. The
638 /// eviction policy defined by this function together with the allocation order
639 /// defined by enqueue() decides which registers ultimately end up being split
642 /// Cascade numbers are used to prevent infinite loops if this function is a
645 /// @param A The live range to be assigned.
646 /// @param IsHint True when A is about to be assigned to its preferred
648 /// @param B The live range to be evicted.
649 /// @param BreaksHint True when B is already assigned to its preferred register.
650 bool RAGreedy::shouldEvict(LiveInterval &A, bool IsHint,
651 LiveInterval &B, bool BreaksHint) {
652 bool CanSplit = getStage(B) < RS_Spill;
654 // Be fairly aggressive about following hints as long as the evictee can be
656 if (CanSplit && IsHint && !BreaksHint)
659 if (A.weight > B.weight) {
660 DEBUG(dbgs() << "should evict: " << B << " w= " << B.weight << '\n');
666 /// canEvictInterference - Return true if all interferences between VirtReg and
667 /// PhysReg can be evicted.
669 /// @param VirtReg Live range that is about to be assigned.
670 /// @param PhysReg Desired register for assignment.
671 /// @param IsHint True when PhysReg is VirtReg's preferred register.
672 /// @param MaxCost Only look for cheaper candidates and update with new cost
673 /// when returning true.
674 /// @returns True when interference can be evicted cheaper than MaxCost.
675 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
676 bool IsHint, EvictionCost &MaxCost) {
677 // It is only possible to evict virtual register interference.
678 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg)
681 bool IsLocal = LIS->intervalIsInOneMBB(VirtReg);
683 // Find VirtReg's cascade number. This will be unassigned if VirtReg was never
684 // involved in an eviction before. If a cascade number was assigned, deny
685 // evicting anything with the same or a newer cascade number. This prevents
686 // infinite eviction loops.
688 // This works out so a register without a cascade number is allowed to evict
689 // anything, and it can be evicted by anything.
690 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
692 Cascade = NextCascade;
695 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
696 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
697 // If there is 10 or more interferences, chances are one is heavier.
698 if (Q.collectInterferingVRegs(10) >= 10)
701 // Check if any interfering live range is heavier than MaxWeight.
702 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
703 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
704 assert(TargetRegisterInfo::isVirtualRegister(Intf->reg) &&
705 "Only expecting virtual register interference from query");
706 // Never evict spill products. They cannot split or spill.
707 if (getStage(*Intf) == RS_Done)
709 // Once a live range becomes small enough, it is urgent that we find a
710 // register for it. This is indicated by an infinite spill weight. These
711 // urgent live ranges get to evict almost anything.
713 // Also allow urgent evictions of unspillable ranges from a strictly
714 // larger allocation order.
715 bool Urgent = !VirtReg.isSpillable() &&
716 (Intf->isSpillable() ||
717 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) <
718 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg)));
719 // Only evict older cascades or live ranges without a cascade.
720 unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;
721 if (Cascade <= IntfCascade) {
724 // We permit breaking cascades for urgent evictions. It should be the
725 // last resort, though, so make it really expensive.
726 Cost.BrokenHints += 10;
728 // Would this break a satisfied hint?
729 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg);
730 // Update eviction cost.
731 Cost.BrokenHints += BreaksHint;
732 Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight);
733 // Abort if this would be too expensive.
734 if (!(Cost < MaxCost))
738 // Apply the eviction policy for non-urgent evictions.
739 if (!shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
741 // If !MaxCost.isMax(), then we're just looking for a cheap register.
742 // Evicting another local live range in this case could lead to suboptimal
744 if (!MaxCost.isMax() && IsLocal && LIS->intervalIsInOneMBB(*Intf) &&
745 (!EnableLocalReassign || !canReassign(*Intf, PhysReg))) {
754 /// evictInterference - Evict any interferring registers that prevent VirtReg
755 /// from being assigned to Physreg. This assumes that canEvictInterference
757 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg,
758 SmallVectorImpl<unsigned> &NewVRegs) {
759 // Make sure that VirtReg has a cascade number, and assign that cascade
760 // number to every evicted register. These live ranges than then only be
761 // evicted by a newer cascade, preventing infinite loops.
762 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
764 Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;
766 DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI)
767 << " interference: Cascade " << Cascade << '\n');
769 // Collect all interfering virtregs first.
770 SmallVector<LiveInterval*, 8> Intfs;
771 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
772 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
773 assert(Q.seenAllInterferences() && "Didn't check all interfererences.");
774 ArrayRef<LiveInterval*> IVR = Q.interferingVRegs();
775 Intfs.append(IVR.begin(), IVR.end());
778 // Evict them second. This will invalidate the queries.
779 for (unsigned i = 0, e = Intfs.size(); i != e; ++i) {
780 LiveInterval *Intf = Intfs[i];
781 // The same VirtReg may be present in multiple RegUnits. Skip duplicates.
782 if (!VRM->hasPhys(Intf->reg))
784 Matrix->unassign(*Intf);
785 assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||
786 VirtReg.isSpillable() < Intf->isSpillable()) &&
787 "Cannot decrease cascade number, illegal eviction");
788 ExtraRegInfo[Intf->reg].Cascade = Cascade;
790 NewVRegs.push_back(Intf->reg);
794 /// tryEvict - Try to evict all interferences for a physreg.
795 /// @param VirtReg Currently unassigned virtual register.
796 /// @param Order Physregs to try.
797 /// @return Physreg to assign VirtReg, or 0.
798 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
799 AllocationOrder &Order,
800 SmallVectorImpl<unsigned> &NewVRegs,
801 unsigned CostPerUseLimit) {
802 NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled);
804 // Keep track of the cheapest interference seen so far.
805 EvictionCost BestCost;
807 unsigned BestPhys = 0;
808 unsigned OrderLimit = Order.getOrder().size();
810 // When we are just looking for a reduced cost per use, don't break any
811 // hints, and only evict smaller spill weights.
812 if (CostPerUseLimit < ~0u) {
813 BestCost.BrokenHints = 0;
814 BestCost.MaxWeight = VirtReg.weight;
816 // Check of any registers in RC are below CostPerUseLimit.
817 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg);
818 unsigned MinCost = RegClassInfo.getMinCost(RC);
819 if (MinCost >= CostPerUseLimit) {
820 DEBUG(dbgs() << RC->getName() << " minimum cost = " << MinCost
821 << ", no cheaper registers to be found.\n");
825 // It is normal for register classes to have a long tail of registers with
826 // the same cost. We don't need to look at them if they're too expensive.
827 if (TRI->getCostPerUse(Order.getOrder().back()) >= CostPerUseLimit) {
828 OrderLimit = RegClassInfo.getLastCostChange(RC);
829 DEBUG(dbgs() << "Only trying the first " << OrderLimit << " regs.\n");
834 while (unsigned PhysReg = Order.next(OrderLimit)) {
835 if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit)
837 // The first use of a callee-saved register in a function has cost 1.
838 // Don't start using a CSR when the CostPerUseLimit is low.
839 if (CostPerUseLimit == 1)
840 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
841 if (!MRI->isPhysRegUsed(CSR)) {
842 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR "
843 << PrintReg(CSR, TRI) << '\n');
847 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost))
853 // Stop if the hint can be used.
861 evictInterference(VirtReg, BestPhys, NewVRegs);
866 //===----------------------------------------------------------------------===//
868 //===----------------------------------------------------------------------===//
870 /// addSplitConstraints - Fill out the SplitConstraints vector based on the
871 /// interference pattern in Physreg and its aliases. Add the constraints to
872 /// SpillPlacement and return the static cost of this split in Cost, assuming
873 /// that all preferences in SplitConstraints are met.
874 /// Return false if there are no bundles with positive bias.
875 bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
876 BlockFrequency &Cost) {
877 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
879 // Reset interference dependent info.
880 SplitConstraints.resize(UseBlocks.size());
881 BlockFrequency StaticCost = 0;
882 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
883 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
884 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
886 BC.Number = BI.MBB->getNumber();
887 Intf.moveToBlock(BC.Number);
888 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
889 BC.Exit = BI.LiveOut ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
890 BC.ChangesValue = BI.FirstDef.isValid();
892 if (!Intf.hasInterference())
895 // Number of spill code instructions to insert.
898 // Interference for the live-in value.
900 if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number))
901 BC.Entry = SpillPlacement::MustSpill, ++Ins;
902 else if (Intf.first() < BI.FirstInstr)
903 BC.Entry = SpillPlacement::PrefSpill, ++Ins;
904 else if (Intf.first() < BI.LastInstr)
908 // Interference for the live-out value.
910 if (Intf.last() >= SA->getLastSplitPoint(BC.Number))
911 BC.Exit = SpillPlacement::MustSpill, ++Ins;
912 else if (Intf.last() > BI.LastInstr)
913 BC.Exit = SpillPlacement::PrefSpill, ++Ins;
914 else if (Intf.last() > BI.FirstInstr)
918 // Accumulate the total frequency of inserted spill code.
920 StaticCost += SpillPlacer->getBlockFrequency(BC.Number);
924 // Add constraints for use-blocks. Note that these are the only constraints
925 // that may add a positive bias, it is downhill from here.
926 SpillPlacer->addConstraints(SplitConstraints);
927 return SpillPlacer->scanActiveBundles();
931 /// addThroughConstraints - Add constraints and links to SpillPlacer from the
932 /// live-through blocks in Blocks.
933 void RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
934 ArrayRef<unsigned> Blocks) {
935 const unsigned GroupSize = 8;
936 SpillPlacement::BlockConstraint BCS[GroupSize];
937 unsigned TBS[GroupSize];
938 unsigned B = 0, T = 0;
940 for (unsigned i = 0; i != Blocks.size(); ++i) {
941 unsigned Number = Blocks[i];
942 Intf.moveToBlock(Number);
944 if (!Intf.hasInterference()) {
945 assert(T < GroupSize && "Array overflow");
947 if (++T == GroupSize) {
948 SpillPlacer->addLinks(makeArrayRef(TBS, T));
954 assert(B < GroupSize && "Array overflow");
955 BCS[B].Number = Number;
957 // Interference for the live-in value.
958 if (Intf.first() <= Indexes->getMBBStartIdx(Number))
959 BCS[B].Entry = SpillPlacement::MustSpill;
961 BCS[B].Entry = SpillPlacement::PrefSpill;
963 // Interference for the live-out value.
964 if (Intf.last() >= SA->getLastSplitPoint(Number))
965 BCS[B].Exit = SpillPlacement::MustSpill;
967 BCS[B].Exit = SpillPlacement::PrefSpill;
969 if (++B == GroupSize) {
970 SpillPlacer->addConstraints(makeArrayRef(BCS, B));
975 SpillPlacer->addConstraints(makeArrayRef(BCS, B));
976 SpillPlacer->addLinks(makeArrayRef(TBS, T));
979 void RAGreedy::growRegion(GlobalSplitCandidate &Cand) {
980 // Keep track of through blocks that have not been added to SpillPlacer.
981 BitVector Todo = SA->getThroughBlocks();
982 SmallVectorImpl<unsigned> &ActiveBlocks = Cand.ActiveBlocks;
983 unsigned AddedTo = 0;
985 unsigned Visited = 0;
989 ArrayRef<unsigned> NewBundles = SpillPlacer->getRecentPositive();
990 // Find new through blocks in the periphery of PrefRegBundles.
991 for (int i = 0, e = NewBundles.size(); i != e; ++i) {
992 unsigned Bundle = NewBundles[i];
993 // Look at all blocks connected to Bundle in the full graph.
994 ArrayRef<unsigned> Blocks = Bundles->getBlocks(Bundle);
995 for (ArrayRef<unsigned>::iterator I = Blocks.begin(), E = Blocks.end();
998 if (!Todo.test(Block))
1001 // This is a new through block. Add it to SpillPlacer later.
1002 ActiveBlocks.push_back(Block);
1008 // Any new blocks to add?
1009 if (ActiveBlocks.size() == AddedTo)
1012 // Compute through constraints from the interference, or assume that all
1013 // through blocks prefer spilling when forming compact regions.
1014 auto NewBlocks = makeArrayRef(ActiveBlocks).slice(AddedTo);
1016 addThroughConstraints(Cand.Intf, NewBlocks);
1018 // Provide a strong negative bias on through blocks to prevent unwanted
1019 // liveness on loop backedges.
1020 SpillPlacer->addPrefSpill(NewBlocks, /* Strong= */ true);
1021 AddedTo = ActiveBlocks.size();
1023 // Perhaps iterating can enable more bundles?
1024 SpillPlacer->iterate();
1026 DEBUG(dbgs() << ", v=" << Visited);
1029 /// calcCompactRegion - Compute the set of edge bundles that should be live
1030 /// when splitting the current live range into compact regions. Compact
1031 /// regions can be computed without looking at interference. They are the
1032 /// regions formed by removing all the live-through blocks from the live range.
1034 /// Returns false if the current live range is already compact, or if the
1035 /// compact regions would form single block regions anyway.
1036 bool RAGreedy::calcCompactRegion(GlobalSplitCandidate &Cand) {
1037 // Without any through blocks, the live range is already compact.
1038 if (!SA->getNumThroughBlocks())
1041 // Compact regions don't correspond to any physreg.
1042 Cand.reset(IntfCache, 0);
1044 DEBUG(dbgs() << "Compact region bundles");
1046 // Use the spill placer to determine the live bundles. GrowRegion pretends
1047 // that all the through blocks have interference when PhysReg is unset.
1048 SpillPlacer->prepare(Cand.LiveBundles);
1050 // The static split cost will be zero since Cand.Intf reports no interference.
1051 BlockFrequency Cost;
1052 if (!addSplitConstraints(Cand.Intf, Cost)) {
1053 DEBUG(dbgs() << ", none.\n");
1058 SpillPlacer->finish();
1060 if (!Cand.LiveBundles.any()) {
1061 DEBUG(dbgs() << ", none.\n");
1066 for (int i = Cand.LiveBundles.find_first(); i>=0;
1067 i = Cand.LiveBundles.find_next(i))
1068 dbgs() << " EB#" << i;
1074 /// calcSpillCost - Compute how expensive it would be to split the live range in
1075 /// SA around all use blocks instead of forming bundle regions.
1076 BlockFrequency RAGreedy::calcSpillCost() {
1077 BlockFrequency Cost = 0;
1078 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1079 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1080 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1081 unsigned Number = BI.MBB->getNumber();
1082 // We normally only need one spill instruction - a load or a store.
1083 Cost += SpillPlacer->getBlockFrequency(Number);
1085 // Unless the value is redefined in the block.
1086 if (BI.LiveIn && BI.LiveOut && BI.FirstDef)
1087 Cost += SpillPlacer->getBlockFrequency(Number);
1092 /// calcGlobalSplitCost - Return the global split cost of following the split
1093 /// pattern in LiveBundles. This cost should be added to the local cost of the
1094 /// interference pattern in SplitConstraints.
1096 BlockFrequency RAGreedy::calcGlobalSplitCost(GlobalSplitCandidate &Cand) {
1097 BlockFrequency GlobalCost = 0;
1098 const BitVector &LiveBundles = Cand.LiveBundles;
1099 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1100 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1101 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1102 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
1103 bool RegIn = LiveBundles[Bundles->getBundle(BC.Number, 0)];
1104 bool RegOut = LiveBundles[Bundles->getBundle(BC.Number, 1)];
1108 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg);
1110 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg);
1112 GlobalCost += SpillPlacer->getBlockFrequency(BC.Number);
1115 for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) {
1116 unsigned Number = Cand.ActiveBlocks[i];
1117 bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)];
1118 bool RegOut = LiveBundles[Bundles->getBundle(Number, 1)];
1119 if (!RegIn && !RegOut)
1121 if (RegIn && RegOut) {
1122 // We need double spill code if this block has interference.
1123 Cand.Intf.moveToBlock(Number);
1124 if (Cand.Intf.hasInterference()) {
1125 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1126 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1130 // live-in / stack-out or stack-in live-out.
1131 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1136 /// splitAroundRegion - Split the current live range around the regions
1137 /// determined by BundleCand and GlobalCand.
1139 /// Before calling this function, GlobalCand and BundleCand must be initialized
1140 /// so each bundle is assigned to a valid candidate, or NoCand for the
1141 /// stack-bound bundles. The shared SA/SE SplitAnalysis and SplitEditor
1142 /// objects must be initialized for the current live range, and intervals
1143 /// created for the used candidates.
1145 /// @param LREdit The LiveRangeEdit object handling the current split.
1146 /// @param UsedCands List of used GlobalCand entries. Every BundleCand value
1147 /// must appear in this list.
1148 void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit,
1149 ArrayRef<unsigned> UsedCands) {
1150 // These are the intervals created for new global ranges. We may create more
1151 // intervals for local ranges.
1152 const unsigned NumGlobalIntvs = LREdit.size();
1153 DEBUG(dbgs() << "splitAroundRegion with " << NumGlobalIntvs << " globals.\n");
1154 assert(NumGlobalIntvs && "No global intervals configured");
1156 // Isolate even single instructions when dealing with a proper sub-class.
1157 // That guarantees register class inflation for the stack interval because it
1159 unsigned Reg = SA->getParent().reg;
1160 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1162 // First handle all the blocks with uses.
1163 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1164 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1165 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1166 unsigned Number = BI.MBB->getNumber();
1167 unsigned IntvIn = 0, IntvOut = 0;
1168 SlotIndex IntfIn, IntfOut;
1170 unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)];
1171 if (CandIn != NoCand) {
1172 GlobalSplitCandidate &Cand = GlobalCand[CandIn];
1173 IntvIn = Cand.IntvIdx;
1174 Cand.Intf.moveToBlock(Number);
1175 IntfIn = Cand.Intf.first();
1179 unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)];
1180 if (CandOut != NoCand) {
1181 GlobalSplitCandidate &Cand = GlobalCand[CandOut];
1182 IntvOut = Cand.IntvIdx;
1183 Cand.Intf.moveToBlock(Number);
1184 IntfOut = Cand.Intf.last();
1188 // Create separate intervals for isolated blocks with multiple uses.
1189 if (!IntvIn && !IntvOut) {
1190 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n");
1191 if (SA->shouldSplitSingleBlock(BI, SingleInstrs))
1192 SE->splitSingleBlock(BI);
1196 if (IntvIn && IntvOut)
1197 SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut);
1199 SE->splitRegInBlock(BI, IntvIn, IntfIn);
1201 SE->splitRegOutBlock(BI, IntvOut, IntfOut);
1204 // Handle live-through blocks. The relevant live-through blocks are stored in
1205 // the ActiveBlocks list with each candidate. We need to filter out
1207 BitVector Todo = SA->getThroughBlocks();
1208 for (unsigned c = 0; c != UsedCands.size(); ++c) {
1209 ArrayRef<unsigned> Blocks = GlobalCand[UsedCands[c]].ActiveBlocks;
1210 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
1211 unsigned Number = Blocks[i];
1212 if (!Todo.test(Number))
1216 unsigned IntvIn = 0, IntvOut = 0;
1217 SlotIndex IntfIn, IntfOut;
1219 unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)];
1220 if (CandIn != NoCand) {
1221 GlobalSplitCandidate &Cand = GlobalCand[CandIn];
1222 IntvIn = Cand.IntvIdx;
1223 Cand.Intf.moveToBlock(Number);
1224 IntfIn = Cand.Intf.first();
1227 unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)];
1228 if (CandOut != NoCand) {
1229 GlobalSplitCandidate &Cand = GlobalCand[CandOut];
1230 IntvOut = Cand.IntvIdx;
1231 Cand.Intf.moveToBlock(Number);
1232 IntfOut = Cand.Intf.last();
1234 if (!IntvIn && !IntvOut)
1236 SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut);
1242 SmallVector<unsigned, 8> IntvMap;
1243 SE->finish(&IntvMap);
1244 DebugVars->splitRegister(Reg, LREdit.regs(), *LIS);
1246 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1247 unsigned OrigBlocks = SA->getNumLiveBlocks();
1249 // Sort out the new intervals created by splitting. We get four kinds:
1250 // - Remainder intervals should not be split again.
1251 // - Candidate intervals can be assigned to Cand.PhysReg.
1252 // - Block-local splits are candidates for local splitting.
1253 // - DCE leftovers should go back on the queue.
1254 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) {
1255 LiveInterval &Reg = LIS->getInterval(LREdit.get(i));
1257 // Ignore old intervals from DCE.
1258 if (getStage(Reg) != RS_New)
1261 // Remainder interval. Don't try splitting again, spill if it doesn't
1263 if (IntvMap[i] == 0) {
1264 setStage(Reg, RS_Spill);
1268 // Global intervals. Allow repeated splitting as long as the number of live
1269 // blocks is strictly decreasing.
1270 if (IntvMap[i] < NumGlobalIntvs) {
1271 if (SA->countLiveBlocks(&Reg) >= OrigBlocks) {
1272 DEBUG(dbgs() << "Main interval covers the same " << OrigBlocks
1273 << " blocks as original.\n");
1274 // Don't allow repeated splitting as a safe guard against looping.
1275 setStage(Reg, RS_Split2);
1280 // Other intervals are treated as new. This includes local intervals created
1281 // for blocks with multiple uses, and anything created by DCE.
1285 MF->verify(this, "After splitting live range around region");
1288 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1289 SmallVectorImpl<unsigned> &NewVRegs) {
1290 unsigned NumCands = 0;
1291 BlockFrequency BestCost;
1293 // Check if we can split this live range around a compact region.
1294 bool HasCompact = calcCompactRegion(GlobalCand.front());
1296 // Yes, keep GlobalCand[0] as the compact region candidate.
1298 BestCost = BlockFrequency::getMaxFrequency();
1300 // No benefit from the compact region, our fallback will be per-block
1301 // splitting. Make sure we find a solution that is cheaper than spilling.
1302 BestCost = calcSpillCost();
1303 DEBUG(dbgs() << "Cost of isolating all blocks = ";
1304 MBFI->printBlockFreq(dbgs(), BestCost) << '\n');
1308 calculateRegionSplitCost(VirtReg, Order, BestCost, NumCands,
1309 false/*IgnoreCSR*/);
1311 // No solutions found, fall back to single block splitting.
1312 if (!HasCompact && BestCand == NoCand)
1315 return doRegionSplit(VirtReg, BestCand, HasCompact, NewVRegs);
1318 unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg,
1319 AllocationOrder &Order,
1320 BlockFrequency &BestCost,
1323 unsigned BestCand = NoCand;
1325 while (unsigned PhysReg = Order.next()) {
1326 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
1327 if (IgnoreCSR && !MRI->isPhysRegUsed(CSR))
1330 // Discard bad candidates before we run out of interference cache cursors.
1331 // This will only affect register classes with a lot of registers (>32).
1332 if (NumCands == IntfCache.getMaxCursors()) {
1333 unsigned WorstCount = ~0u;
1335 for (unsigned i = 0; i != NumCands; ++i) {
1336 if (i == BestCand || !GlobalCand[i].PhysReg)
1338 unsigned Count = GlobalCand[i].LiveBundles.count();
1339 if (Count < WorstCount)
1340 Worst = i, WorstCount = Count;
1343 GlobalCand[Worst] = GlobalCand[NumCands];
1344 if (BestCand == NumCands)
1348 if (GlobalCand.size() <= NumCands)
1349 GlobalCand.resize(NumCands+1);
1350 GlobalSplitCandidate &Cand = GlobalCand[NumCands];
1351 Cand.reset(IntfCache, PhysReg);
1353 SpillPlacer->prepare(Cand.LiveBundles);
1354 BlockFrequency Cost;
1355 if (!addSplitConstraints(Cand.Intf, Cost)) {
1356 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n");
1359 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = ";
1360 MBFI->printBlockFreq(dbgs(), Cost));
1361 if (Cost >= BestCost) {
1363 if (BestCand == NoCand)
1364 dbgs() << " worse than no bundles\n";
1366 dbgs() << " worse than "
1367 << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
1373 SpillPlacer->finish();
1375 // No live bundles, defer to splitSingleBlocks().
1376 if (!Cand.LiveBundles.any()) {
1377 DEBUG(dbgs() << " no bundles.\n");
1381 Cost += calcGlobalSplitCost(Cand);
1383 dbgs() << ", total = "; MBFI->printBlockFreq(dbgs(), Cost)
1385 for (int i = Cand.LiveBundles.find_first(); i>=0;
1386 i = Cand.LiveBundles.find_next(i))
1387 dbgs() << " EB#" << i;
1390 if (Cost < BestCost) {
1391 BestCand = NumCands;
1399 unsigned RAGreedy::doRegionSplit(LiveInterval &VirtReg, unsigned BestCand,
1401 SmallVectorImpl<unsigned> &NewVRegs) {
1402 SmallVector<unsigned, 8> UsedCands;
1403 // Prepare split editor.
1404 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1405 SE->reset(LREdit, SplitSpillMode);
1407 // Assign all edge bundles to the preferred candidate, or NoCand.
1408 BundleCand.assign(Bundles->getNumBundles(), NoCand);
1410 // Assign bundles for the best candidate region.
1411 if (BestCand != NoCand) {
1412 GlobalSplitCandidate &Cand = GlobalCand[BestCand];
1413 if (unsigned B = Cand.getBundles(BundleCand, BestCand)) {
1414 UsedCands.push_back(BestCand);
1415 Cand.IntvIdx = SE->openIntv();
1416 DEBUG(dbgs() << "Split for " << PrintReg(Cand.PhysReg, TRI) << " in "
1417 << B << " bundles, intv " << Cand.IntvIdx << ".\n");
1422 // Assign bundles for the compact region.
1424 GlobalSplitCandidate &Cand = GlobalCand.front();
1425 assert(!Cand.PhysReg && "Compact region has no physreg");
1426 if (unsigned B = Cand.getBundles(BundleCand, 0)) {
1427 UsedCands.push_back(0);
1428 Cand.IntvIdx = SE->openIntv();
1429 DEBUG(dbgs() << "Split for compact region in " << B << " bundles, intv "
1430 << Cand.IntvIdx << ".\n");
1435 splitAroundRegion(LREdit, UsedCands);
1440 //===----------------------------------------------------------------------===//
1441 // Per-Block Splitting
1442 //===----------------------------------------------------------------------===//
1444 /// tryBlockSplit - Split a global live range around every block with uses. This
1445 /// creates a lot of local live ranges, that will be split by tryLocalSplit if
1446 /// they don't allocate.
1447 unsigned RAGreedy::tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1448 SmallVectorImpl<unsigned> &NewVRegs) {
1449 assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed");
1450 unsigned Reg = VirtReg.reg;
1451 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1452 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1453 SE->reset(LREdit, SplitSpillMode);
1454 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1455 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1456 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1457 if (SA->shouldSplitSingleBlock(BI, SingleInstrs))
1458 SE->splitSingleBlock(BI);
1460 // No blocks were split.
1464 // We did split for some blocks.
1465 SmallVector<unsigned, 8> IntvMap;
1466 SE->finish(&IntvMap);
1468 // Tell LiveDebugVariables about the new ranges.
1469 DebugVars->splitRegister(Reg, LREdit.regs(), *LIS);
1471 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1473 // Sort out the new intervals created by splitting. The remainder interval
1474 // goes straight to spilling, the new local ranges get to stay RS_New.
1475 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) {
1476 LiveInterval &LI = LIS->getInterval(LREdit.get(i));
1477 if (getStage(LI) == RS_New && IntvMap[i] == 0)
1478 setStage(LI, RS_Spill);
1482 MF->verify(this, "After splitting live range around basic blocks");
1487 //===----------------------------------------------------------------------===//
1488 // Per-Instruction Splitting
1489 //===----------------------------------------------------------------------===//
1491 /// Get the number of allocatable registers that match the constraints of \p Reg
1492 /// on \p MI and that are also in \p SuperRC.
1493 static unsigned getNumAllocatableRegsForConstraints(
1494 const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC,
1495 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1496 const RegisterClassInfo &RCI) {
1497 assert(SuperRC && "Invalid register class");
1499 const TargetRegisterClass *ConstrainedRC =
1500 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI,
1501 /* ExploreBundle */ true);
1504 return RCI.getNumAllocatableRegs(ConstrainedRC);
1507 /// tryInstructionSplit - Split a live range around individual instructions.
1508 /// This is normally not worthwhile since the spiller is doing essentially the
1509 /// same thing. However, when the live range is in a constrained register
1510 /// class, it may help to insert copies such that parts of the live range can
1511 /// be moved to a larger register class.
1513 /// This is similar to spilling to a larger register class.
1515 RAGreedy::tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1516 SmallVectorImpl<unsigned> &NewVRegs) {
1517 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg);
1518 // There is no point to this if there are no larger sub-classes.
1519 if (!RegClassInfo.isProperSubClass(CurRC))
1522 // Always enable split spill mode, since we're effectively spilling to a
1524 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1525 SE->reset(LREdit, SplitEditor::SM_Size);
1527 ArrayRef<SlotIndex> Uses = SA->getUseSlots();
1528 if (Uses.size() <= 1)
1531 DEBUG(dbgs() << "Split around " << Uses.size() << " individual instrs.\n");
1533 const TargetRegisterClass *SuperRC = TRI->getLargestLegalSuperClass(CurRC);
1534 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC);
1535 // Split around every non-copy instruction if this split will relax
1536 // the constraints on the virtual register.
1537 // Otherwise, splitting just inserts uncoalescable copies that do not help
1539 for (unsigned i = 0; i != Uses.size(); ++i) {
1540 if (const MachineInstr *MI = Indexes->getInstructionFromIndex(Uses[i]))
1541 if (MI->isFullCopy() ||
1542 SuperRCNumAllocatableRegs ==
1543 getNumAllocatableRegsForConstraints(MI, VirtReg.reg, SuperRC, TII,
1545 DEBUG(dbgs() << " skip:\t" << Uses[i] << '\t' << *MI);
1549 SlotIndex SegStart = SE->enterIntvBefore(Uses[i]);
1550 SlotIndex SegStop = SE->leaveIntvAfter(Uses[i]);
1551 SE->useIntv(SegStart, SegStop);
1554 if (LREdit.empty()) {
1555 DEBUG(dbgs() << "All uses were copies.\n");
1559 SmallVector<unsigned, 8> IntvMap;
1560 SE->finish(&IntvMap);
1561 DebugVars->splitRegister(VirtReg.reg, LREdit.regs(), *LIS);
1562 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1564 // Assign all new registers to RS_Spill. This was the last chance.
1565 setStage(LREdit.begin(), LREdit.end(), RS_Spill);
1570 //===----------------------------------------------------------------------===//
1572 //===----------------------------------------------------------------------===//
1575 /// calcGapWeights - Compute the maximum spill weight that needs to be evicted
1576 /// in order to use PhysReg between two entries in SA->UseSlots.
1578 /// GapWeight[i] represents the gap between UseSlots[i] and UseSlots[i+1].
1580 void RAGreedy::calcGapWeights(unsigned PhysReg,
1581 SmallVectorImpl<float> &GapWeight) {
1582 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
1583 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
1584 ArrayRef<SlotIndex> Uses = SA->getUseSlots();
1585 const unsigned NumGaps = Uses.size()-1;
1587 // Start and end points for the interference check.
1588 SlotIndex StartIdx =
1589 BI.LiveIn ? BI.FirstInstr.getBaseIndex() : BI.FirstInstr;
1591 BI.LiveOut ? BI.LastInstr.getBoundaryIndex() : BI.LastInstr;
1593 GapWeight.assign(NumGaps, 0.0f);
1595 // Add interference from each overlapping register.
1596 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1597 if (!Matrix->query(const_cast<LiveInterval&>(SA->getParent()), *Units)
1598 .checkInterference())
1601 // We know that VirtReg is a continuous interval from FirstInstr to
1602 // LastInstr, so we don't need InterferenceQuery.
1604 // Interference that overlaps an instruction is counted in both gaps
1605 // surrounding the instruction. The exception is interference before
1606 // StartIdx and after StopIdx.
1608 LiveIntervalUnion::SegmentIter IntI =
1609 Matrix->getLiveUnions()[*Units] .find(StartIdx);
1610 for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) {
1611 // Skip the gaps before IntI.
1612 while (Uses[Gap+1].getBoundaryIndex() < IntI.start())
1613 if (++Gap == NumGaps)
1618 // Update the gaps covered by IntI.
1619 const float weight = IntI.value()->weight;
1620 for (; Gap != NumGaps; ++Gap) {
1621 GapWeight[Gap] = std::max(GapWeight[Gap], weight);
1622 if (Uses[Gap+1].getBaseIndex() >= IntI.stop())
1630 // Add fixed interference.
1631 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1632 const LiveRange &LR = LIS->getRegUnit(*Units);
1633 LiveRange::const_iterator I = LR.find(StartIdx);
1634 LiveRange::const_iterator E = LR.end();
1636 // Same loop as above. Mark any overlapped gaps as HUGE_VALF.
1637 for (unsigned Gap = 0; I != E && I->start < StopIdx; ++I) {
1638 while (Uses[Gap+1].getBoundaryIndex() < I->start)
1639 if (++Gap == NumGaps)
1644 for (; Gap != NumGaps; ++Gap) {
1645 GapWeight[Gap] = llvm::huge_valf;
1646 if (Uses[Gap+1].getBaseIndex() >= I->end)
1655 /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
1658 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1659 SmallVectorImpl<unsigned> &NewVRegs) {
1660 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
1661 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
1663 // Note that it is possible to have an interval that is live-in or live-out
1664 // while only covering a single block - A phi-def can use undef values from
1665 // predecessors, and the block could be a single-block loop.
1666 // We don't bother doing anything clever about such a case, we simply assume
1667 // that the interval is continuous from FirstInstr to LastInstr. We should
1668 // make sure that we don't do anything illegal to such an interval, though.
1670 ArrayRef<SlotIndex> Uses = SA->getUseSlots();
1671 if (Uses.size() <= 2)
1673 const unsigned NumGaps = Uses.size()-1;
1676 dbgs() << "tryLocalSplit: ";
1677 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
1678 dbgs() << ' ' << Uses[i];
1682 // If VirtReg is live across any register mask operands, compute a list of
1683 // gaps with register masks.
1684 SmallVector<unsigned, 8> RegMaskGaps;
1685 if (Matrix->checkRegMaskInterference(VirtReg)) {
1686 // Get regmask slots for the whole block.
1687 ArrayRef<SlotIndex> RMS = LIS->getRegMaskSlotsInBlock(BI.MBB->getNumber());
1688 DEBUG(dbgs() << RMS.size() << " regmasks in block:");
1689 // Constrain to VirtReg's live range.
1690 unsigned ri = std::lower_bound(RMS.begin(), RMS.end(),
1691 Uses.front().getRegSlot()) - RMS.begin();
1692 unsigned re = RMS.size();
1693 for (unsigned i = 0; i != NumGaps && ri != re; ++i) {
1694 // Look for Uses[i] <= RMS <= Uses[i+1].
1695 assert(!SlotIndex::isEarlierInstr(RMS[ri], Uses[i]));
1696 if (SlotIndex::isEarlierInstr(Uses[i+1], RMS[ri]))
1698 // Skip a regmask on the same instruction as the last use. It doesn't
1699 // overlap the live range.
1700 if (SlotIndex::isSameInstr(Uses[i+1], RMS[ri]) && i+1 == NumGaps)
1702 DEBUG(dbgs() << ' ' << RMS[ri] << ':' << Uses[i] << '-' << Uses[i+1]);
1703 RegMaskGaps.push_back(i);
1704 // Advance ri to the next gap. A regmask on one of the uses counts in
1706 while (ri != re && SlotIndex::isEarlierInstr(RMS[ri], Uses[i+1]))
1709 DEBUG(dbgs() << '\n');
1712 // Since we allow local split results to be split again, there is a risk of
1713 // creating infinite loops. It is tempting to require that the new live
1714 // ranges have less instructions than the original. That would guarantee
1715 // convergence, but it is too strict. A live range with 3 instructions can be
1716 // split 2+3 (including the COPY), and we want to allow that.
1718 // Instead we use these rules:
1720 // 1. Allow any split for ranges with getStage() < RS_Split2. (Except for the
1721 // noop split, of course).
1722 // 2. Require progress be made for ranges with getStage() == RS_Split2. All
1723 // the new ranges must have fewer instructions than before the split.
1724 // 3. New ranges with the same number of instructions are marked RS_Split2,
1725 // smaller ranges are marked RS_New.
1727 // These rules allow a 3 -> 2+3 split once, which we need. They also prevent
1728 // excessive splitting and infinite loops.
1730 bool ProgressRequired = getStage(VirtReg) >= RS_Split2;
1732 // Best split candidate.
1733 unsigned BestBefore = NumGaps;
1734 unsigned BestAfter = 0;
1737 const float blockFreq =
1738 SpillPlacer->getBlockFrequency(BI.MBB->getNumber()).getFrequency() *
1739 (1.0f / MBFI->getEntryFreq());
1740 SmallVector<float, 8> GapWeight;
1743 while (unsigned PhysReg = Order.next()) {
1744 // Keep track of the largest spill weight that would need to be evicted in
1745 // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1].
1746 calcGapWeights(PhysReg, GapWeight);
1748 // Remove any gaps with regmask clobbers.
1749 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg))
1750 for (unsigned i = 0, e = RegMaskGaps.size(); i != e; ++i)
1751 GapWeight[RegMaskGaps[i]] = llvm::huge_valf;
1753 // Try to find the best sequence of gaps to close.
1754 // The new spill weight must be larger than any gap interference.
1756 // We will split before Uses[SplitBefore] and after Uses[SplitAfter].
1757 unsigned SplitBefore = 0, SplitAfter = 1;
1759 // MaxGap should always be max(GapWeight[SplitBefore..SplitAfter-1]).
1760 // It is the spill weight that needs to be evicted.
1761 float MaxGap = GapWeight[0];
1764 // Live before/after split?
1765 const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
1766 const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut;
1768 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' '
1769 << Uses[SplitBefore] << '-' << Uses[SplitAfter]
1770 << " i=" << MaxGap);
1772 // Stop before the interval gets so big we wouldn't be making progress.
1773 if (!LiveBefore && !LiveAfter) {
1774 DEBUG(dbgs() << " all\n");
1777 // Should the interval be extended or shrunk?
1780 // How many gaps would the new range have?
1781 unsigned NewGaps = LiveBefore + SplitAfter - SplitBefore + LiveAfter;
1783 // Legally, without causing looping?
1784 bool Legal = !ProgressRequired || NewGaps < NumGaps;
1786 if (Legal && MaxGap < llvm::huge_valf) {
1787 // Estimate the new spill weight. Each instruction reads or writes the
1788 // register. Conservatively assume there are no read-modify-write
1791 // Try to guess the size of the new interval.
1792 const float EstWeight = normalizeSpillWeight(blockFreq * (NewGaps + 1),
1793 Uses[SplitBefore].distance(Uses[SplitAfter]) +
1794 (LiveBefore + LiveAfter)*SlotIndex::InstrDist);
1795 // Would this split be possible to allocate?
1796 // Never allocate all gaps, we wouldn't be making progress.
1797 DEBUG(dbgs() << " w=" << EstWeight);
1798 if (EstWeight * Hysteresis >= MaxGap) {
1800 float Diff = EstWeight - MaxGap;
1801 if (Diff > BestDiff) {
1802 DEBUG(dbgs() << " (best)");
1803 BestDiff = Hysteresis * Diff;
1804 BestBefore = SplitBefore;
1805 BestAfter = SplitAfter;
1812 if (++SplitBefore < SplitAfter) {
1813 DEBUG(dbgs() << " shrink\n");
1814 // Recompute the max when necessary.
1815 if (GapWeight[SplitBefore - 1] >= MaxGap) {
1816 MaxGap = GapWeight[SplitBefore];
1817 for (unsigned i = SplitBefore + 1; i != SplitAfter; ++i)
1818 MaxGap = std::max(MaxGap, GapWeight[i]);
1825 // Try to extend the interval.
1826 if (SplitAfter >= NumGaps) {
1827 DEBUG(dbgs() << " end\n");
1831 DEBUG(dbgs() << " extend\n");
1832 MaxGap = std::max(MaxGap, GapWeight[SplitAfter++]);
1836 // Didn't find any candidates?
1837 if (BestBefore == NumGaps)
1840 DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore]
1841 << '-' << Uses[BestAfter] << ", " << BestDiff
1842 << ", " << (BestAfter - BestBefore + 1) << " instrs\n");
1844 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
1848 SlotIndex SegStart = SE->enterIntvBefore(Uses[BestBefore]);
1849 SlotIndex SegStop = SE->leaveIntvAfter(Uses[BestAfter]);
1850 SE->useIntv(SegStart, SegStop);
1851 SmallVector<unsigned, 8> IntvMap;
1852 SE->finish(&IntvMap);
1853 DebugVars->splitRegister(VirtReg.reg, LREdit.regs(), *LIS);
1855 // If the new range has the same number of instructions as before, mark it as
1856 // RS_Split2 so the next split will be forced to make progress. Otherwise,
1857 // leave the new intervals as RS_New so they can compete.
1858 bool LiveBefore = BestBefore != 0 || BI.LiveIn;
1859 bool LiveAfter = BestAfter != NumGaps || BI.LiveOut;
1860 unsigned NewGaps = LiveBefore + BestAfter - BestBefore + LiveAfter;
1861 if (NewGaps >= NumGaps) {
1862 DEBUG(dbgs() << "Tagging non-progress ranges: ");
1863 assert(!ProgressRequired && "Didn't make progress when it was required.");
1864 for (unsigned i = 0, e = IntvMap.size(); i != e; ++i)
1865 if (IntvMap[i] == 1) {
1866 setStage(LIS->getInterval(LREdit.get(i)), RS_Split2);
1867 DEBUG(dbgs() << PrintReg(LREdit.get(i)));
1869 DEBUG(dbgs() << '\n');
1876 //===----------------------------------------------------------------------===//
1877 // Live Range Splitting
1878 //===----------------------------------------------------------------------===//
1880 /// trySplit - Try to split VirtReg or one of its interferences, making it
1882 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
1883 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
1884 SmallVectorImpl<unsigned>&NewVRegs) {
1885 // Ranges must be Split2 or less.
1886 if (getStage(VirtReg) >= RS_Spill)
1889 // Local intervals are handled separately.
1890 if (LIS->intervalIsInOneMBB(VirtReg)) {
1891 NamedRegionTimer T("Local Splitting", TimerGroupName, TimePassesIsEnabled);
1892 SA->analyze(&VirtReg);
1893 unsigned PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs);
1894 if (PhysReg || !NewVRegs.empty())
1896 return tryInstructionSplit(VirtReg, Order, NewVRegs);
1899 NamedRegionTimer T("Global Splitting", TimerGroupName, TimePassesIsEnabled);
1901 SA->analyze(&VirtReg);
1903 // FIXME: SplitAnalysis may repair broken live ranges coming from the
1904 // coalescer. That may cause the range to become allocatable which means that
1905 // tryRegionSplit won't be making progress. This check should be replaced with
1906 // an assertion when the coalescer is fixed.
1907 if (SA->didRepairRange()) {
1908 // VirtReg has changed, so all cached queries are invalid.
1909 Matrix->invalidateVirtRegs();
1910 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
1914 // First try to split around a region spanning multiple blocks. RS_Split2
1915 // ranges already made dubious progress with region splitting, so they go
1916 // straight to single block splitting.
1917 if (getStage(VirtReg) < RS_Split2) {
1918 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1919 if (PhysReg || !NewVRegs.empty())
1923 // Then isolate blocks.
1924 return tryBlockSplit(VirtReg, Order, NewVRegs);
1927 //===----------------------------------------------------------------------===//
1928 // Last Chance Recoloring
1929 //===----------------------------------------------------------------------===//
1931 /// mayRecolorAllInterferences - Check if the virtual registers that
1932 /// interfere with \p VirtReg on \p PhysReg (or one of its aliases) may be
1933 /// recolored to free \p PhysReg.
1934 /// When true is returned, \p RecoloringCandidates has been augmented with all
1935 /// the live intervals that need to be recolored in order to free \p PhysReg
1937 /// \p FixedRegisters contains all the virtual registers that cannot be
1940 RAGreedy::mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
1941 SmallLISet &RecoloringCandidates,
1942 const SmallVirtRegSet &FixedRegisters) {
1943 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg);
1945 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1946 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
1947 // If there is LastChanceRecoloringMaxInterference or more interferences,
1948 // chances are one would not be recolorable.
1949 if (Q.collectInterferingVRegs(LastChanceRecoloringMaxInterference) >=
1950 LastChanceRecoloringMaxInterference && !ExhaustiveSearch) {
1951 DEBUG(dbgs() << "Early abort: too many interferences.\n");
1952 CutOffInfo |= CO_Interf;
1955 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
1956 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
1957 // If Intf is done and sit on the same register class as VirtReg,
1958 // it would not be recolorable as it is in the same state as VirtReg.
1959 if ((getStage(*Intf) == RS_Done &&
1960 MRI->getRegClass(Intf->reg) == CurRC) ||
1961 FixedRegisters.count(Intf->reg)) {
1962 DEBUG(dbgs() << "Early abort: the inteference is not recolorable.\n");
1965 RecoloringCandidates.insert(Intf);
1971 /// tryLastChanceRecoloring - Try to assign a color to \p VirtReg by recoloring
1972 /// its interferences.
1973 /// Last chance recoloring chooses a color for \p VirtReg and recolors every
1974 /// virtual register that was using it. The recoloring process may recursively
1975 /// use the last chance recoloring. Therefore, when a virtual register has been
1976 /// assigned a color by this mechanism, it is marked as Fixed, i.e., it cannot
1977 /// be last-chance-recolored again during this recoloring "session".
1980 /// vA can use {R1, R2 }
1981 /// vB can use { R2, R3}
1982 /// vC can use {R1 }
1983 /// Where vA, vB, and vC cannot be split anymore (they are reloads for
1984 /// instance) and they all interfere.
1986 /// vA is assigned R1
1987 /// vB is assigned R2
1988 /// vC tries to evict vA but vA is already done.
1989 /// Regular register allocation fails.
1991 /// Last chance recoloring kicks in:
1992 /// vC does as if vA was evicted => vC uses R1.
1993 /// vC is marked as fixed.
1994 /// vA needs to find a color.
1995 /// None are available.
1996 /// vA cannot evict vC: vC is a fixed virtual register now.
1997 /// vA does as if vB was evicted => vA uses R2.
1998 /// vB needs to find a color.
1999 /// R3 is available.
2000 /// Recoloring => vC = R1, vA = R2, vB = R3
2002 /// \p Order defines the preferred allocation order for \p VirtReg.
2003 /// \p NewRegs will contain any new virtual register that have been created
2004 /// (split, spill) during the process and that must be assigned.
2005 /// \p FixedRegisters contains all the virtual registers that cannot be
2007 /// \p Depth gives the current depth of the last chance recoloring.
2008 /// \return a physical register that can be used for VirtReg or ~0u if none
2010 unsigned RAGreedy::tryLastChanceRecoloring(LiveInterval &VirtReg,
2011 AllocationOrder &Order,
2012 SmallVectorImpl<unsigned> &NewVRegs,
2013 SmallVirtRegSet &FixedRegisters,
2015 DEBUG(dbgs() << "Try last chance recoloring for " << VirtReg << '\n');
2016 // Ranges must be Done.
2017 assert((getStage(VirtReg) >= RS_Done || !VirtReg.isSpillable()) &&
2018 "Last chance recoloring should really be last chance");
2019 // Set the max depth to LastChanceRecoloringMaxDepth.
2020 // We may want to reconsider that if we end up with a too large search space
2021 // for target with hundreds of registers.
2022 // Indeed, in that case we may want to cut the search space earlier.
2023 if (Depth >= LastChanceRecoloringMaxDepth && !ExhaustiveSearch) {
2024 DEBUG(dbgs() << "Abort because max depth has been reached.\n");
2025 CutOffInfo |= CO_Depth;
2029 // Set of Live intervals that will need to be recolored.
2030 SmallLISet RecoloringCandidates;
2031 // Record the original mapping virtual register to physical register in case
2032 // the recoloring fails.
2033 DenseMap<unsigned, unsigned> VirtRegToPhysReg;
2034 // Mark VirtReg as fixed, i.e., it will not be recolored pass this point in
2035 // this recoloring "session".
2036 FixedRegisters.insert(VirtReg.reg);
2039 while (unsigned PhysReg = Order.next()) {
2040 DEBUG(dbgs() << "Try to assign: " << VirtReg << " to "
2041 << PrintReg(PhysReg, TRI) << '\n');
2042 RecoloringCandidates.clear();
2043 VirtRegToPhysReg.clear();
2045 // It is only possible to recolor virtual register interference.
2046 if (Matrix->checkInterference(VirtReg, PhysReg) >
2047 LiveRegMatrix::IK_VirtReg) {
2048 DEBUG(dbgs() << "Some inteferences are not with virtual registers.\n");
2053 // Early give up on this PhysReg if it is obvious we cannot recolor all
2054 // the interferences.
2055 if (!mayRecolorAllInterferences(PhysReg, VirtReg, RecoloringCandidates,
2057 DEBUG(dbgs() << "Some inteferences cannot be recolored.\n");
2061 // RecoloringCandidates contains all the virtual registers that interfer
2062 // with VirtReg on PhysReg (or one of its aliases).
2063 // Enqueue them for recoloring and perform the actual recoloring.
2064 PQueue RecoloringQueue;
2065 for (SmallLISet::iterator It = RecoloringCandidates.begin(),
2066 EndIt = RecoloringCandidates.end();
2067 It != EndIt; ++It) {
2068 unsigned ItVirtReg = (*It)->reg;
2069 enqueue(RecoloringQueue, *It);
2070 assert(VRM->hasPhys(ItVirtReg) &&
2071 "Interferences are supposed to be with allocated vairables");
2073 // Record the current allocation.
2074 VirtRegToPhysReg[ItVirtReg] = VRM->getPhys(ItVirtReg);
2075 // unset the related struct.
2076 Matrix->unassign(**It);
2079 // Do as if VirtReg was assigned to PhysReg so that the underlying
2080 // recoloring has the right information about the interferes and
2081 // available colors.
2082 Matrix->assign(VirtReg, PhysReg);
2084 // Save the current recoloring state.
2085 // If we cannot recolor all the interferences, we will have to start again
2086 // at this point for the next physical register.
2087 SmallVirtRegSet SaveFixedRegisters(FixedRegisters);
2088 if (tryRecoloringCandidates(RecoloringQueue, NewVRegs, FixedRegisters,
2090 // Do not mess up with the global assignment process.
2091 // I.e., VirtReg must be unassigned.
2092 Matrix->unassign(VirtReg);
2096 DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to "
2097 << PrintReg(PhysReg, TRI) << '\n');
2099 // The recoloring attempt failed, undo the changes.
2100 FixedRegisters = SaveFixedRegisters;
2101 Matrix->unassign(VirtReg);
2103 for (SmallLISet::iterator It = RecoloringCandidates.begin(),
2104 EndIt = RecoloringCandidates.end();
2105 It != EndIt; ++It) {
2106 unsigned ItVirtReg = (*It)->reg;
2107 if (VRM->hasPhys(ItVirtReg))
2108 Matrix->unassign(**It);
2109 Matrix->assign(**It, VirtRegToPhysReg[ItVirtReg]);
2113 // Last chance recoloring did not worked either, give up.
2117 /// tryRecoloringCandidates - Try to assign a new color to every register
2118 /// in \RecoloringQueue.
2119 /// \p NewRegs will contain any new virtual register created during the
2120 /// recoloring process.
2121 /// \p FixedRegisters[in/out] contains all the registers that have been
2123 /// \return true if all virtual registers in RecoloringQueue were successfully
2124 /// recolored, false otherwise.
2125 bool RAGreedy::tryRecoloringCandidates(PQueue &RecoloringQueue,
2126 SmallVectorImpl<unsigned> &NewVRegs,
2127 SmallVirtRegSet &FixedRegisters,
2129 while (!RecoloringQueue.empty()) {
2130 LiveInterval *LI = dequeue(RecoloringQueue);
2131 DEBUG(dbgs() << "Try to recolor: " << *LI << '\n');
2133 PhysReg = selectOrSplitImpl(*LI, NewVRegs, FixedRegisters, Depth + 1);
2134 if (PhysReg == ~0u || !PhysReg)
2136 DEBUG(dbgs() << "Recoloring of " << *LI
2137 << " succeeded with: " << PrintReg(PhysReg, TRI) << '\n');
2138 Matrix->assign(*LI, PhysReg);
2139 FixedRegisters.insert(LI->reg);
2144 //===----------------------------------------------------------------------===//
2146 //===----------------------------------------------------------------------===//
2148 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
2149 SmallVectorImpl<unsigned> &NewVRegs) {
2150 CutOffInfo = CO_None;
2151 LLVMContext &Ctx = MF->getFunction()->getContext();
2152 SmallVirtRegSet FixedRegisters;
2153 unsigned Reg = selectOrSplitImpl(VirtReg, NewVRegs, FixedRegisters);
2154 if (Reg == ~0U && (CutOffInfo != CO_None)) {
2155 uint8_t CutOffEncountered = CutOffInfo & (CO_Depth | CO_Interf);
2156 if (CutOffEncountered == CO_Depth)
2157 Ctx.emitError("register allocation failed: maximum depth for recoloring "
2158 "reached. Use -fexhaustive-register-search to skip "
2160 else if (CutOffEncountered == CO_Interf)
2161 Ctx.emitError("register allocation failed: maximum interference for "
2162 "recoloring reached. Use -fexhaustive-register-search "
2164 else if (CutOffEncountered == (CO_Depth | CO_Interf))
2165 Ctx.emitError("register allocation failed: maximum interference and "
2166 "depth for recoloring reached. Use "
2167 "-fexhaustive-register-search to skip cutoffs");
2172 /// Using a CSR for the first time has a cost because it causes push|pop
2173 /// to be added to prologue|epilogue. Splitting a cold section of the live
2174 /// range can have lower cost than using the CSR for the first time;
2175 /// Spilling a live range in the cold path can have lower cost than using
2176 /// the CSR for the first time. Returns the physical register if we decide
2177 /// to use the CSR; otherwise return 0.
2178 unsigned RAGreedy::tryAssignCSRFirstTime(LiveInterval &VirtReg,
2179 AllocationOrder &Order,
2181 unsigned &CostPerUseLimit,
2182 SmallVectorImpl<unsigned> &NewVRegs) {
2183 if (getStage(VirtReg) == RS_Spill && VirtReg.isSpillable()) {
2184 // We choose spill over using the CSR for the first time if the spill cost
2185 // is lower than CSRCost.
2186 SA->analyze(&VirtReg);
2187 if (calcSpillCost() >= CSRCost)
2190 // We are going to spill, set CostPerUseLimit to 1 to make sure that
2191 // we will not use a callee-saved register in tryEvict.
2192 CostPerUseLimit = 1;
2195 if (getStage(VirtReg) < RS_Split) {
2196 // We choose pre-splitting over using the CSR for the first time if
2197 // the cost of splitting is lower than CSRCost.
2198 SA->analyze(&VirtReg);
2199 unsigned NumCands = 0;
2200 BlockFrequency BestCost = CSRCost; // Don't modify CSRCost.
2201 unsigned BestCand = calculateRegionSplitCost(VirtReg, Order, BestCost,
2202 NumCands, true /*IgnoreCSR*/);
2203 if (BestCand == NoCand)
2204 // Use the CSR if we can't find a region split below CSRCost.
2207 // Perform the actual pre-splitting.
2208 doRegionSplit(VirtReg, BestCand, false/*HasCompact*/, NewVRegs);
2214 void RAGreedy::initializeCSRCost() {
2215 // We use the larger one out of the command-line option and the value report
2217 CSRCost = BlockFrequency(
2218 std::max((unsigned)CSRFirstTimeCost, TRI->getCSRFirstUseCost()));
2219 if (!CSRCost.getFrequency())
2222 // Raw cost is relative to Entry == 2^14; scale it appropriately.
2223 uint64_t ActualEntry = MBFI->getEntryFreq();
2228 uint64_t FixedEntry = 1 << 14;
2229 if (ActualEntry < FixedEntry)
2230 CSRCost *= BranchProbability(ActualEntry, FixedEntry);
2231 else if (ActualEntry <= UINT32_MAX)
2232 // Invert the fraction and divide.
2233 CSRCost /= BranchProbability(FixedEntry, ActualEntry);
2235 // Can't use BranchProbability in general, since it takes 32-bit numbers.
2236 CSRCost = CSRCost.getFrequency() * (ActualEntry / FixedEntry);
2239 unsigned RAGreedy::selectOrSplitImpl(LiveInterval &VirtReg,
2240 SmallVectorImpl<unsigned> &NewVRegs,
2241 SmallVirtRegSet &FixedRegisters,
2243 unsigned CostPerUseLimit = ~0u;
2244 // First try assigning a free register.
2245 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
2246 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs)) {
2247 // We check other options if we are using a CSR for the first time.
2248 bool CSRFirstUse = false;
2249 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
2250 if (!MRI->isPhysRegUsed(CSR))
2253 // When NewVRegs is not empty, we may have made decisions such as evicting
2254 // a virtual register, go with the earlier decisions and use the physical
2256 if (CSRCost.getFrequency() && CSRFirstUse && NewVRegs.empty()) {
2257 unsigned CSRReg = tryAssignCSRFirstTime(VirtReg, Order, PhysReg,
2258 CostPerUseLimit, NewVRegs);
2259 if (CSRReg || !NewVRegs.empty())
2260 // Return now if we decide to use a CSR or create new vregs due to
2267 LiveRangeStage Stage = getStage(VirtReg);
2268 DEBUG(dbgs() << StageName[Stage]
2269 << " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n');
2271 // Try to evict a less worthy live range, but only for ranges from the primary
2272 // queue. The RS_Split ranges already failed to do this, and they should not
2273 // get a second chance until they have been split.
2274 if (Stage != RS_Split)
2275 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs, CostPerUseLimit))
2278 assert(NewVRegs.empty() && "Cannot append to existing NewVRegs");
2280 // The first time we see a live range, don't try to split or spill.
2281 // Wait until the second time, when all smaller ranges have been allocated.
2282 // This gives a better picture of the interference to split around.
2283 if (Stage < RS_Split) {
2284 setStage(VirtReg, RS_Split);
2285 DEBUG(dbgs() << "wait for second round\n");
2286 NewVRegs.push_back(VirtReg.reg);
2290 // If we couldn't allocate a register from spilling, there is probably some
2291 // invalid inline assembly. The base class wil report it.
2292 if (Stage >= RS_Done || !VirtReg.isSpillable())
2293 return tryLastChanceRecoloring(VirtReg, Order, NewVRegs, FixedRegisters,
2296 // Try splitting VirtReg or interferences.
2297 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
2298 if (PhysReg || !NewVRegs.empty())
2301 // Finally spill VirtReg itself.
2302 NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
2303 LiveRangeEdit LRE(&VirtReg, NewVRegs, *MF, *LIS, VRM, this);
2304 spiller().spill(LRE);
2305 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Done);
2308 MF->verify(this, "After spilling");
2310 // The live virtual register requesting allocation was spilled, so tell
2311 // the caller not to allocate anything during this round.
2315 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
2316 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
2317 << "********** Function: " << mf.getName() << '\n');
2320 const TargetMachine &TM = MF->getTarget();
2321 TRI = TM.getSubtargetImpl()->getRegisterInfo();
2322 TII = TM.getSubtargetImpl()->getInstrInfo();
2323 RCI.runOnMachineFunction(mf);
2325 EnableLocalReassign = EnableLocalReassignment ||
2326 TM.getSubtargetImpl()->enableRALocalReassignment(TM.getOptLevel());
2329 MF->verify(this, "Before greedy register allocator");
2331 RegAllocBase::init(getAnalysis<VirtRegMap>(),
2332 getAnalysis<LiveIntervals>(),
2333 getAnalysis<LiveRegMatrix>());
2334 Indexes = &getAnalysis<SlotIndexes>();
2335 MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
2336 DomTree = &getAnalysis<MachineDominatorTree>();
2337 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
2338 Loops = &getAnalysis<MachineLoopInfo>();
2339 Bundles = &getAnalysis<EdgeBundles>();
2340 SpillPlacer = &getAnalysis<SpillPlacement>();
2341 DebugVars = &getAnalysis<LiveDebugVariables>();
2343 initializeCSRCost();
2345 calculateSpillWeightsAndHints(*LIS, mf, *Loops, *MBFI);
2349 SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops));
2350 SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree, *MBFI));
2351 ExtraRegInfo.clear();
2352 ExtraRegInfo.resize(MRI->getNumVirtRegs());
2354 IntfCache.init(MF, Matrix->getLiveUnions(), Indexes, LIS, TRI);
2355 GlobalCand.resize(32); // This will grow as needed.