1 //===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RAGreedy function pass for register allocation in
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "AllocationOrder.h"
17 #include "LiveIntervalUnion.h"
18 #include "LiveRangeEdit.h"
19 #include "RegAllocBase.h"
21 #include "SpillPlacement.h"
23 #include "VirtRegMap.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/Function.h"
27 #include "llvm/PassAnalysisSupport.h"
28 #include "llvm/CodeGen/CalcSpillWeights.h"
29 #include "llvm/CodeGen/EdgeBundles.h"
30 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
31 #include "llvm/CodeGen/LiveStackAnalysis.h"
32 #include "llvm/CodeGen/MachineDominators.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineLoopInfo.h"
35 #include "llvm/CodeGen/MachineLoopRanges.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/CodeGen/RegAllocRegistry.h"
39 #include "llvm/CodeGen/RegisterCoalescer.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/raw_ostream.h"
44 #include "llvm/Support/Timer.h"
50 STATISTIC(NumGlobalSplits, "Number of split global live ranges");
51 STATISTIC(NumLocalSplits, "Number of split local live ranges");
52 STATISTIC(NumReassigned, "Number of interferences reassigned");
53 STATISTIC(NumEvicted, "Number of interferences evicted");
55 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
56 createGreedyRegisterAllocator);
59 class RAGreedy : public MachineFunctionPass,
61 private LiveRangeEdit::Delegate {
65 BitVector ReservedRegs;
70 MachineDominatorTree *DomTree;
71 MachineLoopInfo *Loops;
72 MachineLoopRanges *LoopRanges;
74 SpillPlacement *SpillPlacer;
77 std::auto_ptr<Spiller> SpillerInstance;
78 std::priority_queue<std::pair<unsigned, unsigned> > Queue;
80 // Live ranges pass through a number of stages as we try to allocate them.
81 // Some of the stages may also create new live ranges:
83 // - Region splitting.
84 // - Per-block splitting.
88 // Ranges produced by one of the stages skip the previous stages when they are
89 // dequeued. This improves performance because we can skip interference checks
90 // that are unlikely to give any results. It also guarantees that the live
91 // range splitting algorithm terminates, something that is otherwise hard to
94 RS_Original, ///< Never seen before, never split.
95 RS_Second, ///< Second time in the queue.
96 RS_Region, ///< Produced by region splitting.
97 RS_Block, ///< Produced by per-block splitting.
98 RS_Local, ///< Produced by local splitting.
99 RS_Spill ///< Produced by spilling.
102 IndexedMap<unsigned char, VirtReg2IndexFunctor> LRStage;
104 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
105 return LiveRangeStage(LRStage[VirtReg.reg]);
108 template<typename Iterator>
109 void setStage(Iterator Begin, Iterator End, LiveRangeStage NewStage) {
110 LRStage.resize(MRI->getNumVirtRegs());
111 for (;Begin != End; ++Begin)
112 LRStage[(*Begin)->reg] = NewStage;
116 std::auto_ptr<SplitAnalysis> SA;
117 std::auto_ptr<SplitEditor> SE;
119 /// All basic blocks where the current register is live.
120 SmallVector<SpillPlacement::BlockConstraint, 8> SplitConstraints;
122 typedef std::pair<SlotIndex, SlotIndex> IndexPair;
124 /// Global live range splitting candidate info.
125 struct GlobalSplitCandidate {
127 SmallVector<IndexPair, 8> Interference;
128 BitVector LiveBundles;
131 /// Candidate info for for each PhysReg in AllocationOrder.
132 /// This vector never shrinks, but grows to the size of the largest register
134 SmallVector<GlobalSplitCandidate, 32> GlobalCand;
136 /// For every instruction in SA->UseSlots, store the previous non-copy
138 SmallVector<SlotIndex, 8> PrevSlot;
143 /// Return the pass name.
144 virtual const char* getPassName() const {
145 return "Greedy Register Allocator";
148 /// RAGreedy analysis usage.
149 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
150 virtual void releaseMemory();
151 virtual Spiller &spiller() { return *SpillerInstance; }
152 virtual void enqueue(LiveInterval *LI);
153 virtual LiveInterval *dequeue();
154 virtual unsigned selectOrSplit(LiveInterval&,
155 SmallVectorImpl<LiveInterval*>&);
157 /// Perform register allocation.
158 virtual bool runOnMachineFunction(MachineFunction &mf);
163 void LRE_WillEraseInstruction(MachineInstr*);
165 bool checkUncachedInterference(LiveInterval&, unsigned);
166 LiveInterval *getSingleInterference(LiveInterval&, unsigned);
167 bool reassignVReg(LiveInterval &InterferingVReg, unsigned OldPhysReg);
169 void mapGlobalInterference(unsigned, SmallVectorImpl<IndexPair>&);
170 float calcSplitConstraints(const SmallVectorImpl<IndexPair>&);
172 float calcGlobalSplitCost(const BitVector&);
173 void splitAroundRegion(LiveInterval&, unsigned, const BitVector&,
174 SmallVectorImpl<LiveInterval*>&);
175 void calcGapWeights(unsigned, SmallVectorImpl<float>&);
176 SlotIndex getPrevMappedIndex(const MachineInstr*);
177 void calcPrevSlots();
178 unsigned nextSplitPoint(unsigned);
179 bool canEvictInterference(LiveInterval&, unsigned, float&);
181 unsigned tryReassign(LiveInterval&, AllocationOrder&,
182 SmallVectorImpl<LiveInterval*>&);
183 unsigned tryEvict(LiveInterval&, AllocationOrder&,
184 SmallVectorImpl<LiveInterval*>&);
185 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
186 SmallVectorImpl<LiveInterval*>&);
187 unsigned tryLocalSplit(LiveInterval&, AllocationOrder&,
188 SmallVectorImpl<LiveInterval*>&);
189 unsigned trySplit(LiveInterval&, AllocationOrder&,
190 SmallVectorImpl<LiveInterval*>&);
192 } // end anonymous namespace
194 char RAGreedy::ID = 0;
196 FunctionPass* llvm::createGreedyRegisterAllocator() {
197 return new RAGreedy();
200 RAGreedy::RAGreedy(): MachineFunctionPass(ID), LRStage(RS_Original) {
201 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
202 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
203 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
204 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
205 initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
206 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
207 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
208 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
209 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
210 initializeMachineLoopRangesPass(*PassRegistry::getPassRegistry());
211 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
212 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
213 initializeSpillPlacementPass(*PassRegistry::getPassRegistry());
216 void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
217 AU.setPreservesCFG();
218 AU.addRequired<AliasAnalysis>();
219 AU.addPreserved<AliasAnalysis>();
220 AU.addRequired<LiveIntervals>();
221 AU.addRequired<SlotIndexes>();
222 AU.addPreserved<SlotIndexes>();
224 AU.addRequiredID(StrongPHIEliminationID);
225 AU.addRequiredTransitive<RegisterCoalescer>();
226 AU.addRequired<CalculateSpillWeights>();
227 AU.addRequired<LiveStacks>();
228 AU.addPreserved<LiveStacks>();
229 AU.addRequired<MachineDominatorTree>();
230 AU.addPreserved<MachineDominatorTree>();
231 AU.addRequired<MachineLoopInfo>();
232 AU.addPreserved<MachineLoopInfo>();
233 AU.addRequired<MachineLoopRanges>();
234 AU.addPreserved<MachineLoopRanges>();
235 AU.addRequired<VirtRegMap>();
236 AU.addPreserved<VirtRegMap>();
237 AU.addRequired<EdgeBundles>();
238 AU.addRequired<SpillPlacement>();
239 MachineFunctionPass::getAnalysisUsage(AU);
243 //===----------------------------------------------------------------------===//
244 // LiveRangeEdit delegate methods
245 //===----------------------------------------------------------------------===//
247 void RAGreedy::LRE_WillEraseInstruction(MachineInstr *MI) {
248 // LRE itself will remove from SlotIndexes and parent basic block.
249 VRM->RemoveMachineInstrFromMaps(MI);
253 void RAGreedy::releaseMemory() {
254 SpillerInstance.reset(0);
256 RegAllocBase::releaseMemory();
259 void RAGreedy::enqueue(LiveInterval *LI) {
260 // Prioritize live ranges by size, assigning larger ranges first.
261 // The queue holds (size, reg) pairs.
262 const unsigned Size = LI->getSize();
263 const unsigned Reg = LI->reg;
264 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
265 "Can only enqueue virtual registers");
269 if (LRStage[Reg] == RS_Original)
270 // 1st generation ranges are handled first, long -> short.
271 Prio = (1u << 31) + Size;
273 // Repeat offenders are handled second, short -> long
274 Prio = (1u << 30) - Size;
276 // Boost ranges that have a physical register hint.
277 const unsigned Hint = VRM->getRegAllocPref(Reg);
278 if (TargetRegisterInfo::isPhysicalRegister(Hint))
281 Queue.push(std::make_pair(Prio, Reg));
284 LiveInterval *RAGreedy::dequeue() {
287 LiveInterval *LI = &LIS->getInterval(Queue.top().second);
292 //===----------------------------------------------------------------------===//
293 // Register Reassignment
294 //===----------------------------------------------------------------------===//
296 // Check interference without using the cache.
297 bool RAGreedy::checkUncachedInterference(LiveInterval &VirtReg,
299 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
300 LiveIntervalUnion::Query subQ(&VirtReg, &PhysReg2LiveUnion[*AliasI]);
301 if (subQ.checkInterference())
307 /// getSingleInterference - Return the single interfering virtual register
308 /// assigned to PhysReg. Return 0 if more than one virtual register is
310 LiveInterval *RAGreedy::getSingleInterference(LiveInterval &VirtReg,
312 // Check physreg and aliases.
313 LiveInterval *Interference = 0;
314 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
315 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
316 if (Q.checkInterference()) {
319 if (Q.collectInterferingVRegs(2) > 1)
321 Interference = Q.interferingVRegs().front();
327 // Attempt to reassign this virtual register to a different physical register.
329 // FIXME: we are not yet caching these "second-level" interferences discovered
330 // in the sub-queries. These interferences can change with each call to
331 // selectOrSplit. However, we could implement a "may-interfere" cache that
332 // could be conservatively dirtied when we reassign or split.
334 // FIXME: This may result in a lot of alias queries. We could summarize alias
335 // live intervals in their parent register's live union, but it's messy.
336 bool RAGreedy::reassignVReg(LiveInterval &InterferingVReg,
337 unsigned WantedPhysReg) {
338 assert(TargetRegisterInfo::isVirtualRegister(InterferingVReg.reg) &&
339 "Can only reassign virtual registers");
340 assert(TRI->regsOverlap(WantedPhysReg, VRM->getPhys(InterferingVReg.reg)) &&
341 "inconsistent phys reg assigment");
343 AllocationOrder Order(InterferingVReg.reg, *VRM, ReservedRegs);
344 while (unsigned PhysReg = Order.next()) {
345 // Don't reassign to a WantedPhysReg alias.
346 if (TRI->regsOverlap(PhysReg, WantedPhysReg))
349 if (checkUncachedInterference(InterferingVReg, PhysReg))
352 // Reassign the interfering virtual reg to this physical reg.
353 unsigned OldAssign = VRM->getPhys(InterferingVReg.reg);
354 DEBUG(dbgs() << "reassigning: " << InterferingVReg << " from " <<
355 TRI->getName(OldAssign) << " to " << TRI->getName(PhysReg) << '\n');
356 unassign(InterferingVReg, OldAssign);
357 assign(InterferingVReg, PhysReg);
364 /// tryReassign - Try to reassign a single interference to a different physreg.
365 /// @param VirtReg Currently unassigned virtual register.
366 /// @param Order Physregs to try.
367 /// @return Physreg to assign VirtReg, or 0.
368 unsigned RAGreedy::tryReassign(LiveInterval &VirtReg, AllocationOrder &Order,
369 SmallVectorImpl<LiveInterval*> &NewVRegs){
370 NamedRegionTimer T("Reassign", TimerGroupName, TimePassesIsEnabled);
373 while (unsigned PhysReg = Order.next()) {
374 LiveInterval *InterferingVReg = getSingleInterference(VirtReg, PhysReg);
375 if (!InterferingVReg)
377 if (TargetRegisterInfo::isPhysicalRegister(InterferingVReg->reg))
379 if (reassignVReg(*InterferingVReg, PhysReg))
386 //===----------------------------------------------------------------------===//
387 // Interference eviction
388 //===----------------------------------------------------------------------===//
390 /// canEvict - Return true if all interferences between VirtReg and PhysReg can
391 /// be evicted. Set maxWeight to the maximal spill weight of an interference.
392 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
395 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
396 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
397 // If there is 10 or more interferences, chances are one is smaller.
398 if (Q.collectInterferingVRegs(10) >= 10)
401 // Check if any interfering live range is heavier than VirtReg.
402 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
403 LiveInterval *Intf = Q.interferingVRegs()[i];
404 if (TargetRegisterInfo::isPhysicalRegister(Intf->reg))
406 if (Intf->weight >= VirtReg.weight)
408 Weight = std::max(Weight, Intf->weight);
415 /// tryEvict - Try to evict all interferences for a physreg.
416 /// @param VirtReg Currently unassigned virtual register.
417 /// @param Order Physregs to try.
418 /// @return Physreg to assign VirtReg, or 0.
419 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
420 AllocationOrder &Order,
421 SmallVectorImpl<LiveInterval*> &NewVRegs){
422 NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled);
424 // Keep track of the lightest single interference seen so far.
425 float BestWeight = 0;
426 unsigned BestPhys = 0;
429 while (unsigned PhysReg = Order.next()) {
431 if (!canEvictInterference(VirtReg, PhysReg, Weight))
434 // This is an eviction candidate.
435 DEBUG(dbgs() << "max " << PrintReg(PhysReg, TRI) << " interference = "
437 if (BestPhys && Weight >= BestWeight)
443 // Stop if the hint can be used.
444 if (Order.isHint(PhysReg))
451 DEBUG(dbgs() << "evicting " << PrintReg(BestPhys, TRI) << " interference\n");
452 for (const unsigned *AliasI = TRI->getOverlaps(BestPhys); *AliasI; ++AliasI) {
453 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
454 assert(Q.seenAllInterferences() && "Didn't check all interfererences.");
455 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
456 LiveInterval *Intf = Q.interferingVRegs()[i];
457 unassign(*Intf, VRM->getPhys(Intf->reg));
459 NewVRegs.push_back(Intf);
466 //===----------------------------------------------------------------------===//
468 //===----------------------------------------------------------------------===//
470 /// mapGlobalInterference - Compute a map of the interference from PhysReg and
471 /// its aliases in each block in SA->LiveBlocks.
472 /// If LiveBlocks[i] is live-in, Ranges[i].first is the first interference.
473 /// If LiveBlocks[i] is live-out, Ranges[i].second is the last interference.
474 void RAGreedy::mapGlobalInterference(unsigned PhysReg,
475 SmallVectorImpl<IndexPair> &Ranges) {
476 Ranges.assign(SA->LiveBlocks.size(), IndexPair());
477 LiveInterval &VirtReg = const_cast<LiveInterval&>(SA->getParent());
478 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
479 if (!query(VirtReg, *AI).checkInterference())
481 LiveIntervalUnion::SegmentIter IntI =
482 PhysReg2LiveUnion[*AI].find(VirtReg.beginIndex());
485 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
486 const SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
487 IndexPair &IP = Ranges[i];
489 // Skip interference-free blocks.
490 if (IntI.start() >= BI.Stop)
493 // First interference in block.
495 IntI.advanceTo(BI.Start);
498 if (IntI.start() >= BI.Stop)
500 if (!IP.first.isValid() || IntI.start() < IP.first)
501 IP.first = IntI.start();
504 // Last interference in block.
506 IntI.advanceTo(BI.Stop);
507 if (!IntI.valid() || IntI.start() >= BI.Stop)
509 if (IntI.stop() <= BI.Start)
511 if (!IP.second.isValid() || IntI.stop() > IP.second)
512 IP.second = IntI.stop();
518 /// calcSplitConstraints - Fill out the SplitConstraints vector based on the
519 /// interference pattern in Intf. Return the static cost of this split,
520 /// assuming that all preferences in SplitConstraints are met.
521 float RAGreedy::calcSplitConstraints(const SmallVectorImpl<IndexPair> &Intf) {
522 // Reset interference dependent info.
523 SplitConstraints.resize(SA->LiveBlocks.size());
524 float StaticCost = 0;
525 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
526 SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
527 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
528 IndexPair IP = Intf[i];
530 BC.Number = BI.MBB->getNumber();
531 BC.Entry = (BI.Uses && BI.LiveIn) ?
532 SpillPlacement::PrefReg : SpillPlacement::DontCare;
533 BC.Exit = (BI.Uses && BI.LiveOut) ?
534 SpillPlacement::PrefReg : SpillPlacement::DontCare;
536 // Number of spill code instructions to insert.
539 // Interference for the live-in value.
540 if (IP.first.isValid()) {
541 if (IP.first <= BI.Start)
542 BC.Entry = SpillPlacement::MustSpill, Ins += BI.Uses;
544 BC.Entry = SpillPlacement::PrefSpill;
545 else if (IP.first < BI.FirstUse)
546 BC.Entry = SpillPlacement::PrefSpill, ++Ins;
547 else if (IP.first < (BI.LiveThrough ? BI.LastUse : BI.Kill))
551 // Interference for the live-out value.
552 if (IP.second.isValid()) {
553 if (IP.second >= BI.LastSplitPoint)
554 BC.Exit = SpillPlacement::MustSpill, Ins += BI.Uses;
556 BC.Exit = SpillPlacement::PrefSpill;
557 else if (IP.second > BI.LastUse)
558 BC.Exit = SpillPlacement::PrefSpill, ++Ins;
559 else if (IP.second > (BI.LiveThrough ? BI.FirstUse : BI.Def))
563 // Accumulate the total frequency of inserted spill code.
565 StaticCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
571 /// calcGlobalSplitCost - Return the global split cost of following the split
572 /// pattern in LiveBundles. This cost should be added to the local cost of the
573 /// interference pattern in SplitConstraints.
575 float RAGreedy::calcGlobalSplitCost(const BitVector &LiveBundles) {
576 float GlobalCost = 0;
577 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
578 SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
579 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
580 bool RegIn = LiveBundles[Bundles->getBundle(BC.Number, 0)];
581 bool RegOut = LiveBundles[Bundles->getBundle(BC.Number, 1)];
585 Ins += RegIn != RegOut;
588 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg);
590 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg);
593 GlobalCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
598 /// splitAroundRegion - Split VirtReg around the region determined by
599 /// LiveBundles. Make an effort to avoid interference from PhysReg.
601 /// The 'register' interval is going to contain as many uses as possible while
602 /// avoiding interference. The 'stack' interval is the complement constructed by
603 /// SplitEditor. It will contain the rest.
605 void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, unsigned PhysReg,
606 const BitVector &LiveBundles,
607 SmallVectorImpl<LiveInterval*> &NewVRegs) {
609 dbgs() << "Splitting around region for " << PrintReg(PhysReg, TRI)
611 for (int i = LiveBundles.find_first(); i>=0; i = LiveBundles.find_next(i))
612 dbgs() << " EB#" << i;
616 // First compute interference ranges in the live blocks.
617 SmallVector<IndexPair, 8> InterferenceRanges;
618 mapGlobalInterference(PhysReg, InterferenceRanges);
620 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
623 // Create the main cross-block interval.
626 // First add all defs that are live out of a block.
627 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
628 SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
629 bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)];
630 bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)];
632 // Should the register be live out?
633 if (!BI.LiveOut || !RegOut)
636 IndexPair &IP = InterferenceRanges[i];
637 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " -> EB#"
638 << Bundles->getBundle(BI.MBB->getNumber(), 1)
639 << " intf [" << IP.first << ';' << IP.second << ')');
641 // The interference interval should either be invalid or overlap MBB.
642 assert((!IP.first.isValid() || IP.first < BI.Stop) && "Bad interference");
643 assert((!IP.second.isValid() || IP.second > BI.Start)
644 && "Bad interference");
646 // Check interference leaving the block.
647 if (!IP.second.isValid()) {
648 // Block is interference-free.
649 DEBUG(dbgs() << ", no interference");
651 assert(BI.LiveThrough && "No uses, but not live through block?");
652 // Block is live-through without interference.
653 DEBUG(dbgs() << ", no uses"
654 << (RegIn ? ", live-through.\n" : ", stack in.\n"));
656 SE->enterIntvAtEnd(*BI.MBB);
659 if (!BI.LiveThrough) {
660 DEBUG(dbgs() << ", not live-through.\n");
661 SE->useIntv(SE->enterIntvBefore(BI.Def), BI.Stop);
665 // Block is live-through, but entry bundle is on the stack.
666 // Reload just before the first use.
667 DEBUG(dbgs() << ", not live-in, enter before first use.\n");
668 SE->useIntv(SE->enterIntvBefore(BI.FirstUse), BI.Stop);
671 DEBUG(dbgs() << ", live-through.\n");
675 // Block has interference.
676 DEBUG(dbgs() << ", interference to " << IP.second);
678 if (!BI.LiveThrough && IP.second <= BI.Def) {
679 // The interference doesn't reach the outgoing segment.
680 DEBUG(dbgs() << " doesn't affect def from " << BI.Def << '\n');
681 SE->useIntv(BI.Def, BI.Stop);
687 // No uses in block, avoid interference by reloading as late as possible.
688 DEBUG(dbgs() << ", no uses.\n");
689 SlotIndex SegStart = SE->enterIntvAtEnd(*BI.MBB);
690 assert(SegStart >= IP.second && "Couldn't avoid interference");
694 if (IP.second.getBoundaryIndex() < BI.LastUse) {
695 // There are interference-free uses at the end of the block.
696 // Find the first use that can get the live-out register.
697 SmallVectorImpl<SlotIndex>::const_iterator UI =
698 std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(),
699 IP.second.getBoundaryIndex());
700 assert(UI != SA->UseSlots.end() && "Couldn't find last use");
702 assert(Use <= BI.LastUse && "Couldn't find last use");
703 // Only attempt a split befroe the last split point.
704 if (Use.getBaseIndex() <= BI.LastSplitPoint) {
705 DEBUG(dbgs() << ", free use at " << Use << ".\n");
706 SlotIndex SegStart = SE->enterIntvBefore(Use);
707 assert(SegStart >= IP.second && "Couldn't avoid interference");
708 assert(SegStart < BI.LastSplitPoint && "Impossible split point");
709 SE->useIntv(SegStart, BI.Stop);
714 // Interference is after the last use.
715 DEBUG(dbgs() << " after last use.\n");
716 SlotIndex SegStart = SE->enterIntvAtEnd(*BI.MBB);
717 assert(SegStart >= IP.second && "Couldn't avoid interference");
720 // Now all defs leading to live bundles are handled, do everything else.
721 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
722 SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
723 bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)];
724 bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)];
726 // Is the register live-in?
727 if (!BI.LiveIn || !RegIn)
730 // We have an incoming register. Check for interference.
731 IndexPair &IP = InterferenceRanges[i];
733 DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0)
734 << " -> BB#" << BI.MBB->getNumber());
736 // Check interference entering the block.
737 if (!IP.first.isValid()) {
738 // Block is interference-free.
739 DEBUG(dbgs() << ", no interference");
741 assert(BI.LiveThrough && "No uses, but not live through block?");
742 // Block is live-through without interference.
744 DEBUG(dbgs() << ", no uses, live-through.\n");
745 SE->useIntv(BI.Start, BI.Stop);
747 DEBUG(dbgs() << ", no uses, stack-out.\n");
748 SE->leaveIntvAtTop(*BI.MBB);
752 if (!BI.LiveThrough) {
753 DEBUG(dbgs() << ", killed in block.\n");
754 SE->useIntv(BI.Start, SE->leaveIntvAfter(BI.Kill));
758 // Block is live-through, but exit bundle is on the stack.
759 // Spill immediately after the last use.
760 if (BI.LastUse < BI.LastSplitPoint) {
761 DEBUG(dbgs() << ", uses, stack-out.\n");
762 SE->useIntv(BI.Start, SE->leaveIntvAfter(BI.LastUse));
765 // The last use is after the last split point, it is probably an
767 DEBUG(dbgs() << ", uses at " << BI.LastUse << " after split point "
768 << BI.LastSplitPoint << ", stack-out.\n");
769 SlotIndex SegEnd = SE->leaveIntvBefore(BI.LastSplitPoint);
770 SE->useIntv(BI.Start, SegEnd);
771 // Run a double interval from the split to the last use.
772 // This makes it possible to spill the complement without affecting the
774 SE->overlapIntv(SegEnd, BI.LastUse);
777 // Register is live-through.
778 DEBUG(dbgs() << ", uses, live-through.\n");
779 SE->useIntv(BI.Start, BI.Stop);
783 // Block has interference.
784 DEBUG(dbgs() << ", interference from " << IP.first);
786 if (!BI.LiveThrough && IP.first >= BI.Kill) {
787 // The interference doesn't reach the outgoing segment.
788 DEBUG(dbgs() << " doesn't affect kill at " << BI.Kill << '\n');
789 SE->useIntv(BI.Start, BI.Kill);
794 // No uses in block, avoid interference by spilling as soon as possible.
795 DEBUG(dbgs() << ", no uses.\n");
796 SlotIndex SegEnd = SE->leaveIntvAtTop(*BI.MBB);
797 assert(SegEnd <= IP.first && "Couldn't avoid interference");
800 if (IP.first.getBaseIndex() > BI.FirstUse) {
801 // There are interference-free uses at the beginning of the block.
802 // Find the last use that can get the register.
803 SmallVectorImpl<SlotIndex>::const_iterator UI =
804 std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(),
805 IP.first.getBaseIndex());
806 assert(UI != SA->UseSlots.begin() && "Couldn't find first use");
807 SlotIndex Use = (--UI)->getBoundaryIndex();
808 DEBUG(dbgs() << ", free use at " << *UI << ".\n");
809 SlotIndex SegEnd = SE->leaveIntvAfter(Use);
810 assert(SegEnd <= IP.first && "Couldn't avoid interference");
811 SE->useIntv(BI.Start, SegEnd);
815 // Interference is before the first use.
816 DEBUG(dbgs() << " before first use.\n");
817 SlotIndex SegEnd = SE->leaveIntvAtTop(*BI.MBB);
818 assert(SegEnd <= IP.first && "Couldn't avoid interference");
823 // FIXME: Should we be more aggressive about splitting the stack region into
824 // per-block segments? The current approach allows the stack region to
825 // separate into connected components. Some components may be allocatable.
830 MF->verify(this, "After splitting live range around region");
833 // Make sure that at least one of the new intervals can allocate to PhysReg.
834 // That was the whole point of splitting the live range.
836 for (LiveRangeEdit::iterator I = LREdit.begin(), E = LREdit.end(); I != E;
838 if (!checkUncachedInterference(**I, PhysReg)) {
842 assert(found && "No allocatable intervals after pointless splitting");
847 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
848 SmallVectorImpl<LiveInterval*> &NewVRegs) {
849 BitVector LiveBundles, BestBundles;
851 unsigned BestReg = 0;
854 for (unsigned Cand = 0; unsigned PhysReg = Order.next(); ++Cand) {
855 if (GlobalCand.size() <= Cand)
856 GlobalCand.resize(Cand+1);
857 GlobalCand[Cand].PhysReg = PhysReg;
859 mapGlobalInterference(PhysReg, GlobalCand[Cand].Interference);
860 float Cost = calcSplitConstraints(GlobalCand[Cand].Interference);
861 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = " << Cost);
862 if (BestReg && Cost >= BestCost) {
863 DEBUG(dbgs() << " higher.\n");
867 SpillPlacer->placeSpills(SplitConstraints, LiveBundles);
868 // No live bundles, defer to splitSingleBlocks().
869 if (!LiveBundles.any()) {
870 DEBUG(dbgs() << " no bundles.\n");
874 Cost += calcGlobalSplitCost(LiveBundles);
876 dbgs() << ", total = " << Cost << " with bundles";
877 for (int i = LiveBundles.find_first(); i>=0; i = LiveBundles.find_next(i))
878 dbgs() << " EB#" << i;
881 if (!BestReg || Cost < BestCost) {
883 BestCost = 0.98f * Cost; // Prevent rounding effects.
884 BestBundles.swap(LiveBundles);
891 splitAroundRegion(VirtReg, BestReg, BestBundles, NewVRegs);
892 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Region);
897 //===----------------------------------------------------------------------===//
899 //===----------------------------------------------------------------------===//
902 /// calcGapWeights - Compute the maximum spill weight that needs to be evicted
903 /// in order to use PhysReg between two entries in SA->UseSlots.
905 /// GapWeight[i] represents the gap between UseSlots[i] and UseSlots[i+1].
907 void RAGreedy::calcGapWeights(unsigned PhysReg,
908 SmallVectorImpl<float> &GapWeight) {
909 assert(SA->LiveBlocks.size() == 1 && "Not a local interval");
910 const SplitAnalysis::BlockInfo &BI = SA->LiveBlocks.front();
911 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
912 const unsigned NumGaps = Uses.size()-1;
914 // Start and end points for the interference check.
915 SlotIndex StartIdx = BI.LiveIn ? BI.FirstUse.getBaseIndex() : BI.FirstUse;
916 SlotIndex StopIdx = BI.LiveOut ? BI.LastUse.getBoundaryIndex() : BI.LastUse;
918 GapWeight.assign(NumGaps, 0.0f);
920 // Add interference from each overlapping register.
921 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
922 if (!query(const_cast<LiveInterval&>(SA->getParent()), *AI)
923 .checkInterference())
926 // We know that VirtReg is a continuous interval from FirstUse to LastUse,
927 // so we don't need InterferenceQuery.
929 // Interference that overlaps an instruction is counted in both gaps
930 // surrounding the instruction. The exception is interference before
931 // StartIdx and after StopIdx.
933 LiveIntervalUnion::SegmentIter IntI = PhysReg2LiveUnion[*AI].find(StartIdx);
934 for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) {
935 // Skip the gaps before IntI.
936 while (Uses[Gap+1].getBoundaryIndex() < IntI.start())
937 if (++Gap == NumGaps)
942 // Update the gaps covered by IntI.
943 const float weight = IntI.value()->weight;
944 for (; Gap != NumGaps; ++Gap) {
945 GapWeight[Gap] = std::max(GapWeight[Gap], weight);
946 if (Uses[Gap+1].getBaseIndex() >= IntI.stop())
955 /// getPrevMappedIndex - Return the slot index of the last non-copy instruction
956 /// before MI that has a slot index. If MI is the first mapped instruction in
957 /// its block, return the block start index instead.
959 SlotIndex RAGreedy::getPrevMappedIndex(const MachineInstr *MI) {
960 assert(MI && "Missing MachineInstr");
961 const MachineBasicBlock *MBB = MI->getParent();
962 MachineBasicBlock::const_iterator B = MBB->begin(), I = MI;
964 if (!(--I)->isDebugValue() && !I->isCopy())
965 return Indexes->getInstructionIndex(I);
966 return Indexes->getMBBStartIdx(MBB);
969 /// calcPrevSlots - Fill in the PrevSlot array with the index of the previous
970 /// real non-copy instruction for each instruction in SA->UseSlots.
972 void RAGreedy::calcPrevSlots() {
973 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
975 PrevSlot.reserve(Uses.size());
976 for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
977 const MachineInstr *MI = Indexes->getInstructionFromIndex(Uses[i]);
978 PrevSlot.push_back(getPrevMappedIndex(MI).getDefIndex());
982 /// nextSplitPoint - Find the next index into SA->UseSlots > i such that it may
983 /// be beneficial to split before UseSlots[i].
985 /// 0 is always a valid split point
986 unsigned RAGreedy::nextSplitPoint(unsigned i) {
987 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
988 const unsigned Size = Uses.size();
989 assert(i != Size && "No split points after the end");
990 // Allow split before i when Uses[i] is not adjacent to the previous use.
991 while (++i != Size && PrevSlot[i].getBaseIndex() <= Uses[i-1].getBaseIndex())
996 /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
999 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1000 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1001 assert(SA->LiveBlocks.size() == 1 && "Not a local interval");
1002 const SplitAnalysis::BlockInfo &BI = SA->LiveBlocks.front();
1004 // Note that it is possible to have an interval that is live-in or live-out
1005 // while only covering a single block - A phi-def can use undef values from
1006 // predecessors, and the block could be a single-block loop.
1007 // We don't bother doing anything clever about such a case, we simply assume
1008 // that the interval is continuous from FirstUse to LastUse. We should make
1009 // sure that we don't do anything illegal to such an interval, though.
1011 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
1012 if (Uses.size() <= 2)
1014 const unsigned NumGaps = Uses.size()-1;
1017 dbgs() << "tryLocalSplit: ";
1018 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
1019 dbgs() << ' ' << SA->UseSlots[i];
1023 // For every use, find the previous mapped non-copy instruction.
1024 // We use this to detect valid split points, and to estimate new interval
1028 unsigned BestBefore = NumGaps;
1029 unsigned BestAfter = 0;
1032 const float blockFreq = SpillPlacer->getBlockFrequency(BI.MBB->getNumber());
1033 SmallVector<float, 8> GapWeight;
1036 while (unsigned PhysReg = Order.next()) {
1037 // Keep track of the largest spill weight that would need to be evicted in
1038 // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1].
1039 calcGapWeights(PhysReg, GapWeight);
1041 // Try to find the best sequence of gaps to close.
1042 // The new spill weight must be larger than any gap interference.
1044 // We will split before Uses[SplitBefore] and after Uses[SplitAfter].
1045 unsigned SplitBefore = 0, SplitAfter = nextSplitPoint(1) - 1;
1047 // MaxGap should always be max(GapWeight[SplitBefore..SplitAfter-1]).
1048 // It is the spill weight that needs to be evicted.
1049 float MaxGap = GapWeight[0];
1050 for (unsigned i = 1; i != SplitAfter; ++i)
1051 MaxGap = std::max(MaxGap, GapWeight[i]);
1054 // Live before/after split?
1055 const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
1056 const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut;
1058 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' '
1059 << Uses[SplitBefore] << '-' << Uses[SplitAfter]
1060 << " i=" << MaxGap);
1062 // Stop before the interval gets so big we wouldn't be making progress.
1063 if (!LiveBefore && !LiveAfter) {
1064 DEBUG(dbgs() << " all\n");
1067 // Should the interval be extended or shrunk?
1069 if (MaxGap < HUGE_VALF) {
1070 // Estimate the new spill weight.
1072 // Each instruction reads and writes the register, except the first
1073 // instr doesn't read when !FirstLive, and the last instr doesn't write
1076 // We will be inserting copies before and after, so the total number of
1077 // reads and writes is 2 * EstUses.
1079 const unsigned EstUses = 2*(SplitAfter - SplitBefore) +
1080 2*(LiveBefore + LiveAfter);
1082 // Try to guess the size of the new interval. This should be trivial,
1083 // but the slot index of an inserted copy can be a lot smaller than the
1084 // instruction it is inserted before if there are many dead indexes
1087 // We measure the distance from the instruction before SplitBefore to
1088 // get a conservative estimate.
1090 // The final distance can still be different if inserting copies
1091 // triggers a slot index renumbering.
1093 const float EstWeight = normalizeSpillWeight(blockFreq * EstUses,
1094 PrevSlot[SplitBefore].distance(Uses[SplitAfter]));
1095 // Would this split be possible to allocate?
1096 // Never allocate all gaps, we wouldn't be making progress.
1097 float Diff = EstWeight - MaxGap;
1098 DEBUG(dbgs() << " w=" << EstWeight << " d=" << Diff);
1101 if (Diff > BestDiff) {
1102 DEBUG(dbgs() << " (best)");
1104 BestBefore = SplitBefore;
1105 BestAfter = SplitAfter;
1112 SplitBefore = nextSplitPoint(SplitBefore);
1113 if (SplitBefore < SplitAfter) {
1114 DEBUG(dbgs() << " shrink\n");
1115 // Recompute the max when necessary.
1116 if (GapWeight[SplitBefore - 1] >= MaxGap) {
1117 MaxGap = GapWeight[SplitBefore];
1118 for (unsigned i = SplitBefore + 1; i != SplitAfter; ++i)
1119 MaxGap = std::max(MaxGap, GapWeight[i]);
1126 // Try to extend the interval.
1127 if (SplitAfter >= NumGaps) {
1128 DEBUG(dbgs() << " end\n");
1132 DEBUG(dbgs() << " extend\n");
1133 for (unsigned e = nextSplitPoint(SplitAfter + 1) - 1;
1134 SplitAfter != e; ++SplitAfter)
1135 MaxGap = std::max(MaxGap, GapWeight[SplitAfter]);
1140 // Didn't find any candidates?
1141 if (BestBefore == NumGaps)
1144 DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore]
1145 << '-' << Uses[BestAfter] << ", " << BestDiff
1146 << ", " << (BestAfter - BestBefore + 1) << " instrs\n");
1148 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
1152 SlotIndex SegStart = SE->enterIntvBefore(Uses[BestBefore]);
1153 SlotIndex SegStop = SE->leaveIntvAfter(Uses[BestAfter]);
1154 SE->useIntv(SegStart, SegStop);
1157 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Local);
1163 //===----------------------------------------------------------------------===//
1164 // Live Range Splitting
1165 //===----------------------------------------------------------------------===//
1167 /// trySplit - Try to split VirtReg or one of its interferences, making it
1169 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
1170 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
1171 SmallVectorImpl<LiveInterval*>&NewVRegs) {
1172 // Local intervals are handled separately.
1173 if (LIS->intervalIsInOneMBB(VirtReg)) {
1174 NamedRegionTimer T("Local Splitting", TimerGroupName, TimePassesIsEnabled);
1175 SA->analyze(&VirtReg);
1176 return tryLocalSplit(VirtReg, Order, NewVRegs);
1179 NamedRegionTimer T("Global Splitting", TimerGroupName, TimePassesIsEnabled);
1181 // Don't iterate global splitting.
1182 // Move straight to spilling if this range was produced by a global split.
1183 LiveRangeStage Stage = getStage(VirtReg);
1184 if (Stage >= RS_Block)
1187 SA->analyze(&VirtReg);
1189 // First try to split around a region spanning multiple blocks.
1190 if (Stage < RS_Region) {
1191 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1192 if (PhysReg || !NewVRegs.empty())
1196 // Then isolate blocks with multiple uses.
1197 if (Stage < RS_Block) {
1198 SplitAnalysis::BlockPtrSet Blocks;
1199 if (SA->getMultiUseBlocks(Blocks)) {
1200 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
1202 SE->splitSingleBlocks(Blocks);
1203 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Block);
1205 MF->verify(this, "After splitting live range around basic blocks");
1209 // Don't assign any physregs.
1214 //===----------------------------------------------------------------------===//
1216 //===----------------------------------------------------------------------===//
1218 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
1219 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1220 LiveRangeStage Stage = getStage(VirtReg);
1221 if (Stage == RS_Original)
1222 LRStage[VirtReg.reg] = RS_Second;
1224 // First try assigning a free register.
1225 AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);
1226 while (unsigned PhysReg = Order.next()) {
1227 if (!checkPhysRegInterference(VirtReg, PhysReg))
1231 if (unsigned PhysReg = tryReassign(VirtReg, Order, NewVRegs))
1234 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs))
1237 assert(NewVRegs.empty() && "Cannot append to existing NewVRegs");
1239 // The first time we see a live range, don't try to split or spill.
1240 // Wait until the second time, when all smaller ranges have been allocated.
1241 // This gives a better picture of the interference to split around.
1242 if (Stage == RS_Original) {
1243 NewVRegs.push_back(&VirtReg);
1247 assert(Stage < RS_Spill && "Cannot allocate after spilling");
1249 // Try splitting VirtReg or interferences.
1250 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
1251 if (PhysReg || !NewVRegs.empty())
1254 // Finally spill VirtReg itself.
1255 NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
1256 LiveRangeEdit LRE(VirtReg, NewVRegs, this);
1257 spiller().spill(LRE);
1259 // The live virtual register requesting allocation was spilled, so tell
1260 // the caller not to allocate anything during this round.
1264 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
1265 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
1266 << "********** Function: "
1267 << ((Value*)mf.getFunction())->getName() << '\n');
1271 MF->verify(this, "Before greedy register allocator");
1273 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
1274 Indexes = &getAnalysis<SlotIndexes>();
1275 DomTree = &getAnalysis<MachineDominatorTree>();
1276 ReservedRegs = TRI->getReservedRegs(*MF);
1277 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
1278 Loops = &getAnalysis<MachineLoopInfo>();
1279 LoopRanges = &getAnalysis<MachineLoopRanges>();
1280 Bundles = &getAnalysis<EdgeBundles>();
1281 SpillPlacer = &getAnalysis<SpillPlacement>();
1283 SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops));
1284 SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree));
1286 LRStage.resize(MRI->getNumVirtRegs());
1290 LIS->addKillFlags();
1294 NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled);
1295 VRM->rewrite(Indexes);
1298 // The pass output is in VirtRegMap. Release all the transient data.