1 //===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RAGreedy function pass for register allocation in
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "AllocationOrder.h"
17 #include "InterferenceCache.h"
18 #include "LiveDebugVariables.h"
19 #include "LiveRangeEdit.h"
20 #include "RegAllocBase.h"
22 #include "SpillPlacement.h"
24 #include "VirtRegMap.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/Function.h"
28 #include "llvm/PassAnalysisSupport.h"
29 #include "llvm/CodeGen/CalcSpillWeights.h"
30 #include "llvm/CodeGen/EdgeBundles.h"
31 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
32 #include "llvm/CodeGen/LiveStackAnalysis.h"
33 #include "llvm/CodeGen/MachineDominators.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineLoopInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/CodeGen/RegAllocRegistry.h"
39 #include "llvm/Target/TargetOptions.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/raw_ostream.h"
44 #include "llvm/Support/Timer.h"
50 STATISTIC(NumGlobalSplits, "Number of split global live ranges");
51 STATISTIC(NumLocalSplits, "Number of split local live ranges");
52 STATISTIC(NumEvicted, "Number of interferences evicted");
54 static cl::opt<SplitEditor::ComplementSpillMode>
55 SplitSpillMode("split-spill-mode", cl::Hidden,
56 cl::desc("Spill mode for splitting live ranges"),
57 cl::values(clEnumValN(SplitEditor::SM_Partition, "default", "Default"),
58 clEnumValN(SplitEditor::SM_Size, "size", "Optimize for size"),
59 clEnumValN(SplitEditor::SM_Speed, "speed", "Optimize for speed"),
61 cl::init(SplitEditor::SM_Partition));
63 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
64 createGreedyRegisterAllocator);
67 class RAGreedy : public MachineFunctionPass,
69 private LiveRangeEdit::Delegate {
77 MachineDominatorTree *DomTree;
78 MachineLoopInfo *Loops;
80 SpillPlacement *SpillPlacer;
81 LiveDebugVariables *DebugVars;
84 std::auto_ptr<Spiller> SpillerInstance;
85 std::priority_queue<std::pair<unsigned, unsigned> > Queue;
88 // Live ranges pass through a number of stages as we try to allocate them.
89 // Some of the stages may also create new live ranges:
91 // - Region splitting.
92 // - Per-block splitting.
96 // Ranges produced by one of the stages skip the previous stages when they are
97 // dequeued. This improves performance because we can skip interference checks
98 // that are unlikely to give any results. It also guarantees that the live
99 // range splitting algorithm terminates, something that is otherwise hard to
101 enum LiveRangeStage {
102 /// Newly created live range that has never been queued.
105 /// Only attempt assignment and eviction. Then requeue as RS_Split.
108 /// Attempt live range splitting if assignment is impossible.
111 /// Attempt more aggressive live range splitting that is guaranteed to make
112 /// progress. This is used for split products that may not be making
116 /// Live range will be spilled. No more splitting will be attempted.
119 /// There is nothing more we can do to this live range. Abort compilation
120 /// if it can't be assigned.
124 static const char *const StageName[];
126 // RegInfo - Keep additional information about each live range.
128 LiveRangeStage Stage;
130 // Cascade - Eviction loop prevention. See canEvictInterference().
133 RegInfo() : Stage(RS_New), Cascade(0) {}
136 IndexedMap<RegInfo, VirtReg2IndexFunctor> ExtraRegInfo;
138 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
139 return ExtraRegInfo[VirtReg.reg].Stage;
142 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) {
143 ExtraRegInfo.resize(MRI->getNumVirtRegs());
144 ExtraRegInfo[VirtReg.reg].Stage = Stage;
147 template<typename Iterator>
148 void setStage(Iterator Begin, Iterator End, LiveRangeStage NewStage) {
149 ExtraRegInfo.resize(MRI->getNumVirtRegs());
150 for (;Begin != End; ++Begin) {
151 unsigned Reg = (*Begin)->reg;
152 if (ExtraRegInfo[Reg].Stage == RS_New)
153 ExtraRegInfo[Reg].Stage = NewStage;
157 /// Cost of evicting interference.
158 struct EvictionCost {
159 unsigned BrokenHints; ///< Total number of broken hints.
160 float MaxWeight; ///< Maximum spill weight evicted.
162 EvictionCost(unsigned B = 0) : BrokenHints(B), MaxWeight(0) {}
164 bool operator<(const EvictionCost &O) const {
165 if (BrokenHints != O.BrokenHints)
166 return BrokenHints < O.BrokenHints;
167 return MaxWeight < O.MaxWeight;
172 std::auto_ptr<SplitAnalysis> SA;
173 std::auto_ptr<SplitEditor> SE;
175 /// Cached per-block interference maps
176 InterferenceCache IntfCache;
178 /// All basic blocks where the current register has uses.
179 SmallVector<SpillPlacement::BlockConstraint, 8> SplitConstraints;
181 /// Global live range splitting candidate info.
182 struct GlobalSplitCandidate {
183 // Register intended for assignment, or 0.
186 // SplitKit interval index for this candidate.
189 // Interference for PhysReg.
190 InterferenceCache::Cursor Intf;
192 // Bundles where this candidate should be live.
193 BitVector LiveBundles;
194 SmallVector<unsigned, 8> ActiveBlocks;
196 void reset(InterferenceCache &Cache, unsigned Reg) {
199 Intf.setPhysReg(Cache, Reg);
201 ActiveBlocks.clear();
204 // Set B[i] = C for every live bundle where B[i] was NoCand.
205 unsigned getBundles(SmallVectorImpl<unsigned> &B, unsigned C) {
207 for (int i = LiveBundles.find_first(); i >= 0;
208 i = LiveBundles.find_next(i))
209 if (B[i] == NoCand) {
217 /// Candidate info for for each PhysReg in AllocationOrder.
218 /// This vector never shrinks, but grows to the size of the largest register
220 SmallVector<GlobalSplitCandidate, 32> GlobalCand;
222 enum { NoCand = ~0u };
224 /// Candidate map. Each edge bundle is assigned to a GlobalCand entry, or to
225 /// NoCand which indicates the stack interval.
226 SmallVector<unsigned, 32> BundleCand;
231 /// Return the pass name.
232 virtual const char* getPassName() const {
233 return "Greedy Register Allocator";
236 /// RAGreedy analysis usage.
237 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
238 virtual void releaseMemory();
239 virtual Spiller &spiller() { return *SpillerInstance; }
240 virtual void enqueue(LiveInterval *LI);
241 virtual LiveInterval *dequeue();
242 virtual unsigned selectOrSplit(LiveInterval&,
243 SmallVectorImpl<LiveInterval*>&);
245 /// Perform register allocation.
246 virtual bool runOnMachineFunction(MachineFunction &mf);
251 void LRE_WillEraseInstruction(MachineInstr*);
252 bool LRE_CanEraseVirtReg(unsigned);
253 void LRE_WillShrinkVirtReg(unsigned);
254 void LRE_DidCloneVirtReg(unsigned, unsigned);
256 float calcSpillCost();
257 bool addSplitConstraints(InterferenceCache::Cursor, float&);
258 void addThroughConstraints(InterferenceCache::Cursor, ArrayRef<unsigned>);
259 void growRegion(GlobalSplitCandidate &Cand);
260 float calcGlobalSplitCost(GlobalSplitCandidate&);
261 bool calcCompactRegion(GlobalSplitCandidate&);
262 void splitAroundRegion(LiveRangeEdit&, ArrayRef<unsigned>);
263 void calcGapWeights(unsigned, SmallVectorImpl<float>&);
264 bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool);
265 bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&);
266 void evictInterference(LiveInterval&, unsigned,
267 SmallVectorImpl<LiveInterval*>&);
269 unsigned tryAssign(LiveInterval&, AllocationOrder&,
270 SmallVectorImpl<LiveInterval*>&);
271 unsigned tryEvict(LiveInterval&, AllocationOrder&,
272 SmallVectorImpl<LiveInterval*>&, unsigned = ~0u);
273 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
274 SmallVectorImpl<LiveInterval*>&);
275 unsigned tryBlockSplit(LiveInterval&, AllocationOrder&,
276 SmallVectorImpl<LiveInterval*>&);
277 unsigned tryLocalSplit(LiveInterval&, AllocationOrder&,
278 SmallVectorImpl<LiveInterval*>&);
279 unsigned trySplit(LiveInterval&, AllocationOrder&,
280 SmallVectorImpl<LiveInterval*>&);
282 } // end anonymous namespace
284 char RAGreedy::ID = 0;
287 const char *const RAGreedy::StageName[] = {
297 // Hysteresis to use when comparing floats.
298 // This helps stabilize decisions based on float comparisons.
299 const float Hysteresis = 0.98f;
302 FunctionPass* llvm::createGreedyRegisterAllocator() {
303 return new RAGreedy();
306 RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
307 initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
308 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
309 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
310 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
311 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
312 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
313 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
314 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
315 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
316 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
317 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
318 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
319 initializeSpillPlacementPass(*PassRegistry::getPassRegistry());
322 void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
323 AU.setPreservesCFG();
324 AU.addRequired<AliasAnalysis>();
325 AU.addPreserved<AliasAnalysis>();
326 AU.addRequired<LiveIntervals>();
327 AU.addRequired<SlotIndexes>();
328 AU.addPreserved<SlotIndexes>();
329 AU.addRequired<LiveDebugVariables>();
330 AU.addPreserved<LiveDebugVariables>();
332 AU.addRequiredID(StrongPHIEliminationID);
333 AU.addRequiredTransitiveID(RegisterCoalescerPassID);
334 AU.addRequired<CalculateSpillWeights>();
335 AU.addRequired<LiveStacks>();
336 AU.addPreserved<LiveStacks>();
337 AU.addRequired<MachineDominatorTree>();
338 AU.addPreserved<MachineDominatorTree>();
339 AU.addRequired<MachineLoopInfo>();
340 AU.addPreserved<MachineLoopInfo>();
341 AU.addRequired<VirtRegMap>();
342 AU.addPreserved<VirtRegMap>();
343 AU.addRequired<EdgeBundles>();
344 AU.addRequired<SpillPlacement>();
345 MachineFunctionPass::getAnalysisUsage(AU);
349 //===----------------------------------------------------------------------===//
350 // LiveRangeEdit delegate methods
351 //===----------------------------------------------------------------------===//
353 void RAGreedy::LRE_WillEraseInstruction(MachineInstr *MI) {
354 // LRE itself will remove from SlotIndexes and parent basic block.
355 VRM->RemoveMachineInstrFromMaps(MI);
358 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
359 if (unsigned PhysReg = VRM->getPhys(VirtReg)) {
360 unassign(LIS->getInterval(VirtReg), PhysReg);
363 // Unassigned virtreg is probably in the priority queue.
364 // RegAllocBase will erase it after dequeueing.
368 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) {
369 unsigned PhysReg = VRM->getPhys(VirtReg);
373 // Register is assigned, put it back on the queue for reassignment.
374 LiveInterval &LI = LIS->getInterval(VirtReg);
375 unassign(LI, PhysReg);
379 void RAGreedy::LRE_DidCloneVirtReg(unsigned New, unsigned Old) {
380 // Cloning a register we haven't even heard about yet? Just ignore it.
381 if (!ExtraRegInfo.inBounds(Old))
384 // LRE may clone a virtual register because dead code elimination causes it to
385 // be split into connected components. The new components are much smaller
386 // than the original, so they should get a new chance at being assigned.
387 // same stage as the parent.
388 ExtraRegInfo[Old].Stage = RS_Assign;
389 ExtraRegInfo.grow(New);
390 ExtraRegInfo[New] = ExtraRegInfo[Old];
393 void RAGreedy::releaseMemory() {
394 SpillerInstance.reset(0);
395 ExtraRegInfo.clear();
397 RegAllocBase::releaseMemory();
400 void RAGreedy::enqueue(LiveInterval *LI) {
401 // Prioritize live ranges by size, assigning larger ranges first.
402 // The queue holds (size, reg) pairs.
403 const unsigned Size = LI->getSize();
404 const unsigned Reg = LI->reg;
405 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
406 "Can only enqueue virtual registers");
409 ExtraRegInfo.grow(Reg);
410 if (ExtraRegInfo[Reg].Stage == RS_New)
411 ExtraRegInfo[Reg].Stage = RS_Assign;
413 if (ExtraRegInfo[Reg].Stage == RS_Split) {
414 // Unsplit ranges that couldn't be allocated immediately are deferred until
415 // everything else has been allocated.
418 // Everything is allocated in long->short order. Long ranges that don't fit
419 // should be spilled (or split) ASAP so they don't create interference.
420 Prio = (1u << 31) + Size;
422 // Boost ranges that have a physical register hint.
423 if (TargetRegisterInfo::isPhysicalRegister(VRM->getRegAllocPref(Reg)))
427 Queue.push(std::make_pair(Prio, Reg));
430 LiveInterval *RAGreedy::dequeue() {
433 LiveInterval *LI = &LIS->getInterval(Queue.top().second);
439 //===----------------------------------------------------------------------===//
441 //===----------------------------------------------------------------------===//
443 /// tryAssign - Try to assign VirtReg to an available register.
444 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg,
445 AllocationOrder &Order,
446 SmallVectorImpl<LiveInterval*> &NewVRegs) {
449 while ((PhysReg = Order.next()))
450 if (!checkPhysRegInterference(VirtReg, PhysReg))
452 if (!PhysReg || Order.isHint(PhysReg))
455 // PhysReg is available, but there may be a better choice.
457 // If we missed a simple hint, try to cheaply evict interference from the
458 // preferred register.
459 if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg))
460 if (Order.isHint(Hint)) {
461 DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n');
462 EvictionCost MaxCost(1);
463 if (canEvictInterference(VirtReg, Hint, true, MaxCost)) {
464 evictInterference(VirtReg, Hint, NewVRegs);
469 // Try to evict interference from a cheaper alternative.
470 unsigned Cost = TRI->getCostPerUse(PhysReg);
472 // Most registers have 0 additional cost.
476 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost
478 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
479 return CheapReg ? CheapReg : PhysReg;
483 //===----------------------------------------------------------------------===//
484 // Interference eviction
485 //===----------------------------------------------------------------------===//
487 /// shouldEvict - determine if A should evict the assigned live range B. The
488 /// eviction policy defined by this function together with the allocation order
489 /// defined by enqueue() decides which registers ultimately end up being split
492 /// Cascade numbers are used to prevent infinite loops if this function is a
495 /// @param A The live range to be assigned.
496 /// @param IsHint True when A is about to be assigned to its preferred
498 /// @param B The live range to be evicted.
499 /// @param BreaksHint True when B is already assigned to its preferred register.
500 bool RAGreedy::shouldEvict(LiveInterval &A, bool IsHint,
501 LiveInterval &B, bool BreaksHint) {
502 bool CanSplit = getStage(B) < RS_Spill;
504 // Be fairly aggressive about following hints as long as the evictee can be
506 if (CanSplit && IsHint && !BreaksHint)
509 return A.weight > B.weight;
512 /// canEvictInterference - Return true if all interferences between VirtReg and
513 /// PhysReg can be evicted. When OnlyCheap is set, don't do anything
515 /// @param VirtReg Live range that is about to be assigned.
516 /// @param PhysReg Desired register for assignment.
517 /// @prarm IsHint True when PhysReg is VirtReg's preferred register.
518 /// @param MaxCost Only look for cheaper candidates and update with new cost
519 /// when returning true.
520 /// @returns True when interference can be evicted cheaper than MaxCost.
521 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
522 bool IsHint, EvictionCost &MaxCost) {
523 // Find VirtReg's cascade number. This will be unassigned if VirtReg was never
524 // involved in an eviction before. If a cascade number was assigned, deny
525 // evicting anything with the same or a newer cascade number. This prevents
526 // infinite eviction loops.
528 // This works out so a register without a cascade number is allowed to evict
529 // anything, and it can be evicted by anything.
530 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
532 Cascade = NextCascade;
535 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
536 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
537 // If there is 10 or more interferences, chances are one is heavier.
538 if (Q.collectInterferingVRegs(10) >= 10)
541 // Check if any interfering live range is heavier than MaxWeight.
542 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
543 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
544 if (TargetRegisterInfo::isPhysicalRegister(Intf->reg))
546 // Never evict spill products. They cannot split or spill.
547 if (getStage(*Intf) == RS_Done)
549 // Once a live range becomes small enough, it is urgent that we find a
550 // register for it. This is indicated by an infinite spill weight. These
551 // urgent live ranges get to evict almost anything.
552 bool Urgent = !VirtReg.isSpillable() && Intf->isSpillable();
553 // Only evict older cascades or live ranges without a cascade.
554 unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;
555 if (Cascade <= IntfCascade) {
558 // We permit breaking cascades for urgent evictions. It should be the
559 // last resort, though, so make it really expensive.
560 Cost.BrokenHints += 10;
562 // Would this break a satisfied hint?
563 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg);
564 // Update eviction cost.
565 Cost.BrokenHints += BreaksHint;
566 Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight);
567 // Abort if this would be too expensive.
568 if (!(Cost < MaxCost))
570 // Finally, apply the eviction policy for non-urgent evictions.
571 if (!Urgent && !shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
579 /// evictInterference - Evict any interferring registers that prevent VirtReg
580 /// from being assigned to Physreg. This assumes that canEvictInterference
582 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg,
583 SmallVectorImpl<LiveInterval*> &NewVRegs) {
584 // Make sure that VirtReg has a cascade number, and assign that cascade
585 // number to every evicted register. These live ranges than then only be
586 // evicted by a newer cascade, preventing infinite loops.
587 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
589 Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;
591 DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI)
592 << " interference: Cascade " << Cascade << '\n');
593 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
594 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
595 assert(Q.seenAllInterferences() && "Didn't check all interfererences.");
596 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
597 LiveInterval *Intf = Q.interferingVRegs()[i];
598 unassign(*Intf, VRM->getPhys(Intf->reg));
599 assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||
600 VirtReg.isSpillable() < Intf->isSpillable()) &&
601 "Cannot decrease cascade number, illegal eviction");
602 ExtraRegInfo[Intf->reg].Cascade = Cascade;
604 NewVRegs.push_back(Intf);
609 /// tryEvict - Try to evict all interferences for a physreg.
610 /// @param VirtReg Currently unassigned virtual register.
611 /// @param Order Physregs to try.
612 /// @return Physreg to assign VirtReg, or 0.
613 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
614 AllocationOrder &Order,
615 SmallVectorImpl<LiveInterval*> &NewVRegs,
616 unsigned CostPerUseLimit) {
617 NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled);
619 // Keep track of the cheapest interference seen so far.
620 EvictionCost BestCost(~0u);
621 unsigned BestPhys = 0;
623 // When we are just looking for a reduced cost per use, don't break any
624 // hints, and only evict smaller spill weights.
625 if (CostPerUseLimit < ~0u) {
626 BestCost.BrokenHints = 0;
627 BestCost.MaxWeight = VirtReg.weight;
631 while (unsigned PhysReg = Order.next()) {
632 if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit)
634 // The first use of a callee-saved register in a function has cost 1.
635 // Don't start using a CSR when the CostPerUseLimit is low.
636 if (CostPerUseLimit == 1)
637 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
638 if (!MRI->isPhysRegUsed(CSR)) {
639 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR "
640 << PrintReg(CSR, TRI) << '\n');
644 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost))
650 // Stop if the hint can be used.
651 if (Order.isHint(PhysReg))
658 evictInterference(VirtReg, BestPhys, NewVRegs);
663 //===----------------------------------------------------------------------===//
665 //===----------------------------------------------------------------------===//
667 /// addSplitConstraints - Fill out the SplitConstraints vector based on the
668 /// interference pattern in Physreg and its aliases. Add the constraints to
669 /// SpillPlacement and return the static cost of this split in Cost, assuming
670 /// that all preferences in SplitConstraints are met.
671 /// Return false if there are no bundles with positive bias.
672 bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
674 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
676 // Reset interference dependent info.
677 SplitConstraints.resize(UseBlocks.size());
678 float StaticCost = 0;
679 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
680 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
681 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
683 BC.Number = BI.MBB->getNumber();
684 Intf.moveToBlock(BC.Number);
685 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
686 BC.Exit = BI.LiveOut ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
687 BC.ChangesValue = BI.FirstDef;
689 if (!Intf.hasInterference())
692 // Number of spill code instructions to insert.
695 // Interference for the live-in value.
697 if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number))
698 BC.Entry = SpillPlacement::MustSpill, ++Ins;
699 else if (Intf.first() < BI.FirstInstr)
700 BC.Entry = SpillPlacement::PrefSpill, ++Ins;
701 else if (Intf.first() < BI.LastInstr)
705 // Interference for the live-out value.
707 if (Intf.last() >= SA->getLastSplitPoint(BC.Number))
708 BC.Exit = SpillPlacement::MustSpill, ++Ins;
709 else if (Intf.last() > BI.LastInstr)
710 BC.Exit = SpillPlacement::PrefSpill, ++Ins;
711 else if (Intf.last() > BI.FirstInstr)
715 // Accumulate the total frequency of inserted spill code.
717 StaticCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
721 // Add constraints for use-blocks. Note that these are the only constraints
722 // that may add a positive bias, it is downhill from here.
723 SpillPlacer->addConstraints(SplitConstraints);
724 return SpillPlacer->scanActiveBundles();
728 /// addThroughConstraints - Add constraints and links to SpillPlacer from the
729 /// live-through blocks in Blocks.
730 void RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
731 ArrayRef<unsigned> Blocks) {
732 const unsigned GroupSize = 8;
733 SpillPlacement::BlockConstraint BCS[GroupSize];
734 unsigned TBS[GroupSize];
735 unsigned B = 0, T = 0;
737 for (unsigned i = 0; i != Blocks.size(); ++i) {
738 unsigned Number = Blocks[i];
739 Intf.moveToBlock(Number);
741 if (!Intf.hasInterference()) {
742 assert(T < GroupSize && "Array overflow");
744 if (++T == GroupSize) {
745 SpillPlacer->addLinks(makeArrayRef(TBS, T));
751 assert(B < GroupSize && "Array overflow");
752 BCS[B].Number = Number;
754 // Interference for the live-in value.
755 if (Intf.first() <= Indexes->getMBBStartIdx(Number))
756 BCS[B].Entry = SpillPlacement::MustSpill;
758 BCS[B].Entry = SpillPlacement::PrefSpill;
760 // Interference for the live-out value.
761 if (Intf.last() >= SA->getLastSplitPoint(Number))
762 BCS[B].Exit = SpillPlacement::MustSpill;
764 BCS[B].Exit = SpillPlacement::PrefSpill;
766 if (++B == GroupSize) {
767 ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B);
768 SpillPlacer->addConstraints(Array);
773 ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B);
774 SpillPlacer->addConstraints(Array);
775 SpillPlacer->addLinks(makeArrayRef(TBS, T));
778 void RAGreedy::growRegion(GlobalSplitCandidate &Cand) {
779 // Keep track of through blocks that have not been added to SpillPlacer.
780 BitVector Todo = SA->getThroughBlocks();
781 SmallVectorImpl<unsigned> &ActiveBlocks = Cand.ActiveBlocks;
782 unsigned AddedTo = 0;
784 unsigned Visited = 0;
788 ArrayRef<unsigned> NewBundles = SpillPlacer->getRecentPositive();
789 // Find new through blocks in the periphery of PrefRegBundles.
790 for (int i = 0, e = NewBundles.size(); i != e; ++i) {
791 unsigned Bundle = NewBundles[i];
792 // Look at all blocks connected to Bundle in the full graph.
793 ArrayRef<unsigned> Blocks = Bundles->getBlocks(Bundle);
794 for (ArrayRef<unsigned>::iterator I = Blocks.begin(), E = Blocks.end();
797 if (!Todo.test(Block))
800 // This is a new through block. Add it to SpillPlacer later.
801 ActiveBlocks.push_back(Block);
807 // Any new blocks to add?
808 if (ActiveBlocks.size() == AddedTo)
811 // Compute through constraints from the interference, or assume that all
812 // through blocks prefer spilling when forming compact regions.
813 ArrayRef<unsigned> NewBlocks = makeArrayRef(ActiveBlocks).slice(AddedTo);
815 addThroughConstraints(Cand.Intf, NewBlocks);
817 // Provide a strong negative bias on through blocks to prevent unwanted
818 // liveness on loop backedges.
819 SpillPlacer->addPrefSpill(NewBlocks, /* Strong= */ true);
820 AddedTo = ActiveBlocks.size();
822 // Perhaps iterating can enable more bundles?
823 SpillPlacer->iterate();
825 DEBUG(dbgs() << ", v=" << Visited);
828 /// calcCompactRegion - Compute the set of edge bundles that should be live
829 /// when splitting the current live range into compact regions. Compact
830 /// regions can be computed without looking at interference. They are the
831 /// regions formed by removing all the live-through blocks from the live range.
833 /// Returns false if the current live range is already compact, or if the
834 /// compact regions would form single block regions anyway.
835 bool RAGreedy::calcCompactRegion(GlobalSplitCandidate &Cand) {
836 // Without any through blocks, the live range is already compact.
837 if (!SA->getNumThroughBlocks())
840 // Compact regions don't correspond to any physreg.
841 Cand.reset(IntfCache, 0);
843 DEBUG(dbgs() << "Compact region bundles");
845 // Use the spill placer to determine the live bundles. GrowRegion pretends
846 // that all the through blocks have interference when PhysReg is unset.
847 SpillPlacer->prepare(Cand.LiveBundles);
849 // The static split cost will be zero since Cand.Intf reports no interference.
851 if (!addSplitConstraints(Cand.Intf, Cost)) {
852 DEBUG(dbgs() << ", none.\n");
857 SpillPlacer->finish();
859 if (!Cand.LiveBundles.any()) {
860 DEBUG(dbgs() << ", none.\n");
865 for (int i = Cand.LiveBundles.find_first(); i>=0;
866 i = Cand.LiveBundles.find_next(i))
867 dbgs() << " EB#" << i;
873 /// calcSpillCost - Compute how expensive it would be to split the live range in
874 /// SA around all use blocks instead of forming bundle regions.
875 float RAGreedy::calcSpillCost() {
877 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
878 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
879 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
880 unsigned Number = BI.MBB->getNumber();
881 // We normally only need one spill instruction - a load or a store.
882 Cost += SpillPlacer->getBlockFrequency(Number);
884 // Unless the value is redefined in the block.
885 if (BI.LiveIn && BI.LiveOut && BI.FirstDef)
886 Cost += SpillPlacer->getBlockFrequency(Number);
891 /// calcGlobalSplitCost - Return the global split cost of following the split
892 /// pattern in LiveBundles. This cost should be added to the local cost of the
893 /// interference pattern in SplitConstraints.
895 float RAGreedy::calcGlobalSplitCost(GlobalSplitCandidate &Cand) {
896 float GlobalCost = 0;
897 const BitVector &LiveBundles = Cand.LiveBundles;
898 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
899 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
900 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
901 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
902 bool RegIn = LiveBundles[Bundles->getBundle(BC.Number, 0)];
903 bool RegOut = LiveBundles[Bundles->getBundle(BC.Number, 1)];
907 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg);
909 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg);
911 GlobalCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
914 for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) {
915 unsigned Number = Cand.ActiveBlocks[i];
916 bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)];
917 bool RegOut = LiveBundles[Bundles->getBundle(Number, 1)];
918 if (!RegIn && !RegOut)
920 if (RegIn && RegOut) {
921 // We need double spill code if this block has interference.
922 Cand.Intf.moveToBlock(Number);
923 if (Cand.Intf.hasInterference())
924 GlobalCost += 2*SpillPlacer->getBlockFrequency(Number);
927 // live-in / stack-out or stack-in live-out.
928 GlobalCost += SpillPlacer->getBlockFrequency(Number);
933 /// splitAroundRegion - Split the current live range around the regions
934 /// determined by BundleCand and GlobalCand.
936 /// Before calling this function, GlobalCand and BundleCand must be initialized
937 /// so each bundle is assigned to a valid candidate, or NoCand for the
938 /// stack-bound bundles. The shared SA/SE SplitAnalysis and SplitEditor
939 /// objects must be initialized for the current live range, and intervals
940 /// created for the used candidates.
942 /// @param LREdit The LiveRangeEdit object handling the current split.
943 /// @param UsedCands List of used GlobalCand entries. Every BundleCand value
944 /// must appear in this list.
945 void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit,
946 ArrayRef<unsigned> UsedCands) {
947 // These are the intervals created for new global ranges. We may create more
948 // intervals for local ranges.
949 const unsigned NumGlobalIntvs = LREdit.size();
950 DEBUG(dbgs() << "splitAroundRegion with " << NumGlobalIntvs << " globals.\n");
951 assert(NumGlobalIntvs && "No global intervals configured");
953 // Isolate even single instructions when dealing with a proper sub-class.
954 // That guarantees register class inflation for the stack interval because it
956 unsigned Reg = SA->getParent().reg;
957 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
959 // First handle all the blocks with uses.
960 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
961 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
962 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
963 unsigned Number = BI.MBB->getNumber();
964 unsigned IntvIn = 0, IntvOut = 0;
965 SlotIndex IntfIn, IntfOut;
967 unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)];
968 if (CandIn != NoCand) {
969 GlobalSplitCandidate &Cand = GlobalCand[CandIn];
970 IntvIn = Cand.IntvIdx;
971 Cand.Intf.moveToBlock(Number);
972 IntfIn = Cand.Intf.first();
976 unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)];
977 if (CandOut != NoCand) {
978 GlobalSplitCandidate &Cand = GlobalCand[CandOut];
979 IntvOut = Cand.IntvIdx;
980 Cand.Intf.moveToBlock(Number);
981 IntfOut = Cand.Intf.last();
985 // Create separate intervals for isolated blocks with multiple uses.
986 if (!IntvIn && !IntvOut) {
987 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n");
988 if (SA->shouldSplitSingleBlock(BI, SingleInstrs))
989 SE->splitSingleBlock(BI);
993 if (IntvIn && IntvOut)
994 SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut);
996 SE->splitRegInBlock(BI, IntvIn, IntfIn);
998 SE->splitRegOutBlock(BI, IntvOut, IntfOut);
1001 // Handle live-through blocks. The relevant live-through blocks are stored in
1002 // the ActiveBlocks list with each candidate. We need to filter out
1004 BitVector Todo = SA->getThroughBlocks();
1005 for (unsigned c = 0; c != UsedCands.size(); ++c) {
1006 ArrayRef<unsigned> Blocks = GlobalCand[UsedCands[c]].ActiveBlocks;
1007 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
1008 unsigned Number = Blocks[i];
1009 if (!Todo.test(Number))
1013 unsigned IntvIn = 0, IntvOut = 0;
1014 SlotIndex IntfIn, IntfOut;
1016 unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)];
1017 if (CandIn != NoCand) {
1018 GlobalSplitCandidate &Cand = GlobalCand[CandIn];
1019 IntvIn = Cand.IntvIdx;
1020 Cand.Intf.moveToBlock(Number);
1021 IntfIn = Cand.Intf.first();
1024 unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)];
1025 if (CandOut != NoCand) {
1026 GlobalSplitCandidate &Cand = GlobalCand[CandOut];
1027 IntvOut = Cand.IntvIdx;
1028 Cand.Intf.moveToBlock(Number);
1029 IntfOut = Cand.Intf.last();
1031 if (!IntvIn && !IntvOut)
1033 SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut);
1039 SmallVector<unsigned, 8> IntvMap;
1040 SE->finish(&IntvMap);
1041 DebugVars->splitRegister(Reg, LREdit.regs());
1043 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1044 unsigned OrigBlocks = SA->getNumLiveBlocks();
1046 // Sort out the new intervals created by splitting. We get four kinds:
1047 // - Remainder intervals should not be split again.
1048 // - Candidate intervals can be assigned to Cand.PhysReg.
1049 // - Block-local splits are candidates for local splitting.
1050 // - DCE leftovers should go back on the queue.
1051 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) {
1052 LiveInterval &Reg = *LREdit.get(i);
1054 // Ignore old intervals from DCE.
1055 if (getStage(Reg) != RS_New)
1058 // Remainder interval. Don't try splitting again, spill if it doesn't
1060 if (IntvMap[i] == 0) {
1061 setStage(Reg, RS_Spill);
1065 // Global intervals. Allow repeated splitting as long as the number of live
1066 // blocks is strictly decreasing.
1067 if (IntvMap[i] < NumGlobalIntvs) {
1068 if (SA->countLiveBlocks(&Reg) >= OrigBlocks) {
1069 DEBUG(dbgs() << "Main interval covers the same " << OrigBlocks
1070 << " blocks as original.\n");
1071 // Don't allow repeated splitting as a safe guard against looping.
1072 setStage(Reg, RS_Split2);
1077 // Other intervals are treated as new. This includes local intervals created
1078 // for blocks with multiple uses, and anything created by DCE.
1082 MF->verify(this, "After splitting live range around region");
1085 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1086 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1087 unsigned NumCands = 0;
1088 unsigned BestCand = NoCand;
1090 SmallVector<unsigned, 8> UsedCands;
1092 // Check if we can split this live range around a compact region.
1093 bool HasCompact = calcCompactRegion(GlobalCand.front());
1095 // Yes, keep GlobalCand[0] as the compact region candidate.
1097 BestCost = HUGE_VALF;
1099 // No benefit from the compact region, our fallback will be per-block
1100 // splitting. Make sure we find a solution that is cheaper than spilling.
1101 BestCost = Hysteresis * calcSpillCost();
1102 DEBUG(dbgs() << "Cost of isolating all blocks = " << BestCost << '\n');
1106 while (unsigned PhysReg = Order.next()) {
1107 // Discard bad candidates before we run out of interference cache cursors.
1108 // This will only affect register classes with a lot of registers (>32).
1109 if (NumCands == IntfCache.getMaxCursors()) {
1110 unsigned WorstCount = ~0u;
1112 for (unsigned i = 0; i != NumCands; ++i) {
1113 if (i == BestCand || !GlobalCand[i].PhysReg)
1115 unsigned Count = GlobalCand[i].LiveBundles.count();
1116 if (Count < WorstCount)
1117 Worst = i, WorstCount = Count;
1120 GlobalCand[Worst] = GlobalCand[NumCands];
1123 if (GlobalCand.size() <= NumCands)
1124 GlobalCand.resize(NumCands+1);
1125 GlobalSplitCandidate &Cand = GlobalCand[NumCands];
1126 Cand.reset(IntfCache, PhysReg);
1128 SpillPlacer->prepare(Cand.LiveBundles);
1130 if (!addSplitConstraints(Cand.Intf, Cost)) {
1131 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n");
1134 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = " << Cost);
1135 if (Cost >= BestCost) {
1137 if (BestCand == NoCand)
1138 dbgs() << " worse than no bundles\n";
1140 dbgs() << " worse than "
1141 << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
1147 SpillPlacer->finish();
1149 // No live bundles, defer to splitSingleBlocks().
1150 if (!Cand.LiveBundles.any()) {
1151 DEBUG(dbgs() << " no bundles.\n");
1155 Cost += calcGlobalSplitCost(Cand);
1157 dbgs() << ", total = " << Cost << " with bundles";
1158 for (int i = Cand.LiveBundles.find_first(); i>=0;
1159 i = Cand.LiveBundles.find_next(i))
1160 dbgs() << " EB#" << i;
1163 if (Cost < BestCost) {
1164 BestCand = NumCands;
1165 BestCost = Hysteresis * Cost; // Prevent rounding effects.
1170 // No solutions found, fall back to single block splitting.
1171 if (!HasCompact && BestCand == NoCand)
1174 // Prepare split editor.
1175 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
1176 SE->reset(LREdit, SplitSpillMode);
1178 // Assign all edge bundles to the preferred candidate, or NoCand.
1179 BundleCand.assign(Bundles->getNumBundles(), NoCand);
1181 // Assign bundles for the best candidate region.
1182 if (BestCand != NoCand) {
1183 GlobalSplitCandidate &Cand = GlobalCand[BestCand];
1184 if (unsigned B = Cand.getBundles(BundleCand, BestCand)) {
1185 UsedCands.push_back(BestCand);
1186 Cand.IntvIdx = SE->openIntv();
1187 DEBUG(dbgs() << "Split for " << PrintReg(Cand.PhysReg, TRI) << " in "
1188 << B << " bundles, intv " << Cand.IntvIdx << ".\n");
1193 // Assign bundles for the compact region.
1195 GlobalSplitCandidate &Cand = GlobalCand.front();
1196 assert(!Cand.PhysReg && "Compact region has no physreg");
1197 if (unsigned B = Cand.getBundles(BundleCand, 0)) {
1198 UsedCands.push_back(0);
1199 Cand.IntvIdx = SE->openIntv();
1200 DEBUG(dbgs() << "Split for compact region in " << B << " bundles, intv "
1201 << Cand.IntvIdx << ".\n");
1206 splitAroundRegion(LREdit, UsedCands);
1211 //===----------------------------------------------------------------------===//
1212 // Per-Block Splitting
1213 //===----------------------------------------------------------------------===//
1215 /// tryBlockSplit - Split a global live range around every block with uses. This
1216 /// creates a lot of local live ranges, that will be split by tryLocalSplit if
1217 /// they don't allocate.
1218 unsigned RAGreedy::tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1219 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1220 assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed");
1221 unsigned Reg = VirtReg.reg;
1222 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1223 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
1224 SE->reset(LREdit, SplitSpillMode);
1225 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1226 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1227 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1228 if (SA->shouldSplitSingleBlock(BI, SingleInstrs))
1229 SE->splitSingleBlock(BI);
1231 // No blocks were split.
1235 // We did split for some blocks.
1236 SmallVector<unsigned, 8> IntvMap;
1237 SE->finish(&IntvMap);
1239 // Tell LiveDebugVariables about the new ranges.
1240 DebugVars->splitRegister(Reg, LREdit.regs());
1242 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1244 // Sort out the new intervals created by splitting. The remainder interval
1245 // goes straight to spilling, the new local ranges get to stay RS_New.
1246 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) {
1247 LiveInterval &LI = *LREdit.get(i);
1248 if (getStage(LI) == RS_New && IntvMap[i] == 0)
1249 setStage(LI, RS_Spill);
1253 MF->verify(this, "After splitting live range around basic blocks");
1257 //===----------------------------------------------------------------------===//
1259 //===----------------------------------------------------------------------===//
1262 /// calcGapWeights - Compute the maximum spill weight that needs to be evicted
1263 /// in order to use PhysReg between two entries in SA->UseSlots.
1265 /// GapWeight[i] represents the gap between UseSlots[i] and UseSlots[i+1].
1267 void RAGreedy::calcGapWeights(unsigned PhysReg,
1268 SmallVectorImpl<float> &GapWeight) {
1269 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
1270 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
1271 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
1272 const unsigned NumGaps = Uses.size()-1;
1274 // Start and end points for the interference check.
1275 SlotIndex StartIdx =
1276 BI.LiveIn ? BI.FirstInstr.getBaseIndex() : BI.FirstInstr;
1278 BI.LiveOut ? BI.LastInstr.getBoundaryIndex() : BI.LastInstr;
1280 GapWeight.assign(NumGaps, 0.0f);
1282 // Add interference from each overlapping register.
1283 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
1284 if (!query(const_cast<LiveInterval&>(SA->getParent()), *AI)
1285 .checkInterference())
1288 // We know that VirtReg is a continuous interval from FirstInstr to
1289 // LastInstr, so we don't need InterferenceQuery.
1291 // Interference that overlaps an instruction is counted in both gaps
1292 // surrounding the instruction. The exception is interference before
1293 // StartIdx and after StopIdx.
1295 LiveIntervalUnion::SegmentIter IntI = PhysReg2LiveUnion[*AI].find(StartIdx);
1296 for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) {
1297 // Skip the gaps before IntI.
1298 while (Uses[Gap+1].getBoundaryIndex() < IntI.start())
1299 if (++Gap == NumGaps)
1304 // Update the gaps covered by IntI.
1305 const float weight = IntI.value()->weight;
1306 for (; Gap != NumGaps; ++Gap) {
1307 GapWeight[Gap] = std::max(GapWeight[Gap], weight);
1308 if (Uses[Gap+1].getBaseIndex() >= IntI.stop())
1317 /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
1320 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1321 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1322 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
1323 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
1325 // Note that it is possible to have an interval that is live-in or live-out
1326 // while only covering a single block - A phi-def can use undef values from
1327 // predecessors, and the block could be a single-block loop.
1328 // We don't bother doing anything clever about such a case, we simply assume
1329 // that the interval is continuous from FirstInstr to LastInstr. We should
1330 // make sure that we don't do anything illegal to such an interval, though.
1332 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
1333 if (Uses.size() <= 2)
1335 const unsigned NumGaps = Uses.size()-1;
1338 dbgs() << "tryLocalSplit: ";
1339 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
1340 dbgs() << ' ' << SA->UseSlots[i];
1344 // Since we allow local split results to be split again, there is a risk of
1345 // creating infinite loops. It is tempting to require that the new live
1346 // ranges have less instructions than the original. That would guarantee
1347 // convergence, but it is too strict. A live range with 3 instructions can be
1348 // split 2+3 (including the COPY), and we want to allow that.
1350 // Instead we use these rules:
1352 // 1. Allow any split for ranges with getStage() < RS_Split2. (Except for the
1353 // noop split, of course).
1354 // 2. Require progress be made for ranges with getStage() == RS_Split2. All
1355 // the new ranges must have fewer instructions than before the split.
1356 // 3. New ranges with the same number of instructions are marked RS_Split2,
1357 // smaller ranges are marked RS_New.
1359 // These rules allow a 3 -> 2+3 split once, which we need. They also prevent
1360 // excessive splitting and infinite loops.
1362 bool ProgressRequired = getStage(VirtReg) >= RS_Split2;
1364 // Best split candidate.
1365 unsigned BestBefore = NumGaps;
1366 unsigned BestAfter = 0;
1369 const float blockFreq = SpillPlacer->getBlockFrequency(BI.MBB->getNumber());
1370 SmallVector<float, 8> GapWeight;
1373 while (unsigned PhysReg = Order.next()) {
1374 // Keep track of the largest spill weight that would need to be evicted in
1375 // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1].
1376 calcGapWeights(PhysReg, GapWeight);
1378 // Try to find the best sequence of gaps to close.
1379 // The new spill weight must be larger than any gap interference.
1381 // We will split before Uses[SplitBefore] and after Uses[SplitAfter].
1382 unsigned SplitBefore = 0, SplitAfter = 1;
1384 // MaxGap should always be max(GapWeight[SplitBefore..SplitAfter-1]).
1385 // It is the spill weight that needs to be evicted.
1386 float MaxGap = GapWeight[0];
1389 // Live before/after split?
1390 const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
1391 const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut;
1393 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' '
1394 << Uses[SplitBefore] << '-' << Uses[SplitAfter]
1395 << " i=" << MaxGap);
1397 // Stop before the interval gets so big we wouldn't be making progress.
1398 if (!LiveBefore && !LiveAfter) {
1399 DEBUG(dbgs() << " all\n");
1402 // Should the interval be extended or shrunk?
1405 // How many gaps would the new range have?
1406 unsigned NewGaps = LiveBefore + SplitAfter - SplitBefore + LiveAfter;
1408 // Legally, without causing looping?
1409 bool Legal = !ProgressRequired || NewGaps < NumGaps;
1411 if (Legal && MaxGap < HUGE_VALF) {
1412 // Estimate the new spill weight. Each instruction reads or writes the
1413 // register. Conservatively assume there are no read-modify-write
1416 // Try to guess the size of the new interval.
1417 const float EstWeight = normalizeSpillWeight(blockFreq * (NewGaps + 1),
1418 Uses[SplitBefore].distance(Uses[SplitAfter]) +
1419 (LiveBefore + LiveAfter)*SlotIndex::InstrDist);
1420 // Would this split be possible to allocate?
1421 // Never allocate all gaps, we wouldn't be making progress.
1422 DEBUG(dbgs() << " w=" << EstWeight);
1423 if (EstWeight * Hysteresis >= MaxGap) {
1425 float Diff = EstWeight - MaxGap;
1426 if (Diff > BestDiff) {
1427 DEBUG(dbgs() << " (best)");
1428 BestDiff = Hysteresis * Diff;
1429 BestBefore = SplitBefore;
1430 BestAfter = SplitAfter;
1437 if (++SplitBefore < SplitAfter) {
1438 DEBUG(dbgs() << " shrink\n");
1439 // Recompute the max when necessary.
1440 if (GapWeight[SplitBefore - 1] >= MaxGap) {
1441 MaxGap = GapWeight[SplitBefore];
1442 for (unsigned i = SplitBefore + 1; i != SplitAfter; ++i)
1443 MaxGap = std::max(MaxGap, GapWeight[i]);
1450 // Try to extend the interval.
1451 if (SplitAfter >= NumGaps) {
1452 DEBUG(dbgs() << " end\n");
1456 DEBUG(dbgs() << " extend\n");
1457 MaxGap = std::max(MaxGap, GapWeight[SplitAfter++]);
1461 // Didn't find any candidates?
1462 if (BestBefore == NumGaps)
1465 DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore]
1466 << '-' << Uses[BestAfter] << ", " << BestDiff
1467 << ", " << (BestAfter - BestBefore + 1) << " instrs\n");
1469 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
1473 SlotIndex SegStart = SE->enterIntvBefore(Uses[BestBefore]);
1474 SlotIndex SegStop = SE->leaveIntvAfter(Uses[BestAfter]);
1475 SE->useIntv(SegStart, SegStop);
1476 SmallVector<unsigned, 8> IntvMap;
1477 SE->finish(&IntvMap);
1478 DebugVars->splitRegister(VirtReg.reg, LREdit.regs());
1480 // If the new range has the same number of instructions as before, mark it as
1481 // RS_Split2 so the next split will be forced to make progress. Otherwise,
1482 // leave the new intervals as RS_New so they can compete.
1483 bool LiveBefore = BestBefore != 0 || BI.LiveIn;
1484 bool LiveAfter = BestAfter != NumGaps || BI.LiveOut;
1485 unsigned NewGaps = LiveBefore + BestAfter - BestBefore + LiveAfter;
1486 if (NewGaps >= NumGaps) {
1487 DEBUG(dbgs() << "Tagging non-progress ranges: ");
1488 assert(!ProgressRequired && "Didn't make progress when it was required.");
1489 for (unsigned i = 0, e = IntvMap.size(); i != e; ++i)
1490 if (IntvMap[i] == 1) {
1491 setStage(*LREdit.get(i), RS_Split2);
1492 DEBUG(dbgs() << PrintReg(LREdit.get(i)->reg));
1494 DEBUG(dbgs() << '\n');
1501 //===----------------------------------------------------------------------===//
1502 // Live Range Splitting
1503 //===----------------------------------------------------------------------===//
1505 /// trySplit - Try to split VirtReg or one of its interferences, making it
1507 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
1508 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
1509 SmallVectorImpl<LiveInterval*>&NewVRegs) {
1510 // Ranges must be Split2 or less.
1511 if (getStage(VirtReg) >= RS_Spill)
1514 // Local intervals are handled separately.
1515 if (LIS->intervalIsInOneMBB(VirtReg)) {
1516 NamedRegionTimer T("Local Splitting", TimerGroupName, TimePassesIsEnabled);
1517 SA->analyze(&VirtReg);
1518 return tryLocalSplit(VirtReg, Order, NewVRegs);
1521 NamedRegionTimer T("Global Splitting", TimerGroupName, TimePassesIsEnabled);
1523 SA->analyze(&VirtReg);
1525 // FIXME: SplitAnalysis may repair broken live ranges coming from the
1526 // coalescer. That may cause the range to become allocatable which means that
1527 // tryRegionSplit won't be making progress. This check should be replaced with
1528 // an assertion when the coalescer is fixed.
1529 if (SA->didRepairRange()) {
1530 // VirtReg has changed, so all cached queries are invalid.
1531 invalidateVirtRegs();
1532 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
1536 // First try to split around a region spanning multiple blocks. RS_Split2
1537 // ranges already made dubious progress with region splitting, so they go
1538 // straight to single block splitting.
1539 if (getStage(VirtReg) < RS_Split2) {
1540 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1541 if (PhysReg || !NewVRegs.empty())
1545 // Then isolate blocks.
1546 return tryBlockSplit(VirtReg, Order, NewVRegs);
1550 //===----------------------------------------------------------------------===//
1552 //===----------------------------------------------------------------------===//
1554 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
1555 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1556 // First try assigning a free register.
1557 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
1558 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
1561 LiveRangeStage Stage = getStage(VirtReg);
1562 DEBUG(dbgs() << StageName[Stage]
1563 << " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n');
1565 // Try to evict a less worthy live range, but only for ranges from the primary
1566 // queue. The RS_Split ranges already failed to do this, and they should not
1567 // get a second chance until they have been split.
1568 if (Stage != RS_Split)
1569 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs))
1572 assert(NewVRegs.empty() && "Cannot append to existing NewVRegs");
1574 // The first time we see a live range, don't try to split or spill.
1575 // Wait until the second time, when all smaller ranges have been allocated.
1576 // This gives a better picture of the interference to split around.
1577 if (Stage < RS_Split) {
1578 setStage(VirtReg, RS_Split);
1579 DEBUG(dbgs() << "wait for second round\n");
1580 NewVRegs.push_back(&VirtReg);
1584 // If we couldn't allocate a register from spilling, there is probably some
1585 // invalid inline assembly. The base class wil report it.
1586 if (Stage >= RS_Done || !VirtReg.isSpillable())
1589 // Try splitting VirtReg or interferences.
1590 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
1591 if (PhysReg || !NewVRegs.empty())
1594 // Finally spill VirtReg itself.
1595 NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
1596 LiveRangeEdit LRE(VirtReg, NewVRegs, this);
1597 spiller().spill(LRE);
1598 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Done);
1601 MF->verify(this, "After spilling");
1603 // The live virtual register requesting allocation was spilled, so tell
1604 // the caller not to allocate anything during this round.
1608 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
1609 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
1610 << "********** Function: "
1611 << ((Value*)mf.getFunction())->getName() << '\n');
1615 MF->verify(this, "Before greedy register allocator");
1617 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
1618 Indexes = &getAnalysis<SlotIndexes>();
1619 DomTree = &getAnalysis<MachineDominatorTree>();
1620 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
1621 Loops = &getAnalysis<MachineLoopInfo>();
1622 Bundles = &getAnalysis<EdgeBundles>();
1623 SpillPlacer = &getAnalysis<SpillPlacement>();
1624 DebugVars = &getAnalysis<LiveDebugVariables>();
1626 SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops));
1627 SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree));
1628 ExtraRegInfo.clear();
1629 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1631 IntfCache.init(MF, &PhysReg2LiveUnion[0], Indexes, TRI);
1632 GlobalCand.resize(32); // This will grow as needed.
1636 LIS->addKillFlags();
1640 NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled);
1641 VRM->rewrite(Indexes);
1644 // Write out new DBG_VALUE instructions.
1646 NamedRegionTimer T("Emit Debug Info", TimerGroupName, TimePassesIsEnabled);
1647 DebugVars->emitDebugValues(VRM);
1650 // The pass output is in VirtRegMap. Release all the transient data.