1 //===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RAGreedy function pass for register allocation in
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "AllocationOrder.h"
17 #include "InterferenceCache.h"
18 #include "LiveDebugVariables.h"
19 #include "LiveRangeEdit.h"
20 #include "RegAllocBase.h"
22 #include "SpillPlacement.h"
24 #include "VirtRegMap.h"
25 #include "RegisterCoalescer.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Analysis/AliasAnalysis.h"
28 #include "llvm/Function.h"
29 #include "llvm/PassAnalysisSupport.h"
30 #include "llvm/CodeGen/CalcSpillWeights.h"
31 #include "llvm/CodeGen/EdgeBundles.h"
32 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
33 #include "llvm/CodeGen/LiveStackAnalysis.h"
34 #include "llvm/CodeGen/MachineDominators.h"
35 #include "llvm/CodeGen/MachineFunctionPass.h"
36 #include "llvm/CodeGen/MachineLoopInfo.h"
37 #include "llvm/CodeGen/MachineLoopRanges.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/Passes.h"
40 #include "llvm/CodeGen/RegAllocRegistry.h"
41 #include "llvm/Target/TargetOptions.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/raw_ostream.h"
45 #include "llvm/Support/Timer.h"
51 STATISTIC(NumGlobalSplits, "Number of split global live ranges");
52 STATISTIC(NumLocalSplits, "Number of split local live ranges");
53 STATISTIC(NumEvicted, "Number of interferences evicted");
55 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
56 createGreedyRegisterAllocator);
59 class RAGreedy : public MachineFunctionPass,
61 private LiveRangeEdit::Delegate {
69 MachineDominatorTree *DomTree;
70 MachineLoopInfo *Loops;
71 MachineLoopRanges *LoopRanges;
73 SpillPlacement *SpillPlacer;
74 LiveDebugVariables *DebugVars;
77 std::auto_ptr<Spiller> SpillerInstance;
78 std::priority_queue<std::pair<unsigned, unsigned> > Queue;
81 // Live ranges pass through a number of stages as we try to allocate them.
82 // Some of the stages may also create new live ranges:
84 // - Region splitting.
85 // - Per-block splitting.
89 // Ranges produced by one of the stages skip the previous stages when they are
90 // dequeued. This improves performance because we can skip interference checks
91 // that are unlikely to give any results. It also guarantees that the live
92 // range splitting algorithm terminates, something that is otherwise hard to
95 RS_New, ///< Never seen before.
96 RS_First, ///< First time in the queue.
97 RS_Second, ///< Second time in the queue.
98 RS_Global, ///< Produced by global splitting.
99 RS_Local, ///< Produced by local splitting.
100 RS_Spill ///< Produced by spilling.
103 static const char *const StageName[];
105 // RegInfo - Keep additional information about each live range.
107 LiveRangeStage Stage;
109 // Cascade - Eviction loop prevention. See canEvictInterference().
112 RegInfo() : Stage(RS_New), Cascade(0) {}
115 IndexedMap<RegInfo, VirtReg2IndexFunctor> ExtraRegInfo;
117 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
118 return ExtraRegInfo[VirtReg.reg].Stage;
121 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) {
122 ExtraRegInfo.resize(MRI->getNumVirtRegs());
123 ExtraRegInfo[VirtReg.reg].Stage = Stage;
126 template<typename Iterator>
127 void setStage(Iterator Begin, Iterator End, LiveRangeStage NewStage) {
128 ExtraRegInfo.resize(MRI->getNumVirtRegs());
129 for (;Begin != End; ++Begin) {
130 unsigned Reg = (*Begin)->reg;
131 if (ExtraRegInfo[Reg].Stage == RS_New)
132 ExtraRegInfo[Reg].Stage = NewStage;
136 /// Cost of evicting interference.
137 struct EvictionCost {
138 unsigned BrokenHints; ///< Total number of broken hints.
139 float MaxWeight; ///< Maximum spill weight evicted.
141 EvictionCost(unsigned B = 0) : BrokenHints(B), MaxWeight(0) {}
143 bool operator<(const EvictionCost &O) const {
144 if (BrokenHints != O.BrokenHints)
145 return BrokenHints < O.BrokenHints;
146 return MaxWeight < O.MaxWeight;
151 std::auto_ptr<SplitAnalysis> SA;
152 std::auto_ptr<SplitEditor> SE;
154 /// Cached per-block interference maps
155 InterferenceCache IntfCache;
157 /// All basic blocks where the current register has uses.
158 SmallVector<SpillPlacement::BlockConstraint, 8> SplitConstraints;
160 /// Global live range splitting candidate info.
161 struct GlobalSplitCandidate {
163 InterferenceCache::Cursor Intf;
164 BitVector LiveBundles;
165 SmallVector<unsigned, 8> ActiveBlocks;
167 void reset(InterferenceCache &Cache, unsigned Reg) {
169 Intf.setPhysReg(Cache, Reg);
171 ActiveBlocks.clear();
175 /// Candidate info for for each PhysReg in AllocationOrder.
176 /// This vector never shrinks, but grows to the size of the largest register
178 SmallVector<GlobalSplitCandidate, 32> GlobalCand;
183 /// Return the pass name.
184 virtual const char* getPassName() const {
185 return "Greedy Register Allocator";
188 /// RAGreedy analysis usage.
189 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
190 virtual void releaseMemory();
191 virtual Spiller &spiller() { return *SpillerInstance; }
192 virtual void enqueue(LiveInterval *LI);
193 virtual LiveInterval *dequeue();
194 virtual unsigned selectOrSplit(LiveInterval&,
195 SmallVectorImpl<LiveInterval*>&);
197 /// Perform register allocation.
198 virtual bool runOnMachineFunction(MachineFunction &mf);
203 void LRE_WillEraseInstruction(MachineInstr*);
204 bool LRE_CanEraseVirtReg(unsigned);
205 void LRE_WillShrinkVirtReg(unsigned);
206 void LRE_DidCloneVirtReg(unsigned, unsigned);
208 float calcSpillCost();
209 bool addSplitConstraints(InterferenceCache::Cursor, float&);
210 void addThroughConstraints(InterferenceCache::Cursor, ArrayRef<unsigned>);
211 void growRegion(GlobalSplitCandidate &Cand);
212 float calcGlobalSplitCost(GlobalSplitCandidate&);
213 void splitAroundRegion(LiveInterval&, GlobalSplitCandidate&,
214 SmallVectorImpl<LiveInterval*>&);
215 void calcGapWeights(unsigned, SmallVectorImpl<float>&);
216 bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool);
217 bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&);
218 void evictInterference(LiveInterval&, unsigned,
219 SmallVectorImpl<LiveInterval*>&);
221 unsigned tryAssign(LiveInterval&, AllocationOrder&,
222 SmallVectorImpl<LiveInterval*>&);
223 unsigned tryEvict(LiveInterval&, AllocationOrder&,
224 SmallVectorImpl<LiveInterval*>&, unsigned = ~0u);
225 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
226 SmallVectorImpl<LiveInterval*>&);
227 unsigned tryLocalSplit(LiveInterval&, AllocationOrder&,
228 SmallVectorImpl<LiveInterval*>&);
229 unsigned trySplit(LiveInterval&, AllocationOrder&,
230 SmallVectorImpl<LiveInterval*>&);
232 } // end anonymous namespace
234 char RAGreedy::ID = 0;
237 const char *const RAGreedy::StageName[] = {
247 // Hysteresis to use when comparing floats.
248 // This helps stabilize decisions based on float comparisons.
249 const float Hysteresis = 0.98f;
252 FunctionPass* llvm::createGreedyRegisterAllocator() {
253 return new RAGreedy();
256 RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
257 initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
258 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
259 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
260 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
261 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
262 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
263 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
264 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
265 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
266 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
267 initializeMachineLoopRangesPass(*PassRegistry::getPassRegistry());
268 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
269 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
270 initializeSpillPlacementPass(*PassRegistry::getPassRegistry());
273 void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
274 AU.setPreservesCFG();
275 AU.addRequired<AliasAnalysis>();
276 AU.addPreserved<AliasAnalysis>();
277 AU.addRequired<LiveIntervals>();
278 AU.addRequired<SlotIndexes>();
279 AU.addPreserved<SlotIndexes>();
280 AU.addRequired<LiveDebugVariables>();
281 AU.addPreserved<LiveDebugVariables>();
283 AU.addRequiredID(StrongPHIEliminationID);
284 AU.addRequiredTransitive<RegisterCoalescer>();
285 AU.addRequired<CalculateSpillWeights>();
286 AU.addRequired<LiveStacks>();
287 AU.addPreserved<LiveStacks>();
288 AU.addRequired<MachineDominatorTree>();
289 AU.addPreserved<MachineDominatorTree>();
290 AU.addRequired<MachineLoopInfo>();
291 AU.addPreserved<MachineLoopInfo>();
292 AU.addRequired<MachineLoopRanges>();
293 AU.addPreserved<MachineLoopRanges>();
294 AU.addRequired<VirtRegMap>();
295 AU.addPreserved<VirtRegMap>();
296 AU.addRequired<EdgeBundles>();
297 AU.addRequired<SpillPlacement>();
298 MachineFunctionPass::getAnalysisUsage(AU);
302 //===----------------------------------------------------------------------===//
303 // LiveRangeEdit delegate methods
304 //===----------------------------------------------------------------------===//
306 void RAGreedy::LRE_WillEraseInstruction(MachineInstr *MI) {
307 // LRE itself will remove from SlotIndexes and parent basic block.
308 VRM->RemoveMachineInstrFromMaps(MI);
311 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
312 if (unsigned PhysReg = VRM->getPhys(VirtReg)) {
313 unassign(LIS->getInterval(VirtReg), PhysReg);
316 // Unassigned virtreg is probably in the priority queue.
317 // RegAllocBase will erase it after dequeueing.
321 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) {
322 unsigned PhysReg = VRM->getPhys(VirtReg);
326 // Register is assigned, put it back on the queue for reassignment.
327 LiveInterval &LI = LIS->getInterval(VirtReg);
328 unassign(LI, PhysReg);
332 void RAGreedy::LRE_DidCloneVirtReg(unsigned New, unsigned Old) {
333 // LRE may clone a virtual register because dead code elimination causes it to
334 // be split into connected components. Ensure that the new register gets the
335 // same stage as the parent.
336 ExtraRegInfo.grow(New);
337 ExtraRegInfo[New] = ExtraRegInfo[Old];
340 void RAGreedy::releaseMemory() {
341 SpillerInstance.reset(0);
342 ExtraRegInfo.clear();
344 RegAllocBase::releaseMemory();
347 void RAGreedy::enqueue(LiveInterval *LI) {
348 // Prioritize live ranges by size, assigning larger ranges first.
349 // The queue holds (size, reg) pairs.
350 const unsigned Size = LI->getSize();
351 const unsigned Reg = LI->reg;
352 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
353 "Can only enqueue virtual registers");
356 ExtraRegInfo.grow(Reg);
357 if (ExtraRegInfo[Reg].Stage == RS_New)
358 ExtraRegInfo[Reg].Stage = RS_First;
360 if (ExtraRegInfo[Reg].Stage == RS_Second)
361 // Unsplit ranges that couldn't be allocated immediately are deferred until
362 // everything else has been allocated. Long ranges are allocated last so
363 // they are split against realistic interference.
364 Prio = (1u << 31) - Size;
366 // Everything else is allocated in long->short order. Long ranges that don't
367 // fit should be spilled ASAP so they don't create interference.
368 Prio = (1u << 31) + Size;
370 // Boost ranges that have a physical register hint.
371 if (TargetRegisterInfo::isPhysicalRegister(VRM->getRegAllocPref(Reg)))
375 Queue.push(std::make_pair(Prio, Reg));
378 LiveInterval *RAGreedy::dequeue() {
381 LiveInterval *LI = &LIS->getInterval(Queue.top().second);
387 //===----------------------------------------------------------------------===//
389 //===----------------------------------------------------------------------===//
391 /// tryAssign - Try to assign VirtReg to an available register.
392 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg,
393 AllocationOrder &Order,
394 SmallVectorImpl<LiveInterval*> &NewVRegs) {
397 while ((PhysReg = Order.next()))
398 if (!checkPhysRegInterference(VirtReg, PhysReg))
400 if (!PhysReg || Order.isHint(PhysReg))
403 // PhysReg is available, but there may be a better choice.
405 // If we missed a simple hint, try to cheaply evict interference from the
406 // preferred register.
407 if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg))
408 if (Order.isHint(Hint)) {
409 DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n');
410 EvictionCost MaxCost(1);
411 if (canEvictInterference(VirtReg, Hint, true, MaxCost)) {
412 evictInterference(VirtReg, Hint, NewVRegs);
417 // Try to evict interference from a cheaper alternative.
418 unsigned Cost = TRI->getCostPerUse(PhysReg);
420 // Most registers have 0 additional cost.
424 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost
426 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
427 return CheapReg ? CheapReg : PhysReg;
431 //===----------------------------------------------------------------------===//
432 // Interference eviction
433 //===----------------------------------------------------------------------===//
435 /// shouldEvict - determine if A should evict the assigned live range B. The
436 /// eviction policy defined by this function together with the allocation order
437 /// defined by enqueue() decides which registers ultimately end up being split
440 /// Cascade numbers are used to prevent infinite loops if this function is a
443 /// @param A The live range to be assigned.
444 /// @param IsHint True when A is about to be assigned to its preferred
446 /// @param B The live range to be evicted.
447 /// @param BreaksHint True when B is already assigned to its preferred register.
448 bool RAGreedy::shouldEvict(LiveInterval &A, bool IsHint,
449 LiveInterval &B, bool BreaksHint) {
450 bool CanSplit = getStage(B) <= RS_Second;
452 // Be fairly aggressive about following hints as long as the evictee can be
454 if (CanSplit && IsHint && !BreaksHint)
457 return A.weight > B.weight;
460 /// canEvictInterference - Return true if all interferences between VirtReg and
461 /// PhysReg can be evicted. When OnlyCheap is set, don't do anything
463 /// @param VirtReg Live range that is about to be assigned.
464 /// @param PhysReg Desired register for assignment.
465 /// @prarm IsHint True when PhysReg is VirtReg's preferred register.
466 /// @param MaxCost Only look for cheaper candidates and update with new cost
467 /// when returning true.
468 /// @returns True when interference can be evicted cheaper than MaxCost.
469 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
470 bool IsHint, EvictionCost &MaxCost) {
471 // Find VirtReg's cascade number. This will be unassigned if VirtReg was never
472 // involved in an eviction before. If a cascade number was assigned, deny
473 // evicting anything with the same or a newer cascade number. This prevents
474 // infinite eviction loops.
476 // This works out so a register without a cascade number is allowed to evict
477 // anything, and it can be evicted by anything.
478 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
480 Cascade = NextCascade;
483 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
484 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
485 // If there is 10 or more interferences, chances are one is heavier.
486 if (Q.collectInterferingVRegs(10) >= 10)
489 // Check if any interfering live range is heavier than MaxWeight.
490 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
491 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
492 if (TargetRegisterInfo::isPhysicalRegister(Intf->reg))
494 // Never evict spill products. They cannot split or spill.
495 if (getStage(*Intf) == RS_Spill)
497 // Once a live range becomes small enough, it is urgent that we find a
498 // register for it. This is indicated by an infinite spill weight. These
499 // urgent live ranges get to evict almost anything.
500 bool Urgent = !VirtReg.isSpillable() && Intf->isSpillable();
501 // Only evict older cascades or live ranges without a cascade.
502 unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;
503 if (Cascade <= IntfCascade) {
506 // We permit breaking cascades for urgent evictions. It should be the
507 // last resort, though, so make it really expensive.
508 Cost.BrokenHints += 10;
510 // Would this break a satisfied hint?
511 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg);
512 // Update eviction cost.
513 Cost.BrokenHints += BreaksHint;
514 Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight);
515 // Abort if this would be too expensive.
516 if (!(Cost < MaxCost))
518 // Finally, apply the eviction policy for non-urgent evictions.
519 if (!Urgent && !shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
527 /// evictInterference - Evict any interferring registers that prevent VirtReg
528 /// from being assigned to Physreg. This assumes that canEvictInterference
530 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg,
531 SmallVectorImpl<LiveInterval*> &NewVRegs) {
532 // Make sure that VirtReg has a cascade number, and assign that cascade
533 // number to every evicted register. These live ranges than then only be
534 // evicted by a newer cascade, preventing infinite loops.
535 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
537 Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;
539 DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI)
540 << " interference: Cascade " << Cascade << '\n');
541 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
542 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
543 assert(Q.seenAllInterferences() && "Didn't check all interfererences.");
544 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
545 LiveInterval *Intf = Q.interferingVRegs()[i];
546 unassign(*Intf, VRM->getPhys(Intf->reg));
547 assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||
548 VirtReg.isSpillable() < Intf->isSpillable()) &&
549 "Cannot decrease cascade number, illegal eviction");
550 ExtraRegInfo[Intf->reg].Cascade = Cascade;
552 NewVRegs.push_back(Intf);
557 /// tryEvict - Try to evict all interferences for a physreg.
558 /// @param VirtReg Currently unassigned virtual register.
559 /// @param Order Physregs to try.
560 /// @return Physreg to assign VirtReg, or 0.
561 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
562 AllocationOrder &Order,
563 SmallVectorImpl<LiveInterval*> &NewVRegs,
564 unsigned CostPerUseLimit) {
565 NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled);
567 // Keep track of the cheapest interference seen so far.
568 EvictionCost BestCost(~0u);
569 unsigned BestPhys = 0;
571 // When we are just looking for a reduced cost per use, don't break any
572 // hints, and only evict smaller spill weights.
573 if (CostPerUseLimit < ~0u) {
574 BestCost.BrokenHints = 0;
575 BestCost.MaxWeight = VirtReg.weight;
579 while (unsigned PhysReg = Order.next()) {
580 if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit)
582 // The first use of a callee-saved register in a function has cost 1.
583 // Don't start using a CSR when the CostPerUseLimit is low.
584 if (CostPerUseLimit == 1)
585 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
586 if (!MRI->isPhysRegUsed(CSR)) {
587 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR "
588 << PrintReg(CSR, TRI) << '\n');
592 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost))
598 // Stop if the hint can be used.
599 if (Order.isHint(PhysReg))
606 evictInterference(VirtReg, BestPhys, NewVRegs);
611 //===----------------------------------------------------------------------===//
613 //===----------------------------------------------------------------------===//
615 /// addSplitConstraints - Fill out the SplitConstraints vector based on the
616 /// interference pattern in Physreg and its aliases. Add the constraints to
617 /// SpillPlacement and return the static cost of this split in Cost, assuming
618 /// that all preferences in SplitConstraints are met.
619 /// Return false if there are no bundles with positive bias.
620 bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
622 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
624 // Reset interference dependent info.
625 SplitConstraints.resize(UseBlocks.size());
626 float StaticCost = 0;
627 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
628 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
629 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
631 BC.Number = BI.MBB->getNumber();
632 Intf.moveToBlock(BC.Number);
633 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
634 BC.Exit = BI.LiveOut ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
636 if (!Intf.hasInterference())
639 // Number of spill code instructions to insert.
642 // Interference for the live-in value.
644 if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number))
645 BC.Entry = SpillPlacement::MustSpill, ++Ins;
646 else if (Intf.first() < BI.FirstUse)
647 BC.Entry = SpillPlacement::PrefSpill, ++Ins;
648 else if (Intf.first() < BI.LastUse)
652 // Interference for the live-out value.
654 if (Intf.last() >= SA->getLastSplitPoint(BC.Number))
655 BC.Exit = SpillPlacement::MustSpill, ++Ins;
656 else if (Intf.last() > BI.LastUse)
657 BC.Exit = SpillPlacement::PrefSpill, ++Ins;
658 else if (Intf.last() > BI.FirstUse)
662 // Accumulate the total frequency of inserted spill code.
664 StaticCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
668 // Add constraints for use-blocks. Note that these are the only constraints
669 // that may add a positive bias, it is downhill from here.
670 SpillPlacer->addConstraints(SplitConstraints);
671 return SpillPlacer->scanActiveBundles();
675 /// addThroughConstraints - Add constraints and links to SpillPlacer from the
676 /// live-through blocks in Blocks.
677 void RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
678 ArrayRef<unsigned> Blocks) {
679 const unsigned GroupSize = 8;
680 SpillPlacement::BlockConstraint BCS[GroupSize];
681 unsigned TBS[GroupSize];
682 unsigned B = 0, T = 0;
684 for (unsigned i = 0; i != Blocks.size(); ++i) {
685 unsigned Number = Blocks[i];
686 Intf.moveToBlock(Number);
688 if (!Intf.hasInterference()) {
689 assert(T < GroupSize && "Array overflow");
691 if (++T == GroupSize) {
692 SpillPlacer->addLinks(ArrayRef<unsigned>(TBS, T));
698 assert(B < GroupSize && "Array overflow");
699 BCS[B].Number = Number;
701 // Interference for the live-in value.
702 if (Intf.first() <= Indexes->getMBBStartIdx(Number))
703 BCS[B].Entry = SpillPlacement::MustSpill;
705 BCS[B].Entry = SpillPlacement::PrefSpill;
707 // Interference for the live-out value.
708 if (Intf.last() >= SA->getLastSplitPoint(Number))
709 BCS[B].Exit = SpillPlacement::MustSpill;
711 BCS[B].Exit = SpillPlacement::PrefSpill;
713 if (++B == GroupSize) {
714 ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B);
715 SpillPlacer->addConstraints(Array);
720 ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B);
721 SpillPlacer->addConstraints(Array);
722 SpillPlacer->addLinks(ArrayRef<unsigned>(TBS, T));
725 void RAGreedy::growRegion(GlobalSplitCandidate &Cand) {
726 // Keep track of through blocks that have not been added to SpillPlacer.
727 BitVector Todo = SA->getThroughBlocks();
728 SmallVectorImpl<unsigned> &ActiveBlocks = Cand.ActiveBlocks;
729 unsigned AddedTo = 0;
731 unsigned Visited = 0;
735 ArrayRef<unsigned> NewBundles = SpillPlacer->getRecentPositive();
736 // Find new through blocks in the periphery of PrefRegBundles.
737 for (int i = 0, e = NewBundles.size(); i != e; ++i) {
738 unsigned Bundle = NewBundles[i];
739 // Look at all blocks connected to Bundle in the full graph.
740 ArrayRef<unsigned> Blocks = Bundles->getBlocks(Bundle);
741 for (ArrayRef<unsigned>::iterator I = Blocks.begin(), E = Blocks.end();
744 if (!Todo.test(Block))
747 // This is a new through block. Add it to SpillPlacer later.
748 ActiveBlocks.push_back(Block);
754 // Any new blocks to add?
755 if (ActiveBlocks.size() == AddedTo)
757 addThroughConstraints(Cand.Intf,
758 ArrayRef<unsigned>(ActiveBlocks).slice(AddedTo));
759 AddedTo = ActiveBlocks.size();
761 // Perhaps iterating can enable more bundles?
762 SpillPlacer->iterate();
764 DEBUG(dbgs() << ", v=" << Visited);
767 /// calcSpillCost - Compute how expensive it would be to split the live range in
768 /// SA around all use blocks instead of forming bundle regions.
769 float RAGreedy::calcSpillCost() {
771 const LiveInterval &LI = SA->getParent();
772 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
773 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
774 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
775 unsigned Number = BI.MBB->getNumber();
776 // We normally only need one spill instruction - a load or a store.
777 Cost += SpillPlacer->getBlockFrequency(Number);
779 // Unless the value is redefined in the block.
780 if (BI.LiveIn && BI.LiveOut) {
781 SlotIndex Start, Stop;
782 tie(Start, Stop) = Indexes->getMBBRange(Number);
783 LiveInterval::const_iterator I = LI.find(Start);
784 assert(I != LI.end() && "Expected live-in value");
785 // Is there a different live-out value? If so, we need an extra spill
788 Cost += SpillPlacer->getBlockFrequency(Number);
794 /// calcGlobalSplitCost - Return the global split cost of following the split
795 /// pattern in LiveBundles. This cost should be added to the local cost of the
796 /// interference pattern in SplitConstraints.
798 float RAGreedy::calcGlobalSplitCost(GlobalSplitCandidate &Cand) {
799 float GlobalCost = 0;
800 const BitVector &LiveBundles = Cand.LiveBundles;
801 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
802 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
803 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
804 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
805 bool RegIn = LiveBundles[Bundles->getBundle(BC.Number, 0)];
806 bool RegOut = LiveBundles[Bundles->getBundle(BC.Number, 1)];
810 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg);
812 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg);
814 GlobalCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
817 for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) {
818 unsigned Number = Cand.ActiveBlocks[i];
819 bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)];
820 bool RegOut = LiveBundles[Bundles->getBundle(Number, 1)];
821 if (!RegIn && !RegOut)
823 if (RegIn && RegOut) {
824 // We need double spill code if this block has interference.
825 Cand.Intf.moveToBlock(Number);
826 if (Cand.Intf.hasInterference())
827 GlobalCost += 2*SpillPlacer->getBlockFrequency(Number);
830 // live-in / stack-out or stack-in live-out.
831 GlobalCost += SpillPlacer->getBlockFrequency(Number);
836 /// splitAroundRegion - Split VirtReg around the region determined by
837 /// LiveBundles. Make an effort to avoid interference from PhysReg.
839 /// The 'register' interval is going to contain as many uses as possible while
840 /// avoiding interference. The 'stack' interval is the complement constructed by
841 /// SplitEditor. It will contain the rest.
843 void RAGreedy::splitAroundRegion(LiveInterval &VirtReg,
844 GlobalSplitCandidate &Cand,
845 SmallVectorImpl<LiveInterval*> &NewVRegs) {
846 const BitVector &LiveBundles = Cand.LiveBundles;
849 dbgs() << "Splitting around region for " << PrintReg(Cand.PhysReg, TRI)
851 for (int i = LiveBundles.find_first(); i>=0; i = LiveBundles.find_next(i))
852 dbgs() << " EB#" << i;
856 InterferenceCache::Cursor &Intf = Cand.Intf;
857 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
860 // Create the main cross-block interval.
861 const unsigned MainIntv = SE->openIntv();
863 // First handle all the blocks with uses.
864 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
865 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
866 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
867 bool RegIn = BI.LiveIn &&
868 LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)];
869 bool RegOut = BI.LiveOut &&
870 LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)];
872 // Create separate intervals for isolated blocks with multiple uses.
874 // |---o---o---| Enter and leave on the stack.
875 // ____-----____ Create local interval for uses.
877 // | o---o---| Defined in block, leave on stack.
878 // -----____ Create local interval for uses.
880 // |---o---x | Enter on stack, killed in block.
881 // ____----- Create local interval for uses.
883 if (!RegIn && !RegOut) {
884 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n");
885 if (!BI.isOneInstr()) {
886 SE->splitSingleBlock(BI);
887 SE->selectIntv(MainIntv);
892 SlotIndex Start, Stop;
893 tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
894 Intf.moveToBlock(BI.MBB->getNumber());
895 DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0)
896 << (BI.LiveIn ? (RegIn ? " => " : " -> ") : " ")
897 << "BB#" << BI.MBB->getNumber()
898 << (BI.LiveOut ? (RegOut ? " => " : " -> ") : " ")
899 << " EB#" << Bundles->getBundle(BI.MBB->getNumber(), 1)
900 << " [" << Start << ';'
901 << SA->getLastSplitPoint(BI.MBB->getNumber()) << '-' << Stop
902 << ") uses [" << BI.FirstUse << ';' << BI.LastUse
903 << ") intf [" << Intf.first() << ';' << Intf.last() << ')');
905 // The interference interval should either be invalid or overlap MBB.
906 assert((!Intf.hasInterference() || Intf.first() < Stop)
907 && "Bad interference");
908 assert((!Intf.hasInterference() || Intf.last() > Start)
909 && "Bad interference");
911 // We are now ready to decide where to split in the current block. There
912 // are many variables guiding the decision:
914 // - RegIn / RegOut: The global splitting algorithm's decisions for our
915 // ingoing and outgoing bundles.
917 // - BI.BlockIn / BI.BlockOut: Is the live range live-in and/or live-out
920 // - Intf.hasInterference(): Is there interference in this block.
922 // - Intf.first() / Inft.last(): The range of interference.
924 // The live range should be split such that MainIntv is live-in when RegIn
925 // is set, and live-out when RegOut is set. MainIntv should never overlap
926 // the interference, and the stack interval should never have more than one
929 // No splits can be inserted after LastSplitPoint, overlap instead.
930 SlotIndex LastSplitPoint = Stop;
932 LastSplitPoint = SA->getLastSplitPoint(BI.MBB->getNumber());
934 // At this point, we know that either RegIn or RegOut is set. We dealt with
935 // the all-stack case above.
937 // Blocks without interference are relatively easy.
938 if (!Intf.hasInterference()) {
939 DEBUG(dbgs() << ", no interference.\n");
940 SE->selectIntv(MainIntv);
941 // The easiest case has MainIntv live through.
943 // |---o---o---| Live-in, live-out.
944 // ============= Use MainIntv everywhere.
946 SlotIndex From = Start, To = Stop;
948 // Block entry. Reload before the first use if MainIntv is not live-in.
950 // |---o-- Enter on stack.
951 // ____=== Reload before first use.
953 // | o-- Defined in block.
954 // === Use MainIntv from def.
957 From = SE->enterIntvBefore(BI.FirstUse);
959 // Block exit. Handle cases where MainIntv is not live-out.
962 // --x | Killed in block.
963 // === Use MainIntv up to kill.
965 To = SE->leaveIntvAfter(BI.LastUse);
968 // --o---| Live-out on stack.
969 // ===____ Use MainIntv up to last use, switch to stack.
971 // -----o| Live-out on stack, last use after last split point.
972 // ====== Extend MainIntv to last use, overlapping.
973 // \____ Copy to stack interval before last split point.
975 if (BI.LastUse < LastSplitPoint)
976 To = SE->leaveIntvAfter(BI.LastUse);
978 // The last use is after the last split point, it is probably an
980 To = SE->leaveIntvBefore(LastSplitPoint);
981 // Run a double interval from the split to the last use. This makes
982 // it possible to spill the complement without affecting the indirect
984 SE->overlapIntv(To, BI.LastUse);
988 // Paint in MainIntv liveness for this block.
989 SE->useIntv(From, To);
993 // We are now looking at a block with interference, and we know that either
994 // RegIn or RegOut is set.
995 assert(Intf.hasInterference() && (RegIn || RegOut) && "Bad invariant");
997 // If the live range is not live through the block, it is possible that the
998 // interference doesn't even overlap. Deal with those cases first. Since
999 // no copy instructions are required, we can tolerate interference starting
1000 // or ending at the same instruction that kills or defines our live range.
1002 // Live-in, killed before interference.
1004 // ~~~ Interference after kill.
1005 // |---o---x | Killed in block.
1006 // ========= Use MainIntv everywhere.
1008 if (RegIn && !BI.LiveOut && BI.LastUse <= Intf.first()) {
1009 DEBUG(dbgs() << ", live-in, killed before interference.\n");
1010 SE->selectIntv(MainIntv);
1011 SlotIndex To = SE->leaveIntvAfter(BI.LastUse);
1012 SE->useIntv(Start, To);
1016 // Live-out, defined after interference.
1018 // ~~~ Interference before def.
1019 // | o---o---| Defined in block.
1020 // ========= Use MainIntv everywhere.
1022 if (RegOut && !BI.LiveIn && BI.FirstUse >= Intf.last()) {
1023 DEBUG(dbgs() << ", live-out, defined after interference.\n");
1024 SE->selectIntv(MainIntv);
1025 SlotIndex From = SE->enterIntvBefore(BI.FirstUse);
1026 SE->useIntv(From, Stop);
1030 // The interference is now known to overlap the live range, but it may
1031 // still be easy to avoid if all the interference is on one side of the
1032 // uses, and we enter or leave on the stack.
1034 // Live-out on stack, interference after last use.
1036 // ~~~ Interference after last use.
1037 // |---o---o---| Live-out on stack.
1038 // =========____ Leave MainIntv after last use.
1040 // ~ Interference after last use.
1041 // |---o---o--o| Live-out on stack, late last use.
1042 // ============ Copy to stack after LSP, overlap MainIntv.
1043 // \_____ Stack interval is live-out.
1045 if (!RegOut && Intf.first() > BI.LastUse.getBoundaryIndex()) {
1046 assert(RegIn && "Stack-in, stack-out should already be handled");
1047 if (BI.LastUse < LastSplitPoint) {
1048 DEBUG(dbgs() << ", live-in, stack-out, interference after last use.\n");
1049 SE->selectIntv(MainIntv);
1050 SlotIndex To = SE->leaveIntvAfter(BI.LastUse);
1051 assert(To <= Intf.first() && "Expected to avoid interference");
1052 SE->useIntv(Start, To);
1054 DEBUG(dbgs() << ", live-in, stack-out, avoid last split point\n");
1055 SE->selectIntv(MainIntv);
1056 SlotIndex To = SE->leaveIntvBefore(LastSplitPoint);
1057 assert(To <= Intf.first() && "Expected to avoid interference");
1058 SE->overlapIntv(To, BI.LastUse);
1059 SE->useIntv(Start, To);
1064 // Live-in on stack, interference before first use.
1066 // ~~~ Interference before first use.
1067 // |---o---o---| Live-in on stack.
1068 // ____========= Enter MainIntv before first use.
1070 if (!RegIn && Intf.last() < BI.FirstUse.getBaseIndex()) {
1071 assert(RegOut && "Stack-in, stack-out should already be handled");
1072 DEBUG(dbgs() << ", stack-in, interference before first use.\n");
1073 SE->selectIntv(MainIntv);
1074 SlotIndex From = SE->enterIntvBefore(BI.FirstUse);
1075 assert(From >= Intf.last() && "Expected to avoid interference");
1076 SE->useIntv(From, Stop);
1080 // The interference is overlapping somewhere we wanted to use MainIntv. That
1081 // means we need to create a local interval that can be allocated a
1082 // different register.
1083 unsigned LocalIntv = SE->openIntv();
1084 DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n");
1086 // We may be creating copies directly between MainIntv and LocalIntv,
1087 // bypassing the stack interval. When we do that, we should never use the
1088 // leaveIntv* methods as they define values in the stack interval. By
1089 // starting from the end of the block and working our way backwards, we can
1090 // get by with only enterIntv* methods.
1092 // When selecting split points, we generally try to maximize the stack
1093 // interval as long at it contains no uses, maximize the main interval as
1094 // long as it doesn't overlap interference, and minimize the local interval
1095 // that we don't know how to allocate yet.
1097 // Handle the block exit, set Pos to the first handled slot.
1098 SlotIndex Pos = BI.LastUse;
1100 assert(Intf.last() < LastSplitPoint && "Cannot be live-out in register");
1101 // Create a snippet of MainIntv that is live-out.
1103 // ~~~ Interference overlapping uses.
1104 // --o---| Live-out in MainIntv.
1105 // ----=== Switch from LocalIntv to MainIntv after interference.
1107 SE->selectIntv(MainIntv);
1108 Pos = SE->enterIntvAfter(Intf.last());
1109 assert(Pos >= Intf.last() && "Expected to avoid interference");
1110 SE->useIntv(Pos, Stop);
1111 SE->selectIntv(LocalIntv);
1112 } else if (BI.LiveOut) {
1113 if (BI.LastUse < LastSplitPoint) {
1114 // Live-out on the stack.
1116 // ~~~ Interference overlapping uses.
1117 // --o---| Live-out on stack.
1118 // ---____ Switch from LocalIntv to stack after last use.
1120 Pos = SE->leaveIntvAfter(BI.LastUse);
1122 // Live-out on the stack, last use after last split point.
1124 // ~~~ Interference overlapping uses.
1125 // --o--o| Live-out on stack, late use.
1126 // ------ Copy to stack before LSP, overlap LocalIntv.
1129 Pos = SE->leaveIntvBefore(LastSplitPoint);
1130 // We need to overlap LocalIntv so it can reach LastUse.
1131 SE->overlapIntv(Pos, BI.LastUse);
1135 // When not live-out, leave Pos at LastUse. We have handled everything from
1136 // Pos to Stop. Find the starting point for LocalIntv.
1137 assert(SE->currentIntv() == LocalIntv && "Expecting local interval");
1140 assert(Start < Intf.first() && "Cannot be live-in with interference");
1141 // Live-in in MainIntv, only use LocalIntv for interference.
1143 // ~~~ Interference overlapping uses.
1144 // |---o-- Live-in in MainIntv.
1145 // ====--- Switch to LocalIntv before interference.
1147 SlotIndex Switch = SE->enterIntvBefore(std::min(Pos, Intf.first()));
1148 assert(Switch <= Intf.first() && "Expected to avoid interference");
1149 SE->useIntv(Switch, Pos);
1150 SE->selectIntv(MainIntv);
1151 SE->useIntv(Start, Switch);
1153 // Live-in on stack, enter LocalIntv before first use.
1155 // ~~~ Interference overlapping uses.
1156 // |---o-- Live-in in MainIntv.
1157 // ____--- Reload to LocalIntv before interference.
1159 // Defined in block.
1161 // ~~~ Interference overlapping uses.
1162 // | o-- Defined in block.
1163 // --- Begin LocalIntv at first use.
1165 SlotIndex Switch = SE->enterIntvBefore(std::min(Pos, BI.FirstUse));
1166 SE->useIntv(Switch, Pos);
1170 // Handle live-through blocks.
1171 SE->selectIntv(MainIntv);
1172 for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) {
1173 unsigned Number = Cand.ActiveBlocks[i];
1174 bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)];
1175 bool RegOut = LiveBundles[Bundles->getBundle(Number, 1)];
1176 DEBUG(dbgs() << "Live through BB#" << Number << '\n');
1177 if (RegIn && RegOut) {
1178 Intf.moveToBlock(Number);
1179 if (!Intf.hasInterference()) {
1180 SE->useIntv(Indexes->getMBBStartIdx(Number),
1181 Indexes->getMBBEndIdx(Number));
1185 MachineBasicBlock *MBB = MF->getBlockNumbered(Number);
1187 SE->leaveIntvAtTop(*MBB);
1189 SE->enterIntvAtEnd(*MBB);
1194 SmallVector<unsigned, 8> IntvMap;
1195 SE->finish(&IntvMap);
1196 DebugVars->splitRegister(VirtReg.reg, LREdit.regs());
1198 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1199 unsigned OrigBlocks = SA->getNumLiveBlocks();
1201 // Sort out the new intervals created by splitting. We get four kinds:
1202 // - Remainder intervals should not be split again.
1203 // - Candidate intervals can be assigned to Cand.PhysReg.
1204 // - Block-local splits are candidates for local splitting.
1205 // - DCE leftovers should go back on the queue.
1206 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) {
1207 LiveInterval &Reg = *LREdit.get(i);
1209 // Ignore old intervals from DCE.
1210 if (getStage(Reg) != RS_New)
1213 // Remainder interval. Don't try splitting again, spill if it doesn't
1215 if (IntvMap[i] == 0) {
1216 setStage(Reg, RS_Global);
1220 // Main interval. Allow repeated splitting as long as the number of live
1221 // blocks is strictly decreasing.
1222 if (IntvMap[i] == MainIntv) {
1223 if (SA->countLiveBlocks(&Reg) >= OrigBlocks) {
1224 DEBUG(dbgs() << "Main interval covers the same " << OrigBlocks
1225 << " blocks as original.\n");
1226 // Don't allow repeated splitting as a safe guard against looping.
1227 setStage(Reg, RS_Global);
1232 // Other intervals are treated as new. This includes local intervals created
1233 // for blocks with multiple uses, and anything created by DCE.
1237 MF->verify(this, "After splitting live range around region");
1240 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1241 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1242 float BestCost = Hysteresis * calcSpillCost();
1243 DEBUG(dbgs() << "Cost of isolating all blocks = " << BestCost << '\n');
1244 const unsigned NoCand = ~0u;
1245 unsigned BestCand = NoCand;
1246 unsigned NumCands = 0;
1249 while (unsigned PhysReg = Order.next()) {
1250 if (GlobalCand.size() <= NumCands)
1251 GlobalCand.resize(NumCands+1);
1252 GlobalSplitCandidate &Cand = GlobalCand[NumCands];
1253 Cand.reset(IntfCache, PhysReg);
1255 SpillPlacer->prepare(Cand.LiveBundles);
1257 if (!addSplitConstraints(Cand.Intf, Cost)) {
1258 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n");
1261 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = " << Cost);
1262 if (Cost >= BestCost) {
1264 if (BestCand == NoCand)
1265 dbgs() << " worse than no bundles\n";
1267 dbgs() << " worse than "
1268 << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
1274 SpillPlacer->finish();
1276 // No live bundles, defer to splitSingleBlocks().
1277 if (!Cand.LiveBundles.any()) {
1278 DEBUG(dbgs() << " no bundles.\n");
1282 Cost += calcGlobalSplitCost(Cand);
1284 dbgs() << ", total = " << Cost << " with bundles";
1285 for (int i = Cand.LiveBundles.find_first(); i>=0;
1286 i = Cand.LiveBundles.find_next(i))
1287 dbgs() << " EB#" << i;
1290 if (Cost < BestCost) {
1291 BestCand = NumCands;
1292 BestCost = Hysteresis * Cost; // Prevent rounding effects.
1297 if (BestCand == NoCand)
1300 splitAroundRegion(VirtReg, GlobalCand[BestCand], NewVRegs);
1305 //===----------------------------------------------------------------------===//
1307 //===----------------------------------------------------------------------===//
1310 /// calcGapWeights - Compute the maximum spill weight that needs to be evicted
1311 /// in order to use PhysReg between two entries in SA->UseSlots.
1313 /// GapWeight[i] represents the gap between UseSlots[i] and UseSlots[i+1].
1315 void RAGreedy::calcGapWeights(unsigned PhysReg,
1316 SmallVectorImpl<float> &GapWeight) {
1317 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
1318 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
1319 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
1320 const unsigned NumGaps = Uses.size()-1;
1322 // Start and end points for the interference check.
1323 SlotIndex StartIdx = BI.LiveIn ? BI.FirstUse.getBaseIndex() : BI.FirstUse;
1324 SlotIndex StopIdx = BI.LiveOut ? BI.LastUse.getBoundaryIndex() : BI.LastUse;
1326 GapWeight.assign(NumGaps, 0.0f);
1328 // Add interference from each overlapping register.
1329 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
1330 if (!query(const_cast<LiveInterval&>(SA->getParent()), *AI)
1331 .checkInterference())
1334 // We know that VirtReg is a continuous interval from FirstUse to LastUse,
1335 // so we don't need InterferenceQuery.
1337 // Interference that overlaps an instruction is counted in both gaps
1338 // surrounding the instruction. The exception is interference before
1339 // StartIdx and after StopIdx.
1341 LiveIntervalUnion::SegmentIter IntI = PhysReg2LiveUnion[*AI].find(StartIdx);
1342 for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) {
1343 // Skip the gaps before IntI.
1344 while (Uses[Gap+1].getBoundaryIndex() < IntI.start())
1345 if (++Gap == NumGaps)
1350 // Update the gaps covered by IntI.
1351 const float weight = IntI.value()->weight;
1352 for (; Gap != NumGaps; ++Gap) {
1353 GapWeight[Gap] = std::max(GapWeight[Gap], weight);
1354 if (Uses[Gap+1].getBaseIndex() >= IntI.stop())
1363 /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
1366 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1367 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1368 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
1369 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
1371 // Note that it is possible to have an interval that is live-in or live-out
1372 // while only covering a single block - A phi-def can use undef values from
1373 // predecessors, and the block could be a single-block loop.
1374 // We don't bother doing anything clever about such a case, we simply assume
1375 // that the interval is continuous from FirstUse to LastUse. We should make
1376 // sure that we don't do anything illegal to such an interval, though.
1378 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
1379 if (Uses.size() <= 2)
1381 const unsigned NumGaps = Uses.size()-1;
1384 dbgs() << "tryLocalSplit: ";
1385 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
1386 dbgs() << ' ' << SA->UseSlots[i];
1390 // Since we allow local split results to be split again, there is a risk of
1391 // creating infinite loops. It is tempting to require that the new live
1392 // ranges have less instructions than the original. That would guarantee
1393 // convergence, but it is too strict. A live range with 3 instructions can be
1394 // split 2+3 (including the COPY), and we want to allow that.
1396 // Instead we use these rules:
1398 // 1. Allow any split for ranges with getStage() < RS_Local. (Except for the
1399 // noop split, of course).
1400 // 2. Require progress be made for ranges with getStage() >= RS_Local. All
1401 // the new ranges must have fewer instructions than before the split.
1402 // 3. New ranges with the same number of instructions are marked RS_Local,
1403 // smaller ranges are marked RS_New.
1405 // These rules allow a 3 -> 2+3 split once, which we need. They also prevent
1406 // excessive splitting and infinite loops.
1408 bool ProgressRequired = getStage(VirtReg) >= RS_Local;
1410 // Best split candidate.
1411 unsigned BestBefore = NumGaps;
1412 unsigned BestAfter = 0;
1415 const float blockFreq = SpillPlacer->getBlockFrequency(BI.MBB->getNumber());
1416 SmallVector<float, 8> GapWeight;
1419 while (unsigned PhysReg = Order.next()) {
1420 // Keep track of the largest spill weight that would need to be evicted in
1421 // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1].
1422 calcGapWeights(PhysReg, GapWeight);
1424 // Try to find the best sequence of gaps to close.
1425 // The new spill weight must be larger than any gap interference.
1427 // We will split before Uses[SplitBefore] and after Uses[SplitAfter].
1428 unsigned SplitBefore = 0, SplitAfter = 1;
1430 // MaxGap should always be max(GapWeight[SplitBefore..SplitAfter-1]).
1431 // It is the spill weight that needs to be evicted.
1432 float MaxGap = GapWeight[0];
1435 // Live before/after split?
1436 const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
1437 const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut;
1439 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' '
1440 << Uses[SplitBefore] << '-' << Uses[SplitAfter]
1441 << " i=" << MaxGap);
1443 // Stop before the interval gets so big we wouldn't be making progress.
1444 if (!LiveBefore && !LiveAfter) {
1445 DEBUG(dbgs() << " all\n");
1448 // Should the interval be extended or shrunk?
1451 // How many gaps would the new range have?
1452 unsigned NewGaps = LiveBefore + SplitAfter - SplitBefore + LiveAfter;
1454 // Legally, without causing looping?
1455 bool Legal = !ProgressRequired || NewGaps < NumGaps;
1457 if (Legal && MaxGap < HUGE_VALF) {
1458 // Estimate the new spill weight. Each instruction reads or writes the
1459 // register. Conservatively assume there are no read-modify-write
1462 // Try to guess the size of the new interval.
1463 const float EstWeight = normalizeSpillWeight(blockFreq * (NewGaps + 1),
1464 Uses[SplitBefore].distance(Uses[SplitAfter]) +
1465 (LiveBefore + LiveAfter)*SlotIndex::InstrDist);
1466 // Would this split be possible to allocate?
1467 // Never allocate all gaps, we wouldn't be making progress.
1468 DEBUG(dbgs() << " w=" << EstWeight);
1469 if (EstWeight * Hysteresis >= MaxGap) {
1471 float Diff = EstWeight - MaxGap;
1472 if (Diff > BestDiff) {
1473 DEBUG(dbgs() << " (best)");
1474 BestDiff = Hysteresis * Diff;
1475 BestBefore = SplitBefore;
1476 BestAfter = SplitAfter;
1483 if (++SplitBefore < SplitAfter) {
1484 DEBUG(dbgs() << " shrink\n");
1485 // Recompute the max when necessary.
1486 if (GapWeight[SplitBefore - 1] >= MaxGap) {
1487 MaxGap = GapWeight[SplitBefore];
1488 for (unsigned i = SplitBefore + 1; i != SplitAfter; ++i)
1489 MaxGap = std::max(MaxGap, GapWeight[i]);
1496 // Try to extend the interval.
1497 if (SplitAfter >= NumGaps) {
1498 DEBUG(dbgs() << " end\n");
1502 DEBUG(dbgs() << " extend\n");
1503 MaxGap = std::max(MaxGap, GapWeight[SplitAfter++]);
1507 // Didn't find any candidates?
1508 if (BestBefore == NumGaps)
1511 DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore]
1512 << '-' << Uses[BestAfter] << ", " << BestDiff
1513 << ", " << (BestAfter - BestBefore + 1) << " instrs\n");
1515 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
1519 SlotIndex SegStart = SE->enterIntvBefore(Uses[BestBefore]);
1520 SlotIndex SegStop = SE->leaveIntvAfter(Uses[BestAfter]);
1521 SE->useIntv(SegStart, SegStop);
1522 SmallVector<unsigned, 8> IntvMap;
1523 SE->finish(&IntvMap);
1524 DebugVars->splitRegister(VirtReg.reg, LREdit.regs());
1526 // If the new range has the same number of instructions as before, mark it as
1527 // RS_Local so the next split will be forced to make progress. Otherwise,
1528 // leave the new intervals as RS_New so they can compete.
1529 bool LiveBefore = BestBefore != 0 || BI.LiveIn;
1530 bool LiveAfter = BestAfter != NumGaps || BI.LiveOut;
1531 unsigned NewGaps = LiveBefore + BestAfter - BestBefore + LiveAfter;
1532 if (NewGaps >= NumGaps) {
1533 DEBUG(dbgs() << "Tagging non-progress ranges: ");
1534 assert(!ProgressRequired && "Didn't make progress when it was required.");
1535 for (unsigned i = 0, e = IntvMap.size(); i != e; ++i)
1536 if (IntvMap[i] == 1) {
1537 setStage(*LREdit.get(i), RS_Local);
1538 DEBUG(dbgs() << PrintReg(LREdit.get(i)->reg));
1540 DEBUG(dbgs() << '\n');
1547 //===----------------------------------------------------------------------===//
1548 // Live Range Splitting
1549 //===----------------------------------------------------------------------===//
1551 /// trySplit - Try to split VirtReg or one of its interferences, making it
1553 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
1554 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
1555 SmallVectorImpl<LiveInterval*>&NewVRegs) {
1556 // Local intervals are handled separately.
1557 if (LIS->intervalIsInOneMBB(VirtReg)) {
1558 NamedRegionTimer T("Local Splitting", TimerGroupName, TimePassesIsEnabled);
1559 SA->analyze(&VirtReg);
1560 return tryLocalSplit(VirtReg, Order, NewVRegs);
1563 NamedRegionTimer T("Global Splitting", TimerGroupName, TimePassesIsEnabled);
1565 // Don't iterate global splitting.
1566 // Move straight to spilling if this range was produced by a global split.
1567 if (getStage(VirtReg) >= RS_Global)
1570 SA->analyze(&VirtReg);
1572 // FIXME: SplitAnalysis may repair broken live ranges coming from the
1573 // coalescer. That may cause the range to become allocatable which means that
1574 // tryRegionSplit won't be making progress. This check should be replaced with
1575 // an assertion when the coalescer is fixed.
1576 if (SA->didRepairRange()) {
1577 // VirtReg has changed, so all cached queries are invalid.
1578 invalidateVirtRegs();
1579 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
1583 // First try to split around a region spanning multiple blocks.
1584 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1585 if (PhysReg || !NewVRegs.empty())
1588 // Then isolate blocks with multiple uses.
1589 SplitAnalysis::BlockPtrSet Blocks;
1590 if (SA->getMultiUseBlocks(Blocks)) {
1591 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
1593 SE->splitSingleBlocks(Blocks);
1594 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Global);
1596 MF->verify(this, "After splitting live range around basic blocks");
1599 // Don't assign any physregs.
1604 //===----------------------------------------------------------------------===//
1606 //===----------------------------------------------------------------------===//
1608 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
1609 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1610 // First try assigning a free register.
1611 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
1612 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
1615 LiveRangeStage Stage = getStage(VirtReg);
1616 DEBUG(dbgs() << StageName[Stage]
1617 << " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n');
1619 // Try to evict a less worthy live range, but only for ranges from the primary
1620 // queue. The RS_Second ranges already failed to do this, and they should not
1621 // get a second chance until they have been split.
1622 if (Stage != RS_Second)
1623 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs))
1626 assert(NewVRegs.empty() && "Cannot append to existing NewVRegs");
1628 // The first time we see a live range, don't try to split or spill.
1629 // Wait until the second time, when all smaller ranges have been allocated.
1630 // This gives a better picture of the interference to split around.
1631 if (Stage == RS_First) {
1632 setStage(VirtReg, RS_Second);
1633 DEBUG(dbgs() << "wait for second round\n");
1634 NewVRegs.push_back(&VirtReg);
1638 // If we couldn't allocate a register from spilling, there is probably some
1639 // invalid inline assembly. The base class wil report it.
1640 if (Stage >= RS_Spill || !VirtReg.isSpillable())
1643 // Try splitting VirtReg or interferences.
1644 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
1645 if (PhysReg || !NewVRegs.empty())
1648 // Finally spill VirtReg itself.
1649 NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
1650 LiveRangeEdit LRE(VirtReg, NewVRegs, this);
1651 spiller().spill(LRE);
1652 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Spill);
1655 MF->verify(this, "After spilling");
1657 // The live virtual register requesting allocation was spilled, so tell
1658 // the caller not to allocate anything during this round.
1662 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
1663 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
1664 << "********** Function: "
1665 << ((Value*)mf.getFunction())->getName() << '\n');
1669 MF->verify(this, "Before greedy register allocator");
1671 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
1672 Indexes = &getAnalysis<SlotIndexes>();
1673 DomTree = &getAnalysis<MachineDominatorTree>();
1674 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
1675 Loops = &getAnalysis<MachineLoopInfo>();
1676 LoopRanges = &getAnalysis<MachineLoopRanges>();
1677 Bundles = &getAnalysis<EdgeBundles>();
1678 SpillPlacer = &getAnalysis<SpillPlacement>();
1679 DebugVars = &getAnalysis<LiveDebugVariables>();
1681 SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops));
1682 SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree));
1683 ExtraRegInfo.clear();
1684 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1686 IntfCache.init(MF, &PhysReg2LiveUnion[0], Indexes, TRI);
1690 LIS->addKillFlags();
1694 NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled);
1695 VRM->rewrite(Indexes);
1698 // Write out new DBG_VALUE instructions.
1699 DebugVars->emitDebugValues(VRM);
1701 // The pass output is in VirtRegMap. Release all the transient data.