1 //===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RAGreedy function pass for register allocation in
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "AllocationOrder.h"
17 #include "InterferenceCache.h"
18 #include "LiveDebugVariables.h"
19 #include "LiveRangeEdit.h"
20 #include "RegAllocBase.h"
22 #include "SpillPlacement.h"
24 #include "VirtRegMap.h"
25 #include "RegisterCoalescer.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Analysis/AliasAnalysis.h"
28 #include "llvm/Function.h"
29 #include "llvm/PassAnalysisSupport.h"
30 #include "llvm/CodeGen/CalcSpillWeights.h"
31 #include "llvm/CodeGen/EdgeBundles.h"
32 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
33 #include "llvm/CodeGen/LiveStackAnalysis.h"
34 #include "llvm/CodeGen/MachineDominators.h"
35 #include "llvm/CodeGen/MachineFunctionPass.h"
36 #include "llvm/CodeGen/MachineLoopInfo.h"
37 #include "llvm/CodeGen/MachineLoopRanges.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/Passes.h"
40 #include "llvm/CodeGen/RegAllocRegistry.h"
41 #include "llvm/Target/TargetOptions.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/raw_ostream.h"
45 #include "llvm/Support/Timer.h"
51 STATISTIC(NumGlobalSplits, "Number of split global live ranges");
52 STATISTIC(NumLocalSplits, "Number of split local live ranges");
53 STATISTIC(NumEvicted, "Number of interferences evicted");
55 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
56 createGreedyRegisterAllocator);
59 class RAGreedy : public MachineFunctionPass,
61 private LiveRangeEdit::Delegate {
69 MachineDominatorTree *DomTree;
70 MachineLoopInfo *Loops;
71 MachineLoopRanges *LoopRanges;
73 SpillPlacement *SpillPlacer;
74 LiveDebugVariables *DebugVars;
77 std::auto_ptr<Spiller> SpillerInstance;
78 std::priority_queue<std::pair<unsigned, unsigned> > Queue;
80 // Live ranges pass through a number of stages as we try to allocate them.
81 // Some of the stages may also create new live ranges:
83 // - Region splitting.
84 // - Per-block splitting.
88 // Ranges produced by one of the stages skip the previous stages when they are
89 // dequeued. This improves performance because we can skip interference checks
90 // that are unlikely to give any results. It also guarantees that the live
91 // range splitting algorithm terminates, something that is otherwise hard to
94 RS_New, ///< Never seen before.
95 RS_First, ///< First time in the queue.
96 RS_Second, ///< Second time in the queue.
97 RS_Global, ///< Produced by global splitting.
98 RS_Local, ///< Produced by local splitting.
99 RS_Spill ///< Produced by spilling.
102 static const char *const StageName[];
104 IndexedMap<unsigned char, VirtReg2IndexFunctor> LRStage;
106 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
107 return LiveRangeStage(LRStage[VirtReg.reg]);
110 template<typename Iterator>
111 void setStage(Iterator Begin, Iterator End, LiveRangeStage NewStage) {
112 LRStage.resize(MRI->getNumVirtRegs());
113 for (;Begin != End; ++Begin) {
114 unsigned Reg = (*Begin)->reg;
115 if (LRStage[Reg] == RS_New)
116 LRStage[Reg] = NewStage;
120 // Eviction. Sometimes an assigned live range can be evicted without
121 // conditions, but other times it must be split after being evicted to avoid
124 CE_Never, ///< Can never evict.
125 CE_Always, ///< Can always evict.
126 CE_WithSplit ///< Can evict only if range is also split or spilled.
130 std::auto_ptr<SplitAnalysis> SA;
131 std::auto_ptr<SplitEditor> SE;
133 /// Cached per-block interference maps
134 InterferenceCache IntfCache;
136 /// All basic blocks where the current register has uses.
137 SmallVector<SpillPlacement::BlockConstraint, 8> SplitConstraints;
139 /// Global live range splitting candidate info.
140 struct GlobalSplitCandidate {
142 BitVector LiveBundles;
143 SmallVector<unsigned, 8> ActiveBlocks;
145 void reset(unsigned Reg) {
148 ActiveBlocks.clear();
152 /// Candidate info for for each PhysReg in AllocationOrder.
153 /// This vector never shrinks, but grows to the size of the largest register
155 SmallVector<GlobalSplitCandidate, 32> GlobalCand;
160 /// Return the pass name.
161 virtual const char* getPassName() const {
162 return "Greedy Register Allocator";
165 /// RAGreedy analysis usage.
166 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
167 virtual void releaseMemory();
168 virtual Spiller &spiller() { return *SpillerInstance; }
169 virtual void enqueue(LiveInterval *LI);
170 virtual LiveInterval *dequeue();
171 virtual unsigned selectOrSplit(LiveInterval&,
172 SmallVectorImpl<LiveInterval*>&);
174 /// Perform register allocation.
175 virtual bool runOnMachineFunction(MachineFunction &mf);
180 void LRE_WillEraseInstruction(MachineInstr*);
181 bool LRE_CanEraseVirtReg(unsigned);
182 void LRE_WillShrinkVirtReg(unsigned);
183 void LRE_DidCloneVirtReg(unsigned, unsigned);
185 float calcSpillCost();
186 bool addSplitConstraints(InterferenceCache::Cursor, float&);
187 void addThroughConstraints(InterferenceCache::Cursor, ArrayRef<unsigned>);
188 void growRegion(GlobalSplitCandidate &Cand, InterferenceCache::Cursor);
189 float calcGlobalSplitCost(GlobalSplitCandidate&, InterferenceCache::Cursor);
190 void splitAroundRegion(LiveInterval&, GlobalSplitCandidate&,
191 SmallVectorImpl<LiveInterval*>&);
192 void calcGapWeights(unsigned, SmallVectorImpl<float>&);
193 CanEvict canEvict(LiveInterval &A, LiveInterval &B);
194 bool canEvictInterference(LiveInterval&, unsigned, float&);
196 unsigned tryAssign(LiveInterval&, AllocationOrder&,
197 SmallVectorImpl<LiveInterval*>&);
198 unsigned tryEvict(LiveInterval&, AllocationOrder&,
199 SmallVectorImpl<LiveInterval*>&, unsigned = ~0u);
200 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
201 SmallVectorImpl<LiveInterval*>&);
202 unsigned tryLocalSplit(LiveInterval&, AllocationOrder&,
203 SmallVectorImpl<LiveInterval*>&);
204 unsigned trySplit(LiveInterval&, AllocationOrder&,
205 SmallVectorImpl<LiveInterval*>&);
207 } // end anonymous namespace
209 char RAGreedy::ID = 0;
212 const char *const RAGreedy::StageName[] = {
222 // Hysteresis to use when comparing floats.
223 // This helps stabilize decisions based on float comparisons.
224 const float Hysteresis = 0.98f;
227 FunctionPass* llvm::createGreedyRegisterAllocator() {
228 return new RAGreedy();
231 RAGreedy::RAGreedy(): MachineFunctionPass(ID), LRStage(RS_New) {
232 initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
233 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
234 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
235 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
236 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
237 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
238 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
239 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
240 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
241 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
242 initializeMachineLoopRangesPass(*PassRegistry::getPassRegistry());
243 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
244 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
245 initializeSpillPlacementPass(*PassRegistry::getPassRegistry());
248 void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
249 AU.setPreservesCFG();
250 AU.addRequired<AliasAnalysis>();
251 AU.addPreserved<AliasAnalysis>();
252 AU.addRequired<LiveIntervals>();
253 AU.addRequired<SlotIndexes>();
254 AU.addPreserved<SlotIndexes>();
255 AU.addRequired<LiveDebugVariables>();
256 AU.addPreserved<LiveDebugVariables>();
258 AU.addRequiredID(StrongPHIEliminationID);
259 AU.addRequiredTransitive<RegisterCoalescer>();
260 AU.addRequired<CalculateSpillWeights>();
261 AU.addRequired<LiveStacks>();
262 AU.addPreserved<LiveStacks>();
263 AU.addRequired<MachineDominatorTree>();
264 AU.addPreserved<MachineDominatorTree>();
265 AU.addRequired<MachineLoopInfo>();
266 AU.addPreserved<MachineLoopInfo>();
267 AU.addRequired<MachineLoopRanges>();
268 AU.addPreserved<MachineLoopRanges>();
269 AU.addRequired<VirtRegMap>();
270 AU.addPreserved<VirtRegMap>();
271 AU.addRequired<EdgeBundles>();
272 AU.addRequired<SpillPlacement>();
273 MachineFunctionPass::getAnalysisUsage(AU);
277 //===----------------------------------------------------------------------===//
278 // LiveRangeEdit delegate methods
279 //===----------------------------------------------------------------------===//
281 void RAGreedy::LRE_WillEraseInstruction(MachineInstr *MI) {
282 // LRE itself will remove from SlotIndexes and parent basic block.
283 VRM->RemoveMachineInstrFromMaps(MI);
286 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
287 if (unsigned PhysReg = VRM->getPhys(VirtReg)) {
288 unassign(LIS->getInterval(VirtReg), PhysReg);
291 // Unassigned virtreg is probably in the priority queue.
292 // RegAllocBase will erase it after dequeueing.
296 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) {
297 unsigned PhysReg = VRM->getPhys(VirtReg);
301 // Register is assigned, put it back on the queue for reassignment.
302 LiveInterval &LI = LIS->getInterval(VirtReg);
303 unassign(LI, PhysReg);
307 void RAGreedy::LRE_DidCloneVirtReg(unsigned New, unsigned Old) {
308 // LRE may clone a virtual register because dead code elimination causes it to
309 // be split into connected components. Ensure that the new register gets the
310 // same stage as the parent.
312 LRStage[New] = LRStage[Old];
315 void RAGreedy::releaseMemory() {
316 SpillerInstance.reset(0);
319 RegAllocBase::releaseMemory();
322 void RAGreedy::enqueue(LiveInterval *LI) {
323 // Prioritize live ranges by size, assigning larger ranges first.
324 // The queue holds (size, reg) pairs.
325 const unsigned Size = LI->getSize();
326 const unsigned Reg = LI->reg;
327 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
328 "Can only enqueue virtual registers");
332 if (LRStage[Reg] == RS_New)
333 LRStage[Reg] = RS_First;
335 if (LRStage[Reg] == RS_Second)
336 // Unsplit ranges that couldn't be allocated immediately are deferred until
337 // everything else has been allocated. Long ranges are allocated last so
338 // they are split against realistic interference.
339 Prio = (1u << 31) - Size;
341 // Everything else is allocated in long->short order. Long ranges that don't
342 // fit should be spilled ASAP so they don't create interference.
343 Prio = (1u << 31) + Size;
345 // Boost ranges that have a physical register hint.
346 if (TargetRegisterInfo::isPhysicalRegister(VRM->getRegAllocPref(Reg)))
350 Queue.push(std::make_pair(Prio, Reg));
353 LiveInterval *RAGreedy::dequeue() {
356 LiveInterval *LI = &LIS->getInterval(Queue.top().second);
362 //===----------------------------------------------------------------------===//
364 //===----------------------------------------------------------------------===//
366 /// tryAssign - Try to assign VirtReg to an available register.
367 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg,
368 AllocationOrder &Order,
369 SmallVectorImpl<LiveInterval*> &NewVRegs) {
372 while ((PhysReg = Order.next()))
373 if (!checkPhysRegInterference(VirtReg, PhysReg))
375 if (!PhysReg || Order.isHint(PhysReg))
378 // PhysReg is available. Try to evict interference from a cheaper alternative.
379 unsigned Cost = TRI->getCostPerUse(PhysReg);
381 // Most registers have 0 additional cost.
385 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost
387 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
388 return CheapReg ? CheapReg : PhysReg;
392 //===----------------------------------------------------------------------===//
393 // Interference eviction
394 //===----------------------------------------------------------------------===//
396 /// canEvict - determine if A can evict the assigned live range B. The eviction
397 /// policy defined by this function together with the allocation order defined
398 /// by enqueue() decides which registers ultimately end up being split and
401 /// This function must define a non-circular relation when it returns CE_Always,
402 /// otherwise infinite eviction loops are possible. When evicting a <= RS_Second
403 /// range, it is possible to return CE_WithSplit which forces the evicted
404 /// register to be split or spilled before it can evict anything again. That
405 /// guarantees progress.
406 RAGreedy::CanEvict RAGreedy::canEvict(LiveInterval &A, LiveInterval &B) {
407 return A.weight > B.weight ? CE_Always : CE_Never;
410 /// canEvict - Return true if all interferences between VirtReg and PhysReg can
412 /// Return false if any interference is heavier than MaxWeight.
413 /// On return, set MaxWeight to the maximal spill weight of an interference.
414 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
417 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
418 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
419 // If there is 10 or more interferences, chances are one is heavier.
420 if (Q.collectInterferingVRegs(10, MaxWeight) >= 10)
423 // Check if any interfering live range is heavier than MaxWeight.
424 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
425 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
426 if (TargetRegisterInfo::isPhysicalRegister(Intf->reg))
428 if (Intf->weight >= MaxWeight)
430 switch (canEvict(VirtReg, *Intf)) {
436 if (getStage(*Intf) > RS_Second)
440 Weight = std::max(Weight, Intf->weight);
447 /// tryEvict - Try to evict all interferences for a physreg.
448 /// @param VirtReg Currently unassigned virtual register.
449 /// @param Order Physregs to try.
450 /// @return Physreg to assign VirtReg, or 0.
451 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
452 AllocationOrder &Order,
453 SmallVectorImpl<LiveInterval*> &NewVRegs,
454 unsigned CostPerUseLimit) {
455 NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled);
457 // Keep track of the lightest single interference seen so far.
458 float BestWeight = HUGE_VALF;
459 unsigned BestPhys = 0;
462 while (unsigned PhysReg = Order.next()) {
463 if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit)
465 // The first use of a register in a function has cost 1.
466 if (CostPerUseLimit == 1 && !MRI->isPhysRegUsed(PhysReg))
469 float Weight = BestWeight;
470 if (!canEvictInterference(VirtReg, PhysReg, Weight))
473 // This is an eviction candidate.
474 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " interference = "
476 if (BestPhys && Weight >= BestWeight)
482 // Stop if the hint can be used.
483 if (Order.isHint(PhysReg))
490 DEBUG(dbgs() << "evicting " << PrintReg(BestPhys, TRI) << " interference\n");
491 for (const unsigned *AliasI = TRI->getOverlaps(BestPhys); *AliasI; ++AliasI) {
492 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
493 assert(Q.seenAllInterferences() && "Didn't check all interfererences.");
494 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
495 LiveInterval *Intf = Q.interferingVRegs()[i];
496 unassign(*Intf, VRM->getPhys(Intf->reg));
498 NewVRegs.push_back(Intf);
499 // Prevent looping by forcing the evicted ranges to be split before they
500 // can evict anything else.
501 if (getStage(*Intf) < RS_Second &&
502 canEvict(VirtReg, *Intf) == CE_WithSplit)
503 LRStage[Intf->reg] = RS_Second;
510 //===----------------------------------------------------------------------===//
512 //===----------------------------------------------------------------------===//
514 /// addSplitConstraints - Fill out the SplitConstraints vector based on the
515 /// interference pattern in Physreg and its aliases. Add the constraints to
516 /// SpillPlacement and return the static cost of this split in Cost, assuming
517 /// that all preferences in SplitConstraints are met.
518 /// Return false if there are no bundles with positive bias.
519 bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
521 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
523 // Reset interference dependent info.
524 SplitConstraints.resize(UseBlocks.size());
525 float StaticCost = 0;
526 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
527 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
528 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
530 BC.Number = BI.MBB->getNumber();
531 Intf.moveToBlock(BC.Number);
532 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
533 BC.Exit = BI.LiveOut ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
535 if (!Intf.hasInterference())
538 // Number of spill code instructions to insert.
541 // Interference for the live-in value.
543 if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number))
544 BC.Entry = SpillPlacement::MustSpill, ++Ins;
545 else if (Intf.first() < BI.FirstUse)
546 BC.Entry = SpillPlacement::PrefSpill, ++Ins;
547 else if (Intf.first() < BI.LastUse)
551 // Interference for the live-out value.
553 if (Intf.last() >= SA->getLastSplitPoint(BC.Number))
554 BC.Exit = SpillPlacement::MustSpill, ++Ins;
555 else if (Intf.last() > BI.LastUse)
556 BC.Exit = SpillPlacement::PrefSpill, ++Ins;
557 else if (Intf.last() > BI.FirstUse)
561 // Accumulate the total frequency of inserted spill code.
563 StaticCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
567 // Add constraints for use-blocks. Note that these are the only constraints
568 // that may add a positive bias, it is downhill from here.
569 SpillPlacer->addConstraints(SplitConstraints);
570 return SpillPlacer->scanActiveBundles();
574 /// addThroughConstraints - Add constraints and links to SpillPlacer from the
575 /// live-through blocks in Blocks.
576 void RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
577 ArrayRef<unsigned> Blocks) {
578 const unsigned GroupSize = 8;
579 SpillPlacement::BlockConstraint BCS[GroupSize];
580 unsigned TBS[GroupSize];
581 unsigned B = 0, T = 0;
583 for (unsigned i = 0; i != Blocks.size(); ++i) {
584 unsigned Number = Blocks[i];
585 Intf.moveToBlock(Number);
587 if (!Intf.hasInterference()) {
588 assert(T < GroupSize && "Array overflow");
590 if (++T == GroupSize) {
591 SpillPlacer->addLinks(ArrayRef<unsigned>(TBS, T));
597 assert(B < GroupSize && "Array overflow");
598 BCS[B].Number = Number;
600 // Interference for the live-in value.
601 if (Intf.first() <= Indexes->getMBBStartIdx(Number))
602 BCS[B].Entry = SpillPlacement::MustSpill;
604 BCS[B].Entry = SpillPlacement::PrefSpill;
606 // Interference for the live-out value.
607 if (Intf.last() >= SA->getLastSplitPoint(Number))
608 BCS[B].Exit = SpillPlacement::MustSpill;
610 BCS[B].Exit = SpillPlacement::PrefSpill;
612 if (++B == GroupSize) {
613 ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B);
614 SpillPlacer->addConstraints(Array);
619 ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B);
620 SpillPlacer->addConstraints(Array);
621 SpillPlacer->addLinks(ArrayRef<unsigned>(TBS, T));
624 void RAGreedy::growRegion(GlobalSplitCandidate &Cand,
625 InterferenceCache::Cursor Intf) {
626 // Keep track of through blocks that have not been added to SpillPlacer.
627 BitVector Todo = SA->getThroughBlocks();
628 SmallVectorImpl<unsigned> &ActiveBlocks = Cand.ActiveBlocks;
629 unsigned AddedTo = 0;
631 unsigned Visited = 0;
635 ArrayRef<unsigned> NewBundles = SpillPlacer->getRecentPositive();
636 if (NewBundles.empty())
638 // Find new through blocks in the periphery of PrefRegBundles.
639 for (int i = 0, e = NewBundles.size(); i != e; ++i) {
640 unsigned Bundle = NewBundles[i];
641 // Look at all blocks connected to Bundle in the full graph.
642 ArrayRef<unsigned> Blocks = Bundles->getBlocks(Bundle);
643 for (ArrayRef<unsigned>::iterator I = Blocks.begin(), E = Blocks.end();
646 if (!Todo.test(Block))
649 // This is a new through block. Add it to SpillPlacer later.
650 ActiveBlocks.push_back(Block);
656 // Any new blocks to add?
657 if (ActiveBlocks.size() > AddedTo) {
658 ArrayRef<unsigned> Add(&ActiveBlocks[AddedTo],
659 ActiveBlocks.size() - AddedTo);
660 addThroughConstraints(Intf, Add);
661 AddedTo = ActiveBlocks.size();
663 // Perhaps iterating can enable more bundles?
664 SpillPlacer->iterate();
666 DEBUG(dbgs() << ", v=" << Visited);
669 /// calcSpillCost - Compute how expensive it would be to split the live range in
670 /// SA around all use blocks instead of forming bundle regions.
671 float RAGreedy::calcSpillCost() {
673 const LiveInterval &LI = SA->getParent();
674 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
675 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
676 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
677 unsigned Number = BI.MBB->getNumber();
678 // We normally only need one spill instruction - a load or a store.
679 Cost += SpillPlacer->getBlockFrequency(Number);
681 // Unless the value is redefined in the block.
682 if (BI.LiveIn && BI.LiveOut) {
683 SlotIndex Start, Stop;
684 tie(Start, Stop) = Indexes->getMBBRange(Number);
685 LiveInterval::const_iterator I = LI.find(Start);
686 assert(I != LI.end() && "Expected live-in value");
687 // Is there a different live-out value? If so, we need an extra spill
690 Cost += SpillPlacer->getBlockFrequency(Number);
696 /// calcGlobalSplitCost - Return the global split cost of following the split
697 /// pattern in LiveBundles. This cost should be added to the local cost of the
698 /// interference pattern in SplitConstraints.
700 float RAGreedy::calcGlobalSplitCost(GlobalSplitCandidate &Cand,
701 InterferenceCache::Cursor Intf) {
702 float GlobalCost = 0;
703 const BitVector &LiveBundles = Cand.LiveBundles;
704 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
705 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
706 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
707 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
708 bool RegIn = LiveBundles[Bundles->getBundle(BC.Number, 0)];
709 bool RegOut = LiveBundles[Bundles->getBundle(BC.Number, 1)];
713 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg);
715 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg);
717 GlobalCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
720 for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) {
721 unsigned Number = Cand.ActiveBlocks[i];
722 bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)];
723 bool RegOut = LiveBundles[Bundles->getBundle(Number, 1)];
724 if (!RegIn && !RegOut)
726 if (RegIn && RegOut) {
727 // We need double spill code if this block has interference.
728 Intf.moveToBlock(Number);
729 if (Intf.hasInterference())
730 GlobalCost += 2*SpillPlacer->getBlockFrequency(Number);
733 // live-in / stack-out or stack-in live-out.
734 GlobalCost += SpillPlacer->getBlockFrequency(Number);
739 /// splitAroundRegion - Split VirtReg around the region determined by
740 /// LiveBundles. Make an effort to avoid interference from PhysReg.
742 /// The 'register' interval is going to contain as many uses as possible while
743 /// avoiding interference. The 'stack' interval is the complement constructed by
744 /// SplitEditor. It will contain the rest.
746 void RAGreedy::splitAroundRegion(LiveInterval &VirtReg,
747 GlobalSplitCandidate &Cand,
748 SmallVectorImpl<LiveInterval*> &NewVRegs) {
749 const BitVector &LiveBundles = Cand.LiveBundles;
752 dbgs() << "Splitting around region for " << PrintReg(Cand.PhysReg, TRI)
754 for (int i = LiveBundles.find_first(); i>=0; i = LiveBundles.find_next(i))
755 dbgs() << " EB#" << i;
759 InterferenceCache::Cursor Intf(IntfCache, Cand.PhysReg);
760 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
763 // Create the main cross-block interval.
764 const unsigned MainIntv = SE->openIntv();
766 // First handle all the blocks with uses.
767 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
768 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
769 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
770 bool RegIn = BI.LiveIn &&
771 LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)];
772 bool RegOut = BI.LiveOut &&
773 LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)];
775 // Create separate intervals for isolated blocks with multiple uses.
777 // |---o---o---| Enter and leave on the stack.
778 // ____-----____ Create local interval for uses.
780 // | o---o---| Defined in block, leave on stack.
781 // -----____ Create local interval for uses.
783 // |---o---x | Enter on stack, killed in block.
784 // ____----- Create local interval for uses.
786 if (!RegIn && !RegOut) {
787 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n");
788 if (!BI.isOneInstr()) {
789 SE->splitSingleBlock(BI);
790 SE->selectIntv(MainIntv);
795 SlotIndex Start, Stop;
796 tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
797 Intf.moveToBlock(BI.MBB->getNumber());
798 DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0)
799 << (RegIn ? " => " : " -- ")
800 << "BB#" << BI.MBB->getNumber()
801 << (RegOut ? " => " : " -- ")
802 << " EB#" << Bundles->getBundle(BI.MBB->getNumber(), 1)
803 << " [" << Start << ';'
804 << SA->getLastSplitPoint(BI.MBB->getNumber()) << '-' << Stop
805 << ") uses [" << BI.FirstUse << ';' << BI.LastUse
806 << ") intf [" << Intf.first() << ';' << Intf.last() << ')');
808 // The interference interval should either be invalid or overlap MBB.
809 assert((!Intf.hasInterference() || Intf.first() < Stop)
810 && "Bad interference");
811 assert((!Intf.hasInterference() || Intf.last() > Start)
812 && "Bad interference");
814 // We are now ready to decide where to split in the current block. There
815 // are many variables guiding the decision:
817 // - RegIn / RegOut: The global splitting algorithm's decisions for our
818 // ingoing and outgoing bundles.
820 // - BI.BlockIn / BI.BlockOut: Is the live range live-in and/or live-out
823 // - Intf.hasInterference(): Is there interference in this block.
825 // - Intf.first() / Inft.last(): The range of interference.
827 // The live range should be split such that MainIntv is live-in when RegIn
828 // is set, and live-out when RegOut is set. MainIntv should never overlap
829 // the interference, and the stack interval should never have more than one
832 // No splits can be inserted after LastSplitPoint, overlap instead.
833 SlotIndex LastSplitPoint = Stop;
835 LastSplitPoint = SA->getLastSplitPoint(BI.MBB->getNumber());
837 // At this point, we know that either RegIn or RegOut is set. We dealt with
838 // the all-stack case above.
840 // Blocks without interference are relatively easy.
841 if (!Intf.hasInterference()) {
842 DEBUG(dbgs() << ", no interference.\n");
843 SE->selectIntv(MainIntv);
844 // The easiest case has MainIntv live through.
846 // |---o---o---| Live-in, live-out.
847 // ============= Use MainIntv everywhere.
849 SlotIndex From = Start, To = Stop;
851 // Block entry. Reload before the first use if MainIntv is not live-in.
853 // |---o-- Enter on stack.
854 // ____=== Reload before first use.
856 // | o-- Defined in block.
857 // === Use MainIntv from def.
860 From = SE->enterIntvBefore(BI.FirstUse);
862 // Block exit. Handle cases where MainIntv is not live-out.
865 // --x | Killed in block.
866 // === Use MainIntv up to kill.
868 To = SE->leaveIntvAfter(BI.LastUse);
871 // --o---| Live-out on stack.
872 // ===____ Use MainIntv up to last use, switch to stack.
874 // -----o| Live-out on stack, last use after last split point.
875 // ====== Extend MainIntv to last use, overlapping.
876 // \____ Copy to stack interval before last split point.
878 if (BI.LastUse < LastSplitPoint)
879 To = SE->leaveIntvAfter(BI.LastUse);
881 // The last use is after the last split point, it is probably an
883 To = SE->leaveIntvBefore(LastSplitPoint);
884 // Run a double interval from the split to the last use. This makes
885 // it possible to spill the complement without affecting the indirect
887 SE->overlapIntv(To, BI.LastUse);
891 // Paint in MainIntv liveness for this block.
892 SE->useIntv(From, To);
896 // We are now looking at a block with interference, and we know that either
897 // RegIn or RegOut is set.
898 assert(Intf.hasInterference() && (RegIn || RegOut) && "Bad invariant");
900 // If the live range is not live through the block, it is possible that the
901 // interference doesn't even overlap. Deal with those cases first. Since
902 // no copy instructions are required, we can tolerate interference starting
903 // or ending at the same instruction that kills or defines our live range.
905 // Live-in, killed before interference.
907 // ~~~ Interference after kill.
908 // |---o---x | Killed in block.
909 // ========= Use MainIntv everywhere.
911 if (RegIn && !BI.LiveOut && BI.LastUse <= Intf.first()) {
912 DEBUG(dbgs() << ", live-in, killed before interference.\n");
913 SE->selectIntv(MainIntv);
914 SlotIndex To = SE->leaveIntvAfter(BI.LastUse);
915 SE->useIntv(Start, To);
919 // Live-out, defined after interference.
921 // ~~~ Interference before def.
922 // | o---o---| Defined in block.
923 // ========= Use MainIntv everywhere.
925 if (RegOut && !BI.LiveIn && BI.FirstUse >= Intf.last()) {
926 DEBUG(dbgs() << ", live-out, defined after interference.\n");
927 SE->selectIntv(MainIntv);
928 SlotIndex From = SE->enterIntvBefore(BI.FirstUse);
929 SE->useIntv(From, Stop);
933 // The interference is now known to overlap the live range, but it may
934 // still be easy to avoid if all the interference is on one side of the
935 // uses, and we enter or leave on the stack.
937 // Live-out on stack, interference after last use.
939 // ~~~ Interference after last use.
940 // |---o---o---| Live-out on stack.
941 // =========____ Leave MainIntv after last use.
943 // ~ Interference after last use.
944 // |---o---o--o| Live-out on stack, late last use.
945 // =========____ Copy to stack after LSP, overlap MainIntv.
947 if (!RegOut && Intf.first() > BI.LastUse.getBoundaryIndex()) {
948 assert(RegIn && "Stack-in, stack-out should already be handled");
949 if (BI.LastUse < LastSplitPoint) {
950 DEBUG(dbgs() << ", live-in, stack-out, interference after last use.\n");
951 SE->selectIntv(MainIntv);
952 SlotIndex To = SE->leaveIntvAfter(BI.LastUse);
953 assert(To <= Intf.first() && "Expected to avoid interference");
954 SE->useIntv(Start, To);
956 DEBUG(dbgs() << ", live-in, stack-out, avoid last split point\n");
957 SE->selectIntv(MainIntv);
958 SlotIndex To = SE->leaveIntvBefore(LastSplitPoint);
959 assert(To <= Intf.first() && "Expected to avoid interference");
960 SE->overlapIntv(To, BI.LastUse);
961 SE->useIntv(Start, To);
966 // Live-in on stack, interference before first use.
968 // ~~~ Interference before first use.
969 // |---o---o---| Live-in on stack.
970 // ____========= Enter MainIntv before first use.
972 if (!RegIn && Intf.last() < BI.FirstUse.getBaseIndex()) {
973 assert(RegOut && "Stack-in, stack-out should already be handled");
974 DEBUG(dbgs() << ", stack-in, interference before first use.\n");
975 SE->selectIntv(MainIntv);
976 SlotIndex From = SE->enterIntvBefore(BI.FirstUse);
977 assert(From >= Intf.last() && "Expected to avoid interference");
978 SE->useIntv(From, Stop);
982 // The interference is overlapping somewhere we wanted to use MainIntv. That
983 // means we need to create a local interval that can be allocated a
984 // different register.
985 DEBUG(dbgs() << ", creating local interval.\n");
986 unsigned LocalIntv = SE->openIntv();
988 // We may be creating copies directly between MainIntv and LocalIntv,
989 // bypassing the stack interval. When we do that, we should never use the
990 // leaveIntv* methods as they define values in the stack interval. By
991 // starting from the end of the block and working our way backwards, we can
992 // get by with only enterIntv* methods.
994 // When selecting split points, we generally try to maximize the stack
995 // interval as long at it contains no uses, maximize the main interval as
996 // long as it doesn't overlap interference, and minimize the local interval
997 // that we don't know how to allocate yet.
999 // Handle the block exit, set Pos to the first handled slot.
1000 SlotIndex Pos = BI.LastUse;
1002 assert(Intf.last() < LastSplitPoint && "Cannot be live-out in register");
1003 // Create a snippet of MainIntv that is live-out.
1005 // ~~~ Interference overlapping uses.
1006 // --o---| Live-out in MainIntv.
1007 // ----=== Switch from LocalIntv to MainIntv after interference.
1009 SE->selectIntv(MainIntv);
1010 Pos = SE->enterIntvAfter(Intf.last());
1011 assert(Pos >= Intf.last() && "Expected to avoid interference");
1012 SE->useIntv(Pos, Stop);
1013 SE->selectIntv(LocalIntv);
1014 } else if (BI.LiveOut) {
1015 if (BI.LastUse < LastSplitPoint) {
1016 // Live-out on the stack.
1018 // ~~~ Interference overlapping uses.
1019 // --o---| Live-out on stack.
1020 // ---____ Switch from LocalIntv to stack after last use.
1022 Pos = SE->leaveIntvAfter(BI.LastUse);
1024 // Live-out on the stack, last use after last split point.
1026 // ~~~ Interference overlapping uses.
1027 // --o--o| Live-out on stack, late use.
1028 // ------ Copy to stack before LSP, overlap LocalIntv.
1031 Pos = SE->leaveIntvBefore(LastSplitPoint);
1032 // We need to overlap LocalIntv so it can reach LastUse.
1033 SE->overlapIntv(Pos, BI.LastUse);
1037 // When not live-out, leave Pos at LastUse. We have handled everything from
1038 // Pos to Stop. Find the starting point for LocalIntv.
1039 assert(SE->currentIntv() == LocalIntv && "Expecting local interval");
1042 assert(Start < Intf.first() && "Cannot be live-in with interference");
1043 // Live-in in MainIntv, only use LocalIntv for interference.
1045 // ~~~ Interference overlapping uses.
1046 // |---o-- Live-in in MainIntv.
1047 // ====--- Switch to LocalIntv before interference.
1049 SlotIndex Switch = SE->enterIntvBefore(Intf.first());
1050 assert(Switch <= Intf.first() && "Expected to avoid interference");
1051 SE->useIntv(Switch, Pos);
1052 SE->selectIntv(MainIntv);
1053 SE->useIntv(Start, Switch);
1055 // Live-in on stack, enter LocalIntv before first use.
1057 // ~~~ Interference overlapping uses.
1058 // |---o-- Live-in in MainIntv.
1059 // ____--- Reload to LocalIntv before interference.
1061 // Defined in block.
1063 // ~~~ Interference overlapping uses.
1064 // | o-- Defined in block.
1065 // --- Begin LocalIntv at first use.
1067 SlotIndex Switch = SE->enterIntvBefore(BI.FirstUse);
1068 SE->useIntv(Switch, Pos);
1072 // Handle live-through blocks.
1073 SE->selectIntv(MainIntv);
1074 for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) {
1075 unsigned Number = Cand.ActiveBlocks[i];
1076 bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)];
1077 bool RegOut = LiveBundles[Bundles->getBundle(Number, 1)];
1078 DEBUG(dbgs() << "Live through BB#" << Number << '\n');
1079 if (RegIn && RegOut) {
1080 Intf.moveToBlock(Number);
1081 if (!Intf.hasInterference()) {
1082 SE->useIntv(Indexes->getMBBStartIdx(Number),
1083 Indexes->getMBBEndIdx(Number));
1087 MachineBasicBlock *MBB = MF->getBlockNumbered(Number);
1089 SE->leaveIntvAtTop(*MBB);
1091 SE->enterIntvAtEnd(*MBB);
1096 SmallVector<unsigned, 8> IntvMap;
1097 SE->finish(&IntvMap);
1098 DebugVars->splitRegister(VirtReg.reg, LREdit.regs());
1100 LRStage.resize(MRI->getNumVirtRegs());
1101 unsigned OrigBlocks = SA->getNumLiveBlocks();
1103 // Sort out the new intervals created by splitting. We get four kinds:
1104 // - Remainder intervals should not be split again.
1105 // - Candidate intervals can be assigned to Cand.PhysReg.
1106 // - Block-local splits are candidates for local splitting.
1107 // - DCE leftovers should go back on the queue.
1108 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) {
1109 unsigned Reg = LREdit.get(i)->reg;
1111 // Ignore old intervals from DCE.
1112 if (LRStage[Reg] != RS_New)
1115 // Remainder interval. Don't try splitting again, spill if it doesn't
1117 if (IntvMap[i] == 0) {
1118 LRStage[Reg] = RS_Global;
1122 // Main interval. Allow repeated splitting as long as the number of live
1123 // blocks is strictly decreasing.
1124 if (IntvMap[i] == MainIntv) {
1125 if (SA->countLiveBlocks(LREdit.get(i)) >= OrigBlocks) {
1126 DEBUG(dbgs() << "Main interval covers the same " << OrigBlocks
1127 << " blocks as original.\n");
1128 // Don't allow repeated splitting as a safe guard against looping.
1129 LRStage[Reg] = RS_Global;
1134 // Other intervals are treated as new. This includes local intervals created
1135 // for blocks with multiple uses, and anything created by DCE.
1139 MF->verify(this, "After splitting live range around region");
1142 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1143 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1144 float BestCost = Hysteresis * calcSpillCost();
1145 DEBUG(dbgs() << "Cost of isolating all blocks = " << BestCost << '\n');
1146 const unsigned NoCand = ~0u;
1147 unsigned BestCand = NoCand;
1150 for (unsigned Cand = 0; unsigned PhysReg = Order.next(); ++Cand) {
1151 if (GlobalCand.size() <= Cand)
1152 GlobalCand.resize(Cand+1);
1153 GlobalCand[Cand].reset(PhysReg);
1155 SpillPlacer->prepare(GlobalCand[Cand].LiveBundles);
1157 InterferenceCache::Cursor Intf(IntfCache, PhysReg);
1158 if (!addSplitConstraints(Intf, Cost)) {
1159 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n");
1162 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = " << Cost);
1163 if (Cost >= BestCost) {
1165 if (BestCand == NoCand)
1166 dbgs() << " worse than no bundles\n";
1168 dbgs() << " worse than "
1169 << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
1173 growRegion(GlobalCand[Cand], Intf);
1175 SpillPlacer->finish();
1177 // No live bundles, defer to splitSingleBlocks().
1178 if (!GlobalCand[Cand].LiveBundles.any()) {
1179 DEBUG(dbgs() << " no bundles.\n");
1183 Cost += calcGlobalSplitCost(GlobalCand[Cand], Intf);
1185 dbgs() << ", total = " << Cost << " with bundles";
1186 for (int i = GlobalCand[Cand].LiveBundles.find_first(); i>=0;
1187 i = GlobalCand[Cand].LiveBundles.find_next(i))
1188 dbgs() << " EB#" << i;
1191 if (Cost < BestCost) {
1193 BestCost = Hysteresis * Cost; // Prevent rounding effects.
1197 if (BestCand == NoCand)
1200 splitAroundRegion(VirtReg, GlobalCand[BestCand], NewVRegs);
1205 //===----------------------------------------------------------------------===//
1207 //===----------------------------------------------------------------------===//
1210 /// calcGapWeights - Compute the maximum spill weight that needs to be evicted
1211 /// in order to use PhysReg between two entries in SA->UseSlots.
1213 /// GapWeight[i] represents the gap between UseSlots[i] and UseSlots[i+1].
1215 void RAGreedy::calcGapWeights(unsigned PhysReg,
1216 SmallVectorImpl<float> &GapWeight) {
1217 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
1218 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
1219 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
1220 const unsigned NumGaps = Uses.size()-1;
1222 // Start and end points for the interference check.
1223 SlotIndex StartIdx = BI.LiveIn ? BI.FirstUse.getBaseIndex() : BI.FirstUse;
1224 SlotIndex StopIdx = BI.LiveOut ? BI.LastUse.getBoundaryIndex() : BI.LastUse;
1226 GapWeight.assign(NumGaps, 0.0f);
1228 // Add interference from each overlapping register.
1229 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
1230 if (!query(const_cast<LiveInterval&>(SA->getParent()), *AI)
1231 .checkInterference())
1234 // We know that VirtReg is a continuous interval from FirstUse to LastUse,
1235 // so we don't need InterferenceQuery.
1237 // Interference that overlaps an instruction is counted in both gaps
1238 // surrounding the instruction. The exception is interference before
1239 // StartIdx and after StopIdx.
1241 LiveIntervalUnion::SegmentIter IntI = PhysReg2LiveUnion[*AI].find(StartIdx);
1242 for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) {
1243 // Skip the gaps before IntI.
1244 while (Uses[Gap+1].getBoundaryIndex() < IntI.start())
1245 if (++Gap == NumGaps)
1250 // Update the gaps covered by IntI.
1251 const float weight = IntI.value()->weight;
1252 for (; Gap != NumGaps; ++Gap) {
1253 GapWeight[Gap] = std::max(GapWeight[Gap], weight);
1254 if (Uses[Gap+1].getBaseIndex() >= IntI.stop())
1263 /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
1266 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1267 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1268 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
1269 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
1271 // Note that it is possible to have an interval that is live-in or live-out
1272 // while only covering a single block - A phi-def can use undef values from
1273 // predecessors, and the block could be a single-block loop.
1274 // We don't bother doing anything clever about such a case, we simply assume
1275 // that the interval is continuous from FirstUse to LastUse. We should make
1276 // sure that we don't do anything illegal to such an interval, though.
1278 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
1279 if (Uses.size() <= 2)
1281 const unsigned NumGaps = Uses.size()-1;
1284 dbgs() << "tryLocalSplit: ";
1285 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
1286 dbgs() << ' ' << SA->UseSlots[i];
1290 // Since we allow local split results to be split again, there is a risk of
1291 // creating infinite loops. It is tempting to require that the new live
1292 // ranges have less instructions than the original. That would guarantee
1293 // convergence, but it is too strict. A live range with 3 instructions can be
1294 // split 2+3 (including the COPY), and we want to allow that.
1296 // Instead we use these rules:
1298 // 1. Allow any split for ranges with getStage() < RS_Local. (Except for the
1299 // noop split, of course).
1300 // 2. Require progress be made for ranges with getStage() >= RS_Local. All
1301 // the new ranges must have fewer instructions than before the split.
1302 // 3. New ranges with the same number of instructions are marked RS_Local,
1303 // smaller ranges are marked RS_New.
1305 // These rules allow a 3 -> 2+3 split once, which we need. They also prevent
1306 // excessive splitting and infinite loops.
1308 bool ProgressRequired = getStage(VirtReg) >= RS_Local;
1310 // Best split candidate.
1311 unsigned BestBefore = NumGaps;
1312 unsigned BestAfter = 0;
1315 const float blockFreq = SpillPlacer->getBlockFrequency(BI.MBB->getNumber());
1316 SmallVector<float, 8> GapWeight;
1319 while (unsigned PhysReg = Order.next()) {
1320 // Keep track of the largest spill weight that would need to be evicted in
1321 // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1].
1322 calcGapWeights(PhysReg, GapWeight);
1324 // Try to find the best sequence of gaps to close.
1325 // The new spill weight must be larger than any gap interference.
1327 // We will split before Uses[SplitBefore] and after Uses[SplitAfter].
1328 unsigned SplitBefore = 0, SplitAfter = 1;
1330 // MaxGap should always be max(GapWeight[SplitBefore..SplitAfter-1]).
1331 // It is the spill weight that needs to be evicted.
1332 float MaxGap = GapWeight[0];
1335 // Live before/after split?
1336 const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
1337 const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut;
1339 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' '
1340 << Uses[SplitBefore] << '-' << Uses[SplitAfter]
1341 << " i=" << MaxGap);
1343 // Stop before the interval gets so big we wouldn't be making progress.
1344 if (!LiveBefore && !LiveAfter) {
1345 DEBUG(dbgs() << " all\n");
1348 // Should the interval be extended or shrunk?
1351 // How many gaps would the new range have?
1352 unsigned NewGaps = LiveBefore + SplitAfter - SplitBefore + LiveAfter;
1354 // Legally, without causing looping?
1355 bool Legal = !ProgressRequired || NewGaps < NumGaps;
1357 if (Legal && MaxGap < HUGE_VALF) {
1358 // Estimate the new spill weight. Each instruction reads or writes the
1359 // register. Conservatively assume there are no read-modify-write
1362 // Try to guess the size of the new interval.
1363 const float EstWeight = normalizeSpillWeight(blockFreq * (NewGaps + 1),
1364 Uses[SplitBefore].distance(Uses[SplitAfter]) +
1365 (LiveBefore + LiveAfter)*SlotIndex::InstrDist);
1366 // Would this split be possible to allocate?
1367 // Never allocate all gaps, we wouldn't be making progress.
1368 DEBUG(dbgs() << " w=" << EstWeight);
1369 if (EstWeight * Hysteresis >= MaxGap) {
1371 float Diff = EstWeight - MaxGap;
1372 if (Diff > BestDiff) {
1373 DEBUG(dbgs() << " (best)");
1374 BestDiff = Hysteresis * Diff;
1375 BestBefore = SplitBefore;
1376 BestAfter = SplitAfter;
1383 if (++SplitBefore < SplitAfter) {
1384 DEBUG(dbgs() << " shrink\n");
1385 // Recompute the max when necessary.
1386 if (GapWeight[SplitBefore - 1] >= MaxGap) {
1387 MaxGap = GapWeight[SplitBefore];
1388 for (unsigned i = SplitBefore + 1; i != SplitAfter; ++i)
1389 MaxGap = std::max(MaxGap, GapWeight[i]);
1396 // Try to extend the interval.
1397 if (SplitAfter >= NumGaps) {
1398 DEBUG(dbgs() << " end\n");
1402 DEBUG(dbgs() << " extend\n");
1403 MaxGap = std::max(MaxGap, GapWeight[SplitAfter++]);
1407 // Didn't find any candidates?
1408 if (BestBefore == NumGaps)
1411 DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore]
1412 << '-' << Uses[BestAfter] << ", " << BestDiff
1413 << ", " << (BestAfter - BestBefore + 1) << " instrs\n");
1415 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
1419 SlotIndex SegStart = SE->enterIntvBefore(Uses[BestBefore]);
1420 SlotIndex SegStop = SE->leaveIntvAfter(Uses[BestAfter]);
1421 SE->useIntv(SegStart, SegStop);
1422 SmallVector<unsigned, 8> IntvMap;
1423 SE->finish(&IntvMap);
1424 DebugVars->splitRegister(VirtReg.reg, LREdit.regs());
1426 // If the new range has the same number of instructions as before, mark it as
1427 // RS_Local so the next split will be forced to make progress. Otherwise,
1428 // leave the new intervals as RS_New so they can compete.
1429 bool LiveBefore = BestBefore != 0 || BI.LiveIn;
1430 bool LiveAfter = BestAfter != NumGaps || BI.LiveOut;
1431 unsigned NewGaps = LiveBefore + BestAfter - BestBefore + LiveAfter;
1432 if (NewGaps >= NumGaps) {
1433 DEBUG(dbgs() << "Tagging non-progress ranges: ");
1434 assert(!ProgressRequired && "Didn't make progress when it was required.");
1435 LRStage.resize(MRI->getNumVirtRegs());
1436 for (unsigned i = 0, e = IntvMap.size(); i != e; ++i)
1437 if (IntvMap[i] == 1) {
1438 LRStage[LREdit.get(i)->reg] = RS_Local;
1439 DEBUG(dbgs() << PrintReg(LREdit.get(i)->reg));
1441 DEBUG(dbgs() << '\n');
1448 //===----------------------------------------------------------------------===//
1449 // Live Range Splitting
1450 //===----------------------------------------------------------------------===//
1452 /// trySplit - Try to split VirtReg or one of its interferences, making it
1454 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
1455 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
1456 SmallVectorImpl<LiveInterval*>&NewVRegs) {
1457 // Local intervals are handled separately.
1458 if (LIS->intervalIsInOneMBB(VirtReg)) {
1459 NamedRegionTimer T("Local Splitting", TimerGroupName, TimePassesIsEnabled);
1460 SA->analyze(&VirtReg);
1461 return tryLocalSplit(VirtReg, Order, NewVRegs);
1464 NamedRegionTimer T("Global Splitting", TimerGroupName, TimePassesIsEnabled);
1466 // Don't iterate global splitting.
1467 // Move straight to spilling if this range was produced by a global split.
1468 if (getStage(VirtReg) >= RS_Global)
1471 SA->analyze(&VirtReg);
1473 // FIXME: SplitAnalysis may repair broken live ranges coming from the
1474 // coalescer. That may cause the range to become allocatable which means that
1475 // tryRegionSplit won't be making progress. This check should be replaced with
1476 // an assertion when the coalescer is fixed.
1477 if (SA->didRepairRange()) {
1478 // VirtReg has changed, so all cached queries are invalid.
1479 invalidateVirtRegs();
1480 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
1484 // First try to split around a region spanning multiple blocks.
1485 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1486 if (PhysReg || !NewVRegs.empty())
1489 // Then isolate blocks with multiple uses.
1490 SplitAnalysis::BlockPtrSet Blocks;
1491 if (SA->getMultiUseBlocks(Blocks)) {
1492 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
1494 SE->splitSingleBlocks(Blocks);
1495 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Global);
1497 MF->verify(this, "After splitting live range around basic blocks");
1500 // Don't assign any physregs.
1505 //===----------------------------------------------------------------------===//
1507 //===----------------------------------------------------------------------===//
1509 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
1510 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1511 // First try assigning a free register.
1512 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
1513 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
1516 LiveRangeStage Stage = getStage(VirtReg);
1517 DEBUG(dbgs() << StageName[Stage] << '\n');
1519 // Try to evict a less worthy live range, but only for ranges from the primary
1520 // queue. The RS_Second ranges already failed to do this, and they should not
1521 // get a second chance until they have been split.
1522 if (Stage != RS_Second)
1523 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs))
1526 assert(NewVRegs.empty() && "Cannot append to existing NewVRegs");
1528 // The first time we see a live range, don't try to split or spill.
1529 // Wait until the second time, when all smaller ranges have been allocated.
1530 // This gives a better picture of the interference to split around.
1531 if (Stage == RS_First) {
1532 LRStage[VirtReg.reg] = RS_Second;
1533 DEBUG(dbgs() << "wait for second round\n");
1534 NewVRegs.push_back(&VirtReg);
1538 // If we couldn't allocate a register from spilling, there is probably some
1539 // invalid inline assembly. The base class wil report it.
1540 if (Stage >= RS_Spill)
1543 // Try splitting VirtReg or interferences.
1544 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
1545 if (PhysReg || !NewVRegs.empty())
1548 // Finally spill VirtReg itself.
1549 NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
1550 LiveRangeEdit LRE(VirtReg, NewVRegs, this);
1551 spiller().spill(LRE);
1552 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Spill);
1555 MF->verify(this, "After spilling");
1557 // The live virtual register requesting allocation was spilled, so tell
1558 // the caller not to allocate anything during this round.
1562 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
1563 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
1564 << "********** Function: "
1565 << ((Value*)mf.getFunction())->getName() << '\n');
1569 MF->verify(this, "Before greedy register allocator");
1571 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
1572 Indexes = &getAnalysis<SlotIndexes>();
1573 DomTree = &getAnalysis<MachineDominatorTree>();
1574 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
1575 Loops = &getAnalysis<MachineLoopInfo>();
1576 LoopRanges = &getAnalysis<MachineLoopRanges>();
1577 Bundles = &getAnalysis<EdgeBundles>();
1578 SpillPlacer = &getAnalysis<SpillPlacement>();
1579 DebugVars = &getAnalysis<LiveDebugVariables>();
1581 SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops));
1582 SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree));
1584 LRStage.resize(MRI->getNumVirtRegs());
1585 IntfCache.init(MF, &PhysReg2LiveUnion[0], Indexes, TRI);
1589 LIS->addKillFlags();
1593 NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled);
1594 VRM->rewrite(Indexes);
1597 // Write out new DBG_VALUE instructions.
1598 DebugVars->emitDebugValues(VRM);
1600 // The pass output is in VirtRegMap. Release all the transient data.