1 //===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RAGreedy function pass for register allocation in
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "AllocationOrder.h"
17 #include "InterferenceCache.h"
18 #include "LiveRangeEdit.h"
19 #include "RegAllocBase.h"
21 #include "SpillPlacement.h"
23 #include "VirtRegMap.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/Function.h"
27 #include "llvm/PassAnalysisSupport.h"
28 #include "llvm/CodeGen/CalcSpillWeights.h"
29 #include "llvm/CodeGen/EdgeBundles.h"
30 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
31 #include "llvm/CodeGen/LiveStackAnalysis.h"
32 #include "llvm/CodeGen/MachineDominators.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineLoopInfo.h"
35 #include "llvm/CodeGen/MachineLoopRanges.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/CodeGen/RegAllocRegistry.h"
39 #include "llvm/CodeGen/RegisterCoalescer.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/raw_ostream.h"
44 #include "llvm/Support/Timer.h"
50 STATISTIC(NumGlobalSplits, "Number of split global live ranges");
51 STATISTIC(NumLocalSplits, "Number of split local live ranges");
52 STATISTIC(NumEvicted, "Number of interferences evicted");
54 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
55 createGreedyRegisterAllocator);
58 class RAGreedy : public MachineFunctionPass,
60 private LiveRangeEdit::Delegate {
64 BitVector ReservedRegs;
69 MachineDominatorTree *DomTree;
70 MachineLoopInfo *Loops;
71 MachineLoopRanges *LoopRanges;
73 SpillPlacement *SpillPlacer;
76 std::auto_ptr<Spiller> SpillerInstance;
77 std::priority_queue<std::pair<unsigned, unsigned> > Queue;
79 // Live ranges pass through a number of stages as we try to allocate them.
80 // Some of the stages may also create new live ranges:
82 // - Region splitting.
83 // - Per-block splitting.
87 // Ranges produced by one of the stages skip the previous stages when they are
88 // dequeued. This improves performance because we can skip interference checks
89 // that are unlikely to give any results. It also guarantees that the live
90 // range splitting algorithm terminates, something that is otherwise hard to
93 RS_New, ///< Never seen before.
94 RS_First, ///< First time in the queue.
95 RS_Second, ///< Second time in the queue.
96 RS_Region, ///< Produced by region splitting.
97 RS_Block, ///< Produced by per-block splitting.
98 RS_Local, ///< Produced by local splitting.
99 RS_Spill ///< Produced by spilling.
102 IndexedMap<unsigned char, VirtReg2IndexFunctor> LRStage;
104 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
105 return LiveRangeStage(LRStage[VirtReg.reg]);
108 template<typename Iterator>
109 void setStage(Iterator Begin, Iterator End, LiveRangeStage NewStage) {
110 LRStage.resize(MRI->getNumVirtRegs());
111 for (;Begin != End; ++Begin) {
112 unsigned Reg = (*Begin)->reg;
113 if (LRStage[Reg] == RS_New)
114 LRStage[Reg] = NewStage;
119 std::auto_ptr<SplitAnalysis> SA;
120 std::auto_ptr<SplitEditor> SE;
122 /// All basic blocks where the current register is live.
123 SmallVector<SpillPlacement::BlockConstraint, 8> SplitConstraints;
125 typedef std::pair<SlotIndex, SlotIndex> IndexPair;
127 /// Global live range splitting candidate info.
128 struct GlobalSplitCandidate {
130 SmallVector<IndexPair, 8> Interference;
131 BitVector LiveBundles;
134 /// Candidate info for for each PhysReg in AllocationOrder.
135 /// This vector never shrinks, but grows to the size of the largest register
137 SmallVector<GlobalSplitCandidate, 32> GlobalCand;
139 /// For every instruction in SA->UseSlots, store the previous non-copy
141 SmallVector<SlotIndex, 8> PrevSlot;
146 /// Return the pass name.
147 virtual const char* getPassName() const {
148 return "Greedy Register Allocator";
151 /// RAGreedy analysis usage.
152 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
153 virtual void releaseMemory();
154 virtual Spiller &spiller() { return *SpillerInstance; }
155 virtual void enqueue(LiveInterval *LI);
156 virtual LiveInterval *dequeue();
157 virtual unsigned selectOrSplit(LiveInterval&,
158 SmallVectorImpl<LiveInterval*>&);
160 /// Perform register allocation.
161 virtual bool runOnMachineFunction(MachineFunction &mf);
166 void LRE_WillEraseInstruction(MachineInstr*);
167 bool LRE_CanEraseVirtReg(unsigned);
168 void LRE_WillShrinkVirtReg(unsigned);
169 void LRE_DidCloneVirtReg(unsigned, unsigned);
171 void mapGlobalInterference(unsigned, SmallVectorImpl<IndexPair>&);
172 float calcSplitConstraints(const SmallVectorImpl<IndexPair>&);
174 float calcGlobalSplitCost(const BitVector&);
175 void splitAroundRegion(LiveInterval&, unsigned, const BitVector&,
176 SmallVectorImpl<LiveInterval*>&);
177 void calcGapWeights(unsigned, SmallVectorImpl<float>&);
178 SlotIndex getPrevMappedIndex(const MachineInstr*);
179 void calcPrevSlots();
180 unsigned nextSplitPoint(unsigned);
181 bool canEvictInterference(LiveInterval&, unsigned, float&);
183 unsigned tryEvict(LiveInterval&, AllocationOrder&,
184 SmallVectorImpl<LiveInterval*>&);
185 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
186 SmallVectorImpl<LiveInterval*>&);
187 unsigned tryLocalSplit(LiveInterval&, AllocationOrder&,
188 SmallVectorImpl<LiveInterval*>&);
189 unsigned trySplit(LiveInterval&, AllocationOrder&,
190 SmallVectorImpl<LiveInterval*>&);
192 } // end anonymous namespace
194 char RAGreedy::ID = 0;
196 FunctionPass* llvm::createGreedyRegisterAllocator() {
197 return new RAGreedy();
200 RAGreedy::RAGreedy(): MachineFunctionPass(ID), LRStage(RS_New) {
201 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
202 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
203 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
204 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
205 initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
206 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
207 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
208 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
209 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
210 initializeMachineLoopRangesPass(*PassRegistry::getPassRegistry());
211 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
212 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
213 initializeSpillPlacementPass(*PassRegistry::getPassRegistry());
216 void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
217 AU.setPreservesCFG();
218 AU.addRequired<AliasAnalysis>();
219 AU.addPreserved<AliasAnalysis>();
220 AU.addRequired<LiveIntervals>();
221 AU.addRequired<SlotIndexes>();
222 AU.addPreserved<SlotIndexes>();
224 AU.addRequiredID(StrongPHIEliminationID);
225 AU.addRequiredTransitive<RegisterCoalescer>();
226 AU.addRequired<CalculateSpillWeights>();
227 AU.addRequired<LiveStacks>();
228 AU.addPreserved<LiveStacks>();
229 AU.addRequired<MachineDominatorTree>();
230 AU.addPreserved<MachineDominatorTree>();
231 AU.addRequired<MachineLoopInfo>();
232 AU.addPreserved<MachineLoopInfo>();
233 AU.addRequired<MachineLoopRanges>();
234 AU.addPreserved<MachineLoopRanges>();
235 AU.addRequired<VirtRegMap>();
236 AU.addPreserved<VirtRegMap>();
237 AU.addRequired<EdgeBundles>();
238 AU.addRequired<SpillPlacement>();
239 MachineFunctionPass::getAnalysisUsage(AU);
243 //===----------------------------------------------------------------------===//
244 // LiveRangeEdit delegate methods
245 //===----------------------------------------------------------------------===//
247 void RAGreedy::LRE_WillEraseInstruction(MachineInstr *MI) {
248 // LRE itself will remove from SlotIndexes and parent basic block.
249 VRM->RemoveMachineInstrFromMaps(MI);
252 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
253 if (unsigned PhysReg = VRM->getPhys(VirtReg)) {
254 unassign(LIS->getInterval(VirtReg), PhysReg);
257 // Unassigned virtreg is probably in the priority queue.
258 // RegAllocBase will erase it after dequeueing.
262 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) {
263 unsigned PhysReg = VRM->getPhys(VirtReg);
267 // Register is assigned, put it back on the queue for reassignment.
268 LiveInterval &LI = LIS->getInterval(VirtReg);
269 unassign(LI, PhysReg);
273 void RAGreedy::LRE_DidCloneVirtReg(unsigned New, unsigned Old) {
274 // LRE may clone a virtual register because dead code elimination causes it to
275 // be split into connected components. Ensure that the new register gets the
276 // same stage as the parent.
278 LRStage[New] = LRStage[Old];
281 void RAGreedy::releaseMemory() {
282 SpillerInstance.reset(0);
284 RegAllocBase::releaseMemory();
287 void RAGreedy::enqueue(LiveInterval *LI) {
288 // Prioritize live ranges by size, assigning larger ranges first.
289 // The queue holds (size, reg) pairs.
290 const unsigned Size = LI->getSize();
291 const unsigned Reg = LI->reg;
292 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
293 "Can only enqueue virtual registers");
297 if (LRStage[Reg] == RS_New)
298 LRStage[Reg] = RS_First;
300 if (LRStage[Reg] == RS_Second)
301 // Unsplit ranges that couldn't be allocated immediately are deferred until
302 // everything else has been allocated. Long ranges are allocated last so
303 // they are split against realistic interference.
304 Prio = (1u << 31) - Size;
306 // Everything else is allocated in long->short order. Long ranges that don't
307 // fit should be spilled ASAP so they don't create interference.
308 Prio = (1u << 31) + Size;
310 // Boost ranges that have a physical register hint.
311 if (TargetRegisterInfo::isPhysicalRegister(VRM->getRegAllocPref(Reg)))
315 Queue.push(std::make_pair(Prio, Reg));
318 LiveInterval *RAGreedy::dequeue() {
321 LiveInterval *LI = &LIS->getInterval(Queue.top().second);
326 //===----------------------------------------------------------------------===//
327 // Interference eviction
328 //===----------------------------------------------------------------------===//
330 /// canEvict - Return true if all interferences between VirtReg and PhysReg can
331 /// be evicted. Set maxWeight to the maximal spill weight of an interference.
332 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
335 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
336 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
337 // If there is 10 or more interferences, chances are one is smaller.
338 if (Q.collectInterferingVRegs(10) >= 10)
341 // Check if any interfering live range is heavier than VirtReg.
342 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
343 LiveInterval *Intf = Q.interferingVRegs()[i];
344 if (TargetRegisterInfo::isPhysicalRegister(Intf->reg))
346 if (Intf->weight >= VirtReg.weight)
348 Weight = std::max(Weight, Intf->weight);
355 /// tryEvict - Try to evict all interferences for a physreg.
356 /// @param VirtReg Currently unassigned virtual register.
357 /// @param Order Physregs to try.
358 /// @return Physreg to assign VirtReg, or 0.
359 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
360 AllocationOrder &Order,
361 SmallVectorImpl<LiveInterval*> &NewVRegs){
362 NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled);
364 // Keep track of the lightest single interference seen so far.
365 float BestWeight = 0;
366 unsigned BestPhys = 0;
369 while (unsigned PhysReg = Order.next()) {
371 if (!canEvictInterference(VirtReg, PhysReg, Weight))
374 // This is an eviction candidate.
375 DEBUG(dbgs() << "max " << PrintReg(PhysReg, TRI) << " interference = "
377 if (BestPhys && Weight >= BestWeight)
383 // Stop if the hint can be used.
384 if (Order.isHint(PhysReg))
391 DEBUG(dbgs() << "evicting " << PrintReg(BestPhys, TRI) << " interference\n");
392 for (const unsigned *AliasI = TRI->getOverlaps(BestPhys); *AliasI; ++AliasI) {
393 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
394 assert(Q.seenAllInterferences() && "Didn't check all interfererences.");
395 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
396 LiveInterval *Intf = Q.interferingVRegs()[i];
397 unassign(*Intf, VRM->getPhys(Intf->reg));
399 NewVRegs.push_back(Intf);
406 //===----------------------------------------------------------------------===//
408 //===----------------------------------------------------------------------===//
410 /// mapGlobalInterference - Compute a map of the interference from PhysReg and
411 /// its aliases in each block in SA->LiveBlocks.
412 /// If LiveBlocks[i] is live-in, Ranges[i].first is the first interference.
413 /// If LiveBlocks[i] is live-out, Ranges[i].second is the last interference.
414 void RAGreedy::mapGlobalInterference(unsigned PhysReg,
415 SmallVectorImpl<IndexPair> &Ranges) {
416 Ranges.assign(SA->LiveBlocks.size(), IndexPair());
417 LiveInterval &VirtReg = const_cast<LiveInterval&>(SA->getParent());
418 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
419 if (!query(VirtReg, *AI).checkInterference())
421 LiveIntervalUnion::SegmentIter IntI =
422 PhysReg2LiveUnion[*AI].find(VirtReg.beginIndex());
425 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
426 const SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
427 IndexPair &IP = Ranges[i];
429 // Skip interference-free blocks.
430 if (IntI.start() >= BI.Stop)
433 // First interference in block.
435 IntI.advanceTo(BI.Start);
438 if (IntI.start() >= BI.Stop)
440 if (!IP.first.isValid() || IntI.start() < IP.first)
441 IP.first = IntI.start();
444 // Last interference in block.
446 IntI.advanceTo(BI.Stop);
447 if (!IntI.valid() || IntI.start() >= BI.Stop)
449 if (IntI.stop() <= BI.Start)
451 if (!IP.second.isValid() || IntI.stop() > IP.second)
452 IP.second = IntI.stop();
458 /// calcSplitConstraints - Fill out the SplitConstraints vector based on the
459 /// interference pattern in Intf. Return the static cost of this split,
460 /// assuming that all preferences in SplitConstraints are met.
461 float RAGreedy::calcSplitConstraints(const SmallVectorImpl<IndexPair> &Intf) {
462 // Reset interference dependent info.
463 SplitConstraints.resize(SA->LiveBlocks.size());
464 float StaticCost = 0;
465 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
466 SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
467 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
468 IndexPair IP = Intf[i];
470 BC.Number = BI.MBB->getNumber();
471 BC.Entry = (BI.Uses && BI.LiveIn) ?
472 SpillPlacement::PrefReg : SpillPlacement::DontCare;
473 BC.Exit = (BI.Uses && BI.LiveOut) ?
474 SpillPlacement::PrefReg : SpillPlacement::DontCare;
476 // Number of spill code instructions to insert.
479 // Interference for the live-in value.
480 if (IP.first.isValid()) {
481 if (IP.first <= BI.Start)
482 BC.Entry = SpillPlacement::MustSpill, Ins += BI.Uses;
484 BC.Entry = SpillPlacement::PrefSpill;
485 else if (IP.first < BI.FirstUse)
486 BC.Entry = SpillPlacement::PrefSpill, ++Ins;
487 else if (IP.first < (BI.LiveThrough ? BI.LastUse : BI.Kill))
491 // Interference for the live-out value.
492 if (IP.second.isValid()) {
493 if (IP.second >= BI.LastSplitPoint)
494 BC.Exit = SpillPlacement::MustSpill, Ins += BI.Uses;
496 BC.Exit = SpillPlacement::PrefSpill;
497 else if (IP.second > BI.LastUse)
498 BC.Exit = SpillPlacement::PrefSpill, ++Ins;
499 else if (IP.second > (BI.LiveThrough ? BI.FirstUse : BI.Def))
503 // Accumulate the total frequency of inserted spill code.
505 StaticCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
511 /// calcGlobalSplitCost - Return the global split cost of following the split
512 /// pattern in LiveBundles. This cost should be added to the local cost of the
513 /// interference pattern in SplitConstraints.
515 float RAGreedy::calcGlobalSplitCost(const BitVector &LiveBundles) {
516 float GlobalCost = 0;
517 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
518 SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
519 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
520 bool RegIn = LiveBundles[Bundles->getBundle(BC.Number, 0)];
521 bool RegOut = LiveBundles[Bundles->getBundle(BC.Number, 1)];
525 Ins += RegIn != RegOut;
528 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg);
530 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg);
533 GlobalCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
538 /// splitAroundRegion - Split VirtReg around the region determined by
539 /// LiveBundles. Make an effort to avoid interference from PhysReg.
541 /// The 'register' interval is going to contain as many uses as possible while
542 /// avoiding interference. The 'stack' interval is the complement constructed by
543 /// SplitEditor. It will contain the rest.
545 void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, unsigned PhysReg,
546 const BitVector &LiveBundles,
547 SmallVectorImpl<LiveInterval*> &NewVRegs) {
549 dbgs() << "Splitting around region for " << PrintReg(PhysReg, TRI)
551 for (int i = LiveBundles.find_first(); i>=0; i = LiveBundles.find_next(i))
552 dbgs() << " EB#" << i;
556 // First compute interference ranges in the live blocks.
557 SmallVector<IndexPair, 8> InterferenceRanges;
558 mapGlobalInterference(PhysReg, InterferenceRanges);
560 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
563 // Create the main cross-block interval.
566 // First add all defs that are live out of a block.
567 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
568 SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
569 bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)];
570 bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)];
572 // Should the register be live out?
573 if (!BI.LiveOut || !RegOut)
576 IndexPair &IP = InterferenceRanges[i];
577 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " -> EB#"
578 << Bundles->getBundle(BI.MBB->getNumber(), 1)
579 << " [" << BI.Start << ';' << BI.LastSplitPoint << '-'
580 << BI.Stop << ") intf [" << IP.first << ';' << IP.second
583 // The interference interval should either be invalid or overlap MBB.
584 assert((!IP.first.isValid() || IP.first < BI.Stop) && "Bad interference");
585 assert((!IP.second.isValid() || IP.second > BI.Start)
586 && "Bad interference");
588 // Check interference leaving the block.
589 if (!IP.second.isValid()) {
590 // Block is interference-free.
591 DEBUG(dbgs() << ", no interference");
593 assert(BI.LiveThrough && "No uses, but not live through block?");
594 // Block is live-through without interference.
595 DEBUG(dbgs() << ", no uses"
596 << (RegIn ? ", live-through.\n" : ", stack in.\n"));
598 SE->enterIntvAtEnd(*BI.MBB);
601 if (!BI.LiveThrough) {
602 DEBUG(dbgs() << ", not live-through.\n");
603 SE->useIntv(SE->enterIntvBefore(BI.Def), BI.Stop);
607 // Block is live-through, but entry bundle is on the stack.
608 // Reload just before the first use.
609 DEBUG(dbgs() << ", not live-in, enter before first use.\n");
610 SE->useIntv(SE->enterIntvBefore(BI.FirstUse), BI.Stop);
613 DEBUG(dbgs() << ", live-through.\n");
617 // Block has interference.
618 DEBUG(dbgs() << ", interference to " << IP.second);
620 if (!BI.LiveThrough && IP.second <= BI.Def) {
621 // The interference doesn't reach the outgoing segment.
622 DEBUG(dbgs() << " doesn't affect def from " << BI.Def << '\n');
623 SE->useIntv(BI.Def, BI.Stop);
629 // No uses in block, avoid interference by reloading as late as possible.
630 DEBUG(dbgs() << ", no uses.\n");
631 SlotIndex SegStart = SE->enterIntvAtEnd(*BI.MBB);
632 assert(SegStart >= IP.second && "Couldn't avoid interference");
636 if (IP.second.getBoundaryIndex() < BI.LastUse) {
637 // There are interference-free uses at the end of the block.
638 // Find the first use that can get the live-out register.
639 SmallVectorImpl<SlotIndex>::const_iterator UI =
640 std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(),
641 IP.second.getBoundaryIndex());
642 assert(UI != SA->UseSlots.end() && "Couldn't find last use");
644 assert(Use <= BI.LastUse && "Couldn't find last use");
645 // Only attempt a split befroe the last split point.
646 if (Use.getBaseIndex() <= BI.LastSplitPoint) {
647 DEBUG(dbgs() << ", free use at " << Use << ".\n");
648 SlotIndex SegStart = SE->enterIntvBefore(Use);
649 assert(SegStart >= IP.second && "Couldn't avoid interference");
650 assert(SegStart < BI.LastSplitPoint && "Impossible split point");
651 SE->useIntv(SegStart, BI.Stop);
656 // Interference is after the last use.
657 DEBUG(dbgs() << " after last use.\n");
658 SlotIndex SegStart = SE->enterIntvAtEnd(*BI.MBB);
659 assert(SegStart >= IP.second && "Couldn't avoid interference");
662 // Now all defs leading to live bundles are handled, do everything else.
663 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
664 SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
665 bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)];
666 bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)];
668 // Is the register live-in?
669 if (!BI.LiveIn || !RegIn)
672 // We have an incoming register. Check for interference.
673 IndexPair &IP = InterferenceRanges[i];
675 DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0)
676 << " -> BB#" << BI.MBB->getNumber() << " [" << BI.Start << ';'
677 << BI.LastSplitPoint << '-' << BI.Stop << ')');
679 // Check interference entering the block.
680 if (!IP.first.isValid()) {
681 // Block is interference-free.
682 DEBUG(dbgs() << ", no interference");
684 assert(BI.LiveThrough && "No uses, but not live through block?");
685 // Block is live-through without interference.
687 DEBUG(dbgs() << ", no uses, live-through.\n");
688 SE->useIntv(BI.Start, BI.Stop);
690 DEBUG(dbgs() << ", no uses, stack-out.\n");
691 SE->leaveIntvAtTop(*BI.MBB);
695 if (!BI.LiveThrough) {
696 DEBUG(dbgs() << ", killed in block.\n");
697 SE->useIntv(BI.Start, SE->leaveIntvAfter(BI.Kill));
701 // Block is live-through, but exit bundle is on the stack.
702 // Spill immediately after the last use.
703 if (BI.LastUse < BI.LastSplitPoint) {
704 DEBUG(dbgs() << ", uses, stack-out.\n");
705 SE->useIntv(BI.Start, SE->leaveIntvAfter(BI.LastUse));
708 // The last use is after the last split point, it is probably an
710 DEBUG(dbgs() << ", uses at " << BI.LastUse << " after split point "
711 << BI.LastSplitPoint << ", stack-out.\n");
712 SlotIndex SegEnd = SE->leaveIntvBefore(BI.LastSplitPoint);
713 SE->useIntv(BI.Start, SegEnd);
714 // Run a double interval from the split to the last use.
715 // This makes it possible to spill the complement without affecting the
717 SE->overlapIntv(SegEnd, BI.LastUse);
720 // Register is live-through.
721 DEBUG(dbgs() << ", uses, live-through.\n");
722 SE->useIntv(BI.Start, BI.Stop);
726 // Block has interference.
727 DEBUG(dbgs() << ", interference from " << IP.first);
729 if (!BI.LiveThrough && IP.first >= BI.Kill) {
730 // The interference doesn't reach the outgoing segment.
731 DEBUG(dbgs() << " doesn't affect kill at " << BI.Kill << '\n');
732 SE->useIntv(BI.Start, BI.Kill);
737 // No uses in block, avoid interference by spilling as soon as possible.
738 DEBUG(dbgs() << ", no uses.\n");
739 SlotIndex SegEnd = SE->leaveIntvAtTop(*BI.MBB);
740 assert(SegEnd <= IP.first && "Couldn't avoid interference");
743 if (IP.first.getBaseIndex() > BI.FirstUse) {
744 // There are interference-free uses at the beginning of the block.
745 // Find the last use that can get the register.
746 SmallVectorImpl<SlotIndex>::const_iterator UI =
747 std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(),
748 IP.first.getBaseIndex());
749 assert(UI != SA->UseSlots.begin() && "Couldn't find first use");
750 SlotIndex Use = (--UI)->getBoundaryIndex();
751 DEBUG(dbgs() << ", free use at " << *UI << ".\n");
752 SlotIndex SegEnd = SE->leaveIntvAfter(Use);
753 assert(SegEnd <= IP.first && "Couldn't avoid interference");
754 SE->useIntv(BI.Start, SegEnd);
758 // Interference is before the first use.
759 DEBUG(dbgs() << " before first use.\n");
760 SlotIndex SegEnd = SE->leaveIntvAtTop(*BI.MBB);
761 assert(SegEnd <= IP.first && "Couldn't avoid interference");
766 // FIXME: Should we be more aggressive about splitting the stack region into
767 // per-block segments? The current approach allows the stack region to
768 // separate into connected components. Some components may be allocatable.
773 MF->verify(this, "After splitting live range around region");
776 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
777 SmallVectorImpl<LiveInterval*> &NewVRegs) {
778 BitVector LiveBundles, BestBundles;
780 unsigned BestReg = 0;
783 for (unsigned Cand = 0; unsigned PhysReg = Order.next(); ++Cand) {
784 if (GlobalCand.size() <= Cand)
785 GlobalCand.resize(Cand+1);
786 GlobalCand[Cand].PhysReg = PhysReg;
788 mapGlobalInterference(PhysReg, GlobalCand[Cand].Interference);
789 float Cost = calcSplitConstraints(GlobalCand[Cand].Interference);
790 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = " << Cost);
791 if (BestReg && Cost >= BestCost) {
792 DEBUG(dbgs() << " higher.\n");
796 SpillPlacer->placeSpills(SplitConstraints, LiveBundles);
797 // No live bundles, defer to splitSingleBlocks().
798 if (!LiveBundles.any()) {
799 DEBUG(dbgs() << " no bundles.\n");
803 Cost += calcGlobalSplitCost(LiveBundles);
805 dbgs() << ", total = " << Cost << " with bundles";
806 for (int i = LiveBundles.find_first(); i>=0; i = LiveBundles.find_next(i))
807 dbgs() << " EB#" << i;
810 if (!BestReg || Cost < BestCost) {
812 BestCost = 0.98f * Cost; // Prevent rounding effects.
813 BestBundles.swap(LiveBundles);
820 splitAroundRegion(VirtReg, BestReg, BestBundles, NewVRegs);
821 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Region);
826 //===----------------------------------------------------------------------===//
828 //===----------------------------------------------------------------------===//
831 /// calcGapWeights - Compute the maximum spill weight that needs to be evicted
832 /// in order to use PhysReg between two entries in SA->UseSlots.
834 /// GapWeight[i] represents the gap between UseSlots[i] and UseSlots[i+1].
836 void RAGreedy::calcGapWeights(unsigned PhysReg,
837 SmallVectorImpl<float> &GapWeight) {
838 assert(SA->LiveBlocks.size() == 1 && "Not a local interval");
839 const SplitAnalysis::BlockInfo &BI = SA->LiveBlocks.front();
840 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
841 const unsigned NumGaps = Uses.size()-1;
843 // Start and end points for the interference check.
844 SlotIndex StartIdx = BI.LiveIn ? BI.FirstUse.getBaseIndex() : BI.FirstUse;
845 SlotIndex StopIdx = BI.LiveOut ? BI.LastUse.getBoundaryIndex() : BI.LastUse;
847 GapWeight.assign(NumGaps, 0.0f);
849 // Add interference from each overlapping register.
850 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
851 if (!query(const_cast<LiveInterval&>(SA->getParent()), *AI)
852 .checkInterference())
855 // We know that VirtReg is a continuous interval from FirstUse to LastUse,
856 // so we don't need InterferenceQuery.
858 // Interference that overlaps an instruction is counted in both gaps
859 // surrounding the instruction. The exception is interference before
860 // StartIdx and after StopIdx.
862 LiveIntervalUnion::SegmentIter IntI = PhysReg2LiveUnion[*AI].find(StartIdx);
863 for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) {
864 // Skip the gaps before IntI.
865 while (Uses[Gap+1].getBoundaryIndex() < IntI.start())
866 if (++Gap == NumGaps)
871 // Update the gaps covered by IntI.
872 const float weight = IntI.value()->weight;
873 for (; Gap != NumGaps; ++Gap) {
874 GapWeight[Gap] = std::max(GapWeight[Gap], weight);
875 if (Uses[Gap+1].getBaseIndex() >= IntI.stop())
884 /// getPrevMappedIndex - Return the slot index of the last non-copy instruction
885 /// before MI that has a slot index. If MI is the first mapped instruction in
886 /// its block, return the block start index instead.
888 SlotIndex RAGreedy::getPrevMappedIndex(const MachineInstr *MI) {
889 assert(MI && "Missing MachineInstr");
890 const MachineBasicBlock *MBB = MI->getParent();
891 MachineBasicBlock::const_iterator B = MBB->begin(), I = MI;
893 if (!(--I)->isDebugValue() && !I->isCopy())
894 return Indexes->getInstructionIndex(I);
895 return Indexes->getMBBStartIdx(MBB);
898 /// calcPrevSlots - Fill in the PrevSlot array with the index of the previous
899 /// real non-copy instruction for each instruction in SA->UseSlots.
901 void RAGreedy::calcPrevSlots() {
902 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
904 PrevSlot.reserve(Uses.size());
905 for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
906 const MachineInstr *MI = Indexes->getInstructionFromIndex(Uses[i]);
907 PrevSlot.push_back(getPrevMappedIndex(MI).getDefIndex());
911 /// nextSplitPoint - Find the next index into SA->UseSlots > i such that it may
912 /// be beneficial to split before UseSlots[i].
914 /// 0 is always a valid split point
915 unsigned RAGreedy::nextSplitPoint(unsigned i) {
916 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
917 const unsigned Size = Uses.size();
918 assert(i != Size && "No split points after the end");
919 // Allow split before i when Uses[i] is not adjacent to the previous use.
920 while (++i != Size && PrevSlot[i].getBaseIndex() <= Uses[i-1].getBaseIndex())
925 /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
928 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
929 SmallVectorImpl<LiveInterval*> &NewVRegs) {
930 assert(SA->LiveBlocks.size() == 1 && "Not a local interval");
931 const SplitAnalysis::BlockInfo &BI = SA->LiveBlocks.front();
933 // Note that it is possible to have an interval that is live-in or live-out
934 // while only covering a single block - A phi-def can use undef values from
935 // predecessors, and the block could be a single-block loop.
936 // We don't bother doing anything clever about such a case, we simply assume
937 // that the interval is continuous from FirstUse to LastUse. We should make
938 // sure that we don't do anything illegal to such an interval, though.
940 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
941 if (Uses.size() <= 2)
943 const unsigned NumGaps = Uses.size()-1;
946 dbgs() << "tryLocalSplit: ";
947 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
948 dbgs() << ' ' << SA->UseSlots[i];
952 // For every use, find the previous mapped non-copy instruction.
953 // We use this to detect valid split points, and to estimate new interval
957 unsigned BestBefore = NumGaps;
958 unsigned BestAfter = 0;
961 const float blockFreq = SpillPlacer->getBlockFrequency(BI.MBB->getNumber());
962 SmallVector<float, 8> GapWeight;
965 while (unsigned PhysReg = Order.next()) {
966 // Keep track of the largest spill weight that would need to be evicted in
967 // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1].
968 calcGapWeights(PhysReg, GapWeight);
970 // Try to find the best sequence of gaps to close.
971 // The new spill weight must be larger than any gap interference.
973 // We will split before Uses[SplitBefore] and after Uses[SplitAfter].
974 unsigned SplitBefore = 0, SplitAfter = nextSplitPoint(1) - 1;
976 // MaxGap should always be max(GapWeight[SplitBefore..SplitAfter-1]).
977 // It is the spill weight that needs to be evicted.
978 float MaxGap = GapWeight[0];
979 for (unsigned i = 1; i != SplitAfter; ++i)
980 MaxGap = std::max(MaxGap, GapWeight[i]);
983 // Live before/after split?
984 const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
985 const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut;
987 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' '
988 << Uses[SplitBefore] << '-' << Uses[SplitAfter]
991 // Stop before the interval gets so big we wouldn't be making progress.
992 if (!LiveBefore && !LiveAfter) {
993 DEBUG(dbgs() << " all\n");
996 // Should the interval be extended or shrunk?
998 if (MaxGap < HUGE_VALF) {
999 // Estimate the new spill weight.
1001 // Each instruction reads and writes the register, except the first
1002 // instr doesn't read when !FirstLive, and the last instr doesn't write
1005 // We will be inserting copies before and after, so the total number of
1006 // reads and writes is 2 * EstUses.
1008 const unsigned EstUses = 2*(SplitAfter - SplitBefore) +
1009 2*(LiveBefore + LiveAfter);
1011 // Try to guess the size of the new interval. This should be trivial,
1012 // but the slot index of an inserted copy can be a lot smaller than the
1013 // instruction it is inserted before if there are many dead indexes
1016 // We measure the distance from the instruction before SplitBefore to
1017 // get a conservative estimate.
1019 // The final distance can still be different if inserting copies
1020 // triggers a slot index renumbering.
1022 const float EstWeight = normalizeSpillWeight(blockFreq * EstUses,
1023 PrevSlot[SplitBefore].distance(Uses[SplitAfter]));
1024 // Would this split be possible to allocate?
1025 // Never allocate all gaps, we wouldn't be making progress.
1026 float Diff = EstWeight - MaxGap;
1027 DEBUG(dbgs() << " w=" << EstWeight << " d=" << Diff);
1030 if (Diff > BestDiff) {
1031 DEBUG(dbgs() << " (best)");
1033 BestBefore = SplitBefore;
1034 BestAfter = SplitAfter;
1041 SplitBefore = nextSplitPoint(SplitBefore);
1042 if (SplitBefore < SplitAfter) {
1043 DEBUG(dbgs() << " shrink\n");
1044 // Recompute the max when necessary.
1045 if (GapWeight[SplitBefore - 1] >= MaxGap) {
1046 MaxGap = GapWeight[SplitBefore];
1047 for (unsigned i = SplitBefore + 1; i != SplitAfter; ++i)
1048 MaxGap = std::max(MaxGap, GapWeight[i]);
1055 // Try to extend the interval.
1056 if (SplitAfter >= NumGaps) {
1057 DEBUG(dbgs() << " end\n");
1061 DEBUG(dbgs() << " extend\n");
1062 for (unsigned e = nextSplitPoint(SplitAfter + 1) - 1;
1063 SplitAfter != e; ++SplitAfter)
1064 MaxGap = std::max(MaxGap, GapWeight[SplitAfter]);
1069 // Didn't find any candidates?
1070 if (BestBefore == NumGaps)
1073 DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore]
1074 << '-' << Uses[BestAfter] << ", " << BestDiff
1075 << ", " << (BestAfter - BestBefore + 1) << " instrs\n");
1077 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
1081 SlotIndex SegStart = SE->enterIntvBefore(Uses[BestBefore]);
1082 SlotIndex SegStop = SE->leaveIntvAfter(Uses[BestAfter]);
1083 SE->useIntv(SegStart, SegStop);
1086 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Local);
1092 //===----------------------------------------------------------------------===//
1093 // Live Range Splitting
1094 //===----------------------------------------------------------------------===//
1096 /// trySplit - Try to split VirtReg or one of its interferences, making it
1098 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
1099 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
1100 SmallVectorImpl<LiveInterval*>&NewVRegs) {
1101 // Local intervals are handled separately.
1102 if (LIS->intervalIsInOneMBB(VirtReg)) {
1103 NamedRegionTimer T("Local Splitting", TimerGroupName, TimePassesIsEnabled);
1104 SA->analyze(&VirtReg);
1105 return tryLocalSplit(VirtReg, Order, NewVRegs);
1108 NamedRegionTimer T("Global Splitting", TimerGroupName, TimePassesIsEnabled);
1110 // Don't iterate global splitting.
1111 // Move straight to spilling if this range was produced by a global split.
1112 LiveRangeStage Stage = getStage(VirtReg);
1113 if (Stage >= RS_Block)
1116 SA->analyze(&VirtReg);
1118 // First try to split around a region spanning multiple blocks.
1119 if (Stage < RS_Region) {
1120 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1121 if (PhysReg || !NewVRegs.empty())
1125 // Then isolate blocks with multiple uses.
1126 if (Stage < RS_Block) {
1127 SplitAnalysis::BlockPtrSet Blocks;
1128 if (SA->getMultiUseBlocks(Blocks)) {
1129 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
1131 SE->splitSingleBlocks(Blocks);
1132 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Block);
1134 MF->verify(this, "After splitting live range around basic blocks");
1138 // Don't assign any physregs.
1143 //===----------------------------------------------------------------------===//
1145 //===----------------------------------------------------------------------===//
1147 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
1148 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1149 // First try assigning a free register.
1150 AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);
1151 while (unsigned PhysReg = Order.next()) {
1152 if (!checkPhysRegInterference(VirtReg, PhysReg))
1156 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs))
1159 assert(NewVRegs.empty() && "Cannot append to existing NewVRegs");
1161 // The first time we see a live range, don't try to split or spill.
1162 // Wait until the second time, when all smaller ranges have been allocated.
1163 // This gives a better picture of the interference to split around.
1164 LiveRangeStage Stage = getStage(VirtReg);
1165 if (Stage == RS_First) {
1166 LRStage[VirtReg.reg] = RS_Second;
1167 DEBUG(dbgs() << "wait for second round\n");
1168 NewVRegs.push_back(&VirtReg);
1172 assert(Stage < RS_Spill && "Cannot allocate after spilling");
1174 // Try splitting VirtReg or interferences.
1175 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
1176 if (PhysReg || !NewVRegs.empty())
1179 // Finally spill VirtReg itself.
1180 NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
1181 LiveRangeEdit LRE(VirtReg, NewVRegs, this);
1182 spiller().spill(LRE);
1183 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Spill);
1186 MF->verify(this, "After spilling");
1188 // The live virtual register requesting allocation was spilled, so tell
1189 // the caller not to allocate anything during this round.
1193 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
1194 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
1195 << "********** Function: "
1196 << ((Value*)mf.getFunction())->getName() << '\n');
1200 MF->verify(this, "Before greedy register allocator");
1202 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
1203 Indexes = &getAnalysis<SlotIndexes>();
1204 DomTree = &getAnalysis<MachineDominatorTree>();
1205 ReservedRegs = TRI->getReservedRegs(*MF);
1206 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
1207 Loops = &getAnalysis<MachineLoopInfo>();
1208 LoopRanges = &getAnalysis<MachineLoopRanges>();
1209 Bundles = &getAnalysis<EdgeBundles>();
1210 SpillPlacer = &getAnalysis<SpillPlacement>();
1212 SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops));
1213 SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree));
1215 LRStage.resize(MRI->getNumVirtRegs());
1219 LIS->addKillFlags();
1223 NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled);
1224 VRM->rewrite(Indexes);
1227 // The pass output is in VirtRegMap. Release all the transient data.