1 //===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RAGreedy function pass for register allocation in
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "AllocationOrder.h"
17 #include "LiveIntervalUnion.h"
18 #include "LiveRangeEdit.h"
19 #include "RegAllocBase.h"
21 #include "SpillPlacement.h"
23 #include "VirtRegMap.h"
24 #include "VirtRegRewriter.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/Function.h"
27 #include "llvm/PassAnalysisSupport.h"
28 #include "llvm/CodeGen/CalcSpillWeights.h"
29 #include "llvm/CodeGen/EdgeBundles.h"
30 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
31 #include "llvm/CodeGen/LiveStackAnalysis.h"
32 #include "llvm/CodeGen/MachineDominators.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineLoopInfo.h"
35 #include "llvm/CodeGen/MachineLoopRanges.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/CodeGen/RegAllocRegistry.h"
39 #include "llvm/CodeGen/RegisterCoalescer.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/raw_ostream.h"
44 #include "llvm/Support/Timer.h"
48 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
49 createGreedyRegisterAllocator);
52 class RAGreedy : public MachineFunctionPass, public RegAllocBase {
55 BitVector ReservedRegs;
60 MachineDominatorTree *DomTree;
61 MachineLoopInfo *Loops;
62 MachineLoopRanges *LoopRanges;
64 SpillPlacement *SpillPlacer;
67 std::auto_ptr<Spiller> SpillerInstance;
68 std::auto_ptr<SplitAnalysis> SA;
72 /// All basic blocks where the current register is live.
73 SmallVector<SpillPlacement::BlockConstraint, 8> SpillConstraints;
75 /// Additional information about basic blocks where the current variable is
76 /// live. Such a block will look like one of these templates:
78 /// 1. | o---x | Internal to block. Variable is only live in this block.
79 /// 2. |---x | Live-in, kill.
80 /// 3. | o---| Def, live-out.
81 /// 4. |---x o---| Live-in, kill, def, live-out.
82 /// 5. |---o---o---| Live-through with uses or defs.
83 /// 6. |-----------| Live-through without uses. Transparent.
86 MachineBasicBlock *MBB;
87 SlotIndex FirstUse; ///< First instr using current reg.
88 SlotIndex LastUse; ///< Last instr using current reg.
89 SlotIndex Kill; ///< Interval end point inside block.
90 SlotIndex Def; ///< Interval start point inside block.
91 /// Last possible point for splitting live ranges.
92 SlotIndex LastSplitPoint;
93 bool Uses; ///< Current reg has uses or defs in block.
94 bool LiveThrough; ///< Live in whole block (Templ 5. or 6. above).
95 bool LiveIn; ///< Current reg is live in.
96 bool LiveOut; ///< Current reg is live out.
98 // Per-interference pattern scratch data.
99 bool OverlapEntry; ///< Interference overlaps entering interval.
100 bool OverlapExit; ///< Interference overlaps exiting interval.
103 /// Basic blocks where var is live. This array is parallel to
104 /// SpillConstraints.
105 SmallVector<BlockInfo, 8> LiveBlocks;
110 /// Return the pass name.
111 virtual const char* getPassName() const {
112 return "Greedy Register Allocator";
115 /// RAGreedy analysis usage.
116 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
118 virtual void releaseMemory();
120 virtual Spiller &spiller() { return *SpillerInstance; }
122 virtual float getPriority(LiveInterval *LI);
124 virtual unsigned selectOrSplit(LiveInterval&,
125 SmallVectorImpl<LiveInterval*>&);
127 /// Perform register allocation.
128 virtual bool runOnMachineFunction(MachineFunction &mf);
133 bool checkUncachedInterference(LiveInterval&, unsigned);
134 LiveInterval *getSingleInterference(LiveInterval&, unsigned);
135 bool reassignVReg(LiveInterval &InterferingVReg, unsigned OldPhysReg);
136 bool reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg);
137 float calcInterferenceWeight(LiveInterval&, unsigned);
138 void calcLiveBlockInfo(LiveInterval&);
139 float calcInterferenceInfo(LiveInterval&, unsigned);
140 float calcGlobalSplitCost(const BitVector&);
141 void splitAroundRegion(LiveInterval&, unsigned, const BitVector&,
142 SmallVectorImpl<LiveInterval*>&);
144 unsigned tryReassign(LiveInterval&, AllocationOrder&);
145 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
146 SmallVectorImpl<LiveInterval*>&);
147 unsigned trySplit(LiveInterval&, AllocationOrder&,
148 SmallVectorImpl<LiveInterval*>&);
149 unsigned trySpillInterferences(LiveInterval&, AllocationOrder&,
150 SmallVectorImpl<LiveInterval*>&);
152 } // end anonymous namespace
154 char RAGreedy::ID = 0;
156 FunctionPass* llvm::createGreedyRegisterAllocator() {
157 return new RAGreedy();
160 RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
161 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
162 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
163 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
164 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
165 initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
166 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
167 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
168 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
169 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
170 initializeMachineLoopRangesPass(*PassRegistry::getPassRegistry());
171 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
172 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
173 initializeSpillPlacementPass(*PassRegistry::getPassRegistry());
176 void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
177 AU.setPreservesCFG();
178 AU.addRequired<AliasAnalysis>();
179 AU.addPreserved<AliasAnalysis>();
180 AU.addRequired<LiveIntervals>();
181 AU.addRequired<SlotIndexes>();
182 AU.addPreserved<SlotIndexes>();
184 AU.addRequiredID(StrongPHIEliminationID);
185 AU.addRequiredTransitive<RegisterCoalescer>();
186 AU.addRequired<CalculateSpillWeights>();
187 AU.addRequired<LiveStacks>();
188 AU.addPreserved<LiveStacks>();
189 AU.addRequired<MachineDominatorTree>();
190 AU.addPreserved<MachineDominatorTree>();
191 AU.addRequired<MachineLoopInfo>();
192 AU.addPreserved<MachineLoopInfo>();
193 AU.addRequired<MachineLoopRanges>();
194 AU.addPreserved<MachineLoopRanges>();
195 AU.addRequired<VirtRegMap>();
196 AU.addPreserved<VirtRegMap>();
197 AU.addRequired<EdgeBundles>();
198 AU.addRequired<SpillPlacement>();
199 MachineFunctionPass::getAnalysisUsage(AU);
202 void RAGreedy::releaseMemory() {
203 SpillerInstance.reset(0);
204 RegAllocBase::releaseMemory();
207 float RAGreedy::getPriority(LiveInterval *LI) {
208 float Priority = LI->weight;
210 // Prioritize hinted registers so they are allocated first.
211 std::pair<unsigned, unsigned> Hint;
212 if (Hint.first || Hint.second) {
213 // The hint can be target specific, a virtual register, or a physreg.
216 // Prefer physreg hints above anything else.
217 if (Hint.first == 0 && TargetRegisterInfo::isPhysicalRegister(Hint.second))
224 //===----------------------------------------------------------------------===//
225 // Register Reassignment
226 //===----------------------------------------------------------------------===//
228 // Check interference without using the cache.
229 bool RAGreedy::checkUncachedInterference(LiveInterval &VirtReg,
231 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
232 LiveIntervalUnion::Query subQ(&VirtReg, &PhysReg2LiveUnion[*AliasI]);
233 if (subQ.checkInterference())
239 /// getSingleInterference - Return the single interfering virtual register
240 /// assigned to PhysReg. Return 0 if more than one virtual register is
242 LiveInterval *RAGreedy::getSingleInterference(LiveInterval &VirtReg,
244 // Check physreg and aliases.
245 LiveInterval *Interference = 0;
246 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
247 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
248 if (Q.checkInterference()) {
251 Q.collectInterferingVRegs(1);
252 if (!Q.seenAllInterferences())
254 Interference = Q.interferingVRegs().front();
260 // Attempt to reassign this virtual register to a different physical register.
262 // FIXME: we are not yet caching these "second-level" interferences discovered
263 // in the sub-queries. These interferences can change with each call to
264 // selectOrSplit. However, we could implement a "may-interfere" cache that
265 // could be conservatively dirtied when we reassign or split.
267 // FIXME: This may result in a lot of alias queries. We could summarize alias
268 // live intervals in their parent register's live union, but it's messy.
269 bool RAGreedy::reassignVReg(LiveInterval &InterferingVReg,
270 unsigned WantedPhysReg) {
271 assert(TargetRegisterInfo::isVirtualRegister(InterferingVReg.reg) &&
272 "Can only reassign virtual registers");
273 assert(TRI->regsOverlap(WantedPhysReg, VRM->getPhys(InterferingVReg.reg)) &&
274 "inconsistent phys reg assigment");
276 AllocationOrder Order(InterferingVReg.reg, *VRM, ReservedRegs);
277 while (unsigned PhysReg = Order.next()) {
278 // Don't reassign to a WantedPhysReg alias.
279 if (TRI->regsOverlap(PhysReg, WantedPhysReg))
282 if (checkUncachedInterference(InterferingVReg, PhysReg))
285 // Reassign the interfering virtual reg to this physical reg.
286 unsigned OldAssign = VRM->getPhys(InterferingVReg.reg);
287 DEBUG(dbgs() << "reassigning: " << InterferingVReg << " from " <<
288 TRI->getName(OldAssign) << " to " << TRI->getName(PhysReg) << '\n');
289 PhysReg2LiveUnion[OldAssign].extract(InterferingVReg);
290 VRM->clearVirt(InterferingVReg.reg);
291 VRM->assignVirt2Phys(InterferingVReg.reg, PhysReg);
292 PhysReg2LiveUnion[PhysReg].unify(InterferingVReg);
299 /// reassignInterferences - Reassign all interferences to different physical
300 /// registers such that Virtreg can be assigned to PhysReg.
301 /// Currently this only works with a single interference.
302 /// @param VirtReg Currently unassigned virtual register.
303 /// @param PhysReg Physical register to be cleared.
304 /// @return True on success, false if nothing was changed.
305 bool RAGreedy::reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg) {
306 LiveInterval *InterferingVReg = getSingleInterference(VirtReg, PhysReg);
307 if (!InterferingVReg)
309 if (TargetRegisterInfo::isPhysicalRegister(InterferingVReg->reg))
311 return reassignVReg(*InterferingVReg, PhysReg);
314 /// tryReassign - Try to reassign interferences to different physregs.
315 /// @param VirtReg Currently unassigned virtual register.
316 /// @param Order Physregs to try.
317 /// @return Physreg to assign VirtReg, or 0.
318 unsigned RAGreedy::tryReassign(LiveInterval &VirtReg, AllocationOrder &Order) {
319 NamedRegionTimer T("Reassign", TimerGroupName, TimePassesIsEnabled);
321 while (unsigned PhysReg = Order.next())
322 if (reassignInterferences(VirtReg, PhysReg))
328 //===----------------------------------------------------------------------===//
330 //===----------------------------------------------------------------------===//
332 /// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
333 /// where VirtReg is live.
334 /// The SpillConstraints array is minimally initialized with MBB->getNumber().
335 void RAGreedy::calcLiveBlockInfo(LiveInterval &VirtReg) {
337 SpillConstraints.clear();
339 assert(!VirtReg.empty() && "Cannot allocate an empty interval");
340 LiveInterval::const_iterator LVI = VirtReg.begin();
341 LiveInterval::const_iterator LVE = VirtReg.end();
343 SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
344 UseI = SA->UseSlots.begin();
345 UseE = SA->UseSlots.end();
347 // Loop over basic blocks where VirtReg is live.
348 MachineFunction::iterator MFI = Indexes->getMBBFromIndex(LVI->start);
350 // Block constraints depend on the interference pattern.
351 // Just allocate them here, don't compute anything.
352 SpillPlacement::BlockConstraint BC;
353 BC.Number = MFI->getNumber();
354 SpillConstraints.push_back(BC);
358 SlotIndex Start, Stop;
359 tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
361 // The last split point is the latest possible insertion point that dominates
362 // all successor blocks. If interference reaches LastSplitPoint, it is not
363 // possible to insert a split or reload that makes VirtReg live in the
365 MachineBasicBlock::iterator LSP = LIS->getLastSplitPoint(VirtReg, BI.MBB);
366 if (LSP == BI.MBB->end())
367 BI.LastSplitPoint = Stop;
369 BI.LastSplitPoint = Indexes->getInstructionIndex(LSP);
371 // LVI is the first live segment overlapping MBB.
372 BI.LiveIn = LVI->start <= Start;
376 // Find the first and last uses in the block.
377 BI.Uses = SA->hasUses(MFI);
378 if (BI.Uses && UseI != UseE) {
380 assert(BI.FirstUse >= Start);
382 while (UseI != UseE && *UseI < Stop);
383 BI.LastUse = UseI[-1];
384 assert(BI.LastUse < Stop);
387 // Look for gaps in the live range.
390 while (LVI->end < Stop) {
391 SlotIndex LastStop = LVI->end;
392 if (++LVI == LVE || LVI->start >= Stop) {
397 if (LastStop < LVI->start) {
404 // Don't set LiveThrough when the block has a gap.
405 BI.LiveThrough = !hasGap && BI.LiveIn && BI.LiveOut;
406 LiveBlocks.push_back(BI);
408 // LVI is now at LVE or LVI->end >= Stop.
412 // Live segment ends exactly at Stop. Move to the next segment.
413 if (LVI->end == Stop && ++LVI == LVE)
416 // Pick the next basic block.
417 if (LVI->start < Stop)
420 MFI = Indexes->getMBBFromIndex(LVI->start);
424 /// calcInterferenceInfo - Compute per-block outgoing and ingoing constraints
425 /// when considering interference from PhysReg. Also compute an optimistic local
426 /// cost of this interference pattern.
428 /// The final cost of a split is the local cost + global cost of preferences
429 /// broken by SpillPlacement.
431 float RAGreedy::calcInterferenceInfo(LiveInterval &VirtReg, unsigned PhysReg) {
432 // Reset interference dependent info.
433 for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
434 BlockInfo &BI = LiveBlocks[i];
435 SpillPlacement::BlockConstraint &BC = SpillConstraints[i];
436 BC.Entry = (BI.Uses && BI.LiveIn) ?
437 SpillPlacement::PrefReg : SpillPlacement::DontCare;
438 BC.Exit = (BI.Uses && BI.LiveOut) ?
439 SpillPlacement::PrefReg : SpillPlacement::DontCare;
440 BI.OverlapEntry = BI.OverlapExit = false;
443 // Add interference info from each PhysReg alias.
444 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
445 if (!query(VirtReg, *AI).checkInterference())
447 DEBUG(PhysReg2LiveUnion[*AI].print(dbgs(), TRI));
448 LiveIntervalUnion::SegmentIter IntI =
449 PhysReg2LiveUnion[*AI].find(VirtReg.beginIndex());
453 for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
454 BlockInfo &BI = LiveBlocks[i];
455 SpillPlacement::BlockConstraint &BC = SpillConstraints[i];
456 SlotIndex Start, Stop;
457 tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
459 // Skip interference-free blocks.
460 if (IntI.start() >= Stop)
463 // Handle transparent blocks with interference separately.
464 // Transparent blocks never incur any fixed cost.
465 if (BI.LiveThrough && !BI.Uses) {
466 // Check if interference is live-in - force spill.
467 if (BC.Entry != SpillPlacement::MustSpill) {
468 BC.Entry = SpillPlacement::PrefSpill;
469 IntI.advanceTo(Start);
470 if (IntI.valid() && IntI.start() <= Start)
471 BC.Entry = SpillPlacement::MustSpill;
474 // Check if interference is live-out - force spill.
475 if (BC.Exit != SpillPlacement::MustSpill) {
476 BC.Exit = SpillPlacement::PrefSpill;
477 // Any interference overlapping [LastSplitPoint;Stop) forces a spill.
478 IntI.advanceTo(BI.LastSplitPoint.getPrevSlot());
479 if (IntI.valid() && IntI.start() < Stop)
480 BC.Exit = SpillPlacement::MustSpill;
483 // Nothing more to do for this transparent block.
489 // Now we only have blocks with uses left.
490 // Check if the interference overlaps the uses.
491 assert(BI.Uses && "Non-transparent block without any uses");
493 // Check interference on entry.
494 if (BI.LiveIn && BC.Entry != SpillPlacement::MustSpill) {
495 IntI.advanceTo(Start);
499 // Interference is live-in - force spill.
500 if (IntI.start() <= Start)
501 BC.Entry = SpillPlacement::MustSpill;
502 // Not live in, but before the first use.
503 else if (IntI.start() < BI.FirstUse)
504 BC.Entry = SpillPlacement::PrefSpill;
507 // Does interference overlap the uses in the entry segment
509 if (BI.LiveIn && !BI.OverlapEntry) {
510 IntI.advanceTo(BI.FirstUse);
513 // A live-through interval has no kill.
514 // Check [FirstUse;LastUse) instead.
515 if (IntI.start() < (BI.LiveThrough ? BI.LastUse : BI.Kill))
516 BI.OverlapEntry = true;
519 // Does interference overlap the uses in the exit segment [Def;LastUse)?
520 if (BI.LiveOut && !BI.LiveThrough && !BI.OverlapExit) {
521 IntI.advanceTo(BI.Def);
524 if (IntI.start() < BI.LastUse)
525 BI.OverlapExit = true;
528 // Check interference on exit.
529 if (BI.LiveOut && BC.Exit != SpillPlacement::MustSpill) {
530 // Check interference between LastUse and Stop.
531 if (BC.Exit != SpillPlacement::PrefSpill) {
532 IntI.advanceTo(BI.LastUse);
535 if (IntI.start() < Stop)
536 BC.Exit = SpillPlacement::PrefSpill;
538 // Is the interference overlapping the last split point?
539 IntI.advanceTo(BI.LastSplitPoint.getPrevSlot());
542 if (IntI.start() < Stop)
543 BC.Exit = SpillPlacement::MustSpill;
548 // Accumulate a local cost of this interference pattern.
550 for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
551 BlockInfo &BI = LiveBlocks[i];
554 SpillPlacement::BlockConstraint &BC = SpillConstraints[i];
555 unsigned Inserts = 0;
557 // Do we need spill code for the entry segment?
559 Inserts += BI.OverlapEntry || BC.Entry != SpillPlacement::PrefReg;
561 // For the exit segment?
563 Inserts += BI.OverlapExit || BC.Exit != SpillPlacement::PrefReg;
565 // The local cost of spill code in this block is the block frequency times
566 // the number of spill instructions inserted.
568 LocalCost += Inserts * SpillPlacer->getBlockFrequency(BI.MBB);
570 DEBUG(dbgs() << "Local cost of " << PrintReg(PhysReg, TRI) << " = "
571 << LocalCost << '\n');
575 /// calcGlobalSplitCost - Return the global split cost of following the split
576 /// pattern in LiveBundles. This cost should be added to the local cost of the
577 /// interference pattern in SpillConstraints.
579 float RAGreedy::calcGlobalSplitCost(const BitVector &LiveBundles) {
580 float GlobalCost = 0;
581 for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
582 SpillPlacement::BlockConstraint &BC = SpillConstraints[i];
583 unsigned Inserts = 0;
584 // Broken entry preference?
585 Inserts += LiveBundles[Bundles->getBundle(BC.Number, 0)] !=
586 (BC.Entry == SpillPlacement::PrefReg);
587 // Broken exit preference?
588 Inserts += LiveBundles[Bundles->getBundle(BC.Number, 1)] !=
589 (BC.Exit == SpillPlacement::PrefReg);
591 GlobalCost += Inserts * SpillPlacer->getBlockFrequency(LiveBlocks[i].MBB);
593 DEBUG(dbgs() << "Global cost = " << GlobalCost << '\n');
597 /// splitAroundRegion - Split VirtReg around the region determined by
598 /// LiveBundles. Make an effort to avoid interference from PhysReg.
600 /// The 'register' interval is going to contain as many uses as possible while
601 /// avoiding interference. The 'stack' interval is the complement constructed by
602 /// SplitEditor. It will contain the rest.
604 void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, unsigned PhysReg,
605 const BitVector &LiveBundles,
606 SmallVectorImpl<LiveInterval*> &NewVRegs) {
608 dbgs() << "Splitting around region for " << PrintReg(PhysReg, TRI)
610 for (int i = LiveBundles.find_first(); i>=0; i = LiveBundles.find_next(i))
611 dbgs() << " EB#" << i;
615 // First compute interference ranges in the live blocks.
616 typedef std::pair<SlotIndex, SlotIndex> IndexPair;
617 SmallVector<IndexPair, 8> InterferenceRanges;
618 InterferenceRanges.resize(LiveBlocks.size());
619 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
620 if (!query(VirtReg, *AI).checkInterference())
622 LiveIntervalUnion::SegmentIter IntI =
623 PhysReg2LiveUnion[*AI].find(VirtReg.beginIndex());
626 for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
627 const BlockInfo &BI = LiveBlocks[i];
628 IndexPair &IP = InterferenceRanges[i];
629 SlotIndex Start, Stop;
630 tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
631 // Skip interference-free blocks.
632 if (IntI.start() >= Stop)
635 // First interference in block.
637 IntI.advanceTo(Start);
640 if (IntI.start() >= Stop)
642 if (!IP.first.isValid() || IntI.start() < IP.first)
643 IP.first = IntI.start();
646 // Last interference in block.
648 IntI.advanceTo(Stop);
649 if (!IntI.valid() || IntI.start() >= Stop)
651 if (IntI.stop() <= Start)
653 if (!IP.second.isValid() || IntI.stop() > IP.second)
654 IP.second = IntI.stop();
659 SmallVector<LiveInterval*, 4> SpillRegs;
660 LiveRangeEdit LREdit(VirtReg, NewVRegs, SpillRegs);
661 SplitEditor SE(*SA, *LIS, *VRM, *DomTree, LREdit);
663 // Create the main cross-block interval.
666 // First add all defs that are live out of a block.
667 for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
668 BlockInfo &BI = LiveBlocks[i];
669 bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)];
670 bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)];
672 // Should the register be live out?
673 if (!BI.LiveOut || !RegOut)
676 IndexPair &IP = InterferenceRanges[i];
677 SlotIndex Start, Stop;
678 tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
680 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " -> EB#"
681 << Bundles->getBundle(BI.MBB->getNumber(), 1)
682 << " intf [" << IP.first << ';' << IP.second << ')');
684 // The interference interval should either be invalid or overlap MBB.
685 assert((!IP.first.isValid() || IP.first < Stop) && "Bad interference");
686 assert((!IP.second.isValid() || IP.second > Start) && "Bad interference");
688 // Check interference leaving the block.
689 if (!IP.second.isValid()) {
690 // Block is interference-free.
691 DEBUG(dbgs() << ", no interference");
693 assert(BI.LiveThrough && "No uses, but not live through block?");
694 // Block is live-through without interference.
695 DEBUG(dbgs() << ", no uses"
696 << (RegIn ? ", live-through.\n" : ", stack in.\n"));
698 SE.enterIntvAtEnd(*BI.MBB);
701 if (!BI.LiveThrough) {
702 DEBUG(dbgs() << ", not live-through.\n");
703 SE.useIntv(SE.enterIntvBefore(BI.Def), Stop);
707 // Block is live-through, but entry bundle is on the stack.
708 // Reload just before the first use.
709 DEBUG(dbgs() << ", not live-in, enter before first use.\n");
710 SE.useIntv(SE.enterIntvBefore(BI.FirstUse), Stop);
713 DEBUG(dbgs() << ", live-through.\n");
717 // Block has interference.
718 DEBUG(dbgs() << ", interference to " << IP.second);
720 // No uses in block, avoid interference by reloading as late as possible.
721 DEBUG(dbgs() << ", no uses.\n");
722 SE.enterIntvAtEnd(*BI.MBB);
725 if (IP.second < BI.LastUse && IP.second <= BI.LastSplitPoint) {
726 // There are interference-free uses at the end of the block.
727 // Find the first use that can get the live-out register.
728 SmallVectorImpl<SlotIndex>::const_iterator UI =
729 std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(), IP.second);
730 assert(UI != SA->UseSlots.end() && "Couldn't find last use");
732 DEBUG(dbgs() << ", free use at " << Use << ".\n");
733 assert(Use <= BI.LastUse && "Couldn't find last use");
734 SE.useIntv(SE.enterIntvBefore(Use), Stop);
738 // Interference is after the last use.
739 DEBUG(dbgs() << " after last use.\n");
740 SE.enterIntvAtEnd(*BI.MBB);
743 // Now all defs leading to live bundles are handled, do everything else.
744 for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
745 BlockInfo &BI = LiveBlocks[i];
746 bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)];
747 bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)];
749 // Is the register live-in?
750 if (!BI.LiveIn || !RegIn)
753 // We have an incoming register. Check for interference.
754 IndexPair &IP = InterferenceRanges[i];
755 SlotIndex Start, Stop;
756 tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
758 DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0)
759 << " -> BB#" << BI.MBB->getNumber());
761 // Check interference entering the block.
762 if (!IP.first.isValid()) {
763 // Block is interference-free.
764 DEBUG(dbgs() << ", no interference");
766 assert(BI.LiveThrough && "No uses, but not live through block?");
767 // Block is live-through without interference.
769 DEBUG(dbgs() << ", no uses, live-through.\n");
770 SE.useIntv(Start, Stop);
772 DEBUG(dbgs() << ", no uses, stack-out.\n");
773 SE.leaveIntvAtTop(*BI.MBB);
777 if (!BI.LiveThrough) {
778 DEBUG(dbgs() << ", killed in block.\n");
779 SE.useIntv(Start, SE.leaveIntvAfter(BI.Kill));
783 // Block is live-through, but exit bundle is on the stack.
784 // Spill immediately after the last use.
785 DEBUG(dbgs() << ", uses, stack-out.\n");
786 SE.useIntv(Start, SE.leaveIntvAfter(BI.LastUse));
789 // Register is live-through.
790 DEBUG(dbgs() << ", uses, live-through.\n");
791 SE.useIntv(Start, Stop);
795 // Block has interference.
796 DEBUG(dbgs() << ", interference from " << IP.first);
798 // No uses in block, avoid interference by spilling as soon as possible.
799 DEBUG(dbgs() << ", no uses.\n");
800 SE.leaveIntvAtTop(*BI.MBB);
803 if (IP.first > BI.FirstUse) {
804 // There are interference-free uses at the beginning of the block.
805 // Find the last use that can get the register.
806 SmallVectorImpl<SlotIndex>::const_iterator UI =
807 std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(), IP.first);
808 assert(UI != SA->UseSlots.begin() && "Couldn't find first use");
809 SlotIndex Use = (--UI)->getBoundaryIndex();
810 DEBUG(dbgs() << ", free use at " << *UI << ".\n");
811 assert(Use >= BI.FirstUse && Use < IP.first);
812 SE.useIntv(Start, SE.leaveIntvAfter(Use));
816 // Interference is before the first use.
817 DEBUG(dbgs() << " before first use.\n");
818 SE.leaveIntvAtTop(*BI.MBB);
823 // FIXME: Should we be more aggressive about splitting the stack region into
824 // per-block segments? The current approach allows the stack region to
825 // separate into connected components. Some components may be allocatable.
829 MF->verify(this, "After splitting live range around region");
832 // Make sure that at least one of the new intervals can allocate to PhysReg.
833 // That was the whole point of splitting the live range.
835 for (LiveRangeEdit::iterator I = LREdit.begin(), E = LREdit.end(); I != E;
837 if (!checkUncachedInterference(**I, PhysReg)) {
841 assert(found && "No allocatable intervals after pointless splitting");
846 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
847 SmallVectorImpl<LiveInterval*> &NewVRegs) {
848 calcLiveBlockInfo(VirtReg);
849 BitVector LiveBundles, BestBundles;
851 unsigned BestReg = 0;
853 while (unsigned PhysReg = Order.next()) {
854 float Cost = calcInterferenceInfo(VirtReg, PhysReg);
855 if (BestReg && Cost >= BestCost)
858 SpillPlacer->placeSpills(SpillConstraints, LiveBundles);
859 // No live bundles, defer to splitSingleBlocks().
860 if (!LiveBundles.any())
863 Cost += calcGlobalSplitCost(LiveBundles);
864 if (!BestReg || Cost < BestCost) {
867 BestBundles.swap(LiveBundles);
874 splitAroundRegion(VirtReg, BestReg, BestBundles, NewVRegs);
879 //===----------------------------------------------------------------------===//
880 // Live Range Splitting
881 //===----------------------------------------------------------------------===//
883 /// trySplit - Try to split VirtReg or one of its interferences, making it
885 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
886 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
887 SmallVectorImpl<LiveInterval*>&NewVRegs) {
888 NamedRegionTimer T("Splitter", TimerGroupName, TimePassesIsEnabled);
889 SA->analyze(&VirtReg);
891 // Don't attempt splitting on local intervals for now. TBD.
892 if (LIS->intervalIsInOneMBB(VirtReg))
895 // First try to split around a region spanning multiple blocks.
896 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
897 if (PhysReg || !NewVRegs.empty())
900 // Then isolate blocks with multiple uses.
901 SplitAnalysis::BlockPtrSet Blocks;
902 if (SA->getMultiUseBlocks(Blocks)) {
903 SmallVector<LiveInterval*, 4> SpillRegs;
904 LiveRangeEdit LREdit(VirtReg, NewVRegs, SpillRegs);
905 SplitEditor(*SA, *LIS, *VRM, *DomTree, LREdit).splitSingleBlocks(Blocks);
907 MF->verify(this, "After splitting live range around basic blocks");
910 // Don't assign any physregs.
915 //===----------------------------------------------------------------------===//
917 //===----------------------------------------------------------------------===//
919 /// calcInterferenceWeight - Calculate the combined spill weight of
920 /// interferences when assigning VirtReg to PhysReg.
921 float RAGreedy::calcInterferenceWeight(LiveInterval &VirtReg, unsigned PhysReg){
923 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
924 LiveIntervalUnion::Query &Q = query(VirtReg, *AI);
925 Q.collectInterferingVRegs();
926 if (Q.seenUnspillableVReg())
928 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i)
929 Sum += Q.interferingVRegs()[i]->weight;
934 /// trySpillInterferences - Try to spill interfering registers instead of the
935 /// current one. Only do it if the accumulated spill weight is smaller than the
936 /// current spill weight.
937 unsigned RAGreedy::trySpillInterferences(LiveInterval &VirtReg,
938 AllocationOrder &Order,
939 SmallVectorImpl<LiveInterval*> &NewVRegs) {
940 NamedRegionTimer T("Spill Interference", TimerGroupName, TimePassesIsEnabled);
941 unsigned BestPhys = 0;
942 float BestWeight = 0;
945 while (unsigned PhysReg = Order.next()) {
946 float Weight = calcInterferenceWeight(VirtReg, PhysReg);
947 if (Weight == HUGE_VALF || Weight >= VirtReg.weight)
949 if (!BestPhys || Weight < BestWeight)
950 BestPhys = PhysReg, BestWeight = Weight;
953 // No candidates found.
957 // Collect all interfering registers.
958 SmallVector<LiveInterval*, 8> Spills;
959 for (const unsigned *AI = TRI->getOverlaps(BestPhys); *AI; ++AI) {
960 LiveIntervalUnion::Query &Q = query(VirtReg, *AI);
961 Spills.append(Q.interferingVRegs().begin(), Q.interferingVRegs().end());
962 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
963 LiveInterval *VReg = Q.interferingVRegs()[i];
964 PhysReg2LiveUnion[*AI].extract(*VReg);
965 VRM->clearVirt(VReg->reg);
970 DEBUG(dbgs() << "spilling " << Spills.size() << " interferences with weight "
971 << BestWeight << '\n');
972 for (unsigned i = 0, e = Spills.size(); i != e; ++i)
973 spiller().spill(Spills[i], NewVRegs, Spills);
978 //===----------------------------------------------------------------------===//
980 //===----------------------------------------------------------------------===//
982 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
983 SmallVectorImpl<LiveInterval*> &NewVRegs) {
984 // First try assigning a free register.
985 AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);
986 while (unsigned PhysReg = Order.next()) {
987 if (!checkPhysRegInterference(VirtReg, PhysReg))
991 // Try to reassign interferences.
992 if (unsigned PhysReg = tryReassign(VirtReg, Order))
995 assert(NewVRegs.empty() && "Cannot append to existing NewVRegs");
997 // Try splitting VirtReg or interferences.
998 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
999 if (PhysReg || !NewVRegs.empty())
1002 // Try to spill another interfering reg with less spill weight.
1003 PhysReg = trySpillInterferences(VirtReg, Order, NewVRegs);
1007 // Finally spill VirtReg itself.
1008 NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
1009 SmallVector<LiveInterval*, 1> pendingSpills;
1010 spiller().spill(&VirtReg, NewVRegs, pendingSpills);
1012 // The live virtual register requesting allocation was spilled, so tell
1013 // the caller not to allocate anything during this round.
1017 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
1018 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
1019 << "********** Function: "
1020 << ((Value*)mf.getFunction())->getName() << '\n');
1024 MF->verify(this, "Before greedy register allocator");
1026 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
1027 Indexes = &getAnalysis<SlotIndexes>();
1028 DomTree = &getAnalysis<MachineDominatorTree>();
1029 ReservedRegs = TRI->getReservedRegs(*MF);
1030 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
1031 Loops = &getAnalysis<MachineLoopInfo>();
1032 LoopRanges = &getAnalysis<MachineLoopRanges>();
1033 Bundles = &getAnalysis<EdgeBundles>();
1034 SpillPlacer = &getAnalysis<SpillPlacement>();
1036 SA.reset(new SplitAnalysis(*MF, *LIS, *Loops));
1043 NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled);
1044 std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
1045 rewriter->runOnMachineFunction(*MF, *VRM, LIS);
1048 // The pass output is in VirtRegMap. Release all the transient data.