1 //===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RAGreedy function pass for register allocation in
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "LiveIntervalUnion.h"
17 #include "RegAllocBase.h"
19 #include "VirtRegMap.h"
20 #include "VirtRegRewriter.h"
21 #include "llvm/ADT/OwningPtr.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/Function.h"
24 #include "llvm/PassAnalysisSupport.h"
25 #include "llvm/CodeGen/CalcSpillWeights.h"
26 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
27 #include "llvm/CodeGen/LiveStackAnalysis.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineLoopInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/CodeGen/RegAllocRegistry.h"
34 #include "llvm/CodeGen/RegisterCoalescer.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/Target/TargetRegisterInfo.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/raw_ostream.h"
44 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
45 createGreedyRegisterAllocator);
48 class RAGreedy : public MachineFunctionPass, public RegAllocBase {
51 const TargetMachine *TM;
52 MachineRegisterInfo *MRI;
54 BitVector ReservedRegs;
60 std::auto_ptr<Spiller> SpillerInstance;
65 /// Return the pass name.
66 virtual const char* getPassName() const {
67 return "Basic Register Allocator";
70 /// RAGreedy analysis usage.
71 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
73 virtual void releaseMemory();
75 virtual Spiller &spiller() { return *SpillerInstance; }
77 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
78 SmallVectorImpl<LiveInterval*> &SplitVRegs);
80 /// Perform register allocation.
81 virtual bool runOnMachineFunction(MachineFunction &mf);
85 } // end anonymous namespace
87 char RAGreedy::ID = 0;
89 FunctionPass* llvm::createGreedyRegisterAllocator() {
90 return new RAGreedy();
93 RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
94 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
95 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
96 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
97 initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
98 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
99 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
100 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
101 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
102 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
105 void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
106 AU.setPreservesCFG();
107 AU.addRequired<AliasAnalysis>();
108 AU.addPreserved<AliasAnalysis>();
109 AU.addRequired<LiveIntervals>();
110 AU.addPreserved<SlotIndexes>();
112 AU.addRequiredID(StrongPHIEliminationID);
113 AU.addRequiredTransitive<RegisterCoalescer>();
114 AU.addRequired<CalculateSpillWeights>();
115 AU.addRequired<LiveStacks>();
116 AU.addPreserved<LiveStacks>();
117 AU.addRequiredID(MachineDominatorsID);
118 AU.addPreservedID(MachineDominatorsID);
119 AU.addRequired<MachineLoopInfo>();
120 AU.addPreserved<MachineLoopInfo>();
121 AU.addRequired<VirtRegMap>();
122 AU.addPreserved<VirtRegMap>();
123 MachineFunctionPass::getAnalysisUsage(AU);
126 void RAGreedy::releaseMemory() {
127 SpillerInstance.reset(0);
128 RegAllocBase::releaseMemory();
131 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
132 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
133 // Populate a list of physical register spill candidates.
134 SmallVector<unsigned, 8> PhysRegSpillCands;
136 // Check for an available register in this class.
137 const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
138 DEBUG(dbgs() << "RegClass: " << TRC->getName() << ' ');
140 for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
141 E = TRC->allocation_order_end(*MF);
144 unsigned PhysReg = *I;
145 if (ReservedRegs.test(PhysReg)) continue;
147 // Check interference and as a side effect, intialize queries for this
148 // VirtReg and its aliases.
149 unsigned interfReg = checkPhysRegInterference(VirtReg, PhysReg);
150 if (interfReg == 0) {
151 // Found an available register.
154 LiveInterval *interferingVirtReg =
155 Queries[interfReg].firstInterference().liveUnionPos().value();
157 // The current VirtReg must either spillable, or one of its interferences
158 // must have less spill weight.
159 if (interferingVirtReg->weight < VirtReg.weight ) {
160 PhysRegSpillCands.push_back(PhysReg);
163 // Try to spill another interfering reg with less spill weight.
165 // FIXME: RAGreedy will sort this list by spill weight.
166 for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
167 PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
169 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue;
171 assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 &&
172 "Interference after spill.");
173 // Tell the caller to allocate to this newly freed physical register.
176 // No other spill candidates were found, so spill the current VirtReg.
177 DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
178 SmallVector<LiveInterval*, 1> pendingSpills;
180 spiller().spill(&VirtReg, SplitVRegs, pendingSpills);
182 // The live virtual register requesting allocation was spilled, so tell
183 // the caller not to allocate anything during this round.
187 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
188 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
189 << "********** Function: "
190 << ((Value*)mf.getFunction())->getName() << '\n');
193 TM = &mf.getTarget();
194 MRI = &mf.getRegInfo();
196 const TargetRegisterInfo *TRI = TM->getRegisterInfo();
197 RegAllocBase::init(*TRI, getAnalysis<VirtRegMap>(),
198 getAnalysis<LiveIntervals>());
200 ReservedRegs = TRI->getReservedRegs(*MF);
201 SpillerInstance.reset(createSpiller(*this, *MF, *VRM));
206 std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
207 rewriter->runOnMachineFunction(*MF, *VRM, LIS);
209 // The pass output is in VirtRegMap. Release all the transient data.