1 //===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RAGreedy function pass for register allocation in
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "AllocationOrder.h"
17 #include "LiveIntervalUnion.h"
18 #include "LiveRangeEdit.h"
19 #include "RegAllocBase.h"
21 #include "SpillPlacement.h"
23 #include "VirtRegMap.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/Function.h"
27 #include "llvm/PassAnalysisSupport.h"
28 #include "llvm/CodeGen/CalcSpillWeights.h"
29 #include "llvm/CodeGen/EdgeBundles.h"
30 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
31 #include "llvm/CodeGen/LiveStackAnalysis.h"
32 #include "llvm/CodeGen/MachineDominators.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineLoopInfo.h"
35 #include "llvm/CodeGen/MachineLoopRanges.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/CodeGen/RegAllocRegistry.h"
39 #include "llvm/CodeGen/RegisterCoalescer.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/raw_ostream.h"
44 #include "llvm/Support/Timer.h"
50 STATISTIC(NumGlobalSplits, "Number of split global live ranges");
51 STATISTIC(NumLocalSplits, "Number of split local live ranges");
52 STATISTIC(NumReassigned, "Number of interferences reassigned");
53 STATISTIC(NumEvicted, "Number of interferences evicted");
55 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
56 createGreedyRegisterAllocator);
59 class RAGreedy : public MachineFunctionPass, public RegAllocBase {
62 BitVector ReservedRegs;
67 MachineDominatorTree *DomTree;
68 MachineLoopInfo *Loops;
69 MachineLoopRanges *LoopRanges;
71 SpillPlacement *SpillPlacer;
74 std::auto_ptr<Spiller> SpillerInstance;
75 std::priority_queue<std::pair<unsigned, unsigned> > Queue;
77 // Live ranges pass through a number of stages as we try to allocate them.
78 // Some of the stages may also create new live ranges:
80 // - Region splitting.
81 // - Per-block splitting.
85 // Ranges produced by one of the stages skip the previous stages when they are
86 // dequeued. This improves performance because we can skip interference checks
87 // that are unlikely to give any results. It also guarantees that the live
88 // range splitting algorithm terminates, something that is otherwise hard to
91 RS_Original, ///< Never seen before, never split.
92 RS_Second, ///< Second time in the queue.
93 RS_Region, ///< Produced by region splitting.
94 RS_Block, ///< Produced by per-block splitting.
95 RS_Local, ///< Produced by local splitting.
96 RS_Spill ///< Produced by spilling.
99 IndexedMap<unsigned char, VirtReg2IndexFunctor> LRStage;
101 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
102 return LiveRangeStage(LRStage[VirtReg.reg]);
105 template<typename Iterator>
106 void setStage(Iterator Begin, Iterator End, LiveRangeStage NewStage) {
107 LRStage.resize(MRI->getNumVirtRegs());
108 for (;Begin != End; ++Begin)
109 LRStage[(*Begin)->reg] = NewStage;
113 std::auto_ptr<SplitAnalysis> SA;
114 std::auto_ptr<SplitEditor> SE;
116 /// All basic blocks where the current register is live.
117 SmallVector<SpillPlacement::BlockConstraint, 8> SpillConstraints;
119 /// For every instruction in SA->UseSlots, store the previous non-copy
121 SmallVector<SlotIndex, 8> PrevSlot;
126 /// Return the pass name.
127 virtual const char* getPassName() const {
128 return "Greedy Register Allocator";
131 /// RAGreedy analysis usage.
132 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
133 virtual void releaseMemory();
134 virtual Spiller &spiller() { return *SpillerInstance; }
135 virtual void enqueue(LiveInterval *LI);
136 virtual LiveInterval *dequeue();
137 virtual unsigned selectOrSplit(LiveInterval&,
138 SmallVectorImpl<LiveInterval*>&);
140 /// Perform register allocation.
141 virtual bool runOnMachineFunction(MachineFunction &mf);
146 bool checkUncachedInterference(LiveInterval&, unsigned);
147 LiveInterval *getSingleInterference(LiveInterval&, unsigned);
148 bool reassignVReg(LiveInterval &InterferingVReg, unsigned OldPhysReg);
149 float calcInterferenceInfo(LiveInterval&, unsigned);
150 float calcGlobalSplitCost(const BitVector&);
151 void splitAroundRegion(LiveInterval&, unsigned, const BitVector&,
152 SmallVectorImpl<LiveInterval*>&);
153 void calcGapWeights(unsigned, SmallVectorImpl<float>&);
154 SlotIndex getPrevMappedIndex(const MachineInstr*);
155 void calcPrevSlots();
156 unsigned nextSplitPoint(unsigned);
157 bool canEvictInterference(LiveInterval&, unsigned, float&);
159 unsigned tryReassign(LiveInterval&, AllocationOrder&,
160 SmallVectorImpl<LiveInterval*>&);
161 unsigned tryEvict(LiveInterval&, AllocationOrder&,
162 SmallVectorImpl<LiveInterval*>&);
163 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
164 SmallVectorImpl<LiveInterval*>&);
165 unsigned tryLocalSplit(LiveInterval&, AllocationOrder&,
166 SmallVectorImpl<LiveInterval*>&);
167 unsigned trySplit(LiveInterval&, AllocationOrder&,
168 SmallVectorImpl<LiveInterval*>&);
170 } // end anonymous namespace
172 char RAGreedy::ID = 0;
174 FunctionPass* llvm::createGreedyRegisterAllocator() {
175 return new RAGreedy();
178 RAGreedy::RAGreedy(): MachineFunctionPass(ID), LRStage(RS_Original) {
179 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
180 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
181 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
182 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
183 initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
184 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
185 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
186 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
187 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
188 initializeMachineLoopRangesPass(*PassRegistry::getPassRegistry());
189 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
190 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
191 initializeSpillPlacementPass(*PassRegistry::getPassRegistry());
194 void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
195 AU.setPreservesCFG();
196 AU.addRequired<AliasAnalysis>();
197 AU.addPreserved<AliasAnalysis>();
198 AU.addRequired<LiveIntervals>();
199 AU.addRequired<SlotIndexes>();
200 AU.addPreserved<SlotIndexes>();
202 AU.addRequiredID(StrongPHIEliminationID);
203 AU.addRequiredTransitive<RegisterCoalescer>();
204 AU.addRequired<CalculateSpillWeights>();
205 AU.addRequired<LiveStacks>();
206 AU.addPreserved<LiveStacks>();
207 AU.addRequired<MachineDominatorTree>();
208 AU.addPreserved<MachineDominatorTree>();
209 AU.addRequired<MachineLoopInfo>();
210 AU.addPreserved<MachineLoopInfo>();
211 AU.addRequired<MachineLoopRanges>();
212 AU.addPreserved<MachineLoopRanges>();
213 AU.addRequired<VirtRegMap>();
214 AU.addPreserved<VirtRegMap>();
215 AU.addRequired<EdgeBundles>();
216 AU.addRequired<SpillPlacement>();
217 MachineFunctionPass::getAnalysisUsage(AU);
220 void RAGreedy::releaseMemory() {
221 SpillerInstance.reset(0);
223 RegAllocBase::releaseMemory();
226 void RAGreedy::enqueue(LiveInterval *LI) {
227 // Prioritize live ranges by size, assigning larger ranges first.
228 // The queue holds (size, reg) pairs.
229 const unsigned Size = LI->getSize();
230 const unsigned Reg = LI->reg;
231 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
232 "Can only enqueue virtual registers");
236 if (LRStage[Reg] == RS_Original)
237 // 1st generation ranges are handled first, long -> short.
238 Prio = (1u << 31) + Size;
240 // Repeat offenders are handled second, short -> long
241 Prio = (1u << 30) - Size;
243 // Boost ranges that have a physical register hint.
244 const unsigned Hint = VRM->getRegAllocPref(Reg);
245 if (TargetRegisterInfo::isPhysicalRegister(Hint))
248 Queue.push(std::make_pair(Prio, Reg));
251 LiveInterval *RAGreedy::dequeue() {
254 LiveInterval *LI = &LIS->getInterval(Queue.top().second);
259 //===----------------------------------------------------------------------===//
260 // Register Reassignment
261 //===----------------------------------------------------------------------===//
263 // Check interference without using the cache.
264 bool RAGreedy::checkUncachedInterference(LiveInterval &VirtReg,
266 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
267 LiveIntervalUnion::Query subQ(&VirtReg, &PhysReg2LiveUnion[*AliasI]);
268 if (subQ.checkInterference())
274 /// getSingleInterference - Return the single interfering virtual register
275 /// assigned to PhysReg. Return 0 if more than one virtual register is
277 LiveInterval *RAGreedy::getSingleInterference(LiveInterval &VirtReg,
279 // Check physreg and aliases.
280 LiveInterval *Interference = 0;
281 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
282 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
283 if (Q.checkInterference()) {
286 if (Q.collectInterferingVRegs(2) > 1)
288 Interference = Q.interferingVRegs().front();
294 // Attempt to reassign this virtual register to a different physical register.
296 // FIXME: we are not yet caching these "second-level" interferences discovered
297 // in the sub-queries. These interferences can change with each call to
298 // selectOrSplit. However, we could implement a "may-interfere" cache that
299 // could be conservatively dirtied when we reassign or split.
301 // FIXME: This may result in a lot of alias queries. We could summarize alias
302 // live intervals in their parent register's live union, but it's messy.
303 bool RAGreedy::reassignVReg(LiveInterval &InterferingVReg,
304 unsigned WantedPhysReg) {
305 assert(TargetRegisterInfo::isVirtualRegister(InterferingVReg.reg) &&
306 "Can only reassign virtual registers");
307 assert(TRI->regsOverlap(WantedPhysReg, VRM->getPhys(InterferingVReg.reg)) &&
308 "inconsistent phys reg assigment");
310 AllocationOrder Order(InterferingVReg.reg, *VRM, ReservedRegs);
311 while (unsigned PhysReg = Order.next()) {
312 // Don't reassign to a WantedPhysReg alias.
313 if (TRI->regsOverlap(PhysReg, WantedPhysReg))
316 if (checkUncachedInterference(InterferingVReg, PhysReg))
319 // Reassign the interfering virtual reg to this physical reg.
320 unsigned OldAssign = VRM->getPhys(InterferingVReg.reg);
321 DEBUG(dbgs() << "reassigning: " << InterferingVReg << " from " <<
322 TRI->getName(OldAssign) << " to " << TRI->getName(PhysReg) << '\n');
323 unassign(InterferingVReg, OldAssign);
324 assign(InterferingVReg, PhysReg);
331 /// tryReassign - Try to reassign a single interference to a different physreg.
332 /// @param VirtReg Currently unassigned virtual register.
333 /// @param Order Physregs to try.
334 /// @return Physreg to assign VirtReg, or 0.
335 unsigned RAGreedy::tryReassign(LiveInterval &VirtReg, AllocationOrder &Order,
336 SmallVectorImpl<LiveInterval*> &NewVRegs){
337 NamedRegionTimer T("Reassign", TimerGroupName, TimePassesIsEnabled);
340 while (unsigned PhysReg = Order.next()) {
341 LiveInterval *InterferingVReg = getSingleInterference(VirtReg, PhysReg);
342 if (!InterferingVReg)
344 if (TargetRegisterInfo::isPhysicalRegister(InterferingVReg->reg))
346 if (reassignVReg(*InterferingVReg, PhysReg))
353 //===----------------------------------------------------------------------===//
354 // Interference eviction
355 //===----------------------------------------------------------------------===//
357 /// canEvict - Return true if all interferences between VirtReg and PhysReg can
358 /// be evicted. Set maxWeight to the maximal spill weight of an interference.
359 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
362 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
363 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
364 // If there is 10 or more interferences, chances are one is smaller.
365 if (Q.collectInterferingVRegs(10) >= 10)
368 // Check if any interfering live range is heavier than VirtReg.
369 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
370 LiveInterval *Intf = Q.interferingVRegs()[i];
371 if (TargetRegisterInfo::isPhysicalRegister(Intf->reg))
373 if (Intf->weight >= VirtReg.weight)
375 Weight = std::max(Weight, Intf->weight);
382 /// tryEvict - Try to evict all interferences for a physreg.
383 /// @param VirtReg Currently unassigned virtual register.
384 /// @param Order Physregs to try.
385 /// @return Physreg to assign VirtReg, or 0.
386 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
387 AllocationOrder &Order,
388 SmallVectorImpl<LiveInterval*> &NewVRegs){
389 NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled);
391 // Keep track of the lightest single interference seen so far.
392 float BestWeight = 0;
393 unsigned BestPhys = 0;
396 while (unsigned PhysReg = Order.next()) {
398 if (!canEvictInterference(VirtReg, PhysReg, Weight))
401 // This is an eviction candidate.
402 DEBUG(dbgs() << "max " << PrintReg(PhysReg, TRI) << " interference = "
404 if (BestPhys && Weight >= BestWeight)
410 // Stop if the hint can be used.
411 if (Order.isHint(PhysReg))
418 DEBUG(dbgs() << "evicting " << PrintReg(BestPhys, TRI) << " interference\n");
419 for (const unsigned *AliasI = TRI->getOverlaps(BestPhys); *AliasI; ++AliasI) {
420 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
421 assert(Q.seenAllInterferences() && "Didn't check all interfererences.");
422 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
423 LiveInterval *Intf = Q.interferingVRegs()[i];
424 unassign(*Intf, VRM->getPhys(Intf->reg));
426 NewVRegs.push_back(Intf);
433 //===----------------------------------------------------------------------===//
435 //===----------------------------------------------------------------------===//
437 /// calcInterferenceInfo - Compute per-block outgoing and ingoing constraints
438 /// when considering interference from PhysReg. Also compute an optimistic local
439 /// cost of this interference pattern.
441 /// The final cost of a split is the local cost + global cost of preferences
442 /// broken by SpillPlacement.
444 float RAGreedy::calcInterferenceInfo(LiveInterval &VirtReg, unsigned PhysReg) {
445 // Reset interference dependent info.
446 SpillConstraints.resize(SA->LiveBlocks.size());
447 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
448 SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
449 SpillPlacement::BlockConstraint &BC = SpillConstraints[i];
450 BC.Number = BI.MBB->getNumber();
451 BC.Entry = (BI.Uses && BI.LiveIn) ?
452 SpillPlacement::PrefReg : SpillPlacement::DontCare;
453 BC.Exit = (BI.Uses && BI.LiveOut) ?
454 SpillPlacement::PrefReg : SpillPlacement::DontCare;
455 BI.OverlapEntry = BI.OverlapExit = false;
458 // Add interference info from each PhysReg alias.
459 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
460 if (!query(VirtReg, *AI).checkInterference())
462 LiveIntervalUnion::SegmentIter IntI =
463 PhysReg2LiveUnion[*AI].find(VirtReg.beginIndex());
467 // Determine which blocks have interference live in or after the last split
469 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
470 SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
471 SpillPlacement::BlockConstraint &BC = SpillConstraints[i];
473 // Skip interference-free blocks.
474 if (IntI.start() >= BI.Stop)
477 // Is the interference live-in?
479 IntI.advanceTo(BI.Start);
482 if (IntI.start() <= BI.Start)
483 BC.Entry = SpillPlacement::MustSpill;
486 // Is the interference overlapping the last split point?
488 if (IntI.stop() < BI.LastSplitPoint)
489 IntI.advanceTo(BI.LastSplitPoint.getPrevSlot());
492 if (IntI.start() < BI.Stop)
493 BC.Exit = SpillPlacement::MustSpill;
497 // Rewind iterator and check other interferences.
498 IntI.find(VirtReg.beginIndex());
499 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
500 SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
501 SpillPlacement::BlockConstraint &BC = SpillConstraints[i];
503 // Skip interference-free blocks.
504 if (IntI.start() >= BI.Stop)
507 // Handle transparent blocks with interference separately.
508 // Transparent blocks never incur any fixed cost.
509 if (BI.LiveThrough && !BI.Uses) {
510 IntI.advanceTo(BI.Start);
513 if (IntI.start() >= BI.Stop)
516 if (BC.Entry != SpillPlacement::MustSpill)
517 BC.Entry = SpillPlacement::PrefSpill;
518 if (BC.Exit != SpillPlacement::MustSpill)
519 BC.Exit = SpillPlacement::PrefSpill;
523 // Now we only have blocks with uses left.
524 // Check if the interference overlaps the uses.
525 assert(BI.Uses && "Non-transparent block without any uses");
527 // Check interference on entry.
528 if (BI.LiveIn && BC.Entry != SpillPlacement::MustSpill) {
529 IntI.advanceTo(BI.Start);
532 // Not live in, but before the first use.
533 if (IntI.start() < BI.FirstUse) {
534 BC.Entry = SpillPlacement::PrefSpill;
535 // If the block contains a kill from an earlier split, never split
536 // again in the same block.
537 if (!BI.LiveThrough && !SA->isOriginalEndpoint(BI.Kill))
538 BC.Entry = SpillPlacement::MustSpill;
542 // Does interference overlap the uses in the entry segment
544 if (BI.LiveIn && !BI.OverlapEntry) {
545 IntI.advanceTo(BI.FirstUse);
548 // A live-through interval has no kill.
549 // Check [FirstUse;LastUse) instead.
550 if (IntI.start() < (BI.LiveThrough ? BI.LastUse : BI.Kill))
551 BI.OverlapEntry = true;
554 // Does interference overlap the uses in the exit segment [Def;LastUse)?
555 if (BI.LiveOut && !BI.LiveThrough && !BI.OverlapExit) {
556 IntI.advanceTo(BI.Def);
559 if (IntI.start() < BI.LastUse)
560 BI.OverlapExit = true;
563 // Check interference on exit.
564 if (BI.LiveOut && BC.Exit != SpillPlacement::MustSpill) {
565 // Check interference between LastUse and Stop.
566 if (BC.Exit != SpillPlacement::PrefSpill) {
567 IntI.advanceTo(BI.LastUse);
570 if (IntI.start() < BI.Stop) {
571 BC.Exit = SpillPlacement::PrefSpill;
572 // Avoid splitting twice in the same block.
573 if (!BI.LiveThrough && !SA->isOriginalEndpoint(BI.Def))
574 BC.Exit = SpillPlacement::MustSpill;
581 // Accumulate a local cost of this interference pattern.
583 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
584 SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
587 SpillPlacement::BlockConstraint &BC = SpillConstraints[i];
588 unsigned Inserts = 0;
590 // Do we need spill code for the entry segment?
592 Inserts += BI.OverlapEntry || BC.Entry != SpillPlacement::PrefReg;
594 // For the exit segment?
596 Inserts += BI.OverlapExit || BC.Exit != SpillPlacement::PrefReg;
598 // The local cost of spill code in this block is the block frequency times
599 // the number of spill instructions inserted.
601 LocalCost += Inserts * SpillPlacer->getBlockFrequency(BC.Number);
603 DEBUG(dbgs() << "Local cost of " << PrintReg(PhysReg, TRI) << " = "
604 << LocalCost << '\n');
608 /// calcGlobalSplitCost - Return the global split cost of following the split
609 /// pattern in LiveBundles. This cost should be added to the local cost of the
610 /// interference pattern in SpillConstraints.
612 float RAGreedy::calcGlobalSplitCost(const BitVector &LiveBundles) {
613 float GlobalCost = 0;
614 for (unsigned i = 0, e = SpillConstraints.size(); i != e; ++i) {
615 SpillPlacement::BlockConstraint &BC = SpillConstraints[i];
616 unsigned Inserts = 0;
617 // Broken entry preference?
618 Inserts += LiveBundles[Bundles->getBundle(BC.Number, 0)] !=
619 (BC.Entry == SpillPlacement::PrefReg);
620 // Broken exit preference?
621 Inserts += LiveBundles[Bundles->getBundle(BC.Number, 1)] !=
622 (BC.Exit == SpillPlacement::PrefReg);
624 GlobalCost += Inserts * SpillPlacer->getBlockFrequency(BC.Number);
627 dbgs() << "Global cost = " << GlobalCost << " with bundles";
628 for (int i = LiveBundles.find_first(); i>=0; i = LiveBundles.find_next(i))
629 dbgs() << " EB#" << i;
635 /// splitAroundRegion - Split VirtReg around the region determined by
636 /// LiveBundles. Make an effort to avoid interference from PhysReg.
638 /// The 'register' interval is going to contain as many uses as possible while
639 /// avoiding interference. The 'stack' interval is the complement constructed by
640 /// SplitEditor. It will contain the rest.
642 void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, unsigned PhysReg,
643 const BitVector &LiveBundles,
644 SmallVectorImpl<LiveInterval*> &NewVRegs) {
646 dbgs() << "Splitting around region for " << PrintReg(PhysReg, TRI)
648 for (int i = LiveBundles.find_first(); i>=0; i = LiveBundles.find_next(i))
649 dbgs() << " EB#" << i;
653 // First compute interference ranges in the live blocks.
654 typedef std::pair<SlotIndex, SlotIndex> IndexPair;
655 SmallVector<IndexPair, 8> InterferenceRanges;
656 InterferenceRanges.resize(SA->LiveBlocks.size());
657 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
658 if (!query(VirtReg, *AI).checkInterference())
660 LiveIntervalUnion::SegmentIter IntI =
661 PhysReg2LiveUnion[*AI].find(VirtReg.beginIndex());
664 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
665 const SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
666 IndexPair &IP = InterferenceRanges[i];
668 // Skip interference-free blocks.
669 if (IntI.start() >= BI.Stop)
672 // First interference in block.
674 IntI.advanceTo(BI.Start);
677 if (IntI.start() >= BI.Stop)
679 if (!IP.first.isValid() || IntI.start() < IP.first)
680 IP.first = IntI.start();
683 // Last interference in block.
685 IntI.advanceTo(BI.Stop);
686 if (!IntI.valid() || IntI.start() >= BI.Stop)
688 if (IntI.stop() <= BI.Start)
690 if (!IP.second.isValid() || IntI.stop() > IP.second)
691 IP.second = IntI.stop();
696 SmallVector<LiveInterval*, 4> SpillRegs;
697 LiveRangeEdit LREdit(VirtReg, NewVRegs, SpillRegs);
700 // Create the main cross-block interval.
703 // First add all defs that are live out of a block.
704 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
705 SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
706 bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)];
707 bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)];
709 // Should the register be live out?
710 if (!BI.LiveOut || !RegOut)
713 IndexPair &IP = InterferenceRanges[i];
714 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " -> EB#"
715 << Bundles->getBundle(BI.MBB->getNumber(), 1)
716 << " intf [" << IP.first << ';' << IP.second << ')');
718 // The interference interval should either be invalid or overlap MBB.
719 assert((!IP.first.isValid() || IP.first < BI.Stop) && "Bad interference");
720 assert((!IP.second.isValid() || IP.second > BI.Start)
721 && "Bad interference");
723 // Check interference leaving the block.
724 if (!IP.second.isValid()) {
725 // Block is interference-free.
726 DEBUG(dbgs() << ", no interference");
728 assert(BI.LiveThrough && "No uses, but not live through block?");
729 // Block is live-through without interference.
730 DEBUG(dbgs() << ", no uses"
731 << (RegIn ? ", live-through.\n" : ", stack in.\n"));
733 SE->enterIntvAtEnd(*BI.MBB);
736 if (!BI.LiveThrough) {
737 DEBUG(dbgs() << ", not live-through.\n");
738 SE->useIntv(SE->enterIntvBefore(BI.Def), BI.Stop);
742 // Block is live-through, but entry bundle is on the stack.
743 // Reload just before the first use.
744 DEBUG(dbgs() << ", not live-in, enter before first use.\n");
745 SE->useIntv(SE->enterIntvBefore(BI.FirstUse), BI.Stop);
748 DEBUG(dbgs() << ", live-through.\n");
752 // Block has interference.
753 DEBUG(dbgs() << ", interference to " << IP.second);
755 if (!BI.LiveThrough && IP.second <= BI.Def) {
756 // The interference doesn't reach the outgoing segment.
757 DEBUG(dbgs() << " doesn't affect def from " << BI.Def << '\n');
758 SE->useIntv(BI.Def, BI.Stop);
764 // No uses in block, avoid interference by reloading as late as possible.
765 DEBUG(dbgs() << ", no uses.\n");
766 SlotIndex SegStart = SE->enterIntvAtEnd(*BI.MBB);
767 assert(SegStart >= IP.second && "Couldn't avoid interference");
771 if (IP.second.getBoundaryIndex() < BI.LastUse) {
772 // There are interference-free uses at the end of the block.
773 // Find the first use that can get the live-out register.
774 SmallVectorImpl<SlotIndex>::const_iterator UI =
775 std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(),
776 IP.second.getBoundaryIndex());
777 assert(UI != SA->UseSlots.end() && "Couldn't find last use");
779 assert(Use <= BI.LastUse && "Couldn't find last use");
780 // Only attempt a split befroe the last split point.
781 if (Use.getBaseIndex() <= BI.LastSplitPoint) {
782 DEBUG(dbgs() << ", free use at " << Use << ".\n");
783 SlotIndex SegStart = SE->enterIntvBefore(Use);
784 assert(SegStart >= IP.second && "Couldn't avoid interference");
785 assert(SegStart < BI.LastSplitPoint && "Impossible split point");
786 SE->useIntv(SegStart, BI.Stop);
791 // Interference is after the last use.
792 DEBUG(dbgs() << " after last use.\n");
793 SlotIndex SegStart = SE->enterIntvAtEnd(*BI.MBB);
794 assert(SegStart >= IP.second && "Couldn't avoid interference");
797 // Now all defs leading to live bundles are handled, do everything else.
798 for (unsigned i = 0, e = SA->LiveBlocks.size(); i != e; ++i) {
799 SplitAnalysis::BlockInfo &BI = SA->LiveBlocks[i];
800 bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)];
801 bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)];
803 // Is the register live-in?
804 if (!BI.LiveIn || !RegIn)
807 // We have an incoming register. Check for interference.
808 IndexPair &IP = InterferenceRanges[i];
810 DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0)
811 << " -> BB#" << BI.MBB->getNumber());
813 // Check interference entering the block.
814 if (!IP.first.isValid()) {
815 // Block is interference-free.
816 DEBUG(dbgs() << ", no interference");
818 assert(BI.LiveThrough && "No uses, but not live through block?");
819 // Block is live-through without interference.
821 DEBUG(dbgs() << ", no uses, live-through.\n");
822 SE->useIntv(BI.Start, BI.Stop);
824 DEBUG(dbgs() << ", no uses, stack-out.\n");
825 SE->leaveIntvAtTop(*BI.MBB);
829 if (!BI.LiveThrough) {
830 DEBUG(dbgs() << ", killed in block.\n");
831 SE->useIntv(BI.Start, SE->leaveIntvAfter(BI.Kill));
835 // Block is live-through, but exit bundle is on the stack.
836 // Spill immediately after the last use.
837 if (BI.LastUse < BI.LastSplitPoint) {
838 DEBUG(dbgs() << ", uses, stack-out.\n");
839 SE->useIntv(BI.Start, SE->leaveIntvAfter(BI.LastUse));
842 // The last use is after the last split point, it is probably an
844 DEBUG(dbgs() << ", uses at " << BI.LastUse << " after split point "
845 << BI.LastSplitPoint << ", stack-out.\n");
846 SlotIndex SegEnd = SE->leaveIntvBefore(BI.LastSplitPoint);
847 SE->useIntv(BI.Start, SegEnd);
848 // Run a double interval from the split to the last use.
849 // This makes it possible to spill the complement without affecting the
851 SE->overlapIntv(SegEnd, BI.LastUse);
854 // Register is live-through.
855 DEBUG(dbgs() << ", uses, live-through.\n");
856 SE->useIntv(BI.Start, BI.Stop);
860 // Block has interference.
861 DEBUG(dbgs() << ", interference from " << IP.first);
863 if (!BI.LiveThrough && IP.first >= BI.Kill) {
864 // The interference doesn't reach the outgoing segment.
865 DEBUG(dbgs() << " doesn't affect kill at " << BI.Kill << '\n');
866 SE->useIntv(BI.Start, BI.Kill);
871 // No uses in block, avoid interference by spilling as soon as possible.
872 DEBUG(dbgs() << ", no uses.\n");
873 SlotIndex SegEnd = SE->leaveIntvAtTop(*BI.MBB);
874 assert(SegEnd <= IP.first && "Couldn't avoid interference");
877 if (IP.first.getBaseIndex() > BI.FirstUse) {
878 // There are interference-free uses at the beginning of the block.
879 // Find the last use that can get the register.
880 SmallVectorImpl<SlotIndex>::const_iterator UI =
881 std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(),
882 IP.first.getBaseIndex());
883 assert(UI != SA->UseSlots.begin() && "Couldn't find first use");
884 SlotIndex Use = (--UI)->getBoundaryIndex();
885 DEBUG(dbgs() << ", free use at " << *UI << ".\n");
886 SlotIndex SegEnd = SE->leaveIntvAfter(Use);
887 assert(SegEnd <= IP.first && "Couldn't avoid interference");
888 SE->useIntv(BI.Start, SegEnd);
892 // Interference is before the first use.
893 DEBUG(dbgs() << " before first use.\n");
894 SlotIndex SegEnd = SE->leaveIntvAtTop(*BI.MBB);
895 assert(SegEnd <= IP.first && "Couldn't avoid interference");
900 // FIXME: Should we be more aggressive about splitting the stack region into
901 // per-block segments? The current approach allows the stack region to
902 // separate into connected components. Some components may be allocatable.
907 MF->verify(this, "After splitting live range around region");
910 // Make sure that at least one of the new intervals can allocate to PhysReg.
911 // That was the whole point of splitting the live range.
913 for (LiveRangeEdit::iterator I = LREdit.begin(), E = LREdit.end(); I != E;
915 if (!checkUncachedInterference(**I, PhysReg)) {
919 assert(found && "No allocatable intervals after pointless splitting");
924 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
925 SmallVectorImpl<LiveInterval*> &NewVRegs) {
926 BitVector LiveBundles, BestBundles;
928 unsigned BestReg = 0;
930 while (unsigned PhysReg = Order.next()) {
931 float Cost = calcInterferenceInfo(VirtReg, PhysReg);
932 if (BestReg && Cost >= BestCost)
935 SpillPlacer->placeSpills(SpillConstraints, LiveBundles);
936 // No live bundles, defer to splitSingleBlocks().
937 if (!LiveBundles.any())
940 Cost += calcGlobalSplitCost(LiveBundles);
941 if (!BestReg || Cost < BestCost) {
944 BestBundles.swap(LiveBundles);
951 splitAroundRegion(VirtReg, BestReg, BestBundles, NewVRegs);
952 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Region);
957 //===----------------------------------------------------------------------===//
959 //===----------------------------------------------------------------------===//
962 /// calcGapWeights - Compute the maximum spill weight that needs to be evicted
963 /// in order to use PhysReg between two entries in SA->UseSlots.
965 /// GapWeight[i] represents the gap between UseSlots[i] and UseSlots[i+1].
967 void RAGreedy::calcGapWeights(unsigned PhysReg,
968 SmallVectorImpl<float> &GapWeight) {
969 assert(SA->LiveBlocks.size() == 1 && "Not a local interval");
970 const SplitAnalysis::BlockInfo &BI = SA->LiveBlocks.front();
971 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
972 const unsigned NumGaps = Uses.size()-1;
974 // Start and end points for the interference check.
975 SlotIndex StartIdx = BI.LiveIn ? BI.FirstUse.getBaseIndex() : BI.FirstUse;
976 SlotIndex StopIdx = BI.LiveOut ? BI.LastUse.getBoundaryIndex() : BI.LastUse;
978 GapWeight.assign(NumGaps, 0.0f);
980 // Add interference from each overlapping register.
981 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
982 if (!query(const_cast<LiveInterval&>(SA->getParent()), *AI)
983 .checkInterference())
986 // We know that VirtReg is a continuous interval from FirstUse to LastUse,
987 // so we don't need InterferenceQuery.
989 // Interference that overlaps an instruction is counted in both gaps
990 // surrounding the instruction. The exception is interference before
991 // StartIdx and after StopIdx.
993 LiveIntervalUnion::SegmentIter IntI = PhysReg2LiveUnion[*AI].find(StartIdx);
994 for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) {
995 // Skip the gaps before IntI.
996 while (Uses[Gap+1].getBoundaryIndex() < IntI.start())
997 if (++Gap == NumGaps)
1002 // Update the gaps covered by IntI.
1003 const float weight = IntI.value()->weight;
1004 for (; Gap != NumGaps; ++Gap) {
1005 GapWeight[Gap] = std::max(GapWeight[Gap], weight);
1006 if (Uses[Gap+1].getBaseIndex() >= IntI.stop())
1015 /// getPrevMappedIndex - Return the slot index of the last non-copy instruction
1016 /// before MI that has a slot index. If MI is the first mapped instruction in
1017 /// its block, return the block start index instead.
1019 SlotIndex RAGreedy::getPrevMappedIndex(const MachineInstr *MI) {
1020 assert(MI && "Missing MachineInstr");
1021 const MachineBasicBlock *MBB = MI->getParent();
1022 MachineBasicBlock::const_iterator B = MBB->begin(), I = MI;
1024 if (!(--I)->isDebugValue() && !I->isCopy())
1025 return Indexes->getInstructionIndex(I);
1026 return Indexes->getMBBStartIdx(MBB);
1029 /// calcPrevSlots - Fill in the PrevSlot array with the index of the previous
1030 /// real non-copy instruction for each instruction in SA->UseSlots.
1032 void RAGreedy::calcPrevSlots() {
1033 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
1035 PrevSlot.reserve(Uses.size());
1036 for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
1037 const MachineInstr *MI = Indexes->getInstructionFromIndex(Uses[i]);
1038 PrevSlot.push_back(getPrevMappedIndex(MI).getDefIndex());
1042 /// nextSplitPoint - Find the next index into SA->UseSlots > i such that it may
1043 /// be beneficial to split before UseSlots[i].
1045 /// 0 is always a valid split point
1046 unsigned RAGreedy::nextSplitPoint(unsigned i) {
1047 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
1048 const unsigned Size = Uses.size();
1049 assert(i != Size && "No split points after the end");
1050 // Allow split before i when Uses[i] is not adjacent to the previous use.
1051 while (++i != Size && PrevSlot[i].getBaseIndex() <= Uses[i-1].getBaseIndex())
1056 /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
1059 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1060 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1061 assert(SA->LiveBlocks.size() == 1 && "Not a local interval");
1062 const SplitAnalysis::BlockInfo &BI = SA->LiveBlocks.front();
1064 // Note that it is possible to have an interval that is live-in or live-out
1065 // while only covering a single block - A phi-def can use undef values from
1066 // predecessors, and the block could be a single-block loop.
1067 // We don't bother doing anything clever about such a case, we simply assume
1068 // that the interval is continuous from FirstUse to LastUse. We should make
1069 // sure that we don't do anything illegal to such an interval, though.
1071 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
1072 if (Uses.size() <= 2)
1074 const unsigned NumGaps = Uses.size()-1;
1077 dbgs() << "tryLocalSplit: ";
1078 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
1079 dbgs() << ' ' << SA->UseSlots[i];
1083 // For every use, find the previous mapped non-copy instruction.
1084 // We use this to detect valid split points, and to estimate new interval
1088 unsigned BestBefore = NumGaps;
1089 unsigned BestAfter = 0;
1092 const float blockFreq = SpillPlacer->getBlockFrequency(BI.MBB->getNumber());
1093 SmallVector<float, 8> GapWeight;
1096 while (unsigned PhysReg = Order.next()) {
1097 // Keep track of the largest spill weight that would need to be evicted in
1098 // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1].
1099 calcGapWeights(PhysReg, GapWeight);
1101 // Try to find the best sequence of gaps to close.
1102 // The new spill weight must be larger than any gap interference.
1104 // We will split before Uses[SplitBefore] and after Uses[SplitAfter].
1105 unsigned SplitBefore = 0, SplitAfter = nextSplitPoint(1) - 1;
1107 // MaxGap should always be max(GapWeight[SplitBefore..SplitAfter-1]).
1108 // It is the spill weight that needs to be evicted.
1109 float MaxGap = GapWeight[0];
1110 for (unsigned i = 1; i != SplitAfter; ++i)
1111 MaxGap = std::max(MaxGap, GapWeight[i]);
1114 // Live before/after split?
1115 const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
1116 const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut;
1118 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' '
1119 << Uses[SplitBefore] << '-' << Uses[SplitAfter]
1120 << " i=" << MaxGap);
1122 // Stop before the interval gets so big we wouldn't be making progress.
1123 if (!LiveBefore && !LiveAfter) {
1124 DEBUG(dbgs() << " all\n");
1127 // Should the interval be extended or shrunk?
1129 if (MaxGap < HUGE_VALF) {
1130 // Estimate the new spill weight.
1132 // Each instruction reads and writes the register, except the first
1133 // instr doesn't read when !FirstLive, and the last instr doesn't write
1136 // We will be inserting copies before and after, so the total number of
1137 // reads and writes is 2 * EstUses.
1139 const unsigned EstUses = 2*(SplitAfter - SplitBefore) +
1140 2*(LiveBefore + LiveAfter);
1142 // Try to guess the size of the new interval. This should be trivial,
1143 // but the slot index of an inserted copy can be a lot smaller than the
1144 // instruction it is inserted before if there are many dead indexes
1147 // We measure the distance from the instruction before SplitBefore to
1148 // get a conservative estimate.
1150 // The final distance can still be different if inserting copies
1151 // triggers a slot index renumbering.
1153 const float EstWeight = normalizeSpillWeight(blockFreq * EstUses,
1154 PrevSlot[SplitBefore].distance(Uses[SplitAfter]));
1155 // Would this split be possible to allocate?
1156 // Never allocate all gaps, we wouldn't be making progress.
1157 float Diff = EstWeight - MaxGap;
1158 DEBUG(dbgs() << " w=" << EstWeight << " d=" << Diff);
1161 if (Diff > BestDiff) {
1162 DEBUG(dbgs() << " (best)");
1164 BestBefore = SplitBefore;
1165 BestAfter = SplitAfter;
1172 SplitBefore = nextSplitPoint(SplitBefore);
1173 if (SplitBefore < SplitAfter) {
1174 DEBUG(dbgs() << " shrink\n");
1175 // Recompute the max when necessary.
1176 if (GapWeight[SplitBefore - 1] >= MaxGap) {
1177 MaxGap = GapWeight[SplitBefore];
1178 for (unsigned i = SplitBefore + 1; i != SplitAfter; ++i)
1179 MaxGap = std::max(MaxGap, GapWeight[i]);
1186 // Try to extend the interval.
1187 if (SplitAfter >= NumGaps) {
1188 DEBUG(dbgs() << " end\n");
1192 DEBUG(dbgs() << " extend\n");
1193 for (unsigned e = nextSplitPoint(SplitAfter + 1) - 1;
1194 SplitAfter != e; ++SplitAfter)
1195 MaxGap = std::max(MaxGap, GapWeight[SplitAfter]);
1200 // Didn't find any candidates?
1201 if (BestBefore == NumGaps)
1204 DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore]
1205 << '-' << Uses[BestAfter] << ", " << BestDiff
1206 << ", " << (BestAfter - BestBefore + 1) << " instrs\n");
1208 SmallVector<LiveInterval*, 4> SpillRegs;
1209 LiveRangeEdit LREdit(VirtReg, NewVRegs, SpillRegs);
1213 SlotIndex SegStart = SE->enterIntvBefore(Uses[BestBefore]);
1214 SlotIndex SegStop = SE->leaveIntvAfter(Uses[BestAfter]);
1215 SE->useIntv(SegStart, SegStop);
1218 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Local);
1224 //===----------------------------------------------------------------------===//
1225 // Live Range Splitting
1226 //===----------------------------------------------------------------------===//
1228 /// trySplit - Try to split VirtReg or one of its interferences, making it
1230 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
1231 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
1232 SmallVectorImpl<LiveInterval*>&NewVRegs) {
1233 // Local intervals are handled separately.
1234 if (LIS->intervalIsInOneMBB(VirtReg)) {
1235 NamedRegionTimer T("Local Splitting", TimerGroupName, TimePassesIsEnabled);
1236 SA->analyze(&VirtReg);
1237 return tryLocalSplit(VirtReg, Order, NewVRegs);
1240 NamedRegionTimer T("Global Splitting", TimerGroupName, TimePassesIsEnabled);
1242 // Don't iterate global splitting.
1243 // Move straight to spilling if this range was produced by a global split.
1244 LiveRangeStage Stage = getStage(VirtReg);
1245 if (Stage >= RS_Block)
1248 SA->analyze(&VirtReg);
1250 // First try to split around a region spanning multiple blocks.
1251 if (Stage < RS_Region) {
1252 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1253 if (PhysReg || !NewVRegs.empty())
1257 // Then isolate blocks with multiple uses.
1258 if (Stage < RS_Block) {
1259 SplitAnalysis::BlockPtrSet Blocks;
1260 if (SA->getMultiUseBlocks(Blocks)) {
1261 SmallVector<LiveInterval*, 4> SpillRegs;
1262 LiveRangeEdit LREdit(VirtReg, NewVRegs, SpillRegs);
1264 SE->splitSingleBlocks(Blocks);
1265 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Block);
1267 MF->verify(this, "After splitting live range around basic blocks");
1271 // Don't assign any physregs.
1276 //===----------------------------------------------------------------------===//
1278 //===----------------------------------------------------------------------===//
1280 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
1281 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1282 LiveRangeStage Stage = getStage(VirtReg);
1283 if (Stage == RS_Original)
1284 LRStage[VirtReg.reg] = RS_Second;
1286 // First try assigning a free register.
1287 AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);
1288 while (unsigned PhysReg = Order.next()) {
1289 if (!checkPhysRegInterference(VirtReg, PhysReg))
1293 if (unsigned PhysReg = tryReassign(VirtReg, Order, NewVRegs))
1296 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs))
1299 assert(NewVRegs.empty() && "Cannot append to existing NewVRegs");
1301 // The first time we see a live range, don't try to split or spill.
1302 // Wait until the second time, when all smaller ranges have been allocated.
1303 // This gives a better picture of the interference to split around.
1304 if (Stage == RS_Original) {
1305 NewVRegs.push_back(&VirtReg);
1309 assert(Stage < RS_Spill && "Cannot allocate after spilling");
1311 // Try splitting VirtReg or interferences.
1312 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
1313 if (PhysReg || !NewVRegs.empty())
1316 // Finally spill VirtReg itself.
1317 NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
1318 SmallVector<LiveInterval*, 1> pendingSpills;
1319 spiller().spill(&VirtReg, NewVRegs, pendingSpills);
1321 // The live virtual register requesting allocation was spilled, so tell
1322 // the caller not to allocate anything during this round.
1326 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
1327 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
1328 << "********** Function: "
1329 << ((Value*)mf.getFunction())->getName() << '\n');
1333 MF->verify(this, "Before greedy register allocator");
1335 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
1336 Indexes = &getAnalysis<SlotIndexes>();
1337 DomTree = &getAnalysis<MachineDominatorTree>();
1338 ReservedRegs = TRI->getReservedRegs(*MF);
1339 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
1340 Loops = &getAnalysis<MachineLoopInfo>();
1341 LoopRanges = &getAnalysis<MachineLoopRanges>();
1342 Bundles = &getAnalysis<EdgeBundles>();
1343 SpillPlacer = &getAnalysis<SpillPlacement>();
1345 SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops));
1346 SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree));
1348 LRStage.resize(MRI->getNumVirtRegs());
1352 LIS->addKillFlags();
1356 NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled);
1357 VRM->rewrite(Indexes);
1360 // The pass output is in VirtRegMap. Release all the transient data.