1 //===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RAGreedy function pass for register allocation in
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "AllocationOrder.h"
17 #include "InterferenceCache.h"
18 #include "LiveDebugVariables.h"
19 #include "LiveRangeEdit.h"
20 #include "RegAllocBase.h"
22 #include "SpillPlacement.h"
24 #include "VirtRegMap.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/Function.h"
28 #include "llvm/PassAnalysisSupport.h"
29 #include "llvm/CodeGen/CalcSpillWeights.h"
30 #include "llvm/CodeGen/EdgeBundles.h"
31 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
32 #include "llvm/CodeGen/LiveStackAnalysis.h"
33 #include "llvm/CodeGen/MachineDominators.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineLoopInfo.h"
36 #include "llvm/CodeGen/MachineLoopRanges.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/CodeGen/RegAllocRegistry.h"
40 #include "llvm/CodeGen/RegisterCoalescer.h"
41 #include "llvm/Target/TargetOptions.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/raw_ostream.h"
45 #include "llvm/Support/Timer.h"
51 STATISTIC(NumGlobalSplits, "Number of split global live ranges");
52 STATISTIC(NumLocalSplits, "Number of split local live ranges");
53 STATISTIC(NumEvicted, "Number of interferences evicted");
55 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
56 createGreedyRegisterAllocator);
59 class RAGreedy : public MachineFunctionPass,
61 private LiveRangeEdit::Delegate {
65 BitVector ReservedRegs;
70 MachineDominatorTree *DomTree;
71 MachineLoopInfo *Loops;
72 MachineLoopRanges *LoopRanges;
74 SpillPlacement *SpillPlacer;
77 std::auto_ptr<Spiller> SpillerInstance;
78 std::priority_queue<std::pair<unsigned, unsigned> > Queue;
80 // Live ranges pass through a number of stages as we try to allocate them.
81 // Some of the stages may also create new live ranges:
83 // - Region splitting.
84 // - Per-block splitting.
88 // Ranges produced by one of the stages skip the previous stages when they are
89 // dequeued. This improves performance because we can skip interference checks
90 // that are unlikely to give any results. It also guarantees that the live
91 // range splitting algorithm terminates, something that is otherwise hard to
94 RS_New, ///< Never seen before.
95 RS_First, ///< First time in the queue.
96 RS_Second, ///< Second time in the queue.
97 RS_Region, ///< Produced by region splitting.
98 RS_Block, ///< Produced by per-block splitting.
99 RS_Local, ///< Produced by local splitting.
100 RS_Spill ///< Produced by spilling.
103 IndexedMap<unsigned char, VirtReg2IndexFunctor> LRStage;
105 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
106 return LiveRangeStage(LRStage[VirtReg.reg]);
109 template<typename Iterator>
110 void setStage(Iterator Begin, Iterator End, LiveRangeStage NewStage) {
111 LRStage.resize(MRI->getNumVirtRegs());
112 for (;Begin != End; ++Begin) {
113 unsigned Reg = (*Begin)->reg;
114 if (LRStage[Reg] == RS_New)
115 LRStage[Reg] = NewStage;
120 std::auto_ptr<SplitAnalysis> SA;
121 std::auto_ptr<SplitEditor> SE;
123 /// Cached per-block interference maps
124 InterferenceCache IntfCache;
126 /// All basic blocks where the current register is live.
127 SmallVector<SpillPlacement::BlockConstraint, 8> SplitConstraints;
129 /// Global live range splitting candidate info.
130 struct GlobalSplitCandidate {
132 BitVector LiveBundles;
135 /// Candidate info for for each PhysReg in AllocationOrder.
136 /// This vector never shrinks, but grows to the size of the largest register
138 SmallVector<GlobalSplitCandidate, 32> GlobalCand;
140 /// For every instruction in SA->UseSlots, store the previous non-copy
142 SmallVector<SlotIndex, 8> PrevSlot;
147 /// Return the pass name.
148 virtual const char* getPassName() const {
149 return "Greedy Register Allocator";
152 /// RAGreedy analysis usage.
153 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
154 virtual void releaseMemory();
155 virtual Spiller &spiller() { return *SpillerInstance; }
156 virtual void enqueue(LiveInterval *LI);
157 virtual LiveInterval *dequeue();
158 virtual unsigned selectOrSplit(LiveInterval&,
159 SmallVectorImpl<LiveInterval*>&);
161 /// Perform register allocation.
162 virtual bool runOnMachineFunction(MachineFunction &mf);
167 void LRE_WillEraseInstruction(MachineInstr*);
168 bool LRE_CanEraseVirtReg(unsigned);
169 void LRE_WillShrinkVirtReg(unsigned);
170 void LRE_DidCloneVirtReg(unsigned, unsigned);
172 float calcSplitConstraints(unsigned);
173 float calcGlobalSplitCost(const BitVector&);
174 void splitAroundRegion(LiveInterval&, unsigned, const BitVector&,
175 SmallVectorImpl<LiveInterval*>&);
176 void calcGapWeights(unsigned, SmallVectorImpl<float>&);
177 SlotIndex getPrevMappedIndex(const MachineInstr*);
178 void calcPrevSlots();
179 unsigned nextSplitPoint(unsigned);
180 bool canEvictInterference(LiveInterval&, unsigned, float&);
182 unsigned tryEvict(LiveInterval&, AllocationOrder&,
183 SmallVectorImpl<LiveInterval*>&);
184 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
185 SmallVectorImpl<LiveInterval*>&);
186 unsigned tryLocalSplit(LiveInterval&, AllocationOrder&,
187 SmallVectorImpl<LiveInterval*>&);
188 unsigned trySplit(LiveInterval&, AllocationOrder&,
189 SmallVectorImpl<LiveInterval*>&);
191 } // end anonymous namespace
193 char RAGreedy::ID = 0;
195 FunctionPass* llvm::createGreedyRegisterAllocator() {
196 return new RAGreedy();
199 RAGreedy::RAGreedy(): MachineFunctionPass(ID), LRStage(RS_New) {
200 initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
201 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
202 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
203 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
204 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
205 initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
206 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
207 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
208 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
209 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
210 initializeMachineLoopRangesPass(*PassRegistry::getPassRegistry());
211 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
212 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
213 initializeSpillPlacementPass(*PassRegistry::getPassRegistry());
216 void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
217 AU.setPreservesCFG();
218 AU.addRequired<AliasAnalysis>();
219 AU.addPreserved<AliasAnalysis>();
220 AU.addRequired<LiveIntervals>();
221 AU.addRequired<SlotIndexes>();
222 AU.addPreserved<SlotIndexes>();
223 AU.addRequired<LiveDebugVariables>();
224 AU.addPreserved<LiveDebugVariables>();
226 AU.addRequiredID(StrongPHIEliminationID);
227 AU.addRequiredTransitive<RegisterCoalescer>();
228 AU.addRequired<CalculateSpillWeights>();
229 AU.addRequired<LiveStacks>();
230 AU.addPreserved<LiveStacks>();
231 AU.addRequired<MachineDominatorTree>();
232 AU.addPreserved<MachineDominatorTree>();
233 AU.addRequired<MachineLoopInfo>();
234 AU.addPreserved<MachineLoopInfo>();
235 AU.addRequired<MachineLoopRanges>();
236 AU.addPreserved<MachineLoopRanges>();
237 AU.addRequired<VirtRegMap>();
238 AU.addPreserved<VirtRegMap>();
239 AU.addRequired<EdgeBundles>();
240 AU.addRequired<SpillPlacement>();
241 MachineFunctionPass::getAnalysisUsage(AU);
245 //===----------------------------------------------------------------------===//
246 // LiveRangeEdit delegate methods
247 //===----------------------------------------------------------------------===//
249 void RAGreedy::LRE_WillEraseInstruction(MachineInstr *MI) {
250 // LRE itself will remove from SlotIndexes and parent basic block.
251 VRM->RemoveMachineInstrFromMaps(MI);
254 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
255 if (unsigned PhysReg = VRM->getPhys(VirtReg)) {
256 unassign(LIS->getInterval(VirtReg), PhysReg);
259 // Unassigned virtreg is probably in the priority queue.
260 // RegAllocBase will erase it after dequeueing.
264 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) {
265 unsigned PhysReg = VRM->getPhys(VirtReg);
269 // Register is assigned, put it back on the queue for reassignment.
270 LiveInterval &LI = LIS->getInterval(VirtReg);
271 unassign(LI, PhysReg);
275 void RAGreedy::LRE_DidCloneVirtReg(unsigned New, unsigned Old) {
276 // LRE may clone a virtual register because dead code elimination causes it to
277 // be split into connected components. Ensure that the new register gets the
278 // same stage as the parent.
280 LRStage[New] = LRStage[Old];
283 void RAGreedy::releaseMemory() {
284 SpillerInstance.reset(0);
286 RegAllocBase::releaseMemory();
289 void RAGreedy::enqueue(LiveInterval *LI) {
290 // Prioritize live ranges by size, assigning larger ranges first.
291 // The queue holds (size, reg) pairs.
292 const unsigned Size = LI->getSize();
293 const unsigned Reg = LI->reg;
294 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
295 "Can only enqueue virtual registers");
299 if (LRStage[Reg] == RS_New)
300 LRStage[Reg] = RS_First;
302 if (LRStage[Reg] == RS_Second)
303 // Unsplit ranges that couldn't be allocated immediately are deferred until
304 // everything else has been allocated. Long ranges are allocated last so
305 // they are split against realistic interference.
306 Prio = (1u << 31) - Size;
308 // Everything else is allocated in long->short order. Long ranges that don't
309 // fit should be spilled ASAP so they don't create interference.
310 Prio = (1u << 31) + Size;
312 // Boost ranges that have a physical register hint.
313 if (TargetRegisterInfo::isPhysicalRegister(VRM->getRegAllocPref(Reg)))
317 Queue.push(std::make_pair(Prio, Reg));
320 LiveInterval *RAGreedy::dequeue() {
323 LiveInterval *LI = &LIS->getInterval(Queue.top().second);
328 //===----------------------------------------------------------------------===//
329 // Interference eviction
330 //===----------------------------------------------------------------------===//
332 /// canEvict - Return true if all interferences between VirtReg and PhysReg can
333 /// be evicted. Set maxWeight to the maximal spill weight of an interference.
334 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
337 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
338 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
339 // If there is 10 or more interferences, chances are one is smaller.
340 if (Q.collectInterferingVRegs(10) >= 10)
343 // Check if any interfering live range is heavier than VirtReg.
344 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
345 LiveInterval *Intf = Q.interferingVRegs()[i];
346 if (TargetRegisterInfo::isPhysicalRegister(Intf->reg))
348 if (Intf->weight >= VirtReg.weight)
350 Weight = std::max(Weight, Intf->weight);
357 /// tryEvict - Try to evict all interferences for a physreg.
358 /// @param VirtReg Currently unassigned virtual register.
359 /// @param Order Physregs to try.
360 /// @return Physreg to assign VirtReg, or 0.
361 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
362 AllocationOrder &Order,
363 SmallVectorImpl<LiveInterval*> &NewVRegs){
364 NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled);
366 // Keep track of the lightest single interference seen so far.
367 float BestWeight = 0;
368 unsigned BestPhys = 0;
371 while (unsigned PhysReg = Order.next()) {
373 if (!canEvictInterference(VirtReg, PhysReg, Weight))
376 // This is an eviction candidate.
377 DEBUG(dbgs() << "max " << PrintReg(PhysReg, TRI) << " interference = "
379 if (BestPhys && Weight >= BestWeight)
385 // Stop if the hint can be used.
386 if (Order.isHint(PhysReg))
393 DEBUG(dbgs() << "evicting " << PrintReg(BestPhys, TRI) << " interference\n");
394 for (const unsigned *AliasI = TRI->getOverlaps(BestPhys); *AliasI; ++AliasI) {
395 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
396 assert(Q.seenAllInterferences() && "Didn't check all interfererences.");
397 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
398 LiveInterval *Intf = Q.interferingVRegs()[i];
399 unassign(*Intf, VRM->getPhys(Intf->reg));
401 NewVRegs.push_back(Intf);
408 //===----------------------------------------------------------------------===//
410 //===----------------------------------------------------------------------===//
412 /// calcSplitConstraints - Fill out the SplitConstraints vector based on the
413 /// interference pattern in Physreg and its aliases. Return the static cost of
414 /// this split, assuming that all preferences in SplitConstraints are met.
415 float RAGreedy::calcSplitConstraints(unsigned PhysReg) {
416 InterferenceCache::Cursor Intf(IntfCache, PhysReg);
417 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
419 // Reset interference dependent info.
420 SplitConstraints.resize(UseBlocks.size());
421 float StaticCost = 0;
422 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
423 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
424 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
426 BC.Number = BI.MBB->getNumber();
427 Intf.moveToBlock(BC.Number);
428 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
429 BC.Exit = BI.LiveOut ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
431 if (!Intf.hasInterference())
434 // Number of spill code instructions to insert.
437 // Interference for the live-in value.
439 if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number))
440 BC.Entry = SpillPlacement::MustSpill, ++Ins;
441 else if (Intf.first() < BI.FirstUse)
442 BC.Entry = SpillPlacement::PrefSpill, ++Ins;
443 else if (Intf.first() < (BI.LiveThrough ? BI.LastUse : BI.Kill))
447 // Interference for the live-out value.
449 if (Intf.last() >= SA->getLastSplitPoint(BC.Number))
450 BC.Exit = SpillPlacement::MustSpill, ++Ins;
451 else if (Intf.last() > BI.LastUse)
452 BC.Exit = SpillPlacement::PrefSpill, ++Ins;
453 else if (Intf.last() > (BI.LiveThrough ? BI.FirstUse : BI.Def))
457 // Accumulate the total frequency of inserted spill code.
459 StaticCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
462 // Now handle the live-through blocks without uses.
463 ArrayRef<unsigned> ThroughBlocks = SA->getThroughBlocks();
464 SplitConstraints.resize(UseBlocks.size() + ThroughBlocks.size());
465 for (unsigned i = 0; i != ThroughBlocks.size(); ++i) {
466 SpillPlacement::BlockConstraint BC = SplitConstraints[UseBlocks.size() + i];
467 BC.Number = ThroughBlocks[i];
468 BC.Entry = SpillPlacement::DontCare;
469 BC.Exit = SpillPlacement::DontCare;
471 Intf.moveToBlock(BC.Number);
472 if (!Intf.hasInterference())
475 // Interference for the live-in value.
476 if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number))
477 BC.Entry = SpillPlacement::MustSpill;
479 BC.Entry = SpillPlacement::PrefSpill;
481 // Interference for the live-out value.
482 if (Intf.last() >= SA->getLastSplitPoint(BC.Number))
483 BC.Exit = SpillPlacement::MustSpill;
485 BC.Exit = SpillPlacement::PrefSpill;
492 /// calcGlobalSplitCost - Return the global split cost of following the split
493 /// pattern in LiveBundles. This cost should be added to the local cost of the
494 /// interference pattern in SplitConstraints.
496 float RAGreedy::calcGlobalSplitCost(const BitVector &LiveBundles) {
497 float GlobalCost = 0;
498 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
499 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
500 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
501 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
502 bool RegIn = LiveBundles[Bundles->getBundle(BC.Number, 0)];
503 bool RegOut = LiveBundles[Bundles->getBundle(BC.Number, 1)];
507 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg);
509 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg);
511 GlobalCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
514 ArrayRef<unsigned> ThroughBlocks = SA->getThroughBlocks();
515 SplitConstraints.resize(UseBlocks.size() + ThroughBlocks.size());
516 for (unsigned i = 0; i != ThroughBlocks.size(); ++i) {
517 unsigned Number = ThroughBlocks[i];
518 bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)];
519 bool RegOut = LiveBundles[Bundles->getBundle(Number, 1)];
521 GlobalCost += SpillPlacer->getBlockFrequency(Number);
526 /// splitAroundRegion - Split VirtReg around the region determined by
527 /// LiveBundles. Make an effort to avoid interference from PhysReg.
529 /// The 'register' interval is going to contain as many uses as possible while
530 /// avoiding interference. The 'stack' interval is the complement constructed by
531 /// SplitEditor. It will contain the rest.
533 void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, unsigned PhysReg,
534 const BitVector &LiveBundles,
535 SmallVectorImpl<LiveInterval*> &NewVRegs) {
537 dbgs() << "Splitting around region for " << PrintReg(PhysReg, TRI)
539 for (int i = LiveBundles.find_first(); i>=0; i = LiveBundles.find_next(i))
540 dbgs() << " EB#" << i;
544 InterferenceCache::Cursor Intf(IntfCache, PhysReg);
545 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
548 // Create the main cross-block interval.
551 // First add all defs that are live out of a block.
552 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
553 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
554 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
555 bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)];
556 bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)];
558 // Should the register be live out?
559 if (!BI.LiveOut || !RegOut)
562 SlotIndex Start, Stop;
563 tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
564 Intf.moveToBlock(BI.MBB->getNumber());
565 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " -> EB#"
566 << Bundles->getBundle(BI.MBB->getNumber(), 1)
567 << " [" << Start << ';'
568 << SA->getLastSplitPoint(BI.MBB->getNumber()) << '-' << Stop
569 << ") intf [" << Intf.first() << ';' << Intf.last() << ')');
571 // The interference interval should either be invalid or overlap MBB.
572 assert((!Intf.hasInterference() || Intf.first() < Stop)
573 && "Bad interference");
574 assert((!Intf.hasInterference() || Intf.last() > Start)
575 && "Bad interference");
577 // Check interference leaving the block.
578 if (!Intf.hasInterference()) {
579 // Block is interference-free.
580 DEBUG(dbgs() << ", no interference");
581 if (!BI.LiveThrough) {
582 DEBUG(dbgs() << ", not live-through.\n");
583 SE->useIntv(SE->enterIntvBefore(BI.Def), Stop);
587 // Block is live-through, but entry bundle is on the stack.
588 // Reload just before the first use.
589 DEBUG(dbgs() << ", not live-in, enter before first use.\n");
590 SE->useIntv(SE->enterIntvBefore(BI.FirstUse), Stop);
593 DEBUG(dbgs() << ", live-through.\n");
597 // Block has interference.
598 DEBUG(dbgs() << ", interference to " << Intf.last());
600 if (!BI.LiveThrough && Intf.last() <= BI.Def) {
601 // The interference doesn't reach the outgoing segment.
602 DEBUG(dbgs() << " doesn't affect def from " << BI.Def << '\n');
603 SE->useIntv(BI.Def, Stop);
607 SlotIndex LastSplitPoint = SA->getLastSplitPoint(BI.MBB->getNumber());
608 if (Intf.last().getBoundaryIndex() < BI.LastUse) {
609 // There are interference-free uses at the end of the block.
610 // Find the first use that can get the live-out register.
611 SmallVectorImpl<SlotIndex>::const_iterator UI =
612 std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(),
613 Intf.last().getBoundaryIndex());
614 assert(UI != SA->UseSlots.end() && "Couldn't find last use");
616 assert(Use <= BI.LastUse && "Couldn't find last use");
617 // Only attempt a split befroe the last split point.
618 if (Use.getBaseIndex() <= LastSplitPoint) {
619 DEBUG(dbgs() << ", free use at " << Use << ".\n");
620 SlotIndex SegStart = SE->enterIntvBefore(Use);
621 assert(SegStart >= Intf.last() && "Couldn't avoid interference");
622 assert(SegStart < LastSplitPoint && "Impossible split point");
623 SE->useIntv(SegStart, Stop);
628 // Interference is after the last use.
629 DEBUG(dbgs() << " after last use.\n");
630 SlotIndex SegStart = SE->enterIntvAtEnd(*BI.MBB);
631 assert(SegStart >= Intf.last() && "Couldn't avoid interference");
634 // Now all defs leading to live bundles are handled, do everything else.
635 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
636 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
637 bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)];
638 bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)];
640 // Is the register live-in?
641 if (!BI.LiveIn || !RegIn)
644 // We have an incoming register. Check for interference.
645 SlotIndex Start, Stop;
646 tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
647 Intf.moveToBlock(BI.MBB->getNumber());
648 DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0)
649 << " -> BB#" << BI.MBB->getNumber() << " [" << Start << ';'
650 << SA->getLastSplitPoint(BI.MBB->getNumber()) << '-' << Stop
653 // Check interference entering the block.
654 if (!Intf.hasInterference()) {
655 // Block is interference-free.
656 DEBUG(dbgs() << ", no interference");
657 if (!BI.LiveThrough) {
658 DEBUG(dbgs() << ", killed in block.\n");
659 SE->useIntv(Start, SE->leaveIntvAfter(BI.Kill));
663 SlotIndex LastSplitPoint = SA->getLastSplitPoint(BI.MBB->getNumber());
664 // Block is live-through, but exit bundle is on the stack.
665 // Spill immediately after the last use.
666 if (BI.LastUse < LastSplitPoint) {
667 DEBUG(dbgs() << ", uses, stack-out.\n");
668 SE->useIntv(Start, SE->leaveIntvAfter(BI.LastUse));
671 // The last use is after the last split point, it is probably an
673 DEBUG(dbgs() << ", uses at " << BI.LastUse << " after split point "
674 << LastSplitPoint << ", stack-out.\n");
675 SlotIndex SegEnd = SE->leaveIntvBefore(LastSplitPoint);
676 SE->useIntv(Start, SegEnd);
677 // Run a double interval from the split to the last use.
678 // This makes it possible to spill the complement without affecting the
680 SE->overlapIntv(SegEnd, BI.LastUse);
683 // Register is live-through.
684 DEBUG(dbgs() << ", uses, live-through.\n");
685 SE->useIntv(Start, Stop);
689 // Block has interference.
690 DEBUG(dbgs() << ", interference from " << Intf.first());
692 if (!BI.LiveThrough && Intf.first() >= BI.Kill) {
693 // The interference doesn't reach the outgoing segment.
694 DEBUG(dbgs() << " doesn't affect kill at " << BI.Kill << '\n');
695 SE->useIntv(Start, BI.Kill);
699 if (Intf.first().getBaseIndex() > BI.FirstUse) {
700 // There are interference-free uses at the beginning of the block.
701 // Find the last use that can get the register.
702 SmallVectorImpl<SlotIndex>::const_iterator UI =
703 std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(),
704 Intf.first().getBaseIndex());
705 assert(UI != SA->UseSlots.begin() && "Couldn't find first use");
706 SlotIndex Use = (--UI)->getBoundaryIndex();
707 DEBUG(dbgs() << ", free use at " << *UI << ".\n");
708 SlotIndex SegEnd = SE->leaveIntvAfter(Use);
709 assert(SegEnd <= Intf.first() && "Couldn't avoid interference");
710 SE->useIntv(Start, SegEnd);
714 // Interference is before the first use.
715 DEBUG(dbgs() << " before first use.\n");
716 SlotIndex SegEnd = SE->leaveIntvAtTop(*BI.MBB);
717 assert(SegEnd <= Intf.first() && "Couldn't avoid interference");
720 // Handle live-through blocks.
721 ArrayRef<unsigned> ThroughBlocks = SA->getThroughBlocks();
722 for (unsigned i = 0; i != ThroughBlocks.size(); ++i) {
723 unsigned Number = ThroughBlocks[i];
724 bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)];
725 bool RegOut = LiveBundles[Bundles->getBundle(Number, 1)];
726 DEBUG(dbgs() << "Live through BB#" << Number << '\n');
727 if (RegIn && RegOut) {
728 Intf.moveToBlock(Number);
729 if (!Intf.hasInterference()) {
730 SE->useIntv(Indexes->getMBBStartIdx(Number),
731 Indexes->getMBBEndIdx(Number));
735 MachineBasicBlock *MBB = MF->getBlockNumbered(Number);
737 SE->leaveIntvAtTop(*MBB);
739 SE->enterIntvAtEnd(*MBB);
744 // FIXME: Should we be more aggressive about splitting the stack region into
745 // per-block segments? The current approach allows the stack region to
746 // separate into connected components. Some components may be allocatable.
751 MF->verify(this, "After splitting live range around region");
754 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
755 SmallVectorImpl<LiveInterval*> &NewVRegs) {
756 BitVector LiveBundles, BestBundles;
758 unsigned BestReg = 0;
761 for (unsigned Cand = 0; unsigned PhysReg = Order.next(); ++Cand) {
762 if (GlobalCand.size() <= Cand)
763 GlobalCand.resize(Cand+1);
764 GlobalCand[Cand].PhysReg = PhysReg;
766 float Cost = calcSplitConstraints(PhysReg);
767 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = " << Cost);
768 if (BestReg && Cost >= BestCost) {
769 DEBUG(dbgs() << " higher.\n");
773 SpillPlacer->placeSpills(SplitConstraints, LiveBundles);
774 // No live bundles, defer to splitSingleBlocks().
775 if (!LiveBundles.any()) {
776 DEBUG(dbgs() << " no bundles.\n");
780 Cost += calcGlobalSplitCost(LiveBundles);
782 dbgs() << ", total = " << Cost << " with bundles";
783 for (int i = LiveBundles.find_first(); i>=0; i = LiveBundles.find_next(i))
784 dbgs() << " EB#" << i;
787 if (!BestReg || Cost < BestCost) {
789 BestCost = 0.98f * Cost; // Prevent rounding effects.
790 BestBundles.swap(LiveBundles);
797 splitAroundRegion(VirtReg, BestReg, BestBundles, NewVRegs);
798 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Region);
803 //===----------------------------------------------------------------------===//
805 //===----------------------------------------------------------------------===//
808 /// calcGapWeights - Compute the maximum spill weight that needs to be evicted
809 /// in order to use PhysReg between two entries in SA->UseSlots.
811 /// GapWeight[i] represents the gap between UseSlots[i] and UseSlots[i+1].
813 void RAGreedy::calcGapWeights(unsigned PhysReg,
814 SmallVectorImpl<float> &GapWeight) {
815 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
816 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
817 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
818 const unsigned NumGaps = Uses.size()-1;
820 // Start and end points for the interference check.
821 SlotIndex StartIdx = BI.LiveIn ? BI.FirstUse.getBaseIndex() : BI.FirstUse;
822 SlotIndex StopIdx = BI.LiveOut ? BI.LastUse.getBoundaryIndex() : BI.LastUse;
824 GapWeight.assign(NumGaps, 0.0f);
826 // Add interference from each overlapping register.
827 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
828 if (!query(const_cast<LiveInterval&>(SA->getParent()), *AI)
829 .checkInterference())
832 // We know that VirtReg is a continuous interval from FirstUse to LastUse,
833 // so we don't need InterferenceQuery.
835 // Interference that overlaps an instruction is counted in both gaps
836 // surrounding the instruction. The exception is interference before
837 // StartIdx and after StopIdx.
839 LiveIntervalUnion::SegmentIter IntI = PhysReg2LiveUnion[*AI].find(StartIdx);
840 for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) {
841 // Skip the gaps before IntI.
842 while (Uses[Gap+1].getBoundaryIndex() < IntI.start())
843 if (++Gap == NumGaps)
848 // Update the gaps covered by IntI.
849 const float weight = IntI.value()->weight;
850 for (; Gap != NumGaps; ++Gap) {
851 GapWeight[Gap] = std::max(GapWeight[Gap], weight);
852 if (Uses[Gap+1].getBaseIndex() >= IntI.stop())
861 /// getPrevMappedIndex - Return the slot index of the last non-copy instruction
862 /// before MI that has a slot index. If MI is the first mapped instruction in
863 /// its block, return the block start index instead.
865 SlotIndex RAGreedy::getPrevMappedIndex(const MachineInstr *MI) {
866 assert(MI && "Missing MachineInstr");
867 const MachineBasicBlock *MBB = MI->getParent();
868 MachineBasicBlock::const_iterator B = MBB->begin(), I = MI;
870 if (!(--I)->isDebugValue() && !I->isCopy())
871 return Indexes->getInstructionIndex(I);
872 return Indexes->getMBBStartIdx(MBB);
875 /// calcPrevSlots - Fill in the PrevSlot array with the index of the previous
876 /// real non-copy instruction for each instruction in SA->UseSlots.
878 void RAGreedy::calcPrevSlots() {
879 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
881 PrevSlot.reserve(Uses.size());
882 for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
883 const MachineInstr *MI = Indexes->getInstructionFromIndex(Uses[i]);
884 PrevSlot.push_back(getPrevMappedIndex(MI).getDefIndex());
888 /// nextSplitPoint - Find the next index into SA->UseSlots > i such that it may
889 /// be beneficial to split before UseSlots[i].
891 /// 0 is always a valid split point
892 unsigned RAGreedy::nextSplitPoint(unsigned i) {
893 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
894 const unsigned Size = Uses.size();
895 assert(i != Size && "No split points after the end");
896 // Allow split before i when Uses[i] is not adjacent to the previous use.
897 while (++i != Size && PrevSlot[i].getBaseIndex() <= Uses[i-1].getBaseIndex())
902 /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
905 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
906 SmallVectorImpl<LiveInterval*> &NewVRegs) {
907 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
908 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
910 // Note that it is possible to have an interval that is live-in or live-out
911 // while only covering a single block - A phi-def can use undef values from
912 // predecessors, and the block could be a single-block loop.
913 // We don't bother doing anything clever about such a case, we simply assume
914 // that the interval is continuous from FirstUse to LastUse. We should make
915 // sure that we don't do anything illegal to such an interval, though.
917 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots;
918 if (Uses.size() <= 2)
920 const unsigned NumGaps = Uses.size()-1;
923 dbgs() << "tryLocalSplit: ";
924 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
925 dbgs() << ' ' << SA->UseSlots[i];
929 // For every use, find the previous mapped non-copy instruction.
930 // We use this to detect valid split points, and to estimate new interval
934 unsigned BestBefore = NumGaps;
935 unsigned BestAfter = 0;
938 const float blockFreq = SpillPlacer->getBlockFrequency(BI.MBB->getNumber());
939 SmallVector<float, 8> GapWeight;
942 while (unsigned PhysReg = Order.next()) {
943 // Keep track of the largest spill weight that would need to be evicted in
944 // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1].
945 calcGapWeights(PhysReg, GapWeight);
947 // Try to find the best sequence of gaps to close.
948 // The new spill weight must be larger than any gap interference.
950 // We will split before Uses[SplitBefore] and after Uses[SplitAfter].
951 unsigned SplitBefore = 0, SplitAfter = nextSplitPoint(1) - 1;
953 // MaxGap should always be max(GapWeight[SplitBefore..SplitAfter-1]).
954 // It is the spill weight that needs to be evicted.
955 float MaxGap = GapWeight[0];
956 for (unsigned i = 1; i != SplitAfter; ++i)
957 MaxGap = std::max(MaxGap, GapWeight[i]);
960 // Live before/after split?
961 const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
962 const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut;
964 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' '
965 << Uses[SplitBefore] << '-' << Uses[SplitAfter]
968 // Stop before the interval gets so big we wouldn't be making progress.
969 if (!LiveBefore && !LiveAfter) {
970 DEBUG(dbgs() << " all\n");
973 // Should the interval be extended or shrunk?
975 if (MaxGap < HUGE_VALF) {
976 // Estimate the new spill weight.
978 // Each instruction reads and writes the register, except the first
979 // instr doesn't read when !FirstLive, and the last instr doesn't write
982 // We will be inserting copies before and after, so the total number of
983 // reads and writes is 2 * EstUses.
985 const unsigned EstUses = 2*(SplitAfter - SplitBefore) +
986 2*(LiveBefore + LiveAfter);
988 // Try to guess the size of the new interval. This should be trivial,
989 // but the slot index of an inserted copy can be a lot smaller than the
990 // instruction it is inserted before if there are many dead indexes
993 // We measure the distance from the instruction before SplitBefore to
994 // get a conservative estimate.
996 // The final distance can still be different if inserting copies
997 // triggers a slot index renumbering.
999 const float EstWeight = normalizeSpillWeight(blockFreq * EstUses,
1000 PrevSlot[SplitBefore].distance(Uses[SplitAfter]));
1001 // Would this split be possible to allocate?
1002 // Never allocate all gaps, we wouldn't be making progress.
1003 float Diff = EstWeight - MaxGap;
1004 DEBUG(dbgs() << " w=" << EstWeight << " d=" << Diff);
1007 if (Diff > BestDiff) {
1008 DEBUG(dbgs() << " (best)");
1010 BestBefore = SplitBefore;
1011 BestAfter = SplitAfter;
1018 SplitBefore = nextSplitPoint(SplitBefore);
1019 if (SplitBefore < SplitAfter) {
1020 DEBUG(dbgs() << " shrink\n");
1021 // Recompute the max when necessary.
1022 if (GapWeight[SplitBefore - 1] >= MaxGap) {
1023 MaxGap = GapWeight[SplitBefore];
1024 for (unsigned i = SplitBefore + 1; i != SplitAfter; ++i)
1025 MaxGap = std::max(MaxGap, GapWeight[i]);
1032 // Try to extend the interval.
1033 if (SplitAfter >= NumGaps) {
1034 DEBUG(dbgs() << " end\n");
1038 DEBUG(dbgs() << " extend\n");
1039 for (unsigned e = nextSplitPoint(SplitAfter + 1) - 1;
1040 SplitAfter != e; ++SplitAfter)
1041 MaxGap = std::max(MaxGap, GapWeight[SplitAfter]);
1046 // Didn't find any candidates?
1047 if (BestBefore == NumGaps)
1050 DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore]
1051 << '-' << Uses[BestAfter] << ", " << BestDiff
1052 << ", " << (BestAfter - BestBefore + 1) << " instrs\n");
1054 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
1058 SlotIndex SegStart = SE->enterIntvBefore(Uses[BestBefore]);
1059 SlotIndex SegStop = SE->leaveIntvAfter(Uses[BestAfter]);
1060 SE->useIntv(SegStart, SegStop);
1063 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Local);
1069 //===----------------------------------------------------------------------===//
1070 // Live Range Splitting
1071 //===----------------------------------------------------------------------===//
1073 /// trySplit - Try to split VirtReg or one of its interferences, making it
1075 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
1076 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
1077 SmallVectorImpl<LiveInterval*>&NewVRegs) {
1078 // Local intervals are handled separately.
1079 if (LIS->intervalIsInOneMBB(VirtReg)) {
1080 NamedRegionTimer T("Local Splitting", TimerGroupName, TimePassesIsEnabled);
1081 SA->analyze(&VirtReg);
1082 return tryLocalSplit(VirtReg, Order, NewVRegs);
1085 NamedRegionTimer T("Global Splitting", TimerGroupName, TimePassesIsEnabled);
1087 // Don't iterate global splitting.
1088 // Move straight to spilling if this range was produced by a global split.
1089 LiveRangeStage Stage = getStage(VirtReg);
1090 if (Stage >= RS_Block)
1093 SA->analyze(&VirtReg);
1095 // First try to split around a region spanning multiple blocks.
1096 if (Stage < RS_Region) {
1097 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1098 if (PhysReg || !NewVRegs.empty())
1102 // Then isolate blocks with multiple uses.
1103 if (Stage < RS_Block) {
1104 SplitAnalysis::BlockPtrSet Blocks;
1105 if (SA->getMultiUseBlocks(Blocks)) {
1106 LiveRangeEdit LREdit(VirtReg, NewVRegs, this);
1108 SE->splitSingleBlocks(Blocks);
1109 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Block);
1111 MF->verify(this, "After splitting live range around basic blocks");
1115 // Don't assign any physregs.
1120 //===----------------------------------------------------------------------===//
1122 //===----------------------------------------------------------------------===//
1124 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
1125 SmallVectorImpl<LiveInterval*> &NewVRegs) {
1126 // First try assigning a free register.
1127 AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);
1128 while (unsigned PhysReg = Order.next()) {
1129 if (!checkPhysRegInterference(VirtReg, PhysReg))
1133 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs))
1136 assert(NewVRegs.empty() && "Cannot append to existing NewVRegs");
1138 // The first time we see a live range, don't try to split or spill.
1139 // Wait until the second time, when all smaller ranges have been allocated.
1140 // This gives a better picture of the interference to split around.
1141 LiveRangeStage Stage = getStage(VirtReg);
1142 if (Stage == RS_First) {
1143 LRStage[VirtReg.reg] = RS_Second;
1144 DEBUG(dbgs() << "wait for second round\n");
1145 NewVRegs.push_back(&VirtReg);
1149 assert(Stage < RS_Spill && "Cannot allocate after spilling");
1151 // Try splitting VirtReg or interferences.
1152 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
1153 if (PhysReg || !NewVRegs.empty())
1156 // Finally spill VirtReg itself.
1157 NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
1158 LiveRangeEdit LRE(VirtReg, NewVRegs, this);
1159 spiller().spill(LRE);
1160 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Spill);
1163 MF->verify(this, "After spilling");
1165 // The live virtual register requesting allocation was spilled, so tell
1166 // the caller not to allocate anything during this round.
1170 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
1171 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
1172 << "********** Function: "
1173 << ((Value*)mf.getFunction())->getName() << '\n');
1177 MF->verify(this, "Before greedy register allocator");
1179 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
1180 Indexes = &getAnalysis<SlotIndexes>();
1181 DomTree = &getAnalysis<MachineDominatorTree>();
1182 ReservedRegs = TRI->getReservedRegs(*MF);
1183 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
1184 Loops = &getAnalysis<MachineLoopInfo>();
1185 LoopRanges = &getAnalysis<MachineLoopRanges>();
1186 Bundles = &getAnalysis<EdgeBundles>();
1187 SpillPlacer = &getAnalysis<SpillPlacement>();
1189 SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops));
1190 SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree));
1192 LRStage.resize(MRI->getNumVirtRegs());
1193 IntfCache.init(MF, &PhysReg2LiveUnion[0], Indexes, TRI);
1197 LIS->addKillFlags();
1201 NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled);
1202 VRM->rewrite(Indexes);
1205 // Write out new DBG_VALUE instructions.
1206 getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
1208 // The pass output is in VirtRegMap. Release all the transient data.