1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
16 #include "PhysRegTracker.h"
17 #include "VirtRegMap.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/CodeGen/MachineLoopInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/Passes.h"
24 #include "llvm/CodeGen/RegAllocRegistry.h"
25 #include "llvm/CodeGen/RegisterCoalescer.h"
26 #include "llvm/Target/TargetRegisterInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/ADT/EquivalenceClasses.h"
30 #include "llvm/ADT/Statistic.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/Compiler.h"
41 STATISTIC(NumIters , "Number of iterations performed");
42 STATISTIC(NumBacktracks, "Number of times we had to backtrack");
43 STATISTIC(NumCoalesce, "Number of copies coalesced");
45 static RegisterRegAlloc
46 linearscanRegAlloc("linearscan", " linear scan register allocator",
47 createLinearScanRegisterAllocator);
50 struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass {
52 RALinScan() : MachineFunctionPass((intptr_t)&ID) {}
54 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
55 typedef std::vector<IntervalPtr> IntervalPtrs;
57 /// RelatedRegClasses - This structure is built the first time a function is
58 /// compiled, and keeps track of which register classes have registers that
59 /// belong to multiple classes or have aliases that are in other classes.
60 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
61 std::map<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
64 const TargetMachine* tm_;
65 const TargetRegisterInfo* tri_;
66 const TargetInstrInfo* tii_;
67 MachineRegisterInfo *reginfo_;
68 BitVector allocatableRegs_;
70 const MachineLoopInfo *loopInfo;
72 /// handled_ - Intervals are added to the handled_ set in the order of their
73 /// start value. This is uses for backtracking.
74 std::vector<LiveInterval*> handled_;
76 /// fixed_ - Intervals that correspond to machine registers.
80 /// active_ - Intervals that are currently being processed, and which have a
81 /// live range active for the current point.
84 /// inactive_ - Intervals that are currently being processed, but which have
85 /// a hold at the current point.
86 IntervalPtrs inactive_;
88 typedef std::priority_queue<LiveInterval*,
89 std::vector<LiveInterval*>,
90 greater_ptr<LiveInterval> > IntervalHeap;
91 IntervalHeap unhandled_;
92 std::auto_ptr<PhysRegTracker> prt_;
93 std::auto_ptr<VirtRegMap> vrm_;
94 std::auto_ptr<Spiller> spiller_;
97 virtual const char* getPassName() const {
98 return "Linear Scan Register Allocator";
101 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
102 AU.addRequired<LiveIntervals>();
103 // Make sure PassManager knows which analyses to make available
104 // to coalescing and which analyses coalescing invalidates.
105 AU.addRequiredTransitive<RegisterCoalescer>();
106 AU.addRequired<MachineLoopInfo>();
107 AU.addPreserved<MachineLoopInfo>();
108 AU.addPreservedID(MachineDominatorsID);
109 MachineFunctionPass::getAnalysisUsage(AU);
112 /// runOnMachineFunction - register allocate the whole function
113 bool runOnMachineFunction(MachineFunction&);
116 /// linearScan - the linear scan algorithm
119 /// initIntervalSets - initialize the interval sets.
121 void initIntervalSets();
123 /// processActiveIntervals - expire old intervals and move non-overlapping
124 /// ones to the inactive list.
125 void processActiveIntervals(unsigned CurPoint);
127 /// processInactiveIntervals - expire old intervals and move overlapping
128 /// ones to the active list.
129 void processInactiveIntervals(unsigned CurPoint);
131 /// assignRegOrStackSlotAtInterval - assign a register if one
132 /// is available, or spill.
133 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
135 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
136 /// try allocate the definition the same register as the source register
137 /// if the register is not defined during live time of the interval. This
138 /// eliminate a copy. This is used to coalesce copies which were not
139 /// coalesced away before allocation either due to dest and src being in
140 /// different register classes or because the coalescer was overly
142 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
145 /// register handling helpers
148 /// getFreePhysReg - return a free physical register for this virtual
149 /// register interval if we have one, otherwise return 0.
150 unsigned getFreePhysReg(LiveInterval* cur);
152 /// assignVirt2StackSlot - assigns this virtual register to a
153 /// stack slot. returns the stack slot
154 int assignVirt2StackSlot(unsigned virtReg);
156 void ComputeRelatedRegClasses();
158 template <typename ItTy>
159 void printIntervals(const char* const str, ItTy i, ItTy e) const {
160 if (str) DOUT << str << " intervals:\n";
161 for (; i != e; ++i) {
162 DOUT << "\t" << *i->first << " -> ";
163 unsigned reg = i->first->reg;
164 if (TargetRegisterInfo::isVirtualRegister(reg)) {
165 reg = vrm_->getPhys(reg);
167 DOUT << tri_->getName(reg) << '\n';
171 char RALinScan::ID = 0;
174 void RALinScan::ComputeRelatedRegClasses() {
175 const TargetRegisterInfo &TRI = *tri_;
177 // First pass, add all reg classes to the union, and determine at least one
178 // reg class that each register is in.
179 bool HasAliases = false;
180 for (TargetRegisterInfo::regclass_iterator RCI = TRI.regclass_begin(),
181 E = TRI.regclass_end(); RCI != E; ++RCI) {
182 RelatedRegClasses.insert(*RCI);
183 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
185 HasAliases = HasAliases || *TRI.getAliasSet(*I) != 0;
187 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
189 // Already processed this register. Just make sure we know that
190 // multiple register classes share a register.
191 RelatedRegClasses.unionSets(PRC, *RCI);
198 // Second pass, now that we know conservatively what register classes each reg
199 // belongs to, add info about aliases. We don't need to do this for targets
200 // without register aliases.
202 for (std::map<unsigned, const TargetRegisterClass*>::iterator
203 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
205 for (const unsigned *AS = TRI.getAliasSet(I->first); *AS; ++AS)
206 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
209 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
210 /// try allocate the definition the same register as the source register
211 /// if the register is not defined during live time of the interval. This
212 /// eliminate a copy. This is used to coalesce copies which were not
213 /// coalesced away before allocation either due to dest and src being in
214 /// different register classes or because the coalescer was overly
216 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
217 if ((cur.preference && cur.preference == Reg) || !cur.containsOneValue())
220 VNInfo *vni = cur.getValNumInfo(0);
221 if (!vni->def || vni->def == ~1U || vni->def == ~0U)
223 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
224 unsigned SrcReg, DstReg;
225 if (!CopyMI || !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg))
227 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
228 if (!vrm_->isAssignedReg(SrcReg))
231 SrcReg = vrm_->getPhys(SrcReg);
236 const TargetRegisterClass *RC = reginfo_->getRegClass(cur.reg);
237 if (!RC->contains(SrcReg))
241 if (!li_->conflictsWithPhysRegDef(cur, *vrm_, SrcReg)) {
242 DOUT << "Coalescing: " << cur << " -> " << tri_->getName(SrcReg)
244 vrm_->clearVirt(cur.reg);
245 vrm_->assignVirt2Phys(cur.reg, SrcReg);
253 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
255 tm_ = &fn.getTarget();
256 tri_ = tm_->getRegisterInfo();
257 tii_ = tm_->getInstrInfo();
258 reginfo_ = &mf_->getRegInfo();
259 allocatableRegs_ = tri_->getAllocatableSet(fn);
260 li_ = &getAnalysis<LiveIntervals>();
261 loopInfo = &getAnalysis<MachineLoopInfo>();
263 // We don't run the coalescer here because we have no reason to
264 // interact with it. If the coalescer requires interaction, it
265 // won't do anything. If it doesn't require interaction, we assume
266 // it was run as a separate pass.
268 // If this is the first function compiled, compute the related reg classes.
269 if (RelatedRegClasses.empty())
270 ComputeRelatedRegClasses();
272 if (!prt_.get()) prt_.reset(new PhysRegTracker(*tri_));
273 vrm_.reset(new VirtRegMap(*mf_));
274 if (!spiller_.get()) spiller_.reset(createSpiller());
280 // Rewrite spill code and update the PhysRegsUsed set.
281 spiller_->runOnMachineFunction(*mf_, *vrm_);
282 vrm_.reset(); // Free the VirtRegMap
284 while (!unhandled_.empty()) unhandled_.pop();
293 /// initIntervalSets - initialize the interval sets.
295 void RALinScan::initIntervalSets()
297 assert(unhandled_.empty() && fixed_.empty() &&
298 active_.empty() && inactive_.empty() &&
299 "interval sets should be empty on initialization");
301 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
302 if (TargetRegisterInfo::isPhysicalRegister(i->second.reg)) {
303 reginfo_->setPhysRegUsed(i->second.reg);
304 fixed_.push_back(std::make_pair(&i->second, i->second.begin()));
306 unhandled_.push(&i->second);
310 void RALinScan::linearScan()
312 // linear scan algorithm
313 DOUT << "********** LINEAR SCAN **********\n";
314 DOUT << "********** Function: " << mf_->getFunction()->getName() << '\n';
316 DEBUG(printIntervals("fixed", fixed_.begin(), fixed_.end()));
318 while (!unhandled_.empty()) {
319 // pick the interval with the earliest start point
320 LiveInterval* cur = unhandled_.top();
323 DOUT << "\n*** CURRENT ***: " << *cur << '\n';
325 processActiveIntervals(cur->beginNumber());
326 processInactiveIntervals(cur->beginNumber());
328 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
329 "Can only allocate virtual registers!");
331 // Allocating a virtual register. try to find a free
332 // physical register or spill an interval (possibly this one) in order to
334 assignRegOrStackSlotAtInterval(cur);
336 DEBUG(printIntervals("active", active_.begin(), active_.end()));
337 DEBUG(printIntervals("inactive", inactive_.begin(), inactive_.end()));
340 // expire any remaining active intervals
341 while (!active_.empty()) {
342 IntervalPtr &IP = active_.back();
343 unsigned reg = IP.first->reg;
344 DOUT << "\tinterval " << *IP.first << " expired\n";
345 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
346 "Can only allocate virtual registers!");
347 reg = vrm_->getPhys(reg);
348 prt_->delRegUse(reg);
352 // expire any remaining inactive intervals
353 DEBUG(for (IntervalPtrs::reverse_iterator
354 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
355 DOUT << "\tinterval " << *i->first << " expired\n");
358 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
359 MachineFunction::iterator EntryMBB = mf_->begin();
360 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
361 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
362 LiveInterval &cur = i->second;
364 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
367 else if (vrm_->isAssignedReg(cur.reg))
368 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
371 // Ignore splited live intervals.
372 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
374 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
376 const LiveRange &LR = *I;
377 if (li_->findLiveInMBBs(LR, LiveInMBBs)) {
378 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
379 if (LiveInMBBs[i] != EntryMBB)
380 LiveInMBBs[i]->addLiveIn(Reg);
389 /// processActiveIntervals - expire old intervals and move non-overlapping ones
390 /// to the inactive list.
391 void RALinScan::processActiveIntervals(unsigned CurPoint)
393 DOUT << "\tprocessing active intervals:\n";
395 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
396 LiveInterval *Interval = active_[i].first;
397 LiveInterval::iterator IntervalPos = active_[i].second;
398 unsigned reg = Interval->reg;
400 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
402 if (IntervalPos == Interval->end()) { // Remove expired intervals.
403 DOUT << "\t\tinterval " << *Interval << " expired\n";
404 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
405 "Can only allocate virtual registers!");
406 reg = vrm_->getPhys(reg);
407 prt_->delRegUse(reg);
409 // Pop off the end of the list.
410 active_[i] = active_.back();
414 } else if (IntervalPos->start > CurPoint) {
415 // Move inactive intervals to inactive list.
416 DOUT << "\t\tinterval " << *Interval << " inactive\n";
417 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
418 "Can only allocate virtual registers!");
419 reg = vrm_->getPhys(reg);
420 prt_->delRegUse(reg);
422 inactive_.push_back(std::make_pair(Interval, IntervalPos));
424 // Pop off the end of the list.
425 active_[i] = active_.back();
429 // Otherwise, just update the iterator position.
430 active_[i].second = IntervalPos;
435 /// processInactiveIntervals - expire old intervals and move overlapping
436 /// ones to the active list.
437 void RALinScan::processInactiveIntervals(unsigned CurPoint)
439 DOUT << "\tprocessing inactive intervals:\n";
441 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
442 LiveInterval *Interval = inactive_[i].first;
443 LiveInterval::iterator IntervalPos = inactive_[i].second;
444 unsigned reg = Interval->reg;
446 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
448 if (IntervalPos == Interval->end()) { // remove expired intervals.
449 DOUT << "\t\tinterval " << *Interval << " expired\n";
451 // Pop off the end of the list.
452 inactive_[i] = inactive_.back();
453 inactive_.pop_back();
455 } else if (IntervalPos->start <= CurPoint) {
456 // move re-activated intervals in active list
457 DOUT << "\t\tinterval " << *Interval << " active\n";
458 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
459 "Can only allocate virtual registers!");
460 reg = vrm_->getPhys(reg);
461 prt_->addRegUse(reg);
463 active_.push_back(std::make_pair(Interval, IntervalPos));
465 // Pop off the end of the list.
466 inactive_[i] = inactive_.back();
467 inactive_.pop_back();
470 // Otherwise, just update the iterator position.
471 inactive_[i].second = IntervalPos;
476 /// updateSpillWeights - updates the spill weights of the specifed physical
477 /// register and its weight.
478 static void updateSpillWeights(std::vector<float> &Weights,
479 unsigned reg, float weight,
480 const TargetRegisterInfo *TRI) {
481 Weights[reg] += weight;
482 for (const unsigned* as = TRI->getAliasSet(reg); *as; ++as)
483 Weights[*as] += weight;
487 RALinScan::IntervalPtrs::iterator
488 FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
489 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
491 if (I->first == LI) return I;
495 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, unsigned Point){
496 for (unsigned i = 0, e = V.size(); i != e; ++i) {
497 RALinScan::IntervalPtr &IP = V[i];
498 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
500 if (I != IP.first->begin()) --I;
505 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
507 void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
509 DOUT << "\tallocating current interval: ";
511 PhysRegTracker backupPrt = *prt_;
513 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
514 unsigned StartPosition = cur->beginNumber();
515 const TargetRegisterClass *RC = reginfo_->getRegClass(cur->reg);
516 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
518 // If this live interval is defined by a move instruction and its source is
519 // assigned a physical register that is compatible with the target register
520 // class, then we should try to assign it the same register.
521 // This can happen when the move is from a larger register class to a smaller
522 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
523 if (!cur->preference && cur->containsOneValue()) {
524 VNInfo *vni = cur->getValNumInfo(0);
525 if (vni->def && vni->def != ~1U && vni->def != ~0U) {
526 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
527 unsigned SrcReg, DstReg;
528 if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
530 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
532 else if (vrm_->isAssignedReg(SrcReg))
533 Reg = vrm_->getPhys(SrcReg);
534 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
535 cur->preference = Reg;
540 // for every interval in inactive we overlap with, mark the
541 // register as not free and update spill weights.
542 for (IntervalPtrs::const_iterator i = inactive_.begin(),
543 e = inactive_.end(); i != e; ++i) {
544 unsigned Reg = i->first->reg;
545 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
546 "Can only allocate virtual registers!");
547 const TargetRegisterClass *RegRC = reginfo_->getRegClass(Reg);
548 // If this is not in a related reg class to the register we're allocating,
550 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
551 cur->overlapsFrom(*i->first, i->second-1)) {
552 Reg = vrm_->getPhys(Reg);
553 prt_->addRegUse(Reg);
554 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
558 // Speculatively check to see if we can get a register right now. If not,
559 // we know we won't be able to by adding more constraints. If so, we can
560 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
561 // is very bad (it contains all callee clobbered registers for any functions
562 // with a call), so we want to avoid doing that if possible.
563 unsigned physReg = getFreePhysReg(cur);
564 unsigned BestPhysReg = physReg;
566 // We got a register. However, if it's in the fixed_ list, we might
567 // conflict with it. Check to see if we conflict with it or any of its
569 SmallSet<unsigned, 8> RegAliases;
570 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
571 RegAliases.insert(*AS);
573 bool ConflictsWithFixed = false;
574 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
575 IntervalPtr &IP = fixed_[i];
576 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
577 // Okay, this reg is on the fixed list. Check to see if we actually
579 LiveInterval *I = IP.first;
580 if (I->endNumber() > StartPosition) {
581 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
583 if (II != I->begin() && II->start > StartPosition)
585 if (cur->overlapsFrom(*I, II)) {
586 ConflictsWithFixed = true;
593 // Okay, the register picked by our speculative getFreePhysReg call turned
594 // out to be in use. Actually add all of the conflicting fixed registers to
595 // prt so we can do an accurate query.
596 if (ConflictsWithFixed) {
597 // For every interval in fixed we overlap with, mark the register as not
598 // free and update spill weights.
599 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
600 IntervalPtr &IP = fixed_[i];
601 LiveInterval *I = IP.first;
603 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
604 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
605 I->endNumber() > StartPosition) {
606 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
608 if (II != I->begin() && II->start > StartPosition)
610 if (cur->overlapsFrom(*I, II)) {
611 unsigned reg = I->reg;
612 prt_->addRegUse(reg);
613 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
618 // Using the newly updated prt_ object, which includes conflicts in the
619 // future, see if there are any registers available.
620 physReg = getFreePhysReg(cur);
624 // Restore the physical register tracker, removing information about the
628 // if we find a free register, we are done: assign this virtual to
629 // the free physical register and add this interval to the active
632 DOUT << tri_->getName(physReg) << '\n';
633 vrm_->assignVirt2Phys(cur->reg, physReg);
634 prt_->addRegUse(physReg);
635 active_.push_back(std::make_pair(cur, cur->begin()));
636 handled_.push_back(cur);
639 DOUT << "no free registers\n";
641 // Compile the spill weights into an array that is better for scanning.
642 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0);
643 for (std::vector<std::pair<unsigned, float> >::iterator
644 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
645 updateSpillWeights(SpillWeights, I->first, I->second, tri_);
647 // for each interval in active, update spill weights.
648 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
650 unsigned reg = i->first->reg;
651 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
652 "Can only allocate virtual registers!");
653 reg = vrm_->getPhys(reg);
654 updateSpillWeights(SpillWeights, reg, i->first->weight, tri_);
657 DOUT << "\tassigning stack slot at interval "<< *cur << ":\n";
659 // Find a register to spill.
660 float minWeight = HUGE_VALF;
661 unsigned minReg = cur->preference; // Try the preferred register first.
663 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
664 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
665 e = RC->allocation_order_end(*mf_); i != e; ++i) {
667 if (minWeight > SpillWeights[reg]) {
668 minWeight = SpillWeights[reg];
673 // If we didn't find a register that is spillable, try aliases?
675 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
676 e = RC->allocation_order_end(*mf_); i != e; ++i) {
678 // No need to worry about if the alias register size < regsize of RC.
679 // We are going to spill all registers that alias it anyway.
680 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
681 if (minWeight > SpillWeights[*as]) {
682 minWeight = SpillWeights[*as];
688 // All registers must have inf weight. Just grab one!
691 minReg = BestPhysReg;
693 // Get the physical register with the fewest conflicts.
694 unsigned MinConflicts = ~0U;
695 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
696 e = RC->allocation_order_end(*mf_); i != e; ++i) {
698 unsigned NumConflicts = li_->getNumConflictsWithPhysReg(*cur, reg);
699 if (NumConflicts <= MinConflicts) {
700 MinConflicts = NumConflicts;
706 if (cur->weight == HUGE_VALF || cur->getSize() == 1)
707 // Spill a physical register around defs and uses.
708 li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_);
712 DOUT << "\t\tregister with min weight: "
713 << tri_->getName(minReg) << " (" << minWeight << ")\n";
715 // if the current has the minimum weight, we need to spill it and
716 // add any added intervals back to unhandled, and restart
718 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
719 DOUT << "\t\t\tspilling(c): " << *cur << '\n';
720 std::vector<LiveInterval*> added =
721 li_->addIntervalsForSpills(*cur, loopInfo, *vrm_);
723 return; // Early exit if all spills were folded.
725 // Merge added with unhandled. Note that we know that
726 // addIntervalsForSpills returns intervals sorted by their starting
728 for (unsigned i = 0, e = added.size(); i != e; ++i)
729 unhandled_.push(added[i]);
735 // push the current interval back to unhandled since we are going
736 // to re-run at least this iteration. Since we didn't modify it it
737 // should go back right in the front of the list
738 unhandled_.push(cur);
740 // otherwise we spill all intervals aliasing the register with
741 // minimum weight, rollback to the interval with the earliest
742 // start point and let the linear scan algorithm run again
743 std::vector<LiveInterval*> added;
744 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
745 "did not choose a register to spill?");
746 BitVector toSpill(tri_->getNumRegs());
748 // We are going to spill minReg and all its aliases.
749 toSpill[minReg] = true;
750 for (const unsigned* as = tri_->getAliasSet(minReg); *as; ++as)
753 // the earliest start of a spilled interval indicates up to where
754 // in handled we need to roll back
755 unsigned earliestStart = cur->beginNumber();
757 // set of spilled vregs (used later to rollback properly)
758 SmallSet<unsigned, 32> spilled;
760 // spill live intervals of virtual regs mapped to the physical register we
761 // want to clear (and its aliases). We only spill those that overlap with the
762 // current interval as the rest do not affect its allocation. we also keep
763 // track of the earliest start of all spilled live intervals since this will
764 // mark our rollback point.
765 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
766 unsigned reg = i->first->reg;
767 if (//TargetRegisterInfo::isVirtualRegister(reg) &&
768 toSpill[vrm_->getPhys(reg)] &&
769 cur->overlapsFrom(*i->first, i->second)) {
770 DOUT << "\t\t\tspilling(a): " << *i->first << '\n';
771 earliestStart = std::min(earliestStart, i->first->beginNumber());
772 std::vector<LiveInterval*> newIs =
773 li_->addIntervalsForSpills(*i->first, loopInfo, *vrm_);
774 std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
778 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
779 unsigned reg = i->first->reg;
780 if (//TargetRegisterInfo::isVirtualRegister(reg) &&
781 toSpill[vrm_->getPhys(reg)] &&
782 cur->overlapsFrom(*i->first, i->second-1)) {
783 DOUT << "\t\t\tspilling(i): " << *i->first << '\n';
784 earliestStart = std::min(earliestStart, i->first->beginNumber());
785 std::vector<LiveInterval*> newIs =
786 li_->addIntervalsForSpills(*i->first, loopInfo, *vrm_);
787 std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
792 DOUT << "\t\trolling back to: " << earliestStart << '\n';
794 // Scan handled in reverse order up to the earliest start of a
795 // spilled live interval and undo each one, restoring the state of
797 while (!handled_.empty()) {
798 LiveInterval* i = handled_.back();
799 // If this interval starts before t we are done.
800 if (i->beginNumber() < earliestStart)
802 DOUT << "\t\t\tundo changes for: " << *i << '\n';
805 // When undoing a live interval allocation we must know if it is active or
806 // inactive to properly update the PhysRegTracker and the VirtRegMap.
807 IntervalPtrs::iterator it;
808 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
810 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
811 if (!spilled.count(i->reg))
813 prt_->delRegUse(vrm_->getPhys(i->reg));
814 vrm_->clearVirt(i->reg);
815 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
817 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
818 if (!spilled.count(i->reg))
820 vrm_->clearVirt(i->reg);
822 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
823 "Can only allocate virtual registers!");
824 vrm_->clearVirt(i->reg);
828 // It interval has a preference, it must be defined by a copy. Clear the
829 // preference now since the source interval allocation may have been undone
834 // Rewind the iterators in the active, inactive, and fixed lists back to the
835 // point we reverted to.
836 RevertVectorIteratorsTo(active_, earliestStart);
837 RevertVectorIteratorsTo(inactive_, earliestStart);
838 RevertVectorIteratorsTo(fixed_, earliestStart);
840 // scan the rest and undo each interval that expired after t and
841 // insert it in active (the next iteration of the algorithm will
842 // put it in inactive if required)
843 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
844 LiveInterval *HI = handled_[i];
845 if (!HI->expiredAt(earliestStart) &&
846 HI->expiredAt(cur->beginNumber())) {
847 DOUT << "\t\t\tundo changes for: " << *HI << '\n';
848 active_.push_back(std::make_pair(HI, HI->begin()));
849 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
850 prt_->addRegUse(vrm_->getPhys(HI->reg));
854 // merge added with unhandled
855 for (unsigned i = 0, e = added.size(); i != e; ++i)
856 unhandled_.push(added[i]);
859 /// getFreePhysReg - return a free physical register for this virtual register
860 /// interval if we have one, otherwise return 0.
861 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
862 SmallVector<unsigned, 256> inactiveCounts;
863 unsigned MaxInactiveCount = 0;
865 const TargetRegisterClass *RC = reginfo_->getRegClass(cur->reg);
866 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
868 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
870 unsigned reg = i->first->reg;
871 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
872 "Can only allocate virtual registers!");
874 // If this is not in a related reg class to the register we're allocating,
876 const TargetRegisterClass *RegRC = reginfo_->getRegClass(reg);
877 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
878 reg = vrm_->getPhys(reg);
879 if (inactiveCounts.size() <= reg)
880 inactiveCounts.resize(reg+1);
881 ++inactiveCounts[reg];
882 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
886 unsigned FreeReg = 0;
887 unsigned FreeRegInactiveCount = 0;
889 // If copy coalescer has assigned a "preferred" register, check if it's
891 if (cur->preference) {
892 if (prt_->isRegAvail(cur->preference)) {
893 DOUT << "\t\tassigned the preferred register: "
894 << tri_->getName(cur->preference) << "\n";
895 return cur->preference;
897 DOUT << "\t\tunable to assign the preferred register: "
898 << tri_->getName(cur->preference) << "\n";
901 // Scan for the first available register.
902 TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_);
903 TargetRegisterClass::iterator E = RC->allocation_order_end(*mf_);
905 if (prt_->isRegAvail(*I)) {
907 if (FreeReg < inactiveCounts.size())
908 FreeRegInactiveCount = inactiveCounts[FreeReg];
910 FreeRegInactiveCount = 0;
914 // If there are no free regs, or if this reg has the max inactive count,
915 // return this register.
916 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount) return FreeReg;
918 // Continue scanning the registers, looking for the one with the highest
919 // inactive count. Alkis found that this reduced register pressure very
920 // slightly on X86 (in rev 1.94 of this file), though this should probably be
922 for (; I != E; ++I) {
924 if (prt_->isRegAvail(Reg) && Reg < inactiveCounts.size() &&
925 FreeRegInactiveCount < inactiveCounts[Reg]) {
927 FreeRegInactiveCount = inactiveCounts[Reg];
928 if (FreeRegInactiveCount == MaxInactiveCount)
929 break; // We found the one with the max inactive count.
936 FunctionPass* llvm::createLinearScanRegisterAllocator() {
937 return new RALinScan();