1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "VirtRegMap.h"
16 #include "VirtRegRewriter.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/CalcSpillWeights.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegAllocRegistry.h"
27 #include "llvm/CodeGen/RegisterCoalescer.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/ADT/EquivalenceClasses.h"
33 #include "llvm/ADT/SmallSet.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
47 STATISTIC(NumIters , "Number of iterations performed");
48 STATISTIC(NumBacktracks, "Number of times we had to backtrack");
49 STATISTIC(NumCoalesce, "Number of copies coalesced");
50 STATISTIC(NumDowngrade, "Number of registers downgraded");
53 NewHeuristic("new-spilling-heuristic",
54 cl::desc("Use new spilling heuristic"),
55 cl::init(false), cl::Hidden);
58 PreSplitIntervals("pre-alloc-split",
59 cl::desc("Pre-register allocation live interval splitting"),
60 cl::init(false), cl::Hidden);
63 TrivCoalesceEnds("trivial-coalesce-ends",
64 cl::desc("Attempt trivial coalescing of interval ends"),
65 cl::init(false), cl::Hidden);
67 static RegisterRegAlloc
68 linearscanRegAlloc("linearscan", "linear scan register allocator",
69 createLinearScanRegisterAllocator);
72 // When we allocate a register, add it to a fixed-size queue of
73 // registers to skip in subsequent allocations. This trades a small
74 // amount of register pressure and increased spills for flexibility in
75 // the post-pass scheduler.
77 // Note that in a the number of registers used for reloading spills
78 // will be one greater than the value of this option.
80 // One big limitation of this is that it doesn't differentiate between
81 // different register classes. So on x86-64, if there is xmm register
82 // pressure, it can caused fewer GPRs to be held in the queue.
83 static cl::opt<unsigned>
84 NumRecentlyUsedRegs("linearscan-skip-count",
85 cl::desc("Number of registers for linearscan to remember"
90 struct RALinScan : public MachineFunctionPass {
92 RALinScan() : MachineFunctionPass(ID) {
93 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
94 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
95 initializeRegisterCoalescerAnalysisGroup(
96 *PassRegistry::getPassRegistry());
97 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
98 initializePreAllocSplittingPass(*PassRegistry::getPassRegistry());
99 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
100 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
101 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
102 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
104 // Initialize the queue to record recently-used registers.
105 if (NumRecentlyUsedRegs > 0)
106 RecentRegs.resize(NumRecentlyUsedRegs, 0);
107 RecentNext = RecentRegs.begin();
110 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
111 typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
113 /// RelatedRegClasses - This structure is built the first time a function is
114 /// compiled, and keeps track of which register classes have registers that
115 /// belong to multiple classes or have aliases that are in other classes.
116 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
117 DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
119 // NextReloadMap - For each register in the map, it maps to the another
120 // register which is defined by a reload from the same stack slot and
121 // both reloads are in the same basic block.
122 DenseMap<unsigned, unsigned> NextReloadMap;
124 // DowngradedRegs - A set of registers which are being "downgraded", i.e.
125 // un-favored for allocation.
126 SmallSet<unsigned, 8> DowngradedRegs;
128 // DowngradeMap - A map from virtual registers to physical registers being
129 // downgraded for the virtual registers.
130 DenseMap<unsigned, unsigned> DowngradeMap;
132 MachineFunction* mf_;
133 MachineRegisterInfo* mri_;
134 const TargetMachine* tm_;
135 const TargetRegisterInfo* tri_;
136 const TargetInstrInfo* tii_;
137 BitVector allocatableRegs_;
138 BitVector reservedRegs_;
140 MachineLoopInfo *loopInfo;
142 /// handled_ - Intervals are added to the handled_ set in the order of their
143 /// start value. This is uses for backtracking.
144 std::vector<LiveInterval*> handled_;
146 /// fixed_ - Intervals that correspond to machine registers.
150 /// active_ - Intervals that are currently being processed, and which have a
151 /// live range active for the current point.
152 IntervalPtrs active_;
154 /// inactive_ - Intervals that are currently being processed, but which have
155 /// a hold at the current point.
156 IntervalPtrs inactive_;
158 typedef std::priority_queue<LiveInterval*,
159 SmallVector<LiveInterval*, 64>,
160 greater_ptr<LiveInterval> > IntervalHeap;
161 IntervalHeap unhandled_;
163 /// regUse_ - Tracks register usage.
164 SmallVector<unsigned, 32> regUse_;
165 SmallVector<unsigned, 32> regUseBackUp_;
167 /// vrm_ - Tracks register assignments.
170 std::auto_ptr<VirtRegRewriter> rewriter_;
172 std::auto_ptr<Spiller> spiller_;
174 // The queue of recently-used registers.
175 SmallVector<unsigned, 4> RecentRegs;
176 SmallVector<unsigned, 4>::iterator RecentNext;
178 // Record that we just picked this register.
179 void recordRecentlyUsed(unsigned reg) {
180 assert(reg != 0 && "Recently used register is NOREG!");
181 if (!RecentRegs.empty()) {
183 if (RecentNext == RecentRegs.end())
184 RecentNext = RecentRegs.begin();
189 virtual const char* getPassName() const {
190 return "Linear Scan Register Allocator";
193 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
194 AU.setPreservesCFG();
195 AU.addRequired<LiveIntervals>();
196 AU.addPreserved<SlotIndexes>();
198 AU.addRequiredID(StrongPHIEliminationID);
199 // Make sure PassManager knows which analyses to make available
200 // to coalescing and which analyses coalescing invalidates.
201 AU.addRequiredTransitive<RegisterCoalescer>();
202 AU.addRequired<CalculateSpillWeights>();
203 if (PreSplitIntervals)
204 AU.addRequiredID(PreAllocSplittingID);
205 AU.addRequiredID(LiveStacksID);
206 AU.addPreservedID(LiveStacksID);
207 AU.addRequired<MachineLoopInfo>();
208 AU.addPreserved<MachineLoopInfo>();
209 AU.addRequired<VirtRegMap>();
210 AU.addPreserved<VirtRegMap>();
211 AU.addPreservedID(MachineDominatorsID);
212 MachineFunctionPass::getAnalysisUsage(AU);
215 /// runOnMachineFunction - register allocate the whole function
216 bool runOnMachineFunction(MachineFunction&);
218 // Determine if we skip this register due to its being recently used.
219 bool isRecentlyUsed(unsigned reg) const {
220 return std::find(RecentRegs.begin(), RecentRegs.end(), reg) !=
225 /// linearScan - the linear scan algorithm
228 /// initIntervalSets - initialize the interval sets.
230 void initIntervalSets();
232 /// processActiveIntervals - expire old intervals and move non-overlapping
233 /// ones to the inactive list.
234 void processActiveIntervals(SlotIndex CurPoint);
236 /// processInactiveIntervals - expire old intervals and move overlapping
237 /// ones to the active list.
238 void processInactiveIntervals(SlotIndex CurPoint);
240 /// hasNextReloadInterval - Return the next liveinterval that's being
241 /// defined by a reload from the same SS as the specified one.
242 LiveInterval *hasNextReloadInterval(LiveInterval *cur);
244 /// DowngradeRegister - Downgrade a register for allocation.
245 void DowngradeRegister(LiveInterval *li, unsigned Reg);
247 /// UpgradeRegister - Upgrade a register for allocation.
248 void UpgradeRegister(unsigned Reg);
250 /// assignRegOrStackSlotAtInterval - assign a register if one
251 /// is available, or spill.
252 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
254 void updateSpillWeights(std::vector<float> &Weights,
255 unsigned reg, float weight,
256 const TargetRegisterClass *RC);
258 /// findIntervalsToSpill - Determine the intervals to spill for the
259 /// specified interval. It's passed the physical registers whose spill
260 /// weight is the lowest among all the registers whose live intervals
261 /// conflict with the interval.
262 void findIntervalsToSpill(LiveInterval *cur,
263 std::vector<std::pair<unsigned,float> > &Candidates,
265 SmallVector<LiveInterval*, 8> &SpillIntervals);
267 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
268 /// try to allocate the definition to the same register as the source,
269 /// if the register is not defined during the life time of the interval.
270 /// This eliminates a copy, and is used to coalesce copies which were not
271 /// coalesced away before allocation either due to dest and src being in
272 /// different register classes or because the coalescer was overly
274 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
277 /// Register usage / availability tracking helpers.
281 regUse_.resize(tri_->getNumRegs(), 0);
282 regUseBackUp_.resize(tri_->getNumRegs(), 0);
285 void finalizeRegUses() {
287 // Verify all the registers are "freed".
289 for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
290 if (regUse_[i] != 0) {
291 dbgs() << tri_->getName(i) << " is still in use!\n";
299 regUseBackUp_.clear();
302 void addRegUse(unsigned physReg) {
303 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
304 "should be physical register!");
306 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
310 void delRegUse(unsigned physReg) {
311 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
312 "should be physical register!");
313 assert(regUse_[physReg] != 0);
315 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
316 assert(regUse_[*as] != 0);
321 bool isRegAvail(unsigned physReg) const {
322 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
323 "should be physical register!");
324 return regUse_[physReg] == 0;
327 void backUpRegUses() {
328 regUseBackUp_ = regUse_;
331 void restoreRegUses() {
332 regUse_ = regUseBackUp_;
336 /// Register handling helpers.
339 /// getFreePhysReg - return a free physical register for this virtual
340 /// register interval if we have one, otherwise return 0.
341 unsigned getFreePhysReg(LiveInterval* cur);
342 unsigned getFreePhysReg(LiveInterval* cur,
343 const TargetRegisterClass *RC,
344 unsigned MaxInactiveCount,
345 SmallVector<unsigned, 256> &inactiveCounts,
348 /// getFirstNonReservedPhysReg - return the first non-reserved physical
349 /// register in the register class.
350 unsigned getFirstNonReservedPhysReg(const TargetRegisterClass *RC) {
351 TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_);
352 TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_);
353 while (i != aoe && reservedRegs_.test(*i))
355 assert(i != aoe && "All registers reserved?!");
359 void ComputeRelatedRegClasses();
361 template <typename ItTy>
362 void printIntervals(const char* const str, ItTy i, ItTy e) const {
365 dbgs() << str << " intervals:\n";
367 for (; i != e; ++i) {
368 dbgs() << "\t" << *i->first << " -> ";
370 unsigned reg = i->first->reg;
371 if (TargetRegisterInfo::isVirtualRegister(reg))
372 reg = vrm_->getPhys(reg);
374 dbgs() << tri_->getName(reg) << '\n';
379 char RALinScan::ID = 0;
382 INITIALIZE_PASS_BEGIN(RALinScan, "linearscan-regalloc",
383 "Linear Scan Register Allocator", false, false)
384 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
385 INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination)
386 INITIALIZE_PASS_DEPENDENCY(CalculateSpillWeights)
387 INITIALIZE_PASS_DEPENDENCY(PreAllocSplitting)
388 INITIALIZE_PASS_DEPENDENCY(LiveStacks)
389 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
390 INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
391 INITIALIZE_AG_DEPENDENCY(RegisterCoalescer)
392 INITIALIZE_PASS_END(RALinScan, "linearscan-regalloc",
393 "Linear Scan Register Allocator", false, false)
395 void RALinScan::ComputeRelatedRegClasses() {
396 // First pass, add all reg classes to the union, and determine at least one
397 // reg class that each register is in.
398 bool HasAliases = false;
399 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
400 E = tri_->regclass_end(); RCI != E; ++RCI) {
401 RelatedRegClasses.insert(*RCI);
402 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
404 HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
406 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
408 // Already processed this register. Just make sure we know that
409 // multiple register classes share a register.
410 RelatedRegClasses.unionSets(PRC, *RCI);
417 // Second pass, now that we know conservatively what register classes each reg
418 // belongs to, add info about aliases. We don't need to do this for targets
419 // without register aliases.
421 for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
422 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
424 for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
425 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
428 /// attemptTrivialCoalescing - If a simple interval is defined by a copy, try
429 /// allocate the definition the same register as the source register if the
430 /// register is not defined during live time of the interval. If the interval is
431 /// killed by a copy, try to use the destination register. This eliminates a
432 /// copy. This is used to coalesce copies which were not coalesced away before
433 /// allocation either due to dest and src being in different register classes or
434 /// because the coalescer was overly conservative.
435 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
436 unsigned Preference = vrm_->getRegAllocPref(cur.reg);
437 if ((Preference && Preference == Reg) || !cur.containsOneValue())
440 // We cannot handle complicated live ranges. Simple linear stuff only.
441 if (cur.ranges.size() != 1)
444 const LiveRange &range = cur.ranges.front();
446 VNInfo *vni = range.valno;
452 MachineInstr *CopyMI;
453 if ((CopyMI = li_->getInstructionFromIndex(vni->def)) && CopyMI->isCopy())
454 // Defined by a copy, try to extend SrcReg forward
455 CandReg = CopyMI->getOperand(1).getReg();
456 else if (TrivCoalesceEnds &&
457 (CopyMI = li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
458 CopyMI->isCopy() && cur.reg == CopyMI->getOperand(1).getReg())
459 // Only used by a copy, try to extend DstReg backwards
460 CandReg = CopyMI->getOperand(0).getReg();
465 if (TargetRegisterInfo::isVirtualRegister(CandReg)) {
466 if (!vrm_->isAssignedReg(CandReg))
468 CandReg = vrm_->getPhys(CandReg);
473 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
474 if (!RC->contains(CandReg))
477 if (li_->conflictsWithPhysReg(cur, *vrm_, CandReg))
481 DEBUG(dbgs() << "Coalescing: " << cur << " -> " << tri_->getName(CandReg)
483 vrm_->clearVirt(cur.reg);
484 vrm_->assignVirt2Phys(cur.reg, CandReg);
490 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
492 mri_ = &fn.getRegInfo();
493 tm_ = &fn.getTarget();
494 tri_ = tm_->getRegisterInfo();
495 tii_ = tm_->getInstrInfo();
496 allocatableRegs_ = tri_->getAllocatableSet(fn);
497 reservedRegs_ = tri_->getReservedRegs(fn);
498 li_ = &getAnalysis<LiveIntervals>();
499 loopInfo = &getAnalysis<MachineLoopInfo>();
501 // We don't run the coalescer here because we have no reason to
502 // interact with it. If the coalescer requires interaction, it
503 // won't do anything. If it doesn't require interaction, we assume
504 // it was run as a separate pass.
506 // If this is the first function compiled, compute the related reg classes.
507 if (RelatedRegClasses.empty())
508 ComputeRelatedRegClasses();
510 // Also resize register usage trackers.
513 vrm_ = &getAnalysis<VirtRegMap>();
514 if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
516 spiller_.reset(createSpiller(*this, *mf_, *vrm_));
522 // Rewrite spill code and update the PhysRegsUsed set.
523 rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
525 assert(unhandled_.empty() && "Unhandled live intervals remain!");
533 NextReloadMap.clear();
534 DowngradedRegs.clear();
535 DowngradeMap.clear();
541 /// initIntervalSets - initialize the interval sets.
543 void RALinScan::initIntervalSets()
545 assert(unhandled_.empty() && fixed_.empty() &&
546 active_.empty() && inactive_.empty() &&
547 "interval sets should be empty on initialization");
549 handled_.reserve(li_->getNumIntervals());
551 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
552 if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
553 if (!i->second->empty()) {
554 mri_->setPhysRegUsed(i->second->reg);
555 fixed_.push_back(std::make_pair(i->second, i->second->begin()));
558 if (i->second->empty()) {
559 assignRegOrStackSlotAtInterval(i->second);
562 unhandled_.push(i->second);
567 void RALinScan::linearScan() {
568 // linear scan algorithm
570 dbgs() << "********** LINEAR SCAN **********\n"
571 << "********** Function: "
572 << mf_->getFunction()->getName() << '\n';
573 printIntervals("fixed", fixed_.begin(), fixed_.end());
576 while (!unhandled_.empty()) {
577 // pick the interval with the earliest start point
578 LiveInterval* cur = unhandled_.top();
581 DEBUG(dbgs() << "\n*** CURRENT ***: " << *cur << '\n');
583 assert(!cur->empty() && "Empty interval in unhandled set.");
585 processActiveIntervals(cur->beginIndex());
586 processInactiveIntervals(cur->beginIndex());
588 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
589 "Can only allocate virtual registers!");
591 // Allocating a virtual register. try to find a free
592 // physical register or spill an interval (possibly this one) in order to
594 assignRegOrStackSlotAtInterval(cur);
597 printIntervals("active", active_.begin(), active_.end());
598 printIntervals("inactive", inactive_.begin(), inactive_.end());
602 // Expire any remaining active intervals
603 while (!active_.empty()) {
604 IntervalPtr &IP = active_.back();
605 unsigned reg = IP.first->reg;
606 DEBUG(dbgs() << "\tinterval " << *IP.first << " expired\n");
607 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
608 "Can only allocate virtual registers!");
609 reg = vrm_->getPhys(reg);
614 // Expire any remaining inactive intervals
616 for (IntervalPtrs::reverse_iterator
617 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
618 dbgs() << "\tinterval " << *i->first << " expired\n";
622 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
623 MachineFunction::iterator EntryMBB = mf_->begin();
624 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
625 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
626 LiveInterval &cur = *i->second;
628 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
631 else if (vrm_->isAssignedReg(cur.reg))
632 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
635 // Ignore splited live intervals.
636 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
639 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
641 const LiveRange &LR = *I;
642 if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
643 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
644 if (LiveInMBBs[i] != EntryMBB) {
645 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
646 "Adding a virtual register to livein set?");
647 LiveInMBBs[i]->addLiveIn(Reg);
654 DEBUG(dbgs() << *vrm_);
656 // Look for physical registers that end up not being allocated even though
657 // register allocator had to spill other registers in its register class.
658 if (!vrm_->FindUnusedRegisters(li_))
662 /// processActiveIntervals - expire old intervals and move non-overlapping ones
663 /// to the inactive list.
664 void RALinScan::processActiveIntervals(SlotIndex CurPoint)
666 DEBUG(dbgs() << "\tprocessing active intervals:\n");
668 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
669 LiveInterval *Interval = active_[i].first;
670 LiveInterval::iterator IntervalPos = active_[i].second;
671 unsigned reg = Interval->reg;
673 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
675 if (IntervalPos == Interval->end()) { // Remove expired intervals.
676 DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
677 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
678 "Can only allocate virtual registers!");
679 reg = vrm_->getPhys(reg);
682 // Pop off the end of the list.
683 active_[i] = active_.back();
687 } else if (IntervalPos->start > CurPoint) {
688 // Move inactive intervals to inactive list.
689 DEBUG(dbgs() << "\t\tinterval " << *Interval << " inactive\n");
690 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
691 "Can only allocate virtual registers!");
692 reg = vrm_->getPhys(reg);
695 inactive_.push_back(std::make_pair(Interval, IntervalPos));
697 // Pop off the end of the list.
698 active_[i] = active_.back();
702 // Otherwise, just update the iterator position.
703 active_[i].second = IntervalPos;
708 /// processInactiveIntervals - expire old intervals and move overlapping
709 /// ones to the active list.
710 void RALinScan::processInactiveIntervals(SlotIndex CurPoint)
712 DEBUG(dbgs() << "\tprocessing inactive intervals:\n");
714 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
715 LiveInterval *Interval = inactive_[i].first;
716 LiveInterval::iterator IntervalPos = inactive_[i].second;
717 unsigned reg = Interval->reg;
719 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
721 if (IntervalPos == Interval->end()) { // remove expired intervals.
722 DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
724 // Pop off the end of the list.
725 inactive_[i] = inactive_.back();
726 inactive_.pop_back();
728 } else if (IntervalPos->start <= CurPoint) {
729 // move re-activated intervals in active list
730 DEBUG(dbgs() << "\t\tinterval " << *Interval << " active\n");
731 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
732 "Can only allocate virtual registers!");
733 reg = vrm_->getPhys(reg);
736 active_.push_back(std::make_pair(Interval, IntervalPos));
738 // Pop off the end of the list.
739 inactive_[i] = inactive_.back();
740 inactive_.pop_back();
743 // Otherwise, just update the iterator position.
744 inactive_[i].second = IntervalPos;
749 /// updateSpillWeights - updates the spill weights of the specifed physical
750 /// register and its weight.
751 void RALinScan::updateSpillWeights(std::vector<float> &Weights,
752 unsigned reg, float weight,
753 const TargetRegisterClass *RC) {
754 SmallSet<unsigned, 4> Processed;
755 SmallSet<unsigned, 4> SuperAdded;
756 SmallVector<unsigned, 4> Supers;
757 Weights[reg] += weight;
758 Processed.insert(reg);
759 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
760 Weights[*as] += weight;
761 Processed.insert(*as);
762 if (tri_->isSubRegister(*as, reg) &&
763 SuperAdded.insert(*as) &&
765 Supers.push_back(*as);
769 // If the alias is a super-register, and the super-register is in the
770 // register class we are trying to allocate. Then add the weight to all
771 // sub-registers of the super-register even if they are not aliases.
772 // e.g. allocating for GR32, bh is not used, updating bl spill weight.
773 // bl should get the same spill weight otherwise it will be choosen
774 // as a spill candidate since spilling bh doesn't make ebx available.
775 for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
776 for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
777 if (!Processed.count(*sr))
778 Weights[*sr] += weight;
783 RALinScan::IntervalPtrs::iterator
784 FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
785 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
787 if (I->first == LI) return I;
791 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V,
793 for (unsigned i = 0, e = V.size(); i != e; ++i) {
794 RALinScan::IntervalPtr &IP = V[i];
795 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
797 if (I != IP.first->begin()) --I;
802 /// getConflictWeight - Return the number of conflicts between cur
803 /// live interval and defs and uses of Reg weighted by loop depthes.
805 float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
806 MachineRegisterInfo *mri_,
807 MachineLoopInfo *loopInfo) {
809 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
810 E = mri_->reg_end(); I != E; ++I) {
811 MachineInstr *MI = &*I;
812 if (cur->liveAt(li_->getInstructionIndex(MI))) {
813 unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
814 Conflicts += std::pow(10.0f, (float)loopDepth);
820 /// findIntervalsToSpill - Determine the intervals to spill for the
821 /// specified interval. It's passed the physical registers whose spill
822 /// weight is the lowest among all the registers whose live intervals
823 /// conflict with the interval.
824 void RALinScan::findIntervalsToSpill(LiveInterval *cur,
825 std::vector<std::pair<unsigned,float> > &Candidates,
827 SmallVector<LiveInterval*, 8> &SpillIntervals) {
828 // We have figured out the *best* register to spill. But there are other
829 // registers that are pretty good as well (spill weight within 3%). Spill
830 // the one that has fewest defs and uses that conflict with cur.
831 float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
832 SmallVector<LiveInterval*, 8> SLIs[3];
835 dbgs() << "\tConsidering " << NumCands << " candidates: ";
836 for (unsigned i = 0; i != NumCands; ++i)
837 dbgs() << tri_->getName(Candidates[i].first) << " ";
841 // Calculate the number of conflicts of each candidate.
842 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
843 unsigned Reg = i->first->reg;
844 unsigned PhysReg = vrm_->getPhys(Reg);
845 if (!cur->overlapsFrom(*i->first, i->second))
847 for (unsigned j = 0; j < NumCands; ++j) {
848 unsigned Candidate = Candidates[j].first;
849 if (tri_->regsOverlap(PhysReg, Candidate)) {
851 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
852 SLIs[j].push_back(i->first);
857 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
858 unsigned Reg = i->first->reg;
859 unsigned PhysReg = vrm_->getPhys(Reg);
860 if (!cur->overlapsFrom(*i->first, i->second-1))
862 for (unsigned j = 0; j < NumCands; ++j) {
863 unsigned Candidate = Candidates[j].first;
864 if (tri_->regsOverlap(PhysReg, Candidate)) {
866 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
867 SLIs[j].push_back(i->first);
872 // Which is the best candidate?
873 unsigned BestCandidate = 0;
874 float MinConflicts = Conflicts[0];
875 for (unsigned i = 1; i != NumCands; ++i) {
876 if (Conflicts[i] < MinConflicts) {
878 MinConflicts = Conflicts[i];
882 std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
883 std::back_inserter(SpillIntervals));
887 struct WeightCompare {
889 const RALinScan &Allocator;
892 WeightCompare(const RALinScan &Alloc) : Allocator(Alloc) {}
894 typedef std::pair<unsigned, float> RegWeightPair;
895 bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
896 return LHS.second < RHS.second && !Allocator.isRecentlyUsed(LHS.first);
901 static bool weightsAreClose(float w1, float w2) {
905 float diff = w1 - w2;
906 if (diff <= 0.02f) // Within 0.02f
908 return (diff / w2) <= 0.05f; // Within 5%.
911 LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
912 DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
913 if (I == NextReloadMap.end())
915 return &li_->getInterval(I->second);
918 void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
919 bool isNew = DowngradedRegs.insert(Reg);
920 isNew = isNew; // Silence compiler warning.
921 assert(isNew && "Multiple reloads holding the same register?");
922 DowngradeMap.insert(std::make_pair(li->reg, Reg));
923 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS) {
924 isNew = DowngradedRegs.insert(*AS);
925 isNew = isNew; // Silence compiler warning.
926 assert(isNew && "Multiple reloads holding the same register?");
927 DowngradeMap.insert(std::make_pair(li->reg, *AS));
932 void RALinScan::UpgradeRegister(unsigned Reg) {
934 DowngradedRegs.erase(Reg);
935 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
936 DowngradedRegs.erase(*AS);
942 bool operator()(LiveInterval* A, LiveInterval* B) {
943 return A->beginIndex() < B->beginIndex();
948 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
950 void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
951 DEBUG(dbgs() << "\tallocating current interval: ");
953 // This is an implicitly defined live interval, just assign any register.
954 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
956 unsigned physReg = vrm_->getRegAllocPref(cur->reg);
958 physReg = getFirstNonReservedPhysReg(RC);
959 DEBUG(dbgs() << tri_->getName(physReg) << '\n');
960 // Note the register is not really in use.
961 vrm_->assignVirt2Phys(cur->reg, physReg);
967 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
968 SlotIndex StartPosition = cur->beginIndex();
969 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
971 // If start of this live interval is defined by a move instruction and its
972 // source is assigned a physical register that is compatible with the target
973 // register class, then we should try to assign it the same register.
974 // This can happen when the move is from a larger register class to a smaller
975 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
976 if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
977 VNInfo *vni = cur->begin()->valno;
978 if (!vni->isUnused()) {
979 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
980 if (CopyMI && CopyMI->isCopy()) {
981 unsigned DstSubReg = CopyMI->getOperand(0).getSubReg();
982 unsigned SrcReg = CopyMI->getOperand(1).getReg();
983 unsigned SrcSubReg = CopyMI->getOperand(1).getSubReg();
985 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
987 else if (vrm_->isAssignedReg(SrcReg))
988 Reg = vrm_->getPhys(SrcReg);
991 Reg = tri_->getSubReg(Reg, SrcSubReg);
993 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
994 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
995 mri_->setRegAllocationHint(cur->reg, 0, Reg);
1001 // For every interval in inactive we overlap with, mark the
1002 // register as not free and update spill weights.
1003 for (IntervalPtrs::const_iterator i = inactive_.begin(),
1004 e = inactive_.end(); i != e; ++i) {
1005 unsigned Reg = i->first->reg;
1006 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
1007 "Can only allocate virtual registers!");
1008 const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
1009 // If this is not in a related reg class to the register we're allocating,
1011 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1012 cur->overlapsFrom(*i->first, i->second-1)) {
1013 Reg = vrm_->getPhys(Reg);
1015 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
1019 // Speculatively check to see if we can get a register right now. If not,
1020 // we know we won't be able to by adding more constraints. If so, we can
1021 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
1022 // is very bad (it contains all callee clobbered registers for any functions
1023 // with a call), so we want to avoid doing that if possible.
1024 unsigned physReg = getFreePhysReg(cur);
1025 unsigned BestPhysReg = physReg;
1027 // We got a register. However, if it's in the fixed_ list, we might
1028 // conflict with it. Check to see if we conflict with it or any of its
1030 SmallSet<unsigned, 8> RegAliases;
1031 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
1032 RegAliases.insert(*AS);
1034 bool ConflictsWithFixed = false;
1035 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1036 IntervalPtr &IP = fixed_[i];
1037 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
1038 // Okay, this reg is on the fixed list. Check to see if we actually
1040 LiveInterval *I = IP.first;
1041 if (I->endIndex() > StartPosition) {
1042 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1044 if (II != I->begin() && II->start > StartPosition)
1046 if (cur->overlapsFrom(*I, II)) {
1047 ConflictsWithFixed = true;
1054 // Okay, the register picked by our speculative getFreePhysReg call turned
1055 // out to be in use. Actually add all of the conflicting fixed registers to
1056 // regUse_ so we can do an accurate query.
1057 if (ConflictsWithFixed) {
1058 // For every interval in fixed we overlap with, mark the register as not
1059 // free and update spill weights.
1060 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1061 IntervalPtr &IP = fixed_[i];
1062 LiveInterval *I = IP.first;
1064 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
1065 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1066 I->endIndex() > StartPosition) {
1067 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1069 if (II != I->begin() && II->start > StartPosition)
1071 if (cur->overlapsFrom(*I, II)) {
1072 unsigned reg = I->reg;
1074 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
1079 // Using the newly updated regUse_ object, which includes conflicts in the
1080 // future, see if there are any registers available.
1081 physReg = getFreePhysReg(cur);
1085 // Restore the physical register tracker, removing information about the
1089 // If we find a free register, we are done: assign this virtual to
1090 // the free physical register and add this interval to the active
1093 DEBUG(dbgs() << tri_->getName(physReg) << '\n');
1094 vrm_->assignVirt2Phys(cur->reg, physReg);
1096 active_.push_back(std::make_pair(cur, cur->begin()));
1097 handled_.push_back(cur);
1099 // "Upgrade" the physical register since it has been allocated.
1100 UpgradeRegister(physReg);
1101 if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
1102 // "Downgrade" physReg to try to keep physReg from being allocated until
1103 // the next reload from the same SS is allocated.
1104 mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg);
1105 DowngradeRegister(cur, physReg);
1109 DEBUG(dbgs() << "no free registers\n");
1111 // Compile the spill weights into an array that is better for scanning.
1112 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
1113 for (std::vector<std::pair<unsigned, float> >::iterator
1114 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
1115 updateSpillWeights(SpillWeights, I->first, I->second, RC);
1117 // for each interval in active, update spill weights.
1118 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
1120 unsigned reg = i->first->reg;
1121 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1122 "Can only allocate virtual registers!");
1123 reg = vrm_->getPhys(reg);
1124 updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
1127 DEBUG(dbgs() << "\tassigning stack slot at interval "<< *cur << ":\n");
1129 // Find a register to spill.
1130 float minWeight = HUGE_VALF;
1131 unsigned minReg = 0;
1134 std::vector<std::pair<unsigned,float> > RegsWeights;
1135 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
1136 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1137 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1139 float regWeight = SpillWeights[reg];
1140 // Don't even consider reserved regs.
1141 if (reservedRegs_.test(reg))
1143 // Skip recently allocated registers and reserved registers.
1144 if (minWeight > regWeight && !isRecentlyUsed(reg))
1146 RegsWeights.push_back(std::make_pair(reg, regWeight));
1149 // If we didn't find a register that is spillable, try aliases?
1151 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1152 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1154 if (reservedRegs_.test(reg))
1156 // No need to worry about if the alias register size < regsize of RC.
1157 // We are going to spill all registers that alias it anyway.
1158 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
1159 RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
1163 // Sort all potential spill candidates by weight.
1164 std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare(*this));
1165 minReg = RegsWeights[0].first;
1166 minWeight = RegsWeights[0].second;
1167 if (minWeight == HUGE_VALF) {
1168 // All registers must have inf weight. Just grab one!
1169 minReg = BestPhysReg ? BestPhysReg : getFirstNonReservedPhysReg(RC);
1170 if (cur->weight == HUGE_VALF ||
1171 li_->getApproximateInstructionCount(*cur) == 0) {
1172 // Spill a physical register around defs and uses.
1173 if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
1174 // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
1175 // in fixed_. Reset them.
1176 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1177 IntervalPtr &IP = fixed_[i];
1178 LiveInterval *I = IP.first;
1179 if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
1180 IP.second = I->advanceTo(I->begin(), StartPosition);
1183 DowngradedRegs.clear();
1184 assignRegOrStackSlotAtInterval(cur);
1186 assert(false && "Ran out of registers during register allocation!");
1187 report_fatal_error("Ran out of registers during register allocation!");
1193 // Find up to 3 registers to consider as spill candidates.
1194 unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
1195 while (LastCandidate > 1) {
1196 if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
1202 dbgs() << "\t\tregister(s) with min weight(s): ";
1204 for (unsigned i = 0; i != LastCandidate; ++i)
1205 dbgs() << tri_->getName(RegsWeights[i].first)
1206 << " (" << RegsWeights[i].second << ")\n";
1209 // If the current has the minimum weight, we need to spill it and
1210 // add any added intervals back to unhandled, and restart
1212 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
1213 DEBUG(dbgs() << "\t\t\tspilling(c): " << *cur << '\n');
1214 SmallVector<LiveInterval*, 8> spillIs, added;
1215 spiller_->spill(cur, added, spillIs);
1217 std::sort(added.begin(), added.end(), LISorter());
1219 return; // Early exit if all spills were folded.
1221 // Merge added with unhandled. Note that we have already sorted
1222 // intervals returned by addIntervalsForSpills by their starting
1224 // This also update the NextReloadMap. That is, it adds mapping from a
1225 // register defined by a reload from SS to the next reload from SS in the
1226 // same basic block.
1227 MachineBasicBlock *LastReloadMBB = 0;
1228 LiveInterval *LastReload = 0;
1229 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1230 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1231 LiveInterval *ReloadLi = added[i];
1232 if (ReloadLi->weight == HUGE_VALF &&
1233 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1234 SlotIndex ReloadIdx = ReloadLi->beginIndex();
1235 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1236 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1237 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1238 // Last reload of same SS is in the same MBB. We want to try to
1239 // allocate both reloads the same register and make sure the reg
1240 // isn't clobbered in between if at all possible.
1241 assert(LastReload->beginIndex() < ReloadIdx);
1242 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1244 LastReloadMBB = ReloadMBB;
1245 LastReload = ReloadLi;
1246 LastReloadSS = ReloadSS;
1248 unhandled_.push(ReloadLi);
1255 // Push the current interval back to unhandled since we are going
1256 // to re-run at least this iteration. Since we didn't modify it it
1257 // should go back right in the front of the list
1258 unhandled_.push(cur);
1260 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
1261 "did not choose a register to spill?");
1263 // We spill all intervals aliasing the register with
1264 // minimum weight, rollback to the interval with the earliest
1265 // start point and let the linear scan algorithm run again
1266 SmallVector<LiveInterval*, 8> spillIs;
1268 // Determine which intervals have to be spilled.
1269 findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
1271 // Set of spilled vregs (used later to rollback properly)
1272 SmallSet<unsigned, 8> spilled;
1274 // The earliest start of a Spilled interval indicates up to where
1275 // in handled we need to roll back
1276 assert(!spillIs.empty() && "No spill intervals?");
1277 SlotIndex earliestStart = spillIs[0]->beginIndex();
1279 // Spill live intervals of virtual regs mapped to the physical register we
1280 // want to clear (and its aliases). We only spill those that overlap with the
1281 // current interval as the rest do not affect its allocation. we also keep
1282 // track of the earliest start of all spilled live intervals since this will
1283 // mark our rollback point.
1284 SmallVector<LiveInterval*, 8> added;
1285 while (!spillIs.empty()) {
1286 LiveInterval *sli = spillIs.back();
1288 DEBUG(dbgs() << "\t\t\tspilling(a): " << *sli << '\n');
1289 if (sli->beginIndex() < earliestStart)
1290 earliestStart = sli->beginIndex();
1291 spiller_->spill(sli, added, spillIs);
1292 spilled.insert(sli->reg);
1295 // Include any added intervals in earliestStart.
1296 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1297 SlotIndex SI = added[i]->beginIndex();
1298 if (SI < earliestStart)
1302 DEBUG(dbgs() << "\t\trolling back to: " << earliestStart << '\n');
1304 // Scan handled in reverse order up to the earliest start of a
1305 // spilled live interval and undo each one, restoring the state of
1307 while (!handled_.empty()) {
1308 LiveInterval* i = handled_.back();
1309 // If this interval starts before t we are done.
1310 if (!i->empty() && i->beginIndex() < earliestStart)
1312 DEBUG(dbgs() << "\t\t\tundo changes for: " << *i << '\n');
1313 handled_.pop_back();
1315 // When undoing a live interval allocation we must know if it is active or
1316 // inactive to properly update regUse_ and the VirtRegMap.
1317 IntervalPtrs::iterator it;
1318 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
1320 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1321 if (!spilled.count(i->reg))
1323 delRegUse(vrm_->getPhys(i->reg));
1324 vrm_->clearVirt(i->reg);
1325 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
1326 inactive_.erase(it);
1327 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1328 if (!spilled.count(i->reg))
1330 vrm_->clearVirt(i->reg);
1332 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
1333 "Can only allocate virtual registers!");
1334 vrm_->clearVirt(i->reg);
1338 DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
1339 if (ii == DowngradeMap.end())
1340 // It interval has a preference, it must be defined by a copy. Clear the
1341 // preference now since the source interval allocation may have been
1343 mri_->setRegAllocationHint(i->reg, 0, 0);
1345 UpgradeRegister(ii->second);
1349 // Rewind the iterators in the active, inactive, and fixed lists back to the
1350 // point we reverted to.
1351 RevertVectorIteratorsTo(active_, earliestStart);
1352 RevertVectorIteratorsTo(inactive_, earliestStart);
1353 RevertVectorIteratorsTo(fixed_, earliestStart);
1355 // Scan the rest and undo each interval that expired after t and
1356 // insert it in active (the next iteration of the algorithm will
1357 // put it in inactive if required)
1358 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
1359 LiveInterval *HI = handled_[i];
1360 if (!HI->expiredAt(earliestStart) &&
1361 HI->expiredAt(cur->beginIndex())) {
1362 DEBUG(dbgs() << "\t\t\tundo changes for: " << *HI << '\n');
1363 active_.push_back(std::make_pair(HI, HI->begin()));
1364 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
1365 addRegUse(vrm_->getPhys(HI->reg));
1369 // Merge added with unhandled.
1370 // This also update the NextReloadMap. That is, it adds mapping from a
1371 // register defined by a reload from SS to the next reload from SS in the
1372 // same basic block.
1373 MachineBasicBlock *LastReloadMBB = 0;
1374 LiveInterval *LastReload = 0;
1375 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1376 std::sort(added.begin(), added.end(), LISorter());
1377 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1378 LiveInterval *ReloadLi = added[i];
1379 if (ReloadLi->weight == HUGE_VALF &&
1380 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1381 SlotIndex ReloadIdx = ReloadLi->beginIndex();
1382 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1383 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1384 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1385 // Last reload of same SS is in the same MBB. We want to try to
1386 // allocate both reloads the same register and make sure the reg
1387 // isn't clobbered in between if at all possible.
1388 assert(LastReload->beginIndex() < ReloadIdx);
1389 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1391 LastReloadMBB = ReloadMBB;
1392 LastReload = ReloadLi;
1393 LastReloadSS = ReloadSS;
1395 unhandled_.push(ReloadLi);
1399 unsigned RALinScan::getFreePhysReg(LiveInterval* cur,
1400 const TargetRegisterClass *RC,
1401 unsigned MaxInactiveCount,
1402 SmallVector<unsigned, 256> &inactiveCounts,
1404 unsigned FreeReg = 0;
1405 unsigned FreeRegInactiveCount = 0;
1407 std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(cur->reg);
1408 // Resolve second part of the hint (if possible) given the current allocation.
1409 unsigned physReg = Hint.second;
1411 TargetRegisterInfo::isVirtualRegister(physReg) && vrm_->hasPhys(physReg))
1412 physReg = vrm_->getPhys(physReg);
1414 TargetRegisterClass::iterator I, E;
1415 tie(I, E) = tri_->getAllocationOrder(RC, Hint.first, physReg, *mf_);
1416 assert(I != E && "No allocatable register in this register class!");
1418 // Scan for the first available register.
1419 for (; I != E; ++I) {
1421 // Ignore "downgraded" registers.
1422 if (SkipDGRegs && DowngradedRegs.count(Reg))
1424 // Skip reserved registers.
1425 if (reservedRegs_.test(Reg))
1427 // Skip recently allocated registers.
1428 if (isRegAvail(Reg) && !isRecentlyUsed(Reg)) {
1430 if (FreeReg < inactiveCounts.size())
1431 FreeRegInactiveCount = inactiveCounts[FreeReg];
1433 FreeRegInactiveCount = 0;
1438 // If there are no free regs, or if this reg has the max inactive count,
1439 // return this register.
1440 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount) {
1441 // Remember what register we picked so we can skip it next time.
1442 if (FreeReg != 0) recordRecentlyUsed(FreeReg);
1446 // Continue scanning the registers, looking for the one with the highest
1447 // inactive count. Alkis found that this reduced register pressure very
1448 // slightly on X86 (in rev 1.94 of this file), though this should probably be
1450 for (; I != E; ++I) {
1452 // Ignore "downgraded" registers.
1453 if (SkipDGRegs && DowngradedRegs.count(Reg))
1455 // Skip reserved registers.
1456 if (reservedRegs_.test(Reg))
1458 if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
1459 FreeRegInactiveCount < inactiveCounts[Reg] && !isRecentlyUsed(Reg)) {
1461 FreeRegInactiveCount = inactiveCounts[Reg];
1462 if (FreeRegInactiveCount == MaxInactiveCount)
1463 break; // We found the one with the max inactive count.
1467 // Remember what register we picked so we can skip it next time.
1468 recordRecentlyUsed(FreeReg);
1473 /// getFreePhysReg - return a free physical register for this virtual register
1474 /// interval if we have one, otherwise return 0.
1475 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
1476 SmallVector<unsigned, 256> inactiveCounts;
1477 unsigned MaxInactiveCount = 0;
1479 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
1480 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1482 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
1484 unsigned reg = i->first->reg;
1485 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1486 "Can only allocate virtual registers!");
1488 // If this is not in a related reg class to the register we're allocating,
1490 const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
1491 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
1492 reg = vrm_->getPhys(reg);
1493 if (inactiveCounts.size() <= reg)
1494 inactiveCounts.resize(reg+1);
1495 ++inactiveCounts[reg];
1496 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
1500 // If copy coalescer has assigned a "preferred" register, check if it's
1502 unsigned Preference = vrm_->getRegAllocPref(cur->reg);
1504 DEBUG(dbgs() << "(preferred: " << tri_->getName(Preference) << ") ");
1505 if (isRegAvail(Preference) &&
1506 RC->contains(Preference))
1510 if (!DowngradedRegs.empty()) {
1511 unsigned FreeReg = getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts,
1516 return getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts, false);
1519 FunctionPass* llvm::createLinearScanRegisterAllocator() {
1520 return new RALinScan();