1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "VirtRegMap.h"
16 #include "VirtRegRewriter.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/CalcSpillWeights.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/LiveStackAnalysis.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/MachineLoopInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/RegAllocRegistry.h"
28 #include "llvm/CodeGen/RegisterCoalescer.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/ADT/EquivalenceClasses.h"
34 #include "llvm/ADT/SmallSet.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/ADT/STLExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
48 STATISTIC(NumIters , "Number of iterations performed");
49 STATISTIC(NumBacktracks, "Number of times we had to backtrack");
50 STATISTIC(NumCoalesce, "Number of copies coalesced");
51 STATISTIC(NumDowngrade, "Number of registers downgraded");
54 NewHeuristic("new-spilling-heuristic",
55 cl::desc("Use new spilling heuristic"),
56 cl::init(false), cl::Hidden);
59 PreSplitIntervals("pre-alloc-split",
60 cl::desc("Pre-register allocation live interval splitting"),
61 cl::init(false), cl::Hidden);
64 TrivCoalesceEnds("trivial-coalesce-ends",
65 cl::desc("Attempt trivial coalescing of interval ends"),
66 cl::init(false), cl::Hidden);
68 static RegisterRegAlloc
69 linearscanRegAlloc("linearscan", "linear scan register allocator",
70 createLinearScanRegisterAllocator);
73 // When we allocate a register, add it to a fixed-size queue of
74 // registers to skip in subsequent allocations. This trades a small
75 // amount of register pressure and increased spills for flexibility in
76 // the post-pass scheduler.
78 // Note that in a the number of registers used for reloading spills
79 // will be one greater than the value of this option.
81 // One big limitation of this is that it doesn't differentiate between
82 // different register classes. So on x86-64, if there is xmm register
83 // pressure, it can caused fewer GPRs to be held in the queue.
84 static cl::opt<unsigned>
85 NumRecentlyUsedRegs("linearscan-skip-count",
86 cl::desc("Number of registers for linearscan to remember to skip."),
90 struct RALinScan : public MachineFunctionPass {
92 RALinScan() : MachineFunctionPass(&ID) {
93 // Initialize the queue to record recently-used registers.
94 if (NumRecentlyUsedRegs > 0)
95 RecentRegs.resize(NumRecentlyUsedRegs, 0);
96 RecentNext = RecentRegs.begin();
99 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
100 typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
102 /// RelatedRegClasses - This structure is built the first time a function is
103 /// compiled, and keeps track of which register classes have registers that
104 /// belong to multiple classes or have aliases that are in other classes.
105 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
106 DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
108 // NextReloadMap - For each register in the map, it maps to the another
109 // register which is defined by a reload from the same stack slot and
110 // both reloads are in the same basic block.
111 DenseMap<unsigned, unsigned> NextReloadMap;
113 // DowngradedRegs - A set of registers which are being "downgraded", i.e.
114 // un-favored for allocation.
115 SmallSet<unsigned, 8> DowngradedRegs;
117 // DowngradeMap - A map from virtual registers to physical registers being
118 // downgraded for the virtual registers.
119 DenseMap<unsigned, unsigned> DowngradeMap;
121 MachineFunction* mf_;
122 MachineRegisterInfo* mri_;
123 const TargetMachine* tm_;
124 const TargetRegisterInfo* tri_;
125 const TargetInstrInfo* tii_;
126 BitVector allocatableRegs_;
129 const MachineLoopInfo *loopInfo;
131 /// handled_ - Intervals are added to the handled_ set in the order of their
132 /// start value. This is uses for backtracking.
133 std::vector<LiveInterval*> handled_;
135 /// fixed_ - Intervals that correspond to machine registers.
139 /// active_ - Intervals that are currently being processed, and which have a
140 /// live range active for the current point.
141 IntervalPtrs active_;
143 /// inactive_ - Intervals that are currently being processed, but which have
144 /// a hold at the current point.
145 IntervalPtrs inactive_;
147 typedef std::priority_queue<LiveInterval*,
148 SmallVector<LiveInterval*, 64>,
149 greater_ptr<LiveInterval> > IntervalHeap;
150 IntervalHeap unhandled_;
152 /// regUse_ - Tracks register usage.
153 SmallVector<unsigned, 32> regUse_;
154 SmallVector<unsigned, 32> regUseBackUp_;
156 /// vrm_ - Tracks register assignments.
159 std::auto_ptr<VirtRegRewriter> rewriter_;
161 std::auto_ptr<Spiller> spiller_;
163 // The queue of recently-used registers.
164 SmallVector<unsigned, 4> RecentRegs;
165 SmallVector<unsigned, 4>::iterator RecentNext;
167 // Record that we just picked this register.
168 void recordRecentlyUsed(unsigned reg) {
169 assert(reg != 0 && "Recently used register is NOREG!");
170 if (!RecentRegs.empty()) {
172 if (RecentNext == RecentRegs.end())
173 RecentNext = RecentRegs.begin();
178 virtual const char* getPassName() const {
179 return "Linear Scan Register Allocator";
182 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
183 AU.setPreservesCFG();
184 AU.addRequired<LiveIntervals>();
185 AU.addPreserved<SlotIndexes>();
187 AU.addRequiredID(StrongPHIEliminationID);
188 // Make sure PassManager knows which analyses to make available
189 // to coalescing and which analyses coalescing invalidates.
190 AU.addRequiredTransitive<RegisterCoalescer>();
191 AU.addRequired<CalculateSpillWeights>();
192 if (PreSplitIntervals)
193 AU.addRequiredID(PreAllocSplittingID);
194 AU.addRequired<LiveStacks>();
195 AU.addPreserved<LiveStacks>();
196 AU.addRequired<MachineLoopInfo>();
197 AU.addPreserved<MachineLoopInfo>();
198 AU.addRequired<VirtRegMap>();
199 AU.addPreserved<VirtRegMap>();
200 AU.addPreservedID(MachineDominatorsID);
201 MachineFunctionPass::getAnalysisUsage(AU);
204 /// runOnMachineFunction - register allocate the whole function
205 bool runOnMachineFunction(MachineFunction&);
207 // Determine if we skip this register due to its being recently used.
208 bool isRecentlyUsed(unsigned reg) const {
209 return std::find(RecentRegs.begin(), RecentRegs.end(), reg) !=
214 /// linearScan - the linear scan algorithm
217 /// initIntervalSets - initialize the interval sets.
219 void initIntervalSets();
221 /// processActiveIntervals - expire old intervals and move non-overlapping
222 /// ones to the inactive list.
223 void processActiveIntervals(SlotIndex CurPoint);
225 /// processInactiveIntervals - expire old intervals and move overlapping
226 /// ones to the active list.
227 void processInactiveIntervals(SlotIndex CurPoint);
229 /// hasNextReloadInterval - Return the next liveinterval that's being
230 /// defined by a reload from the same SS as the specified one.
231 LiveInterval *hasNextReloadInterval(LiveInterval *cur);
233 /// DowngradeRegister - Downgrade a register for allocation.
234 void DowngradeRegister(LiveInterval *li, unsigned Reg);
236 /// UpgradeRegister - Upgrade a register for allocation.
237 void UpgradeRegister(unsigned Reg);
239 /// assignRegOrStackSlotAtInterval - assign a register if one
240 /// is available, or spill.
241 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
243 void updateSpillWeights(std::vector<float> &Weights,
244 unsigned reg, float weight,
245 const TargetRegisterClass *RC);
247 /// findIntervalsToSpill - Determine the intervals to spill for the
248 /// specified interval. It's passed the physical registers whose spill
249 /// weight is the lowest among all the registers whose live intervals
250 /// conflict with the interval.
251 void findIntervalsToSpill(LiveInterval *cur,
252 std::vector<std::pair<unsigned,float> > &Candidates,
254 SmallVector<LiveInterval*, 8> &SpillIntervals);
256 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
257 /// try allocate the definition the same register as the source register
258 /// if the register is not defined during live time of the interval. This
259 /// eliminate a copy. This is used to coalesce copies which were not
260 /// coalesced away before allocation either due to dest and src being in
261 /// different register classes or because the coalescer was overly
263 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
266 /// Register usage / availability tracking helpers.
270 regUse_.resize(tri_->getNumRegs(), 0);
271 regUseBackUp_.resize(tri_->getNumRegs(), 0);
274 void finalizeRegUses() {
276 // Verify all the registers are "freed".
278 for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
279 if (regUse_[i] != 0) {
280 dbgs() << tri_->getName(i) << " is still in use!\n";
288 regUseBackUp_.clear();
291 void addRegUse(unsigned physReg) {
292 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
293 "should be physical register!");
295 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
299 void delRegUse(unsigned physReg) {
300 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
301 "should be physical register!");
302 assert(regUse_[physReg] != 0);
304 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
305 assert(regUse_[*as] != 0);
310 bool isRegAvail(unsigned physReg) const {
311 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
312 "should be physical register!");
313 return regUse_[physReg] == 0;
316 void backUpRegUses() {
317 regUseBackUp_ = regUse_;
320 void restoreRegUses() {
321 regUse_ = regUseBackUp_;
325 /// Register handling helpers.
328 /// getFreePhysReg - return a free physical register for this virtual
329 /// register interval if we have one, otherwise return 0.
330 unsigned getFreePhysReg(LiveInterval* cur);
331 unsigned getFreePhysReg(LiveInterval* cur,
332 const TargetRegisterClass *RC,
333 unsigned MaxInactiveCount,
334 SmallVector<unsigned, 256> &inactiveCounts,
337 void ComputeRelatedRegClasses();
339 template <typename ItTy>
340 void printIntervals(const char* const str, ItTy i, ItTy e) const {
343 dbgs() << str << " intervals:\n";
345 for (; i != e; ++i) {
346 dbgs() << "\t" << *i->first << " -> ";
348 unsigned reg = i->first->reg;
349 if (TargetRegisterInfo::isVirtualRegister(reg))
350 reg = vrm_->getPhys(reg);
352 dbgs() << tri_->getName(reg) << '\n';
357 char RALinScan::ID = 0;
360 static RegisterPass<RALinScan>
361 X("linearscan-regalloc", "Linear Scan Register Allocator");
363 void RALinScan::ComputeRelatedRegClasses() {
364 // First pass, add all reg classes to the union, and determine at least one
365 // reg class that each register is in.
366 bool HasAliases = false;
367 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
368 E = tri_->regclass_end(); RCI != E; ++RCI) {
369 RelatedRegClasses.insert(*RCI);
370 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
372 HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
374 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
376 // Already processed this register. Just make sure we know that
377 // multiple register classes share a register.
378 RelatedRegClasses.unionSets(PRC, *RCI);
385 // Second pass, now that we know conservatively what register classes each reg
386 // belongs to, add info about aliases. We don't need to do this for targets
387 // without register aliases.
389 for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
390 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
392 for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
393 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
396 /// attemptTrivialCoalescing - If a simple interval is defined by a copy, try
397 /// allocate the definition the same register as the source register if the
398 /// register is not defined during live time of the interval. If the interval is
399 /// killed by a copy, try to use the destination register. This eliminates a
400 /// copy. This is used to coalesce copies which were not coalesced away before
401 /// allocation either due to dest and src being in different register classes or
402 /// because the coalescer was overly conservative.
403 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
404 unsigned Preference = vrm_->getRegAllocPref(cur.reg);
405 if ((Preference && Preference == Reg) || !cur.containsOneValue())
408 // We cannot handle complicated live ranges. Simple linear stuff only.
409 if (cur.ranges.size() != 1)
412 const LiveRange &range = cur.ranges.front();
414 VNInfo *vni = range.valno;
420 MachineInstr *CopyMI;
421 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
422 if (vni->def != SlotIndex() && vni->isDefAccurate() &&
423 (CopyMI = li_->getInstructionFromIndex(vni->def)) &&
424 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
425 // Defined by a copy, try to extend SrcReg forward
427 else if (TrivCoalesceEnds &&
429 li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
430 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
432 // Only used by a copy, try to extend DstReg backwards
438 if (TargetRegisterInfo::isVirtualRegister(CandReg)) {
439 if (!vrm_->isAssignedReg(CandReg))
441 CandReg = vrm_->getPhys(CandReg);
446 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
447 if (!RC->contains(CandReg))
450 if (li_->conflictsWithPhysReg(cur, *vrm_, CandReg))
454 DEBUG(dbgs() << "Coalescing: " << cur << " -> " << tri_->getName(CandReg)
456 vrm_->clearVirt(cur.reg);
457 vrm_->assignVirt2Phys(cur.reg, CandReg);
463 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
465 mri_ = &fn.getRegInfo();
466 tm_ = &fn.getTarget();
467 tri_ = tm_->getRegisterInfo();
468 tii_ = tm_->getInstrInfo();
469 allocatableRegs_ = tri_->getAllocatableSet(fn);
470 li_ = &getAnalysis<LiveIntervals>();
471 ls_ = &getAnalysis<LiveStacks>();
472 loopInfo = &getAnalysis<MachineLoopInfo>();
474 // We don't run the coalescer here because we have no reason to
475 // interact with it. If the coalescer requires interaction, it
476 // won't do anything. If it doesn't require interaction, we assume
477 // it was run as a separate pass.
479 // If this is the first function compiled, compute the related reg classes.
480 if (RelatedRegClasses.empty())
481 ComputeRelatedRegClasses();
483 // Also resize register usage trackers.
486 vrm_ = &getAnalysis<VirtRegMap>();
487 if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
489 spiller_.reset(createSpiller(mf_, li_, loopInfo, vrm_));
495 // Rewrite spill code and update the PhysRegsUsed set.
496 rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
498 assert(unhandled_.empty() && "Unhandled live intervals remain!");
506 NextReloadMap.clear();
507 DowngradedRegs.clear();
508 DowngradeMap.clear();
514 /// initIntervalSets - initialize the interval sets.
516 void RALinScan::initIntervalSets()
518 assert(unhandled_.empty() && fixed_.empty() &&
519 active_.empty() && inactive_.empty() &&
520 "interval sets should be empty on initialization");
522 handled_.reserve(li_->getNumIntervals());
524 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
525 if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
526 if (!i->second->empty()) {
527 mri_->setPhysRegUsed(i->second->reg);
528 fixed_.push_back(std::make_pair(i->second, i->second->begin()));
531 if (i->second->empty()) {
532 assignRegOrStackSlotAtInterval(i->second);
535 unhandled_.push(i->second);
540 void RALinScan::linearScan() {
541 // linear scan algorithm
543 dbgs() << "********** LINEAR SCAN **********\n"
544 << "********** Function: "
545 << mf_->getFunction()->getName() << '\n';
546 printIntervals("fixed", fixed_.begin(), fixed_.end());
549 while (!unhandled_.empty()) {
550 // pick the interval with the earliest start point
551 LiveInterval* cur = unhandled_.top();
554 DEBUG(dbgs() << "\n*** CURRENT ***: " << *cur << '\n');
556 assert(!cur->empty() && "Empty interval in unhandled set.");
558 processActiveIntervals(cur->beginIndex());
559 processInactiveIntervals(cur->beginIndex());
561 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
562 "Can only allocate virtual registers!");
564 // Allocating a virtual register. try to find a free
565 // physical register or spill an interval (possibly this one) in order to
567 assignRegOrStackSlotAtInterval(cur);
570 printIntervals("active", active_.begin(), active_.end());
571 printIntervals("inactive", inactive_.begin(), inactive_.end());
575 // Expire any remaining active intervals
576 while (!active_.empty()) {
577 IntervalPtr &IP = active_.back();
578 unsigned reg = IP.first->reg;
579 DEBUG(dbgs() << "\tinterval " << *IP.first << " expired\n");
580 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
581 "Can only allocate virtual registers!");
582 reg = vrm_->getPhys(reg);
587 // Expire any remaining inactive intervals
589 for (IntervalPtrs::reverse_iterator
590 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
591 dbgs() << "\tinterval " << *i->first << " expired\n";
595 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
596 MachineFunction::iterator EntryMBB = mf_->begin();
597 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
598 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
599 LiveInterval &cur = *i->second;
601 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
604 else if (vrm_->isAssignedReg(cur.reg))
605 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
608 // Ignore splited live intervals.
609 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
612 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
614 const LiveRange &LR = *I;
615 if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
616 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
617 if (LiveInMBBs[i] != EntryMBB) {
618 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
619 "Adding a virtual register to livein set?");
620 LiveInMBBs[i]->addLiveIn(Reg);
627 DEBUG(dbgs() << *vrm_);
629 // Look for physical registers that end up not being allocated even though
630 // register allocator had to spill other registers in its register class.
631 if (ls_->getNumIntervals() == 0)
633 if (!vrm_->FindUnusedRegisters(li_))
637 /// processActiveIntervals - expire old intervals and move non-overlapping ones
638 /// to the inactive list.
639 void RALinScan::processActiveIntervals(SlotIndex CurPoint)
641 DEBUG(dbgs() << "\tprocessing active intervals:\n");
643 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
644 LiveInterval *Interval = active_[i].first;
645 LiveInterval::iterator IntervalPos = active_[i].second;
646 unsigned reg = Interval->reg;
648 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
650 if (IntervalPos == Interval->end()) { // Remove expired intervals.
651 DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
652 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
653 "Can only allocate virtual registers!");
654 reg = vrm_->getPhys(reg);
657 // Pop off the end of the list.
658 active_[i] = active_.back();
662 } else if (IntervalPos->start > CurPoint) {
663 // Move inactive intervals to inactive list.
664 DEBUG(dbgs() << "\t\tinterval " << *Interval << " inactive\n");
665 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
666 "Can only allocate virtual registers!");
667 reg = vrm_->getPhys(reg);
670 inactive_.push_back(std::make_pair(Interval, IntervalPos));
672 // Pop off the end of the list.
673 active_[i] = active_.back();
677 // Otherwise, just update the iterator position.
678 active_[i].second = IntervalPos;
683 /// processInactiveIntervals - expire old intervals and move overlapping
684 /// ones to the active list.
685 void RALinScan::processInactiveIntervals(SlotIndex CurPoint)
687 DEBUG(dbgs() << "\tprocessing inactive intervals:\n");
689 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
690 LiveInterval *Interval = inactive_[i].first;
691 LiveInterval::iterator IntervalPos = inactive_[i].second;
692 unsigned reg = Interval->reg;
694 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
696 if (IntervalPos == Interval->end()) { // remove expired intervals.
697 DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
699 // Pop off the end of the list.
700 inactive_[i] = inactive_.back();
701 inactive_.pop_back();
703 } else if (IntervalPos->start <= CurPoint) {
704 // move re-activated intervals in active list
705 DEBUG(dbgs() << "\t\tinterval " << *Interval << " active\n");
706 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
707 "Can only allocate virtual registers!");
708 reg = vrm_->getPhys(reg);
711 active_.push_back(std::make_pair(Interval, IntervalPos));
713 // Pop off the end of the list.
714 inactive_[i] = inactive_.back();
715 inactive_.pop_back();
718 // Otherwise, just update the iterator position.
719 inactive_[i].second = IntervalPos;
724 /// updateSpillWeights - updates the spill weights of the specifed physical
725 /// register and its weight.
726 void RALinScan::updateSpillWeights(std::vector<float> &Weights,
727 unsigned reg, float weight,
728 const TargetRegisterClass *RC) {
729 SmallSet<unsigned, 4> Processed;
730 SmallSet<unsigned, 4> SuperAdded;
731 SmallVector<unsigned, 4> Supers;
732 Weights[reg] += weight;
733 Processed.insert(reg);
734 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
735 Weights[*as] += weight;
736 Processed.insert(*as);
737 if (tri_->isSubRegister(*as, reg) &&
738 SuperAdded.insert(*as) &&
740 Supers.push_back(*as);
744 // If the alias is a super-register, and the super-register is in the
745 // register class we are trying to allocate. Then add the weight to all
746 // sub-registers of the super-register even if they are not aliases.
747 // e.g. allocating for GR32, bh is not used, updating bl spill weight.
748 // bl should get the same spill weight otherwise it will be choosen
749 // as a spill candidate since spilling bh doesn't make ebx available.
750 for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
751 for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
752 if (!Processed.count(*sr))
753 Weights[*sr] += weight;
758 RALinScan::IntervalPtrs::iterator
759 FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
760 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
762 if (I->first == LI) return I;
766 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, SlotIndex Point){
767 for (unsigned i = 0, e = V.size(); i != e; ++i) {
768 RALinScan::IntervalPtr &IP = V[i];
769 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
771 if (I != IP.first->begin()) --I;
776 /// addStackInterval - Create a LiveInterval for stack if the specified live
777 /// interval has been spilled.
778 static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
780 MachineRegisterInfo* mri_, VirtRegMap &vrm_) {
781 int SS = vrm_.getStackSlot(cur->reg);
782 if (SS == VirtRegMap::NO_STACK_SLOT)
785 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
786 LiveInterval &SI = ls_->getOrCreateInterval(SS, RC);
789 if (SI.hasAtLeastOneValue())
790 VNI = SI.getValNumInfo(0);
792 VNI = SI.getNextValue(SlotIndex(), 0, false,
793 ls_->getVNInfoAllocator());
795 LiveInterval &RI = li_->getInterval(cur->reg);
796 // FIXME: This may be overly conservative.
797 SI.MergeRangesInAsValue(RI, VNI);
800 /// getConflictWeight - Return the number of conflicts between cur
801 /// live interval and defs and uses of Reg weighted by loop depthes.
803 float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
804 MachineRegisterInfo *mri_,
805 const MachineLoopInfo *loopInfo) {
807 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
808 E = mri_->reg_end(); I != E; ++I) {
809 MachineInstr *MI = &*I;
810 if (cur->liveAt(li_->getInstructionIndex(MI))) {
811 unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
812 Conflicts += std::pow(10.0f, (float)loopDepth);
818 /// findIntervalsToSpill - Determine the intervals to spill for the
819 /// specified interval. It's passed the physical registers whose spill
820 /// weight is the lowest among all the registers whose live intervals
821 /// conflict with the interval.
822 void RALinScan::findIntervalsToSpill(LiveInterval *cur,
823 std::vector<std::pair<unsigned,float> > &Candidates,
825 SmallVector<LiveInterval*, 8> &SpillIntervals) {
826 // We have figured out the *best* register to spill. But there are other
827 // registers that are pretty good as well (spill weight within 3%). Spill
828 // the one that has fewest defs and uses that conflict with cur.
829 float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
830 SmallVector<LiveInterval*, 8> SLIs[3];
833 dbgs() << "\tConsidering " << NumCands << " candidates: ";
834 for (unsigned i = 0; i != NumCands; ++i)
835 dbgs() << tri_->getName(Candidates[i].first) << " ";
839 // Calculate the number of conflicts of each candidate.
840 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
841 unsigned Reg = i->first->reg;
842 unsigned PhysReg = vrm_->getPhys(Reg);
843 if (!cur->overlapsFrom(*i->first, i->second))
845 for (unsigned j = 0; j < NumCands; ++j) {
846 unsigned Candidate = Candidates[j].first;
847 if (tri_->regsOverlap(PhysReg, Candidate)) {
849 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
850 SLIs[j].push_back(i->first);
855 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
856 unsigned Reg = i->first->reg;
857 unsigned PhysReg = vrm_->getPhys(Reg);
858 if (!cur->overlapsFrom(*i->first, i->second-1))
860 for (unsigned j = 0; j < NumCands; ++j) {
861 unsigned Candidate = Candidates[j].first;
862 if (tri_->regsOverlap(PhysReg, Candidate)) {
864 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
865 SLIs[j].push_back(i->first);
870 // Which is the best candidate?
871 unsigned BestCandidate = 0;
872 float MinConflicts = Conflicts[0];
873 for (unsigned i = 1; i != NumCands; ++i) {
874 if (Conflicts[i] < MinConflicts) {
876 MinConflicts = Conflicts[i];
880 std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
881 std::back_inserter(SpillIntervals));
885 struct WeightCompare {
887 const RALinScan &Allocator;
890 WeightCompare(const RALinScan &Alloc) : Allocator(Alloc) {}
892 typedef std::pair<unsigned, float> RegWeightPair;
893 bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
894 return LHS.second < RHS.second && !Allocator.isRecentlyUsed(LHS.first);
899 static bool weightsAreClose(float w1, float w2) {
903 float diff = w1 - w2;
904 if (diff <= 0.02f) // Within 0.02f
906 return (diff / w2) <= 0.05f; // Within 5%.
909 LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
910 DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
911 if (I == NextReloadMap.end())
913 return &li_->getInterval(I->second);
916 void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
917 bool isNew = DowngradedRegs.insert(Reg);
918 isNew = isNew; // Silence compiler warning.
919 assert(isNew && "Multiple reloads holding the same register?");
920 DowngradeMap.insert(std::make_pair(li->reg, Reg));
921 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS) {
922 isNew = DowngradedRegs.insert(*AS);
923 isNew = isNew; // Silence compiler warning.
924 assert(isNew && "Multiple reloads holding the same register?");
925 DowngradeMap.insert(std::make_pair(li->reg, *AS));
930 void RALinScan::UpgradeRegister(unsigned Reg) {
932 DowngradedRegs.erase(Reg);
933 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
934 DowngradedRegs.erase(*AS);
940 bool operator()(LiveInterval* A, LiveInterval* B) {
941 return A->beginIndex() < B->beginIndex();
946 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
948 void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
949 DEBUG(dbgs() << "\tallocating current interval: ");
951 // This is an implicitly defined live interval, just assign any register.
952 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
954 unsigned physReg = vrm_->getRegAllocPref(cur->reg);
956 physReg = *RC->allocation_order_begin(*mf_);
957 DEBUG(dbgs() << tri_->getName(physReg) << '\n');
958 // Note the register is not really in use.
959 vrm_->assignVirt2Phys(cur->reg, physReg);
965 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
966 SlotIndex StartPosition = cur->beginIndex();
967 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
969 // If start of this live interval is defined by a move instruction and its
970 // source is assigned a physical register that is compatible with the target
971 // register class, then we should try to assign it the same register.
972 // This can happen when the move is from a larger register class to a smaller
973 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
974 if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
975 VNInfo *vni = cur->begin()->valno;
976 if ((vni->def != SlotIndex()) && !vni->isUnused() &&
977 vni->isDefAccurate()) {
978 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
979 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
981 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
983 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
985 else if (vrm_->isAssignedReg(SrcReg))
986 Reg = vrm_->getPhys(SrcReg);
989 Reg = tri_->getSubReg(Reg, SrcSubReg);
991 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
992 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
993 mri_->setRegAllocationHint(cur->reg, 0, Reg);
999 // For every interval in inactive we overlap with, mark the
1000 // register as not free and update spill weights.
1001 for (IntervalPtrs::const_iterator i = inactive_.begin(),
1002 e = inactive_.end(); i != e; ++i) {
1003 unsigned Reg = i->first->reg;
1004 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
1005 "Can only allocate virtual registers!");
1006 const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
1007 // If this is not in a related reg class to the register we're allocating,
1009 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1010 cur->overlapsFrom(*i->first, i->second-1)) {
1011 Reg = vrm_->getPhys(Reg);
1013 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
1017 // Speculatively check to see if we can get a register right now. If not,
1018 // we know we won't be able to by adding more constraints. If so, we can
1019 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
1020 // is very bad (it contains all callee clobbered registers for any functions
1021 // with a call), so we want to avoid doing that if possible.
1022 unsigned physReg = getFreePhysReg(cur);
1023 unsigned BestPhysReg = physReg;
1025 // We got a register. However, if it's in the fixed_ list, we might
1026 // conflict with it. Check to see if we conflict with it or any of its
1028 SmallSet<unsigned, 8> RegAliases;
1029 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
1030 RegAliases.insert(*AS);
1032 bool ConflictsWithFixed = false;
1033 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1034 IntervalPtr &IP = fixed_[i];
1035 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
1036 // Okay, this reg is on the fixed list. Check to see if we actually
1038 LiveInterval *I = IP.first;
1039 if (I->endIndex() > StartPosition) {
1040 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1042 if (II != I->begin() && II->start > StartPosition)
1044 if (cur->overlapsFrom(*I, II)) {
1045 ConflictsWithFixed = true;
1052 // Okay, the register picked by our speculative getFreePhysReg call turned
1053 // out to be in use. Actually add all of the conflicting fixed registers to
1054 // regUse_ so we can do an accurate query.
1055 if (ConflictsWithFixed) {
1056 // For every interval in fixed we overlap with, mark the register as not
1057 // free and update spill weights.
1058 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1059 IntervalPtr &IP = fixed_[i];
1060 LiveInterval *I = IP.first;
1062 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
1063 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1064 I->endIndex() > StartPosition) {
1065 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1067 if (II != I->begin() && II->start > StartPosition)
1069 if (cur->overlapsFrom(*I, II)) {
1070 unsigned reg = I->reg;
1072 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
1077 // Using the newly updated regUse_ object, which includes conflicts in the
1078 // future, see if there are any registers available.
1079 physReg = getFreePhysReg(cur);
1083 // Restore the physical register tracker, removing information about the
1087 // If we find a free register, we are done: assign this virtual to
1088 // the free physical register and add this interval to the active
1091 DEBUG(dbgs() << tri_->getName(physReg) << '\n');
1092 vrm_->assignVirt2Phys(cur->reg, physReg);
1094 active_.push_back(std::make_pair(cur, cur->begin()));
1095 handled_.push_back(cur);
1097 // "Upgrade" the physical register since it has been allocated.
1098 UpgradeRegister(physReg);
1099 if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
1100 // "Downgrade" physReg to try to keep physReg from being allocated until
1101 // the next reload from the same SS is allocated.
1102 mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg);
1103 DowngradeRegister(cur, physReg);
1107 DEBUG(dbgs() << "no free registers\n");
1109 // Compile the spill weights into an array that is better for scanning.
1110 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
1111 for (std::vector<std::pair<unsigned, float> >::iterator
1112 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
1113 updateSpillWeights(SpillWeights, I->first, I->second, RC);
1115 // for each interval in active, update spill weights.
1116 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
1118 unsigned reg = i->first->reg;
1119 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1120 "Can only allocate virtual registers!");
1121 reg = vrm_->getPhys(reg);
1122 updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
1125 DEBUG(dbgs() << "\tassigning stack slot at interval "<< *cur << ":\n");
1127 // Find a register to spill.
1128 float minWeight = HUGE_VALF;
1129 unsigned minReg = 0;
1132 std::vector<std::pair<unsigned,float> > RegsWeights;
1133 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
1134 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1135 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1137 float regWeight = SpillWeights[reg];
1138 // Skip recently allocated registers.
1139 if (minWeight > regWeight && !isRecentlyUsed(reg))
1141 RegsWeights.push_back(std::make_pair(reg, regWeight));
1144 // If we didn't find a register that is spillable, try aliases?
1146 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1147 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1149 // No need to worry about if the alias register size < regsize of RC.
1150 // We are going to spill all registers that alias it anyway.
1151 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
1152 RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
1156 // Sort all potential spill candidates by weight.
1157 std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare(*this));
1158 minReg = RegsWeights[0].first;
1159 minWeight = RegsWeights[0].second;
1160 if (minWeight == HUGE_VALF) {
1161 // All registers must have inf weight. Just grab one!
1162 minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
1163 if (cur->weight == HUGE_VALF ||
1164 li_->getApproximateInstructionCount(*cur) == 0) {
1165 // Spill a physical register around defs and uses.
1166 if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
1167 // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
1168 // in fixed_. Reset them.
1169 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1170 IntervalPtr &IP = fixed_[i];
1171 LiveInterval *I = IP.first;
1172 if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
1173 IP.second = I->advanceTo(I->begin(), StartPosition);
1176 DowngradedRegs.clear();
1177 assignRegOrStackSlotAtInterval(cur);
1179 assert(false && "Ran out of registers during register allocation!");
1180 report_fatal_error("Ran out of registers during register allocation!");
1186 // Find up to 3 registers to consider as spill candidates.
1187 unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
1188 while (LastCandidate > 1) {
1189 if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
1195 dbgs() << "\t\tregister(s) with min weight(s): ";
1197 for (unsigned i = 0; i != LastCandidate; ++i)
1198 dbgs() << tri_->getName(RegsWeights[i].first)
1199 << " (" << RegsWeights[i].second << ")\n";
1202 // If the current has the minimum weight, we need to spill it and
1203 // add any added intervals back to unhandled, and restart
1205 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
1206 DEBUG(dbgs() << "\t\t\tspilling(c): " << *cur << '\n');
1207 SmallVector<LiveInterval*, 8> spillIs;
1208 std::vector<LiveInterval*> added;
1209 spiller_->spill(cur, added, spillIs);
1211 std::sort(added.begin(), added.end(), LISorter());
1212 addStackInterval(cur, ls_, li_, mri_, *vrm_);
1214 return; // Early exit if all spills were folded.
1216 // Merge added with unhandled. Note that we have already sorted
1217 // intervals returned by addIntervalsForSpills by their starting
1219 // This also update the NextReloadMap. That is, it adds mapping from a
1220 // register defined by a reload from SS to the next reload from SS in the
1221 // same basic block.
1222 MachineBasicBlock *LastReloadMBB = 0;
1223 LiveInterval *LastReload = 0;
1224 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1225 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1226 LiveInterval *ReloadLi = added[i];
1227 if (ReloadLi->weight == HUGE_VALF &&
1228 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1229 SlotIndex ReloadIdx = ReloadLi->beginIndex();
1230 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1231 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1232 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1233 // Last reload of same SS is in the same MBB. We want to try to
1234 // allocate both reloads the same register and make sure the reg
1235 // isn't clobbered in between if at all possible.
1236 assert(LastReload->beginIndex() < ReloadIdx);
1237 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1239 LastReloadMBB = ReloadMBB;
1240 LastReload = ReloadLi;
1241 LastReloadSS = ReloadSS;
1243 unhandled_.push(ReloadLi);
1250 // Push the current interval back to unhandled since we are going
1251 // to re-run at least this iteration. Since we didn't modify it it
1252 // should go back right in the front of the list
1253 unhandled_.push(cur);
1255 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
1256 "did not choose a register to spill?");
1258 // We spill all intervals aliasing the register with
1259 // minimum weight, rollback to the interval with the earliest
1260 // start point and let the linear scan algorithm run again
1261 SmallVector<LiveInterval*, 8> spillIs;
1263 // Determine which intervals have to be spilled.
1264 findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
1266 // Set of spilled vregs (used later to rollback properly)
1267 SmallSet<unsigned, 8> spilled;
1269 // The earliest start of a Spilled interval indicates up to where
1270 // in handled we need to roll back
1271 assert(!spillIs.empty() && "No spill intervals?");
1272 SlotIndex earliestStart = spillIs[0]->beginIndex();
1274 // Spill live intervals of virtual regs mapped to the physical register we
1275 // want to clear (and its aliases). We only spill those that overlap with the
1276 // current interval as the rest do not affect its allocation. we also keep
1277 // track of the earliest start of all spilled live intervals since this will
1278 // mark our rollback point.
1279 std::vector<LiveInterval*> added;
1280 while (!spillIs.empty()) {
1281 LiveInterval *sli = spillIs.back();
1283 DEBUG(dbgs() << "\t\t\tspilling(a): " << *sli << '\n');
1284 if (sli->beginIndex() < earliestStart)
1285 earliestStart = sli->beginIndex();
1287 spiller_->spill(sli, added, spillIs, &earliestStart);
1288 addStackInterval(sli, ls_, li_, mri_, *vrm_);
1289 spilled.insert(sli->reg);
1292 DEBUG(dbgs() << "\t\trolling back to: " << earliestStart << '\n');
1294 // Scan handled in reverse order up to the earliest start of a
1295 // spilled live interval and undo each one, restoring the state of
1297 while (!handled_.empty()) {
1298 LiveInterval* i = handled_.back();
1299 // If this interval starts before t we are done.
1300 if (!i->empty() && i->beginIndex() < earliestStart)
1302 DEBUG(dbgs() << "\t\t\tundo changes for: " << *i << '\n');
1303 handled_.pop_back();
1305 // When undoing a live interval allocation we must know if it is active or
1306 // inactive to properly update regUse_ and the VirtRegMap.
1307 IntervalPtrs::iterator it;
1308 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
1310 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1311 if (!spilled.count(i->reg))
1313 delRegUse(vrm_->getPhys(i->reg));
1314 vrm_->clearVirt(i->reg);
1315 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
1316 inactive_.erase(it);
1317 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1318 if (!spilled.count(i->reg))
1320 vrm_->clearVirt(i->reg);
1322 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
1323 "Can only allocate virtual registers!");
1324 vrm_->clearVirt(i->reg);
1328 DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
1329 if (ii == DowngradeMap.end())
1330 // It interval has a preference, it must be defined by a copy. Clear the
1331 // preference now since the source interval allocation may have been
1333 mri_->setRegAllocationHint(i->reg, 0, 0);
1335 UpgradeRegister(ii->second);
1339 // Rewind the iterators in the active, inactive, and fixed lists back to the
1340 // point we reverted to.
1341 RevertVectorIteratorsTo(active_, earliestStart);
1342 RevertVectorIteratorsTo(inactive_, earliestStart);
1343 RevertVectorIteratorsTo(fixed_, earliestStart);
1345 // Scan the rest and undo each interval that expired after t and
1346 // insert it in active (the next iteration of the algorithm will
1347 // put it in inactive if required)
1348 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
1349 LiveInterval *HI = handled_[i];
1350 if (!HI->expiredAt(earliestStart) &&
1351 HI->expiredAt(cur->beginIndex())) {
1352 DEBUG(dbgs() << "\t\t\tundo changes for: " << *HI << '\n');
1353 active_.push_back(std::make_pair(HI, HI->begin()));
1354 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
1355 addRegUse(vrm_->getPhys(HI->reg));
1359 // Merge added with unhandled.
1360 // This also update the NextReloadMap. That is, it adds mapping from a
1361 // register defined by a reload from SS to the next reload from SS in the
1362 // same basic block.
1363 MachineBasicBlock *LastReloadMBB = 0;
1364 LiveInterval *LastReload = 0;
1365 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1366 std::sort(added.begin(), added.end(), LISorter());
1367 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1368 LiveInterval *ReloadLi = added[i];
1369 if (ReloadLi->weight == HUGE_VALF &&
1370 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1371 SlotIndex ReloadIdx = ReloadLi->beginIndex();
1372 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1373 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1374 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1375 // Last reload of same SS is in the same MBB. We want to try to
1376 // allocate both reloads the same register and make sure the reg
1377 // isn't clobbered in between if at all possible.
1378 assert(LastReload->beginIndex() < ReloadIdx);
1379 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1381 LastReloadMBB = ReloadMBB;
1382 LastReload = ReloadLi;
1383 LastReloadSS = ReloadSS;
1385 unhandled_.push(ReloadLi);
1389 unsigned RALinScan::getFreePhysReg(LiveInterval* cur,
1390 const TargetRegisterClass *RC,
1391 unsigned MaxInactiveCount,
1392 SmallVector<unsigned, 256> &inactiveCounts,
1394 unsigned FreeReg = 0;
1395 unsigned FreeRegInactiveCount = 0;
1397 std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(cur->reg);
1398 // Resolve second part of the hint (if possible) given the current allocation.
1399 unsigned physReg = Hint.second;
1401 TargetRegisterInfo::isVirtualRegister(physReg) && vrm_->hasPhys(physReg))
1402 physReg = vrm_->getPhys(physReg);
1404 TargetRegisterClass::iterator I, E;
1405 tie(I, E) = tri_->getAllocationOrder(RC, Hint.first, physReg, *mf_);
1406 assert(I != E && "No allocatable register in this register class!");
1408 // Scan for the first available register.
1409 for (; I != E; ++I) {
1411 // Ignore "downgraded" registers.
1412 if (SkipDGRegs && DowngradedRegs.count(Reg))
1414 // Skip recently allocated registers.
1415 if (isRegAvail(Reg) && !isRecentlyUsed(Reg)) {
1417 if (FreeReg < inactiveCounts.size())
1418 FreeRegInactiveCount = inactiveCounts[FreeReg];
1420 FreeRegInactiveCount = 0;
1425 // If there are no free regs, or if this reg has the max inactive count,
1426 // return this register.
1427 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount) {
1428 // Remember what register we picked so we can skip it next time.
1429 if (FreeReg != 0) recordRecentlyUsed(FreeReg);
1433 // Continue scanning the registers, looking for the one with the highest
1434 // inactive count. Alkis found that this reduced register pressure very
1435 // slightly on X86 (in rev 1.94 of this file), though this should probably be
1437 for (; I != E; ++I) {
1439 // Ignore "downgraded" registers.
1440 if (SkipDGRegs && DowngradedRegs.count(Reg))
1442 if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
1443 FreeRegInactiveCount < inactiveCounts[Reg] && !isRecentlyUsed(Reg)) {
1445 FreeRegInactiveCount = inactiveCounts[Reg];
1446 if (FreeRegInactiveCount == MaxInactiveCount)
1447 break; // We found the one with the max inactive count.
1451 // Remember what register we picked so we can skip it next time.
1452 recordRecentlyUsed(FreeReg);
1457 /// getFreePhysReg - return a free physical register for this virtual register
1458 /// interval if we have one, otherwise return 0.
1459 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
1460 SmallVector<unsigned, 256> inactiveCounts;
1461 unsigned MaxInactiveCount = 0;
1463 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
1464 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1466 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
1468 unsigned reg = i->first->reg;
1469 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1470 "Can only allocate virtual registers!");
1472 // If this is not in a related reg class to the register we're allocating,
1474 const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
1475 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
1476 reg = vrm_->getPhys(reg);
1477 if (inactiveCounts.size() <= reg)
1478 inactiveCounts.resize(reg+1);
1479 ++inactiveCounts[reg];
1480 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
1484 // If copy coalescer has assigned a "preferred" register, check if it's
1486 unsigned Preference = vrm_->getRegAllocPref(cur->reg);
1488 DEBUG(dbgs() << "(preferred: " << tri_->getName(Preference) << ") ");
1489 if (isRegAvail(Preference) &&
1490 RC->contains(Preference))
1494 if (!DowngradedRegs.empty()) {
1495 unsigned FreeReg = getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts,
1500 return getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts, false);
1503 FunctionPass* llvm::createLinearScanRegisterAllocator() {
1504 return new RALinScan();