1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "VirtRegMap.h"
16 #include "VirtRegRewriter.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/LiveStackAnalysis.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegAllocRegistry.h"
27 #include "llvm/CodeGen/RegisterCoalescer.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/ADT/EquivalenceClasses.h"
33 #include "llvm/ADT/SmallSet.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
47 STATISTIC(NumIters , "Number of iterations performed");
48 STATISTIC(NumBacktracks, "Number of times we had to backtrack");
49 STATISTIC(NumCoalesce, "Number of copies coalesced");
50 STATISTIC(NumDowngrade, "Number of registers downgraded");
53 NewHeuristic("new-spilling-heuristic",
54 cl::desc("Use new spilling heuristic"),
55 cl::init(false), cl::Hidden);
58 PreSplitIntervals("pre-alloc-split",
59 cl::desc("Pre-register allocation live interval splitting"),
60 cl::init(false), cl::Hidden);
63 TrivCoalesceEnds("trivial-coalesce-ends",
64 cl::desc("Attempt trivial coalescing of interval ends"),
65 cl::init(false), cl::Hidden);
67 static RegisterRegAlloc
68 linearscanRegAlloc("linearscan", "linear scan register allocator",
69 createLinearScanRegisterAllocator);
72 // When we allocate a register, add it to a fixed-size queue of
73 // registers to skip in subsequent allocations. This trades a small
74 // amount of register pressure and increased spills for flexibility in
75 // the post-pass scheduler.
77 // Note that in a the number of registers used for reloading spills
78 // will be one greater than the value of this option.
80 // One big limitation of this is that it doesn't differentiate between
81 // different register classes. So on x86-64, if there is xmm register
82 // pressure, it can caused fewer GPRs to be held in the queue.
83 static cl::opt<unsigned>
84 NumRecentlyUsedRegs("linearscan-skip-count",
85 cl::desc("Number of registers for linearscan to remember to skip."),
89 struct RALinScan : public MachineFunctionPass {
91 RALinScan() : MachineFunctionPass(&ID) {
92 // Initialize the queue to record recently-used registers.
93 if (NumRecentlyUsedRegs > 0)
94 RecentRegs.resize(NumRecentlyUsedRegs, 0);
95 RecentNext = RecentRegs.begin();
98 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
99 typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
101 /// RelatedRegClasses - This structure is built the first time a function is
102 /// compiled, and keeps track of which register classes have registers that
103 /// belong to multiple classes or have aliases that are in other classes.
104 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
105 DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
107 // NextReloadMap - For each register in the map, it maps to the another
108 // register which is defined by a reload from the same stack slot and
109 // both reloads are in the same basic block.
110 DenseMap<unsigned, unsigned> NextReloadMap;
112 // DowngradedRegs - A set of registers which are being "downgraded", i.e.
113 // un-favored for allocation.
114 SmallSet<unsigned, 8> DowngradedRegs;
116 // DowngradeMap - A map from virtual registers to physical registers being
117 // downgraded for the virtual registers.
118 DenseMap<unsigned, unsigned> DowngradeMap;
120 MachineFunction* mf_;
121 MachineRegisterInfo* mri_;
122 const TargetMachine* tm_;
123 const TargetRegisterInfo* tri_;
124 const TargetInstrInfo* tii_;
125 BitVector allocatableRegs_;
128 const MachineLoopInfo *loopInfo;
130 /// handled_ - Intervals are added to the handled_ set in the order of their
131 /// start value. This is uses for backtracking.
132 std::vector<LiveInterval*> handled_;
134 /// fixed_ - Intervals that correspond to machine registers.
138 /// active_ - Intervals that are currently being processed, and which have a
139 /// live range active for the current point.
140 IntervalPtrs active_;
142 /// inactive_ - Intervals that are currently being processed, but which have
143 /// a hold at the current point.
144 IntervalPtrs inactive_;
146 typedef std::priority_queue<LiveInterval*,
147 SmallVector<LiveInterval*, 64>,
148 greater_ptr<LiveInterval> > IntervalHeap;
149 IntervalHeap unhandled_;
151 /// regUse_ - Tracks register usage.
152 SmallVector<unsigned, 32> regUse_;
153 SmallVector<unsigned, 32> regUseBackUp_;
155 /// vrm_ - Tracks register assignments.
158 std::auto_ptr<VirtRegRewriter> rewriter_;
160 std::auto_ptr<Spiller> spiller_;
162 // The queue of recently-used registers.
163 SmallVector<unsigned, 4> RecentRegs;
164 SmallVector<unsigned, 4>::iterator RecentNext;
166 // Record that we just picked this register.
167 void recordRecentlyUsed(unsigned reg) {
168 assert(reg != 0 && "Recently used register is NOREG!");
169 if (!RecentRegs.empty()) {
171 if (RecentNext == RecentRegs.end())
172 RecentNext = RecentRegs.begin();
177 virtual const char* getPassName() const {
178 return "Linear Scan Register Allocator";
181 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
182 AU.setPreservesCFG();
183 AU.addRequired<LiveIntervals>();
184 AU.addPreserved<SlotIndexes>();
186 AU.addRequiredID(StrongPHIEliminationID);
187 // Make sure PassManager knows which analyses to make available
188 // to coalescing and which analyses coalescing invalidates.
189 AU.addRequiredTransitive<RegisterCoalescer>();
190 if (PreSplitIntervals)
191 AU.addRequiredID(PreAllocSplittingID);
192 AU.addRequired<LiveStacks>();
193 AU.addPreserved<LiveStacks>();
194 AU.addRequired<MachineLoopInfo>();
195 AU.addPreserved<MachineLoopInfo>();
196 AU.addRequired<VirtRegMap>();
197 AU.addPreserved<VirtRegMap>();
198 AU.addPreservedID(MachineDominatorsID);
199 MachineFunctionPass::getAnalysisUsage(AU);
202 /// runOnMachineFunction - register allocate the whole function
203 bool runOnMachineFunction(MachineFunction&);
205 // Determine if we skip this register due to its being recently used.
206 bool isRecentlyUsed(unsigned reg) const {
207 return std::find(RecentRegs.begin(), RecentRegs.end(), reg) !=
212 /// linearScan - the linear scan algorithm
215 /// initIntervalSets - initialize the interval sets.
217 void initIntervalSets();
219 /// processActiveIntervals - expire old intervals and move non-overlapping
220 /// ones to the inactive list.
221 void processActiveIntervals(SlotIndex CurPoint);
223 /// processInactiveIntervals - expire old intervals and move overlapping
224 /// ones to the active list.
225 void processInactiveIntervals(SlotIndex CurPoint);
227 /// hasNextReloadInterval - Return the next liveinterval that's being
228 /// defined by a reload from the same SS as the specified one.
229 LiveInterval *hasNextReloadInterval(LiveInterval *cur);
231 /// DowngradeRegister - Downgrade a register for allocation.
232 void DowngradeRegister(LiveInterval *li, unsigned Reg);
234 /// UpgradeRegister - Upgrade a register for allocation.
235 void UpgradeRegister(unsigned Reg);
237 /// assignRegOrStackSlotAtInterval - assign a register if one
238 /// is available, or spill.
239 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
241 void updateSpillWeights(std::vector<float> &Weights,
242 unsigned reg, float weight,
243 const TargetRegisterClass *RC);
245 /// findIntervalsToSpill - Determine the intervals to spill for the
246 /// specified interval. It's passed the physical registers whose spill
247 /// weight is the lowest among all the registers whose live intervals
248 /// conflict with the interval.
249 void findIntervalsToSpill(LiveInterval *cur,
250 std::vector<std::pair<unsigned,float> > &Candidates,
252 SmallVector<LiveInterval*, 8> &SpillIntervals);
254 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
255 /// try allocate the definition the same register as the source register
256 /// if the register is not defined during live time of the interval. This
257 /// eliminate a copy. This is used to coalesce copies which were not
258 /// coalesced away before allocation either due to dest and src being in
259 /// different register classes or because the coalescer was overly
261 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
264 /// Register usage / availability tracking helpers.
268 regUse_.resize(tri_->getNumRegs(), 0);
269 regUseBackUp_.resize(tri_->getNumRegs(), 0);
272 void finalizeRegUses() {
274 // Verify all the registers are "freed".
276 for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
277 if (regUse_[i] != 0) {
278 errs() << tri_->getName(i) << " is still in use!\n";
286 regUseBackUp_.clear();
289 void addRegUse(unsigned physReg) {
290 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
291 "should be physical register!");
293 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
297 void delRegUse(unsigned physReg) {
298 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
299 "should be physical register!");
300 assert(regUse_[physReg] != 0);
302 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
303 assert(regUse_[*as] != 0);
308 bool isRegAvail(unsigned physReg) const {
309 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
310 "should be physical register!");
311 return regUse_[physReg] == 0;
314 void backUpRegUses() {
315 regUseBackUp_ = regUse_;
318 void restoreRegUses() {
319 regUse_ = regUseBackUp_;
323 /// Register handling helpers.
326 /// getFreePhysReg - return a free physical register for this virtual
327 /// register interval if we have one, otherwise return 0.
328 unsigned getFreePhysReg(LiveInterval* cur);
329 unsigned getFreePhysReg(LiveInterval* cur,
330 const TargetRegisterClass *RC,
331 unsigned MaxInactiveCount,
332 SmallVector<unsigned, 256> &inactiveCounts,
335 /// assignVirt2StackSlot - assigns this virtual register to a
336 /// stack slot. returns the stack slot
337 int assignVirt2StackSlot(unsigned virtReg);
339 void ComputeRelatedRegClasses();
341 template <typename ItTy>
342 void printIntervals(const char* const str, ItTy i, ItTy e) const {
345 errs() << str << " intervals:\n";
347 for (; i != e; ++i) {
348 errs() << "\t" << *i->first << " -> ";
350 unsigned reg = i->first->reg;
351 if (TargetRegisterInfo::isVirtualRegister(reg))
352 reg = vrm_->getPhys(reg);
354 errs() << tri_->getName(reg) << '\n';
359 char RALinScan::ID = 0;
362 static RegisterPass<RALinScan>
363 X("linearscan-regalloc", "Linear Scan Register Allocator");
365 void RALinScan::ComputeRelatedRegClasses() {
366 // First pass, add all reg classes to the union, and determine at least one
367 // reg class that each register is in.
368 bool HasAliases = false;
369 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
370 E = tri_->regclass_end(); RCI != E; ++RCI) {
371 RelatedRegClasses.insert(*RCI);
372 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
374 HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
376 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
378 // Already processed this register. Just make sure we know that
379 // multiple register classes share a register.
380 RelatedRegClasses.unionSets(PRC, *RCI);
387 // Second pass, now that we know conservatively what register classes each reg
388 // belongs to, add info about aliases. We don't need to do this for targets
389 // without register aliases.
391 for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
392 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
394 for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
395 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
398 /// attemptTrivialCoalescing - If a simple interval is defined by a copy, try
399 /// allocate the definition the same register as the source register if the
400 /// register is not defined during live time of the interval. If the interval is
401 /// killed by a copy, try to use the destination register. This eliminates a
402 /// copy. This is used to coalesce copies which were not coalesced away before
403 /// allocation either due to dest and src being in different register classes or
404 /// because the coalescer was overly conservative.
405 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
406 unsigned Preference = vrm_->getRegAllocPref(cur.reg);
407 if ((Preference && Preference == Reg) || !cur.containsOneValue())
410 // We cannot handle complicated live ranges. Simple linear stuff only.
411 if (cur.ranges.size() != 1)
414 const LiveRange &range = cur.ranges.front();
416 VNInfo *vni = range.valno;
422 MachineInstr *CopyMI;
423 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
424 if (vni->def != SlotIndex() && vni->isDefAccurate() &&
425 (CopyMI = li_->getInstructionFromIndex(vni->def)) &&
426 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
427 // Defined by a copy, try to extend SrcReg forward
429 else if (TrivCoalesceEnds &&
431 li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
432 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
434 // Only used by a copy, try to extend DstReg backwards
440 if (TargetRegisterInfo::isVirtualRegister(CandReg)) {
441 if (!vrm_->isAssignedReg(CandReg))
443 CandReg = vrm_->getPhys(CandReg);
448 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
449 if (!RC->contains(CandReg))
452 if (li_->conflictsWithPhysReg(cur, *vrm_, CandReg))
456 DEBUG(errs() << "Coalescing: " << cur << " -> " << tri_->getName(CandReg)
458 vrm_->clearVirt(cur.reg);
459 vrm_->assignVirt2Phys(cur.reg, CandReg);
465 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
467 mri_ = &fn.getRegInfo();
468 tm_ = &fn.getTarget();
469 tri_ = tm_->getRegisterInfo();
470 tii_ = tm_->getInstrInfo();
471 allocatableRegs_ = tri_->getAllocatableSet(fn);
472 li_ = &getAnalysis<LiveIntervals>();
473 ls_ = &getAnalysis<LiveStacks>();
474 loopInfo = &getAnalysis<MachineLoopInfo>();
476 // We don't run the coalescer here because we have no reason to
477 // interact with it. If the coalescer requires interaction, it
478 // won't do anything. If it doesn't require interaction, we assume
479 // it was run as a separate pass.
481 // If this is the first function compiled, compute the related reg classes.
482 if (RelatedRegClasses.empty())
483 ComputeRelatedRegClasses();
485 // Also resize register usage trackers.
488 vrm_ = &getAnalysis<VirtRegMap>();
489 if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
491 spiller_.reset(createSpiller(mf_, li_, loopInfo, vrm_));
497 // Rewrite spill code and update the PhysRegsUsed set.
498 rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
500 assert(unhandled_.empty() && "Unhandled live intervals remain!");
508 NextReloadMap.clear();
509 DowngradedRegs.clear();
510 DowngradeMap.clear();
516 /// initIntervalSets - initialize the interval sets.
518 void RALinScan::initIntervalSets()
520 assert(unhandled_.empty() && fixed_.empty() &&
521 active_.empty() && inactive_.empty() &&
522 "interval sets should be empty on initialization");
524 handled_.reserve(li_->getNumIntervals());
526 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
527 if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
528 if (!i->second->empty()) {
529 mri_->setPhysRegUsed(i->second->reg);
530 fixed_.push_back(std::make_pair(i->second, i->second->begin()));
533 if (i->second->empty()) {
534 assignRegOrStackSlotAtInterval(i->second);
537 unhandled_.push(i->second);
542 void RALinScan::linearScan() {
543 // linear scan algorithm
545 errs() << "********** LINEAR SCAN **********\n"
546 << "********** Function: "
547 << mf_->getFunction()->getName() << '\n';
548 printIntervals("fixed", fixed_.begin(), fixed_.end());
551 while (!unhandled_.empty()) {
552 // pick the interval with the earliest start point
553 LiveInterval* cur = unhandled_.top();
556 DEBUG(errs() << "\n*** CURRENT ***: " << *cur << '\n');
558 assert(!cur->empty() && "Empty interval in unhandled set.");
560 processActiveIntervals(cur->beginIndex());
561 processInactiveIntervals(cur->beginIndex());
563 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
564 "Can only allocate virtual registers!");
566 // Allocating a virtual register. try to find a free
567 // physical register or spill an interval (possibly this one) in order to
569 assignRegOrStackSlotAtInterval(cur);
572 printIntervals("active", active_.begin(), active_.end());
573 printIntervals("inactive", inactive_.begin(), inactive_.end());
577 // Expire any remaining active intervals
578 while (!active_.empty()) {
579 IntervalPtr &IP = active_.back();
580 unsigned reg = IP.first->reg;
581 DEBUG(errs() << "\tinterval " << *IP.first << " expired\n");
582 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
583 "Can only allocate virtual registers!");
584 reg = vrm_->getPhys(reg);
589 // Expire any remaining inactive intervals
591 for (IntervalPtrs::reverse_iterator
592 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
593 errs() << "\tinterval " << *i->first << " expired\n";
597 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
598 MachineFunction::iterator EntryMBB = mf_->begin();
599 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
600 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
601 LiveInterval &cur = *i->second;
603 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
606 else if (vrm_->isAssignedReg(cur.reg))
607 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
610 // Ignore splited live intervals.
611 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
614 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
616 const LiveRange &LR = *I;
617 if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
618 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
619 if (LiveInMBBs[i] != EntryMBB) {
620 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
621 "Adding a virtual register to livein set?");
622 LiveInMBBs[i]->addLiveIn(Reg);
629 DEBUG(errs() << *vrm_);
631 // Look for physical registers that end up not being allocated even though
632 // register allocator had to spill other registers in its register class.
633 if (ls_->getNumIntervals() == 0)
635 if (!vrm_->FindUnusedRegisters(li_))
639 /// processActiveIntervals - expire old intervals and move non-overlapping ones
640 /// to the inactive list.
641 void RALinScan::processActiveIntervals(SlotIndex CurPoint)
643 DEBUG(errs() << "\tprocessing active intervals:\n");
645 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
646 LiveInterval *Interval = active_[i].first;
647 LiveInterval::iterator IntervalPos = active_[i].second;
648 unsigned reg = Interval->reg;
650 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
652 if (IntervalPos == Interval->end()) { // Remove expired intervals.
653 DEBUG(errs() << "\t\tinterval " << *Interval << " expired\n");
654 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
655 "Can only allocate virtual registers!");
656 reg = vrm_->getPhys(reg);
659 // Pop off the end of the list.
660 active_[i] = active_.back();
664 } else if (IntervalPos->start > CurPoint) {
665 // Move inactive intervals to inactive list.
666 DEBUG(errs() << "\t\tinterval " << *Interval << " inactive\n");
667 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
668 "Can only allocate virtual registers!");
669 reg = vrm_->getPhys(reg);
672 inactive_.push_back(std::make_pair(Interval, IntervalPos));
674 // Pop off the end of the list.
675 active_[i] = active_.back();
679 // Otherwise, just update the iterator position.
680 active_[i].second = IntervalPos;
685 /// processInactiveIntervals - expire old intervals and move overlapping
686 /// ones to the active list.
687 void RALinScan::processInactiveIntervals(SlotIndex CurPoint)
689 DEBUG(errs() << "\tprocessing inactive intervals:\n");
691 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
692 LiveInterval *Interval = inactive_[i].first;
693 LiveInterval::iterator IntervalPos = inactive_[i].second;
694 unsigned reg = Interval->reg;
696 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
698 if (IntervalPos == Interval->end()) { // remove expired intervals.
699 DEBUG(errs() << "\t\tinterval " << *Interval << " expired\n");
701 // Pop off the end of the list.
702 inactive_[i] = inactive_.back();
703 inactive_.pop_back();
705 } else if (IntervalPos->start <= CurPoint) {
706 // move re-activated intervals in active list
707 DEBUG(errs() << "\t\tinterval " << *Interval << " active\n");
708 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
709 "Can only allocate virtual registers!");
710 reg = vrm_->getPhys(reg);
713 active_.push_back(std::make_pair(Interval, IntervalPos));
715 // Pop off the end of the list.
716 inactive_[i] = inactive_.back();
717 inactive_.pop_back();
720 // Otherwise, just update the iterator position.
721 inactive_[i].second = IntervalPos;
726 /// updateSpillWeights - updates the spill weights of the specifed physical
727 /// register and its weight.
728 void RALinScan::updateSpillWeights(std::vector<float> &Weights,
729 unsigned reg, float weight,
730 const TargetRegisterClass *RC) {
731 SmallSet<unsigned, 4> Processed;
732 SmallSet<unsigned, 4> SuperAdded;
733 SmallVector<unsigned, 4> Supers;
734 Weights[reg] += weight;
735 Processed.insert(reg);
736 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
737 Weights[*as] += weight;
738 Processed.insert(*as);
739 if (tri_->isSubRegister(*as, reg) &&
740 SuperAdded.insert(*as) &&
742 Supers.push_back(*as);
746 // If the alias is a super-register, and the super-register is in the
747 // register class we are trying to allocate. Then add the weight to all
748 // sub-registers of the super-register even if they are not aliases.
749 // e.g. allocating for GR32, bh is not used, updating bl spill weight.
750 // bl should get the same spill weight otherwise it will be choosen
751 // as a spill candidate since spilling bh doesn't make ebx available.
752 for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
753 for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
754 if (!Processed.count(*sr))
755 Weights[*sr] += weight;
760 RALinScan::IntervalPtrs::iterator
761 FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
762 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
764 if (I->first == LI) return I;
768 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, SlotIndex Point){
769 for (unsigned i = 0, e = V.size(); i != e; ++i) {
770 RALinScan::IntervalPtr &IP = V[i];
771 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
773 if (I != IP.first->begin()) --I;
778 /// addStackInterval - Create a LiveInterval for stack if the specified live
779 /// interval has been spilled.
780 static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
782 MachineRegisterInfo* mri_, VirtRegMap &vrm_) {
783 int SS = vrm_.getStackSlot(cur->reg);
784 if (SS == VirtRegMap::NO_STACK_SLOT)
787 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
788 LiveInterval &SI = ls_->getOrCreateInterval(SS, RC);
791 if (SI.hasAtLeastOneValue())
792 VNI = SI.getValNumInfo(0);
794 VNI = SI.getNextValue(SlotIndex(), 0, false,
795 ls_->getVNInfoAllocator());
797 LiveInterval &RI = li_->getInterval(cur->reg);
798 // FIXME: This may be overly conservative.
799 SI.MergeRangesInAsValue(RI, VNI);
802 /// getConflictWeight - Return the number of conflicts between cur
803 /// live interval and defs and uses of Reg weighted by loop depthes.
805 float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
806 MachineRegisterInfo *mri_,
807 const MachineLoopInfo *loopInfo) {
809 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
810 E = mri_->reg_end(); I != E; ++I) {
811 MachineInstr *MI = &*I;
812 if (cur->liveAt(li_->getInstructionIndex(MI))) {
813 unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
814 Conflicts += powf(10.0f, (float)loopDepth);
820 /// findIntervalsToSpill - Determine the intervals to spill for the
821 /// specified interval. It's passed the physical registers whose spill
822 /// weight is the lowest among all the registers whose live intervals
823 /// conflict with the interval.
824 void RALinScan::findIntervalsToSpill(LiveInterval *cur,
825 std::vector<std::pair<unsigned,float> > &Candidates,
827 SmallVector<LiveInterval*, 8> &SpillIntervals) {
828 // We have figured out the *best* register to spill. But there are other
829 // registers that are pretty good as well (spill weight within 3%). Spill
830 // the one that has fewest defs and uses that conflict with cur.
831 float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
832 SmallVector<LiveInterval*, 8> SLIs[3];
835 errs() << "\tConsidering " << NumCands << " candidates: ";
836 for (unsigned i = 0; i != NumCands; ++i)
837 errs() << tri_->getName(Candidates[i].first) << " ";
841 // Calculate the number of conflicts of each candidate.
842 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
843 unsigned Reg = i->first->reg;
844 unsigned PhysReg = vrm_->getPhys(Reg);
845 if (!cur->overlapsFrom(*i->first, i->second))
847 for (unsigned j = 0; j < NumCands; ++j) {
848 unsigned Candidate = Candidates[j].first;
849 if (tri_->regsOverlap(PhysReg, Candidate)) {
851 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
852 SLIs[j].push_back(i->first);
857 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
858 unsigned Reg = i->first->reg;
859 unsigned PhysReg = vrm_->getPhys(Reg);
860 if (!cur->overlapsFrom(*i->first, i->second-1))
862 for (unsigned j = 0; j < NumCands; ++j) {
863 unsigned Candidate = Candidates[j].first;
864 if (tri_->regsOverlap(PhysReg, Candidate)) {
866 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
867 SLIs[j].push_back(i->first);
872 // Which is the best candidate?
873 unsigned BestCandidate = 0;
874 float MinConflicts = Conflicts[0];
875 for (unsigned i = 1; i != NumCands; ++i) {
876 if (Conflicts[i] < MinConflicts) {
878 MinConflicts = Conflicts[i];
882 std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
883 std::back_inserter(SpillIntervals));
887 struct WeightCompare {
889 const RALinScan &Allocator;
892 WeightCompare(const RALinScan &Alloc) : Allocator(Alloc) {};
894 typedef std::pair<unsigned, float> RegWeightPair;
895 bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
896 return LHS.second < RHS.second && !Allocator.isRecentlyUsed(LHS.first);
901 static bool weightsAreClose(float w1, float w2) {
905 float diff = w1 - w2;
906 if (diff <= 0.02f) // Within 0.02f
908 return (diff / w2) <= 0.05f; // Within 5%.
911 LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
912 DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
913 if (I == NextReloadMap.end())
915 return &li_->getInterval(I->second);
918 void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
919 bool isNew = DowngradedRegs.insert(Reg);
920 isNew = isNew; // Silence compiler warning.
921 assert(isNew && "Multiple reloads holding the same register?");
922 DowngradeMap.insert(std::make_pair(li->reg, Reg));
923 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS) {
924 isNew = DowngradedRegs.insert(*AS);
925 isNew = isNew; // Silence compiler warning.
926 assert(isNew && "Multiple reloads holding the same register?");
927 DowngradeMap.insert(std::make_pair(li->reg, *AS));
932 void RALinScan::UpgradeRegister(unsigned Reg) {
934 DowngradedRegs.erase(Reg);
935 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
936 DowngradedRegs.erase(*AS);
942 bool operator()(LiveInterval* A, LiveInterval* B) {
943 return A->beginIndex() < B->beginIndex();
948 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
950 void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
951 DEBUG(errs() << "\tallocating current interval: ");
953 // This is an implicitly defined live interval, just assign any register.
954 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
956 unsigned physReg = vrm_->getRegAllocPref(cur->reg);
958 physReg = *RC->allocation_order_begin(*mf_);
959 DEBUG(errs() << tri_->getName(physReg) << '\n');
960 // Note the register is not really in use.
961 vrm_->assignVirt2Phys(cur->reg, physReg);
967 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
968 SlotIndex StartPosition = cur->beginIndex();
969 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
971 // If start of this live interval is defined by a move instruction and its
972 // source is assigned a physical register that is compatible with the target
973 // register class, then we should try to assign it the same register.
974 // This can happen when the move is from a larger register class to a smaller
975 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
976 if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
977 VNInfo *vni = cur->begin()->valno;
978 if ((vni->def != SlotIndex()) && !vni->isUnused() &&
979 vni->isDefAccurate()) {
980 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
981 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
983 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
985 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
987 else if (vrm_->isAssignedReg(SrcReg))
988 Reg = vrm_->getPhys(SrcReg);
991 Reg = tri_->getSubReg(Reg, SrcSubReg);
993 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
994 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
995 mri_->setRegAllocationHint(cur->reg, 0, Reg);
1001 // For every interval in inactive we overlap with, mark the
1002 // register as not free and update spill weights.
1003 for (IntervalPtrs::const_iterator i = inactive_.begin(),
1004 e = inactive_.end(); i != e; ++i) {
1005 unsigned Reg = i->first->reg;
1006 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
1007 "Can only allocate virtual registers!");
1008 const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
1009 // If this is not in a related reg class to the register we're allocating,
1011 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1012 cur->overlapsFrom(*i->first, i->second-1)) {
1013 Reg = vrm_->getPhys(Reg);
1015 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
1019 // Speculatively check to see if we can get a register right now. If not,
1020 // we know we won't be able to by adding more constraints. If so, we can
1021 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
1022 // is very bad (it contains all callee clobbered registers for any functions
1023 // with a call), so we want to avoid doing that if possible.
1024 unsigned physReg = getFreePhysReg(cur);
1025 unsigned BestPhysReg = physReg;
1027 // We got a register. However, if it's in the fixed_ list, we might
1028 // conflict with it. Check to see if we conflict with it or any of its
1030 SmallSet<unsigned, 8> RegAliases;
1031 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
1032 RegAliases.insert(*AS);
1034 bool ConflictsWithFixed = false;
1035 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1036 IntervalPtr &IP = fixed_[i];
1037 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
1038 // Okay, this reg is on the fixed list. Check to see if we actually
1040 LiveInterval *I = IP.first;
1041 if (I->endIndex() > StartPosition) {
1042 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1044 if (II != I->begin() && II->start > StartPosition)
1046 if (cur->overlapsFrom(*I, II)) {
1047 ConflictsWithFixed = true;
1054 // Okay, the register picked by our speculative getFreePhysReg call turned
1055 // out to be in use. Actually add all of the conflicting fixed registers to
1056 // regUse_ so we can do an accurate query.
1057 if (ConflictsWithFixed) {
1058 // For every interval in fixed we overlap with, mark the register as not
1059 // free and update spill weights.
1060 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1061 IntervalPtr &IP = fixed_[i];
1062 LiveInterval *I = IP.first;
1064 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
1065 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1066 I->endIndex() > StartPosition) {
1067 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1069 if (II != I->begin() && II->start > StartPosition)
1071 if (cur->overlapsFrom(*I, II)) {
1072 unsigned reg = I->reg;
1074 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
1079 // Using the newly updated regUse_ object, which includes conflicts in the
1080 // future, see if there are any registers available.
1081 physReg = getFreePhysReg(cur);
1085 // Restore the physical register tracker, removing information about the
1089 // If we find a free register, we are done: assign this virtual to
1090 // the free physical register and add this interval to the active
1093 DEBUG(errs() << tri_->getName(physReg) << '\n');
1094 vrm_->assignVirt2Phys(cur->reg, physReg);
1096 active_.push_back(std::make_pair(cur, cur->begin()));
1097 handled_.push_back(cur);
1099 // "Upgrade" the physical register since it has been allocated.
1100 UpgradeRegister(physReg);
1101 if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
1102 // "Downgrade" physReg to try to keep physReg from being allocated until
1103 // the next reload from the same SS is allocated.
1104 mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg);
1105 DowngradeRegister(cur, physReg);
1109 DEBUG(errs() << "no free registers\n");
1111 // Compile the spill weights into an array that is better for scanning.
1112 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
1113 for (std::vector<std::pair<unsigned, float> >::iterator
1114 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
1115 updateSpillWeights(SpillWeights, I->first, I->second, RC);
1117 // for each interval in active, update spill weights.
1118 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
1120 unsigned reg = i->first->reg;
1121 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1122 "Can only allocate virtual registers!");
1123 reg = vrm_->getPhys(reg);
1124 updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
1127 DEBUG(errs() << "\tassigning stack slot at interval "<< *cur << ":\n");
1129 // Find a register to spill.
1130 float minWeight = HUGE_VALF;
1131 unsigned minReg = 0;
1134 std::vector<std::pair<unsigned,float> > RegsWeights;
1135 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
1136 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1137 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1139 float regWeight = SpillWeights[reg];
1140 // Skip recently allocated registers.
1141 if (minWeight > regWeight && !isRecentlyUsed(reg))
1143 RegsWeights.push_back(std::make_pair(reg, regWeight));
1146 // If we didn't find a register that is spillable, try aliases?
1148 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1149 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1151 // No need to worry about if the alias register size < regsize of RC.
1152 // We are going to spill all registers that alias it anyway.
1153 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
1154 RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
1158 // Sort all potential spill candidates by weight.
1159 std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare(*this));
1160 minReg = RegsWeights[0].first;
1161 minWeight = RegsWeights[0].second;
1162 if (minWeight == HUGE_VALF) {
1163 // All registers must have inf weight. Just grab one!
1164 minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
1165 if (cur->weight == HUGE_VALF ||
1166 li_->getApproximateInstructionCount(*cur) == 0) {
1167 // Spill a physical register around defs and uses.
1168 if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
1169 // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
1170 // in fixed_. Reset them.
1171 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1172 IntervalPtr &IP = fixed_[i];
1173 LiveInterval *I = IP.first;
1174 if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
1175 IP.second = I->advanceTo(I->begin(), StartPosition);
1178 DowngradedRegs.clear();
1179 assignRegOrStackSlotAtInterval(cur);
1181 assert(false && "Ran out of registers during register allocation!");
1182 llvm_report_error("Ran out of registers during register allocation!");
1188 // Find up to 3 registers to consider as spill candidates.
1189 unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
1190 while (LastCandidate > 1) {
1191 if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
1197 errs() << "\t\tregister(s) with min weight(s): ";
1199 for (unsigned i = 0; i != LastCandidate; ++i)
1200 errs() << tri_->getName(RegsWeights[i].first)
1201 << " (" << RegsWeights[i].second << ")\n";
1204 // If the current has the minimum weight, we need to spill it and
1205 // add any added intervals back to unhandled, and restart
1207 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
1208 DEBUG(errs() << "\t\t\tspilling(c): " << *cur << '\n');
1209 SmallVector<LiveInterval*, 8> spillIs;
1210 std::vector<LiveInterval*> added;
1212 added = spiller_->spill(cur, spillIs);
1214 std::sort(added.begin(), added.end(), LISorter());
1215 addStackInterval(cur, ls_, li_, mri_, *vrm_);
1217 return; // Early exit if all spills were folded.
1219 // Merge added with unhandled. Note that we have already sorted
1220 // intervals returned by addIntervalsForSpills by their starting
1222 // This also update the NextReloadMap. That is, it adds mapping from a
1223 // register defined by a reload from SS to the next reload from SS in the
1224 // same basic block.
1225 MachineBasicBlock *LastReloadMBB = 0;
1226 LiveInterval *LastReload = 0;
1227 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1228 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1229 LiveInterval *ReloadLi = added[i];
1230 if (ReloadLi->weight == HUGE_VALF &&
1231 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1232 SlotIndex ReloadIdx = ReloadLi->beginIndex();
1233 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1234 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1235 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1236 // Last reload of same SS is in the same MBB. We want to try to
1237 // allocate both reloads the same register and make sure the reg
1238 // isn't clobbered in between if at all possible.
1239 assert(LastReload->beginIndex() < ReloadIdx);
1240 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1242 LastReloadMBB = ReloadMBB;
1243 LastReload = ReloadLi;
1244 LastReloadSS = ReloadSS;
1246 unhandled_.push(ReloadLi);
1253 // Push the current interval back to unhandled since we are going
1254 // to re-run at least this iteration. Since we didn't modify it it
1255 // should go back right in the front of the list
1256 unhandled_.push(cur);
1258 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
1259 "did not choose a register to spill?");
1261 // We spill all intervals aliasing the register with
1262 // minimum weight, rollback to the interval with the earliest
1263 // start point and let the linear scan algorithm run again
1264 SmallVector<LiveInterval*, 8> spillIs;
1266 // Determine which intervals have to be spilled.
1267 findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
1269 // Set of spilled vregs (used later to rollback properly)
1270 SmallSet<unsigned, 8> spilled;
1272 // The earliest start of a Spilled interval indicates up to where
1273 // in handled we need to roll back
1274 assert(!spillIs.empty() && "No spill intervals?");
1275 SlotIndex earliestStart = spillIs[0]->beginIndex();
1277 // Spill live intervals of virtual regs mapped to the physical register we
1278 // want to clear (and its aliases). We only spill those that overlap with the
1279 // current interval as the rest do not affect its allocation. we also keep
1280 // track of the earliest start of all spilled live intervals since this will
1281 // mark our rollback point.
1282 std::vector<LiveInterval*> added;
1283 while (!spillIs.empty()) {
1284 LiveInterval *sli = spillIs.back();
1286 DEBUG(errs() << "\t\t\tspilling(a): " << *sli << '\n');
1287 if (sli->beginIndex() < earliestStart)
1288 earliestStart = sli->beginIndex();
1290 std::vector<LiveInterval*> newIs;
1291 newIs = spiller_->spill(sli, spillIs, &earliestStart);
1292 addStackInterval(sli, ls_, li_, mri_, *vrm_);
1293 std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
1294 spilled.insert(sli->reg);
1297 DEBUG(errs() << "\t\trolling back to: " << earliestStart << '\n');
1299 // Scan handled in reverse order up to the earliest start of a
1300 // spilled live interval and undo each one, restoring the state of
1302 while (!handled_.empty()) {
1303 LiveInterval* i = handled_.back();
1304 // If this interval starts before t we are done.
1305 if (!i->empty() && i->beginIndex() < earliestStart)
1307 DEBUG(errs() << "\t\t\tundo changes for: " << *i << '\n');
1308 handled_.pop_back();
1310 // When undoing a live interval allocation we must know if it is active or
1311 // inactive to properly update regUse_ and the VirtRegMap.
1312 IntervalPtrs::iterator it;
1313 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
1315 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1316 if (!spilled.count(i->reg))
1318 delRegUse(vrm_->getPhys(i->reg));
1319 vrm_->clearVirt(i->reg);
1320 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
1321 inactive_.erase(it);
1322 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1323 if (!spilled.count(i->reg))
1325 vrm_->clearVirt(i->reg);
1327 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
1328 "Can only allocate virtual registers!");
1329 vrm_->clearVirt(i->reg);
1333 DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
1334 if (ii == DowngradeMap.end())
1335 // It interval has a preference, it must be defined by a copy. Clear the
1336 // preference now since the source interval allocation may have been
1338 mri_->setRegAllocationHint(i->reg, 0, 0);
1340 UpgradeRegister(ii->second);
1344 // Rewind the iterators in the active, inactive, and fixed lists back to the
1345 // point we reverted to.
1346 RevertVectorIteratorsTo(active_, earliestStart);
1347 RevertVectorIteratorsTo(inactive_, earliestStart);
1348 RevertVectorIteratorsTo(fixed_, earliestStart);
1350 // Scan the rest and undo each interval that expired after t and
1351 // insert it in active (the next iteration of the algorithm will
1352 // put it in inactive if required)
1353 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
1354 LiveInterval *HI = handled_[i];
1355 if (!HI->expiredAt(earliestStart) &&
1356 HI->expiredAt(cur->beginIndex())) {
1357 DEBUG(errs() << "\t\t\tundo changes for: " << *HI << '\n');
1358 active_.push_back(std::make_pair(HI, HI->begin()));
1359 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
1360 addRegUse(vrm_->getPhys(HI->reg));
1364 // Merge added with unhandled.
1365 // This also update the NextReloadMap. That is, it adds mapping from a
1366 // register defined by a reload from SS to the next reload from SS in the
1367 // same basic block.
1368 MachineBasicBlock *LastReloadMBB = 0;
1369 LiveInterval *LastReload = 0;
1370 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1371 std::sort(added.begin(), added.end(), LISorter());
1372 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1373 LiveInterval *ReloadLi = added[i];
1374 if (ReloadLi->weight == HUGE_VALF &&
1375 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1376 SlotIndex ReloadIdx = ReloadLi->beginIndex();
1377 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1378 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1379 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1380 // Last reload of same SS is in the same MBB. We want to try to
1381 // allocate both reloads the same register and make sure the reg
1382 // isn't clobbered in between if at all possible.
1383 assert(LastReload->beginIndex() < ReloadIdx);
1384 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1386 LastReloadMBB = ReloadMBB;
1387 LastReload = ReloadLi;
1388 LastReloadSS = ReloadSS;
1390 unhandled_.push(ReloadLi);
1394 unsigned RALinScan::getFreePhysReg(LiveInterval* cur,
1395 const TargetRegisterClass *RC,
1396 unsigned MaxInactiveCount,
1397 SmallVector<unsigned, 256> &inactiveCounts,
1399 unsigned FreeReg = 0;
1400 unsigned FreeRegInactiveCount = 0;
1402 std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(cur->reg);
1403 // Resolve second part of the hint (if possible) given the current allocation.
1404 unsigned physReg = Hint.second;
1406 TargetRegisterInfo::isVirtualRegister(physReg) && vrm_->hasPhys(physReg))
1407 physReg = vrm_->getPhys(physReg);
1409 TargetRegisterClass::iterator I, E;
1410 tie(I, E) = tri_->getAllocationOrder(RC, Hint.first, physReg, *mf_);
1411 assert(I != E && "No allocatable register in this register class!");
1413 // Scan for the first available register.
1414 for (; I != E; ++I) {
1416 // Ignore "downgraded" registers.
1417 if (SkipDGRegs && DowngradedRegs.count(Reg))
1419 // Skip recently allocated registers.
1420 if (isRegAvail(Reg) && !isRecentlyUsed(Reg)) {
1422 if (FreeReg < inactiveCounts.size())
1423 FreeRegInactiveCount = inactiveCounts[FreeReg];
1425 FreeRegInactiveCount = 0;
1430 // If there are no free regs, or if this reg has the max inactive count,
1431 // return this register.
1432 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount) {
1433 // Remember what register we picked so we can skip it next time.
1434 if (FreeReg != 0) recordRecentlyUsed(FreeReg);
1438 // Continue scanning the registers, looking for the one with the highest
1439 // inactive count. Alkis found that this reduced register pressure very
1440 // slightly on X86 (in rev 1.94 of this file), though this should probably be
1442 for (; I != E; ++I) {
1444 // Ignore "downgraded" registers.
1445 if (SkipDGRegs && DowngradedRegs.count(Reg))
1447 if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
1448 FreeRegInactiveCount < inactiveCounts[Reg] && !isRecentlyUsed(Reg)) {
1450 FreeRegInactiveCount = inactiveCounts[Reg];
1451 if (FreeRegInactiveCount == MaxInactiveCount)
1452 break; // We found the one with the max inactive count.
1456 // Remember what register we picked so we can skip it next time.
1457 recordRecentlyUsed(FreeReg);
1462 /// getFreePhysReg - return a free physical register for this virtual register
1463 /// interval if we have one, otherwise return 0.
1464 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
1465 SmallVector<unsigned, 256> inactiveCounts;
1466 unsigned MaxInactiveCount = 0;
1468 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
1469 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1471 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
1473 unsigned reg = i->first->reg;
1474 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1475 "Can only allocate virtual registers!");
1477 // If this is not in a related reg class to the register we're allocating,
1479 const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
1480 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
1481 reg = vrm_->getPhys(reg);
1482 if (inactiveCounts.size() <= reg)
1483 inactiveCounts.resize(reg+1);
1484 ++inactiveCounts[reg];
1485 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
1489 // If copy coalescer has assigned a "preferred" register, check if it's
1491 unsigned Preference = vrm_->getRegAllocPref(cur->reg);
1493 DEBUG(errs() << "(preferred: " << tri_->getName(Preference) << ") ");
1494 if (isRegAvail(Preference) &&
1495 RC->contains(Preference))
1499 if (!DowngradedRegs.empty()) {
1500 unsigned FreeReg = getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts,
1505 return getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts, false);
1508 FunctionPass* llvm::createLinearScanRegisterAllocator() {
1509 return new RALinScan();