1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "VirtRegMap.h"
16 #include "VirtRegRewriter.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/LiveStackAnalysis.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegAllocRegistry.h"
27 #include "llvm/CodeGen/RegisterCoalescer.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/ADT/EquivalenceClasses.h"
33 #include "llvm/ADT/SmallSet.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/Compiler.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/raw_ostream.h"
49 STATISTIC(NumIters , "Number of iterations performed");
50 STATISTIC(NumBacktracks, "Number of times we had to backtrack");
51 STATISTIC(NumCoalesce, "Number of copies coalesced");
52 STATISTIC(NumDowngrade, "Number of registers downgraded");
55 NewHeuristic("new-spilling-heuristic",
56 cl::desc("Use new spilling heuristic"),
57 cl::init(false), cl::Hidden);
60 PreSplitIntervals("pre-alloc-split",
61 cl::desc("Pre-register allocation live interval splitting"),
62 cl::init(false), cl::Hidden);
65 NewSpillFramework("new-spill-framework",
66 cl::desc("New spilling framework"),
67 cl::init(false), cl::Hidden);
69 static RegisterRegAlloc
70 linearscanRegAlloc("linearscan", "linear scan register allocator",
71 createLinearScanRegisterAllocator);
74 struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass {
76 RALinScan() : MachineFunctionPass(&ID) {}
78 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
79 typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
81 /// RelatedRegClasses - This structure is built the first time a function is
82 /// compiled, and keeps track of which register classes have registers that
83 /// belong to multiple classes or have aliases that are in other classes.
84 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
85 DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
87 // NextReloadMap - For each register in the map, it maps to the another
88 // register which is defined by a reload from the same stack slot and
89 // both reloads are in the same basic block.
90 DenseMap<unsigned, unsigned> NextReloadMap;
92 // DowngradedRegs - A set of registers which are being "downgraded", i.e.
93 // un-favored for allocation.
94 SmallSet<unsigned, 8> DowngradedRegs;
96 // DowngradeMap - A map from virtual registers to physical registers being
97 // downgraded for the virtual registers.
98 DenseMap<unsigned, unsigned> DowngradeMap;
100 MachineFunction* mf_;
101 MachineRegisterInfo* mri_;
102 const TargetMachine* tm_;
103 const TargetRegisterInfo* tri_;
104 const TargetInstrInfo* tii_;
105 BitVector allocatableRegs_;
108 const MachineLoopInfo *loopInfo;
110 /// handled_ - Intervals are added to the handled_ set in the order of their
111 /// start value. This is uses for backtracking.
112 std::vector<LiveInterval*> handled_;
114 /// fixed_ - Intervals that correspond to machine registers.
118 /// active_ - Intervals that are currently being processed, and which have a
119 /// live range active for the current point.
120 IntervalPtrs active_;
122 /// inactive_ - Intervals that are currently being processed, but which have
123 /// a hold at the current point.
124 IntervalPtrs inactive_;
126 typedef std::priority_queue<LiveInterval*,
127 SmallVector<LiveInterval*, 64>,
128 greater_ptr<LiveInterval> > IntervalHeap;
129 IntervalHeap unhandled_;
131 /// regUse_ - Tracks register usage.
132 SmallVector<unsigned, 32> regUse_;
133 SmallVector<unsigned, 32> regUseBackUp_;
135 /// vrm_ - Tracks register assignments.
138 std::auto_ptr<VirtRegRewriter> rewriter_;
140 std::auto_ptr<Spiller> spiller_;
143 virtual const char* getPassName() const {
144 return "Linear Scan Register Allocator";
147 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
148 AU.addRequired<LiveIntervals>();
150 AU.addRequiredID(StrongPHIEliminationID);
151 // Make sure PassManager knows which analyses to make available
152 // to coalescing and which analyses coalescing invalidates.
153 AU.addRequiredTransitive<RegisterCoalescer>();
154 if (PreSplitIntervals)
155 AU.addRequiredID(PreAllocSplittingID);
156 AU.addRequired<LiveStacks>();
157 AU.addPreserved<LiveStacks>();
158 AU.addRequired<MachineLoopInfo>();
159 AU.addPreserved<MachineLoopInfo>();
160 AU.addRequired<VirtRegMap>();
161 AU.addPreserved<VirtRegMap>();
162 AU.addPreservedID(MachineDominatorsID);
163 MachineFunctionPass::getAnalysisUsage(AU);
166 /// runOnMachineFunction - register allocate the whole function
167 bool runOnMachineFunction(MachineFunction&);
170 /// linearScan - the linear scan algorithm
173 /// initIntervalSets - initialize the interval sets.
175 void initIntervalSets();
177 /// processActiveIntervals - expire old intervals and move non-overlapping
178 /// ones to the inactive list.
179 void processActiveIntervals(unsigned CurPoint);
181 /// processInactiveIntervals - expire old intervals and move overlapping
182 /// ones to the active list.
183 void processInactiveIntervals(unsigned CurPoint);
185 /// hasNextReloadInterval - Return the next liveinterval that's being
186 /// defined by a reload from the same SS as the specified one.
187 LiveInterval *hasNextReloadInterval(LiveInterval *cur);
189 /// DowngradeRegister - Downgrade a register for allocation.
190 void DowngradeRegister(LiveInterval *li, unsigned Reg);
192 /// UpgradeRegister - Upgrade a register for allocation.
193 void UpgradeRegister(unsigned Reg);
195 /// assignRegOrStackSlotAtInterval - assign a register if one
196 /// is available, or spill.
197 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
199 void updateSpillWeights(std::vector<float> &Weights,
200 unsigned reg, float weight,
201 const TargetRegisterClass *RC);
203 /// findIntervalsToSpill - Determine the intervals to spill for the
204 /// specified interval. It's passed the physical registers whose spill
205 /// weight is the lowest among all the registers whose live intervals
206 /// conflict with the interval.
207 void findIntervalsToSpill(LiveInterval *cur,
208 std::vector<std::pair<unsigned,float> > &Candidates,
210 SmallVector<LiveInterval*, 8> &SpillIntervals);
212 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
213 /// try allocate the definition the same register as the source register
214 /// if the register is not defined during live time of the interval. This
215 /// eliminate a copy. This is used to coalesce copies which were not
216 /// coalesced away before allocation either due to dest and src being in
217 /// different register classes or because the coalescer was overly
219 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
222 /// Register usage / availability tracking helpers.
226 regUse_.resize(tri_->getNumRegs(), 0);
227 regUseBackUp_.resize(tri_->getNumRegs(), 0);
230 void finalizeRegUses() {
232 // Verify all the registers are "freed".
234 for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
235 if (regUse_[i] != 0) {
236 cerr << tri_->getName(i) << " is still in use!\n";
244 regUseBackUp_.clear();
247 void addRegUse(unsigned physReg) {
248 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
249 "should be physical register!");
251 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
255 void delRegUse(unsigned physReg) {
256 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
257 "should be physical register!");
258 assert(regUse_[physReg] != 0);
260 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
261 assert(regUse_[*as] != 0);
266 bool isRegAvail(unsigned physReg) const {
267 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
268 "should be physical register!");
269 return regUse_[physReg] == 0;
272 void backUpRegUses() {
273 regUseBackUp_ = regUse_;
276 void restoreRegUses() {
277 regUse_ = regUseBackUp_;
281 /// Register handling helpers.
284 /// getFreePhysReg - return a free physical register for this virtual
285 /// register interval if we have one, otherwise return 0.
286 unsigned getFreePhysReg(LiveInterval* cur);
287 unsigned getFreePhysReg(LiveInterval* cur,
288 const TargetRegisterClass *RC,
289 unsigned MaxInactiveCount,
290 SmallVector<unsigned, 256> &inactiveCounts,
293 /// assignVirt2StackSlot - assigns this virtual register to a
294 /// stack slot. returns the stack slot
295 int assignVirt2StackSlot(unsigned virtReg);
297 void ComputeRelatedRegClasses();
299 template <typename ItTy>
300 void printIntervals(const char* const str, ItTy i, ItTy e) const {
301 if (str) DOUT << str << " intervals:\n";
302 for (; i != e; ++i) {
303 DOUT << "\t" << *i->first << " -> ";
304 unsigned reg = i->first->reg;
305 if (TargetRegisterInfo::isVirtualRegister(reg)) {
306 reg = vrm_->getPhys(reg);
308 DOUT << tri_->getName(reg) << '\n';
312 char RALinScan::ID = 0;
315 static RegisterPass<RALinScan>
316 X("linearscan-regalloc", "Linear Scan Register Allocator");
318 void RALinScan::ComputeRelatedRegClasses() {
319 // First pass, add all reg classes to the union, and determine at least one
320 // reg class that each register is in.
321 bool HasAliases = false;
322 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
323 E = tri_->regclass_end(); RCI != E; ++RCI) {
324 RelatedRegClasses.insert(*RCI);
325 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
327 HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
329 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
331 // Already processed this register. Just make sure we know that
332 // multiple register classes share a register.
333 RelatedRegClasses.unionSets(PRC, *RCI);
340 // Second pass, now that we know conservatively what register classes each reg
341 // belongs to, add info about aliases. We don't need to do this for targets
342 // without register aliases.
344 for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
345 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
347 for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
348 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
351 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
352 /// try allocate the definition the same register as the source register
353 /// if the register is not defined during live time of the interval. This
354 /// eliminate a copy. This is used to coalesce copies which were not
355 /// coalesced away before allocation either due to dest and src being in
356 /// different register classes or because the coalescer was overly
358 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
359 unsigned Preference = vrm_->getRegAllocPref(cur.reg);
360 if ((Preference && Preference == Reg) || !cur.containsOneValue())
363 VNInfo *vni = cur.begin()->valno;
364 if (!vni->def || vni->isUnused() || !vni->isDefAccurate())
366 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
367 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg, PhysReg;
369 !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
372 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
373 if (!vrm_->isAssignedReg(SrcReg))
375 PhysReg = vrm_->getPhys(SrcReg);
380 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
381 if (!RC->contains(PhysReg))
385 if (!li_->conflictsWithPhysRegDef(cur, *vrm_, PhysReg)) {
386 DOUT << "Coalescing: " << cur << " -> " << tri_->getName(PhysReg)
388 vrm_->clearVirt(cur.reg);
389 vrm_->assignVirt2Phys(cur.reg, PhysReg);
391 // Remove unnecessary kills since a copy does not clobber the register.
392 if (li_->hasInterval(SrcReg)) {
393 LiveInterval &SrcLI = li_->getInterval(SrcReg);
394 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(cur.reg),
395 E = mri_->reg_end(); I != E; ++I) {
396 MachineOperand &O = I.getOperand();
397 if (!O.isUse() || !O.isKill())
399 MachineInstr *MI = &*I;
400 if (SrcLI.liveAt(li_->getDefIndex(li_->getInstructionIndex(MI))))
412 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
414 mri_ = &fn.getRegInfo();
415 tm_ = &fn.getTarget();
416 tri_ = tm_->getRegisterInfo();
417 tii_ = tm_->getInstrInfo();
418 allocatableRegs_ = tri_->getAllocatableSet(fn);
419 li_ = &getAnalysis<LiveIntervals>();
420 ls_ = &getAnalysis<LiveStacks>();
421 loopInfo = &getAnalysis<MachineLoopInfo>();
423 // We don't run the coalescer here because we have no reason to
424 // interact with it. If the coalescer requires interaction, it
425 // won't do anything. If it doesn't require interaction, we assume
426 // it was run as a separate pass.
428 // If this is the first function compiled, compute the related reg classes.
429 if (RelatedRegClasses.empty())
430 ComputeRelatedRegClasses();
432 // Also resize register usage trackers.
435 vrm_ = &getAnalysis<VirtRegMap>();
436 if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
438 if (NewSpillFramework) {
439 spiller_.reset(createSpiller(mf_, li_, ls_, vrm_));
446 // Rewrite spill code and update the PhysRegsUsed set.
447 rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
449 assert(unhandled_.empty() && "Unhandled live intervals remain!");
457 NextReloadMap.clear();
458 DowngradedRegs.clear();
459 DowngradeMap.clear();
465 /// initIntervalSets - initialize the interval sets.
467 void RALinScan::initIntervalSets()
469 assert(unhandled_.empty() && fixed_.empty() &&
470 active_.empty() && inactive_.empty() &&
471 "interval sets should be empty on initialization");
473 handled_.reserve(li_->getNumIntervals());
475 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
476 if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
477 mri_->setPhysRegUsed(i->second->reg);
478 fixed_.push_back(std::make_pair(i->second, i->second->begin()));
480 unhandled_.push(i->second);
484 void RALinScan::linearScan()
486 // linear scan algorithm
487 DOUT << "********** LINEAR SCAN **********\n";
488 DEBUG(errs() << "********** Function: "
489 << mf_->getFunction()->getName() << '\n');
491 DEBUG(printIntervals("fixed", fixed_.begin(), fixed_.end()));
493 while (!unhandled_.empty()) {
494 // pick the interval with the earliest start point
495 LiveInterval* cur = unhandled_.top();
498 DOUT << "\n*** CURRENT ***: " << *cur << '\n';
501 processActiveIntervals(cur->beginNumber());
502 processInactiveIntervals(cur->beginNumber());
504 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
505 "Can only allocate virtual registers!");
508 // Allocating a virtual register. try to find a free
509 // physical register or spill an interval (possibly this one) in order to
511 assignRegOrStackSlotAtInterval(cur);
513 DEBUG(printIntervals("active", active_.begin(), active_.end()));
514 DEBUG(printIntervals("inactive", inactive_.begin(), inactive_.end()));
517 // Expire any remaining active intervals
518 while (!active_.empty()) {
519 IntervalPtr &IP = active_.back();
520 unsigned reg = IP.first->reg;
521 DOUT << "\tinterval " << *IP.first << " expired\n";
522 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
523 "Can only allocate virtual registers!");
524 reg = vrm_->getPhys(reg);
529 // Expire any remaining inactive intervals
530 DEBUG(for (IntervalPtrs::reverse_iterator
531 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
532 DOUT << "\tinterval " << *i->first << " expired\n");
535 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
536 MachineFunction::iterator EntryMBB = mf_->begin();
537 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
538 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
539 LiveInterval &cur = *i->second;
541 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
544 else if (vrm_->isAssignedReg(cur.reg))
545 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
548 // Ignore splited live intervals.
549 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
552 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
554 const LiveRange &LR = *I;
555 if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
556 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
557 if (LiveInMBBs[i] != EntryMBB) {
558 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
559 "Adding a virtual register to livein set?");
560 LiveInMBBs[i]->addLiveIn(Reg);
569 // Look for physical registers that end up not being allocated even though
570 // register allocator had to spill other registers in its register class.
571 if (ls_->getNumIntervals() == 0)
573 if (!vrm_->FindUnusedRegisters(li_))
577 /// processActiveIntervals - expire old intervals and move non-overlapping ones
578 /// to the inactive list.
579 void RALinScan::processActiveIntervals(unsigned CurPoint)
581 DOUT << "\tprocessing active intervals:\n";
583 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
584 LiveInterval *Interval = active_[i].first;
585 LiveInterval::iterator IntervalPos = active_[i].second;
586 unsigned reg = Interval->reg;
588 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
590 if (IntervalPos == Interval->end()) { // Remove expired intervals.
591 DOUT << "\t\tinterval " << *Interval << " expired\n";
592 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
593 "Can only allocate virtual registers!");
594 reg = vrm_->getPhys(reg);
597 // Pop off the end of the list.
598 active_[i] = active_.back();
602 } else if (IntervalPos->start > CurPoint) {
603 // Move inactive intervals to inactive list.
604 DOUT << "\t\tinterval " << *Interval << " inactive\n";
605 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
606 "Can only allocate virtual registers!");
607 reg = vrm_->getPhys(reg);
610 inactive_.push_back(std::make_pair(Interval, IntervalPos));
612 // Pop off the end of the list.
613 active_[i] = active_.back();
617 // Otherwise, just update the iterator position.
618 active_[i].second = IntervalPos;
623 /// processInactiveIntervals - expire old intervals and move overlapping
624 /// ones to the active list.
625 void RALinScan::processInactiveIntervals(unsigned CurPoint)
627 DOUT << "\tprocessing inactive intervals:\n";
629 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
630 LiveInterval *Interval = inactive_[i].first;
631 LiveInterval::iterator IntervalPos = inactive_[i].second;
632 unsigned reg = Interval->reg;
634 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
636 if (IntervalPos == Interval->end()) { // remove expired intervals.
637 DOUT << "\t\tinterval " << *Interval << " expired\n";
639 // Pop off the end of the list.
640 inactive_[i] = inactive_.back();
641 inactive_.pop_back();
643 } else if (IntervalPos->start <= CurPoint) {
644 // move re-activated intervals in active list
645 DOUT << "\t\tinterval " << *Interval << " active\n";
646 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
647 "Can only allocate virtual registers!");
648 reg = vrm_->getPhys(reg);
651 active_.push_back(std::make_pair(Interval, IntervalPos));
653 // Pop off the end of the list.
654 inactive_[i] = inactive_.back();
655 inactive_.pop_back();
658 // Otherwise, just update the iterator position.
659 inactive_[i].second = IntervalPos;
664 /// updateSpillWeights - updates the spill weights of the specifed physical
665 /// register and its weight.
666 void RALinScan::updateSpillWeights(std::vector<float> &Weights,
667 unsigned reg, float weight,
668 const TargetRegisterClass *RC) {
669 SmallSet<unsigned, 4> Processed;
670 SmallSet<unsigned, 4> SuperAdded;
671 SmallVector<unsigned, 4> Supers;
672 Weights[reg] += weight;
673 Processed.insert(reg);
674 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
675 Weights[*as] += weight;
676 Processed.insert(*as);
677 if (tri_->isSubRegister(*as, reg) &&
678 SuperAdded.insert(*as) &&
680 Supers.push_back(*as);
684 // If the alias is a super-register, and the super-register is in the
685 // register class we are trying to allocate. Then add the weight to all
686 // sub-registers of the super-register even if they are not aliases.
687 // e.g. allocating for GR32, bh is not used, updating bl spill weight.
688 // bl should get the same spill weight otherwise it will be choosen
689 // as a spill candidate since spilling bh doesn't make ebx available.
690 for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
691 for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
692 if (!Processed.count(*sr))
693 Weights[*sr] += weight;
698 RALinScan::IntervalPtrs::iterator
699 FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
700 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
702 if (I->first == LI) return I;
706 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, unsigned Point){
707 for (unsigned i = 0, e = V.size(); i != e; ++i) {
708 RALinScan::IntervalPtr &IP = V[i];
709 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
711 if (I != IP.first->begin()) --I;
716 /// addStackInterval - Create a LiveInterval for stack if the specified live
717 /// interval has been spilled.
718 static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
720 MachineRegisterInfo* mri_, VirtRegMap &vrm_) {
721 int SS = vrm_.getStackSlot(cur->reg);
722 if (SS == VirtRegMap::NO_STACK_SLOT)
725 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
726 LiveInterval &SI = ls_->getOrCreateInterval(SS, RC);
729 if (SI.hasAtLeastOneValue())
730 VNI = SI.getValNumInfo(0);
732 VNI = SI.getNextValue(0, 0, false, ls_->getVNInfoAllocator());
734 LiveInterval &RI = li_->getInterval(cur->reg);
735 // FIXME: This may be overly conservative.
736 SI.MergeRangesInAsValue(RI, VNI);
739 /// getConflictWeight - Return the number of conflicts between cur
740 /// live interval and defs and uses of Reg weighted by loop depthes.
742 float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
743 MachineRegisterInfo *mri_,
744 const MachineLoopInfo *loopInfo) {
746 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
747 E = mri_->reg_end(); I != E; ++I) {
748 MachineInstr *MI = &*I;
749 if (cur->liveAt(li_->getInstructionIndex(MI))) {
750 unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
751 Conflicts += powf(10.0f, (float)loopDepth);
757 /// findIntervalsToSpill - Determine the intervals to spill for the
758 /// specified interval. It's passed the physical registers whose spill
759 /// weight is the lowest among all the registers whose live intervals
760 /// conflict with the interval.
761 void RALinScan::findIntervalsToSpill(LiveInterval *cur,
762 std::vector<std::pair<unsigned,float> > &Candidates,
764 SmallVector<LiveInterval*, 8> &SpillIntervals) {
765 // We have figured out the *best* register to spill. But there are other
766 // registers that are pretty good as well (spill weight within 3%). Spill
767 // the one that has fewest defs and uses that conflict with cur.
768 float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
769 SmallVector<LiveInterval*, 8> SLIs[3];
771 DOUT << "\tConsidering " << NumCands << " candidates: ";
772 DEBUG(for (unsigned i = 0; i != NumCands; ++i)
773 DOUT << tri_->getName(Candidates[i].first) << " ";
776 // Calculate the number of conflicts of each candidate.
777 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
778 unsigned Reg = i->first->reg;
779 unsigned PhysReg = vrm_->getPhys(Reg);
780 if (!cur->overlapsFrom(*i->first, i->second))
782 for (unsigned j = 0; j < NumCands; ++j) {
783 unsigned Candidate = Candidates[j].first;
784 if (tri_->regsOverlap(PhysReg, Candidate)) {
786 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
787 SLIs[j].push_back(i->first);
792 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
793 unsigned Reg = i->first->reg;
794 unsigned PhysReg = vrm_->getPhys(Reg);
795 if (!cur->overlapsFrom(*i->first, i->second-1))
797 for (unsigned j = 0; j < NumCands; ++j) {
798 unsigned Candidate = Candidates[j].first;
799 if (tri_->regsOverlap(PhysReg, Candidate)) {
801 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
802 SLIs[j].push_back(i->first);
807 // Which is the best candidate?
808 unsigned BestCandidate = 0;
809 float MinConflicts = Conflicts[0];
810 for (unsigned i = 1; i != NumCands; ++i) {
811 if (Conflicts[i] < MinConflicts) {
813 MinConflicts = Conflicts[i];
817 std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
818 std::back_inserter(SpillIntervals));
822 struct WeightCompare {
823 typedef std::pair<unsigned, float> RegWeightPair;
824 bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
825 return LHS.second < RHS.second;
830 static bool weightsAreClose(float w1, float w2) {
834 float diff = w1 - w2;
835 if (diff <= 0.02f) // Within 0.02f
837 return (diff / w2) <= 0.05f; // Within 5%.
840 LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
841 DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
842 if (I == NextReloadMap.end())
844 return &li_->getInterval(I->second);
847 void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
848 bool isNew = DowngradedRegs.insert(Reg);
849 isNew = isNew; // Silence compiler warning.
850 assert(isNew && "Multiple reloads holding the same register?");
851 DowngradeMap.insert(std::make_pair(li->reg, Reg));
852 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS) {
853 isNew = DowngradedRegs.insert(*AS);
854 isNew = isNew; // Silence compiler warning.
855 assert(isNew && "Multiple reloads holding the same register?");
856 DowngradeMap.insert(std::make_pair(li->reg, *AS));
861 void RALinScan::UpgradeRegister(unsigned Reg) {
863 DowngradedRegs.erase(Reg);
864 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
865 DowngradedRegs.erase(*AS);
871 bool operator()(LiveInterval* A, LiveInterval* B) {
872 return A->beginNumber() < B->beginNumber();
877 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
879 void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
881 DOUT << "\tallocating current interval: ";
883 // This is an implicitly defined live interval, just assign any register.
884 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
886 unsigned physReg = vrm_->getRegAllocPref(cur->reg);
888 physReg = *RC->allocation_order_begin(*mf_);
889 DOUT << tri_->getName(physReg) << '\n';
890 // Note the register is not really in use.
891 vrm_->assignVirt2Phys(cur->reg, physReg);
897 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
898 unsigned StartPosition = cur->beginNumber();
899 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
901 // If start of this live interval is defined by a move instruction and its
902 // source is assigned a physical register that is compatible with the target
903 // register class, then we should try to assign it the same register.
904 // This can happen when the move is from a larger register class to a smaller
905 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
906 if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
907 VNInfo *vni = cur->begin()->valno;
908 if (vni->def && !vni->isUnused() && vni->isDefAccurate()) {
909 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
910 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
912 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
914 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
916 else if (vrm_->isAssignedReg(SrcReg))
917 Reg = vrm_->getPhys(SrcReg);
920 Reg = tri_->getSubReg(Reg, SrcSubReg);
922 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
923 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
924 mri_->setRegAllocationHint(cur->reg, 0, Reg);
930 // For every interval in inactive we overlap with, mark the
931 // register as not free and update spill weights.
932 for (IntervalPtrs::const_iterator i = inactive_.begin(),
933 e = inactive_.end(); i != e; ++i) {
934 unsigned Reg = i->first->reg;
935 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
936 "Can only allocate virtual registers!");
937 const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
938 // If this is not in a related reg class to the register we're allocating,
940 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
941 cur->overlapsFrom(*i->first, i->second-1)) {
942 Reg = vrm_->getPhys(Reg);
944 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
948 // Speculatively check to see if we can get a register right now. If not,
949 // we know we won't be able to by adding more constraints. If so, we can
950 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
951 // is very bad (it contains all callee clobbered registers for any functions
952 // with a call), so we want to avoid doing that if possible.
953 unsigned physReg = getFreePhysReg(cur);
954 unsigned BestPhysReg = physReg;
956 // We got a register. However, if it's in the fixed_ list, we might
957 // conflict with it. Check to see if we conflict with it or any of its
959 SmallSet<unsigned, 8> RegAliases;
960 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
961 RegAliases.insert(*AS);
963 bool ConflictsWithFixed = false;
964 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
965 IntervalPtr &IP = fixed_[i];
966 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
967 // Okay, this reg is on the fixed list. Check to see if we actually
969 LiveInterval *I = IP.first;
970 if (I->endNumber() > StartPosition) {
971 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
973 if (II != I->begin() && II->start > StartPosition)
975 if (cur->overlapsFrom(*I, II)) {
976 ConflictsWithFixed = true;
983 // Okay, the register picked by our speculative getFreePhysReg call turned
984 // out to be in use. Actually add all of the conflicting fixed registers to
985 // regUse_ so we can do an accurate query.
986 if (ConflictsWithFixed) {
987 // For every interval in fixed we overlap with, mark the register as not
988 // free and update spill weights.
989 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
990 IntervalPtr &IP = fixed_[i];
991 LiveInterval *I = IP.first;
993 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
994 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
995 I->endNumber() > StartPosition) {
996 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
998 if (II != I->begin() && II->start > StartPosition)
1000 if (cur->overlapsFrom(*I, II)) {
1001 unsigned reg = I->reg;
1003 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
1008 // Using the newly updated regUse_ object, which includes conflicts in the
1009 // future, see if there are any registers available.
1010 physReg = getFreePhysReg(cur);
1014 // Restore the physical register tracker, removing information about the
1018 // If we find a free register, we are done: assign this virtual to
1019 // the free physical register and add this interval to the active
1022 DOUT << tri_->getName(physReg) << '\n';
1023 vrm_->assignVirt2Phys(cur->reg, physReg);
1025 active_.push_back(std::make_pair(cur, cur->begin()));
1026 handled_.push_back(cur);
1028 // "Upgrade" the physical register since it has been allocated.
1029 UpgradeRegister(physReg);
1030 if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
1031 // "Downgrade" physReg to try to keep physReg from being allocated until
1032 // the next reload from the same SS is allocated.
1033 mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg);
1034 DowngradeRegister(cur, physReg);
1038 DOUT << "no free registers\n";
1040 // Compile the spill weights into an array that is better for scanning.
1041 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
1042 for (std::vector<std::pair<unsigned, float> >::iterator
1043 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
1044 updateSpillWeights(SpillWeights, I->first, I->second, RC);
1046 // for each interval in active, update spill weights.
1047 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
1049 unsigned reg = i->first->reg;
1050 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1051 "Can only allocate virtual registers!");
1052 reg = vrm_->getPhys(reg);
1053 updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
1056 DOUT << "\tassigning stack slot at interval "<< *cur << ":\n";
1058 // Find a register to spill.
1059 float minWeight = HUGE_VALF;
1060 unsigned minReg = 0;
1063 std::vector<std::pair<unsigned,float> > RegsWeights;
1064 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
1065 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1066 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1068 float regWeight = SpillWeights[reg];
1069 if (minWeight > regWeight)
1071 RegsWeights.push_back(std::make_pair(reg, regWeight));
1074 // If we didn't find a register that is spillable, try aliases?
1076 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1077 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1079 // No need to worry about if the alias register size < regsize of RC.
1080 // We are going to spill all registers that alias it anyway.
1081 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
1082 RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
1086 // Sort all potential spill candidates by weight.
1087 std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare());
1088 minReg = RegsWeights[0].first;
1089 minWeight = RegsWeights[0].second;
1090 if (minWeight == HUGE_VALF) {
1091 // All registers must have inf weight. Just grab one!
1092 minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
1093 if (cur->weight == HUGE_VALF ||
1094 li_->getApproximateInstructionCount(*cur) == 0) {
1095 // Spill a physical register around defs and uses.
1096 if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
1097 // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
1098 // in fixed_. Reset them.
1099 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1100 IntervalPtr &IP = fixed_[i];
1101 LiveInterval *I = IP.first;
1102 if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
1103 IP.second = I->advanceTo(I->begin(), StartPosition);
1106 DowngradedRegs.clear();
1107 assignRegOrStackSlotAtInterval(cur);
1109 llvm_report_error("Ran out of registers during register allocation!");
1115 // Find up to 3 registers to consider as spill candidates.
1116 unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
1117 while (LastCandidate > 1) {
1118 if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
1123 DOUT << "\t\tregister(s) with min weight(s): ";
1124 DEBUG(for (unsigned i = 0; i != LastCandidate; ++i)
1125 DOUT << tri_->getName(RegsWeights[i].first)
1126 << " (" << RegsWeights[i].second << ")\n");
1128 // If the current has the minimum weight, we need to spill it and
1129 // add any added intervals back to unhandled, and restart
1131 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
1132 DOUT << "\t\t\tspilling(c): " << *cur << '\n';
1133 SmallVector<LiveInterval*, 8> spillIs;
1134 std::vector<LiveInterval*> added;
1136 if (!NewSpillFramework) {
1137 added = li_->addIntervalsForSpills(*cur, spillIs, loopInfo, *vrm_);
1139 added = spiller_->spill(cur);
1142 std::sort(added.begin(), added.end(), LISorter());
1143 addStackInterval(cur, ls_, li_, mri_, *vrm_);
1145 return; // Early exit if all spills were folded.
1147 // Merge added with unhandled. Note that we have already sorted
1148 // intervals returned by addIntervalsForSpills by their starting
1150 // This also update the NextReloadMap. That is, it adds mapping from a
1151 // register defined by a reload from SS to the next reload from SS in the
1152 // same basic block.
1153 MachineBasicBlock *LastReloadMBB = 0;
1154 LiveInterval *LastReload = 0;
1155 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1156 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1157 LiveInterval *ReloadLi = added[i];
1158 if (ReloadLi->weight == HUGE_VALF &&
1159 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1160 unsigned ReloadIdx = ReloadLi->beginNumber();
1161 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1162 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1163 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1164 // Last reload of same SS is in the same MBB. We want to try to
1165 // allocate both reloads the same register and make sure the reg
1166 // isn't clobbered in between if at all possible.
1167 assert(LastReload->beginNumber() < ReloadIdx);
1168 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1170 LastReloadMBB = ReloadMBB;
1171 LastReload = ReloadLi;
1172 LastReloadSS = ReloadSS;
1174 unhandled_.push(ReloadLi);
1181 // Push the current interval back to unhandled since we are going
1182 // to re-run at least this iteration. Since we didn't modify it it
1183 // should go back right in the front of the list
1184 unhandled_.push(cur);
1186 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
1187 "did not choose a register to spill?");
1189 // We spill all intervals aliasing the register with
1190 // minimum weight, rollback to the interval with the earliest
1191 // start point and let the linear scan algorithm run again
1192 SmallVector<LiveInterval*, 8> spillIs;
1194 // Determine which intervals have to be spilled.
1195 findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
1197 // Set of spilled vregs (used later to rollback properly)
1198 SmallSet<unsigned, 8> spilled;
1200 // The earliest start of a Spilled interval indicates up to where
1201 // in handled we need to roll back
1203 LiveInterval *earliestStartInterval = cur;
1205 // Spill live intervals of virtual regs mapped to the physical register we
1206 // want to clear (and its aliases). We only spill those that overlap with the
1207 // current interval as the rest do not affect its allocation. we also keep
1208 // track of the earliest start of all spilled live intervals since this will
1209 // mark our rollback point.
1210 std::vector<LiveInterval*> added;
1211 while (!spillIs.empty()) {
1212 LiveInterval *sli = spillIs.back();
1214 DOUT << "\t\t\tspilling(a): " << *sli << '\n';
1215 earliestStartInterval =
1216 (earliestStartInterval->beginNumber() < sli->beginNumber()) ?
1217 earliestStartInterval : sli;
1219 std::vector<LiveInterval*> newIs;
1220 if (!NewSpillFramework) {
1221 newIs = li_->addIntervalsForSpills(*sli, spillIs, loopInfo, *vrm_);
1223 newIs = spiller_->spill(sli);
1225 addStackInterval(sli, ls_, li_, mri_, *vrm_);
1226 std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
1227 spilled.insert(sli->reg);
1230 unsigned earliestStart = earliestStartInterval->beginNumber();
1232 DOUT << "\t\trolling back to: " << earliestStart << '\n';
1234 // Scan handled in reverse order up to the earliest start of a
1235 // spilled live interval and undo each one, restoring the state of
1237 while (!handled_.empty()) {
1238 LiveInterval* i = handled_.back();
1239 // If this interval starts before t we are done.
1240 if (i->beginNumber() < earliestStart)
1242 DOUT << "\t\t\tundo changes for: " << *i << '\n';
1243 handled_.pop_back();
1245 // When undoing a live interval allocation we must know if it is active or
1246 // inactive to properly update regUse_ and the VirtRegMap.
1247 IntervalPtrs::iterator it;
1248 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
1250 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1251 if (!spilled.count(i->reg))
1253 delRegUse(vrm_->getPhys(i->reg));
1254 vrm_->clearVirt(i->reg);
1255 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
1256 inactive_.erase(it);
1257 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1258 if (!spilled.count(i->reg))
1260 vrm_->clearVirt(i->reg);
1262 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
1263 "Can only allocate virtual registers!");
1264 vrm_->clearVirt(i->reg);
1268 DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
1269 if (ii == DowngradeMap.end())
1270 // It interval has a preference, it must be defined by a copy. Clear the
1271 // preference now since the source interval allocation may have been
1273 mri_->setRegAllocationHint(i->reg, 0, 0);
1275 UpgradeRegister(ii->second);
1279 // Rewind the iterators in the active, inactive, and fixed lists back to the
1280 // point we reverted to.
1281 RevertVectorIteratorsTo(active_, earliestStart);
1282 RevertVectorIteratorsTo(inactive_, earliestStart);
1283 RevertVectorIteratorsTo(fixed_, earliestStart);
1285 // Scan the rest and undo each interval that expired after t and
1286 // insert it in active (the next iteration of the algorithm will
1287 // put it in inactive if required)
1288 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
1289 LiveInterval *HI = handled_[i];
1290 if (!HI->expiredAt(earliestStart) &&
1291 HI->expiredAt(cur->beginNumber())) {
1292 DOUT << "\t\t\tundo changes for: " << *HI << '\n';
1293 active_.push_back(std::make_pair(HI, HI->begin()));
1294 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
1295 addRegUse(vrm_->getPhys(HI->reg));
1299 // Merge added with unhandled.
1300 // This also update the NextReloadMap. That is, it adds mapping from a
1301 // register defined by a reload from SS to the next reload from SS in the
1302 // same basic block.
1303 MachineBasicBlock *LastReloadMBB = 0;
1304 LiveInterval *LastReload = 0;
1305 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1306 std::sort(added.begin(), added.end(), LISorter());
1307 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1308 LiveInterval *ReloadLi = added[i];
1309 if (ReloadLi->weight == HUGE_VALF &&
1310 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1311 unsigned ReloadIdx = ReloadLi->beginNumber();
1312 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1313 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1314 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1315 // Last reload of same SS is in the same MBB. We want to try to
1316 // allocate both reloads the same register and make sure the reg
1317 // isn't clobbered in between if at all possible.
1318 assert(LastReload->beginNumber() < ReloadIdx);
1319 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1321 LastReloadMBB = ReloadMBB;
1322 LastReload = ReloadLi;
1323 LastReloadSS = ReloadSS;
1325 unhandled_.push(ReloadLi);
1329 unsigned RALinScan::getFreePhysReg(LiveInterval* cur,
1330 const TargetRegisterClass *RC,
1331 unsigned MaxInactiveCount,
1332 SmallVector<unsigned, 256> &inactiveCounts,
1334 unsigned FreeReg = 0;
1335 unsigned FreeRegInactiveCount = 0;
1337 std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(cur->reg);
1338 // Resolve second part of the hint (if possible) given the current allocation.
1339 unsigned physReg = Hint.second;
1341 TargetRegisterInfo::isVirtualRegister(physReg) && vrm_->hasPhys(physReg))
1342 physReg = vrm_->getPhys(physReg);
1344 TargetRegisterClass::iterator I, E;
1345 tie(I, E) = tri_->getAllocationOrder(RC, Hint.first, physReg, *mf_);
1346 assert(I != E && "No allocatable register in this register class!");
1348 // Scan for the first available register.
1349 for (; I != E; ++I) {
1351 // Ignore "downgraded" registers.
1352 if (SkipDGRegs && DowngradedRegs.count(Reg))
1354 if (isRegAvail(Reg)) {
1356 if (FreeReg < inactiveCounts.size())
1357 FreeRegInactiveCount = inactiveCounts[FreeReg];
1359 FreeRegInactiveCount = 0;
1364 // If there are no free regs, or if this reg has the max inactive count,
1365 // return this register.
1366 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount)
1369 // Continue scanning the registers, looking for the one with the highest
1370 // inactive count. Alkis found that this reduced register pressure very
1371 // slightly on X86 (in rev 1.94 of this file), though this should probably be
1373 for (; I != E; ++I) {
1375 // Ignore "downgraded" registers.
1376 if (SkipDGRegs && DowngradedRegs.count(Reg))
1378 if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
1379 FreeRegInactiveCount < inactiveCounts[Reg]) {
1381 FreeRegInactiveCount = inactiveCounts[Reg];
1382 if (FreeRegInactiveCount == MaxInactiveCount)
1383 break; // We found the one with the max inactive count.
1390 /// getFreePhysReg - return a free physical register for this virtual register
1391 /// interval if we have one, otherwise return 0.
1392 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
1393 SmallVector<unsigned, 256> inactiveCounts;
1394 unsigned MaxInactiveCount = 0;
1396 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
1397 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1399 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
1401 unsigned reg = i->first->reg;
1402 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1403 "Can only allocate virtual registers!");
1405 // If this is not in a related reg class to the register we're allocating,
1407 const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
1408 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
1409 reg = vrm_->getPhys(reg);
1410 if (inactiveCounts.size() <= reg)
1411 inactiveCounts.resize(reg+1);
1412 ++inactiveCounts[reg];
1413 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
1417 // If copy coalescer has assigned a "preferred" register, check if it's
1419 unsigned Preference = vrm_->getRegAllocPref(cur->reg);
1421 DOUT << "(preferred: " << tri_->getName(Preference) << ") ";
1422 if (isRegAvail(Preference) &&
1423 RC->contains(Preference))
1427 if (!DowngradedRegs.empty()) {
1428 unsigned FreeReg = getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts,
1433 return getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts, false);
1436 FunctionPass* llvm::createLinearScanRegisterAllocator() {
1437 return new RALinScan();