1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "VirtRegMap.h"
16 #include "VirtRegRewriter.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/CalcSpillWeights.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/LiveStackAnalysis.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/MachineLoopInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/RegAllocRegistry.h"
28 #include "llvm/CodeGen/RegisterCoalescer.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/ADT/EquivalenceClasses.h"
34 #include "llvm/ADT/SmallSet.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/ADT/STLExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
48 STATISTIC(NumIters , "Number of iterations performed");
49 STATISTIC(NumBacktracks, "Number of times we had to backtrack");
50 STATISTIC(NumCoalesce, "Number of copies coalesced");
51 STATISTIC(NumDowngrade, "Number of registers downgraded");
54 NewHeuristic("new-spilling-heuristic",
55 cl::desc("Use new spilling heuristic"),
56 cl::init(false), cl::Hidden);
59 PreSplitIntervals("pre-alloc-split",
60 cl::desc("Pre-register allocation live interval splitting"),
61 cl::init(false), cl::Hidden);
64 TrivCoalesceEnds("trivial-coalesce-ends",
65 cl::desc("Attempt trivial coalescing of interval ends"),
66 cl::init(false), cl::Hidden);
68 static RegisterRegAlloc
69 linearscanRegAlloc("linearscan", "linear scan register allocator",
70 createLinearScanRegisterAllocator);
73 // When we allocate a register, add it to a fixed-size queue of
74 // registers to skip in subsequent allocations. This trades a small
75 // amount of register pressure and increased spills for flexibility in
76 // the post-pass scheduler.
78 // Note that in a the number of registers used for reloading spills
79 // will be one greater than the value of this option.
81 // One big limitation of this is that it doesn't differentiate between
82 // different register classes. So on x86-64, if there is xmm register
83 // pressure, it can caused fewer GPRs to be held in the queue.
84 static cl::opt<unsigned>
85 NumRecentlyUsedRegs("linearscan-skip-count",
86 cl::desc("Number of registers for linearscan to remember"
91 struct RALinScan : public MachineFunctionPass {
93 RALinScan() : MachineFunctionPass(ID) {
94 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
95 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
96 initializeRegisterCoalescerAnalysisGroup(
97 *PassRegistry::getPassRegistry());
98 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
99 initializePreAllocSplittingPass(*PassRegistry::getPassRegistry());
100 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
101 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
102 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
103 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
105 // Initialize the queue to record recently-used registers.
106 if (NumRecentlyUsedRegs > 0)
107 RecentRegs.resize(NumRecentlyUsedRegs, 0);
108 RecentNext = RecentRegs.begin();
111 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
112 typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
114 /// RelatedRegClasses - This structure is built the first time a function is
115 /// compiled, and keeps track of which register classes have registers that
116 /// belong to multiple classes or have aliases that are in other classes.
117 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
118 DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
120 // NextReloadMap - For each register in the map, it maps to the another
121 // register which is defined by a reload from the same stack slot and
122 // both reloads are in the same basic block.
123 DenseMap<unsigned, unsigned> NextReloadMap;
125 // DowngradedRegs - A set of registers which are being "downgraded", i.e.
126 // un-favored for allocation.
127 SmallSet<unsigned, 8> DowngradedRegs;
129 // DowngradeMap - A map from virtual registers to physical registers being
130 // downgraded for the virtual registers.
131 DenseMap<unsigned, unsigned> DowngradeMap;
133 MachineFunction* mf_;
134 MachineRegisterInfo* mri_;
135 const TargetMachine* tm_;
136 const TargetRegisterInfo* tri_;
137 const TargetInstrInfo* tii_;
138 BitVector allocatableRegs_;
139 BitVector reservedRegs_;
142 MachineLoopInfo *loopInfo;
144 /// handled_ - Intervals are added to the handled_ set in the order of their
145 /// start value. This is uses for backtracking.
146 std::vector<LiveInterval*> handled_;
148 /// fixed_ - Intervals that correspond to machine registers.
152 /// active_ - Intervals that are currently being processed, and which have a
153 /// live range active for the current point.
154 IntervalPtrs active_;
156 /// inactive_ - Intervals that are currently being processed, but which have
157 /// a hold at the current point.
158 IntervalPtrs inactive_;
160 typedef std::priority_queue<LiveInterval*,
161 SmallVector<LiveInterval*, 64>,
162 greater_ptr<LiveInterval> > IntervalHeap;
163 IntervalHeap unhandled_;
165 /// regUse_ - Tracks register usage.
166 SmallVector<unsigned, 32> regUse_;
167 SmallVector<unsigned, 32> regUseBackUp_;
169 /// vrm_ - Tracks register assignments.
172 std::auto_ptr<VirtRegRewriter> rewriter_;
174 std::auto_ptr<Spiller> spiller_;
176 // The queue of recently-used registers.
177 SmallVector<unsigned, 4> RecentRegs;
178 SmallVector<unsigned, 4>::iterator RecentNext;
180 // Record that we just picked this register.
181 void recordRecentlyUsed(unsigned reg) {
182 assert(reg != 0 && "Recently used register is NOREG!");
183 if (!RecentRegs.empty()) {
185 if (RecentNext == RecentRegs.end())
186 RecentNext = RecentRegs.begin();
191 virtual const char* getPassName() const {
192 return "Linear Scan Register Allocator";
195 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
196 AU.setPreservesCFG();
197 AU.addRequired<LiveIntervals>();
198 AU.addPreserved<SlotIndexes>();
200 AU.addRequiredID(StrongPHIEliminationID);
201 // Make sure PassManager knows which analyses to make available
202 // to coalescing and which analyses coalescing invalidates.
203 AU.addRequiredTransitive<RegisterCoalescer>();
204 AU.addRequired<CalculateSpillWeights>();
205 if (PreSplitIntervals)
206 AU.addRequiredID(PreAllocSplittingID);
207 AU.addRequired<LiveStacks>();
208 AU.addPreserved<LiveStacks>();
209 AU.addRequired<MachineLoopInfo>();
210 AU.addPreserved<MachineLoopInfo>();
211 AU.addRequired<VirtRegMap>();
212 AU.addPreserved<VirtRegMap>();
213 AU.addPreservedID(MachineDominatorsID);
214 MachineFunctionPass::getAnalysisUsage(AU);
217 /// runOnMachineFunction - register allocate the whole function
218 bool runOnMachineFunction(MachineFunction&);
220 // Determine if we skip this register due to its being recently used.
221 bool isRecentlyUsed(unsigned reg) const {
222 return std::find(RecentRegs.begin(), RecentRegs.end(), reg) !=
227 /// linearScan - the linear scan algorithm
230 /// initIntervalSets - initialize the interval sets.
232 void initIntervalSets();
234 /// processActiveIntervals - expire old intervals and move non-overlapping
235 /// ones to the inactive list.
236 void processActiveIntervals(SlotIndex CurPoint);
238 /// processInactiveIntervals - expire old intervals and move overlapping
239 /// ones to the active list.
240 void processInactiveIntervals(SlotIndex CurPoint);
242 /// hasNextReloadInterval - Return the next liveinterval that's being
243 /// defined by a reload from the same SS as the specified one.
244 LiveInterval *hasNextReloadInterval(LiveInterval *cur);
246 /// DowngradeRegister - Downgrade a register for allocation.
247 void DowngradeRegister(LiveInterval *li, unsigned Reg);
249 /// UpgradeRegister - Upgrade a register for allocation.
250 void UpgradeRegister(unsigned Reg);
252 /// assignRegOrStackSlotAtInterval - assign a register if one
253 /// is available, or spill.
254 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
256 void updateSpillWeights(std::vector<float> &Weights,
257 unsigned reg, float weight,
258 const TargetRegisterClass *RC);
260 /// findIntervalsToSpill - Determine the intervals to spill for the
261 /// specified interval. It's passed the physical registers whose spill
262 /// weight is the lowest among all the registers whose live intervals
263 /// conflict with the interval.
264 void findIntervalsToSpill(LiveInterval *cur,
265 std::vector<std::pair<unsigned,float> > &Candidates,
267 SmallVector<LiveInterval*, 8> &SpillIntervals);
269 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
270 /// try to allocate the definition to the same register as the source,
271 /// if the register is not defined during the life time of the interval.
272 /// This eliminates a copy, and is used to coalesce copies which were not
273 /// coalesced away before allocation either due to dest and src being in
274 /// different register classes or because the coalescer was overly
276 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
279 /// Register usage / availability tracking helpers.
283 regUse_.resize(tri_->getNumRegs(), 0);
284 regUseBackUp_.resize(tri_->getNumRegs(), 0);
287 void finalizeRegUses() {
289 // Verify all the registers are "freed".
291 for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
292 if (regUse_[i] != 0) {
293 dbgs() << tri_->getName(i) << " is still in use!\n";
301 regUseBackUp_.clear();
304 void addRegUse(unsigned physReg) {
305 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
306 "should be physical register!");
308 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
312 void delRegUse(unsigned physReg) {
313 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
314 "should be physical register!");
315 assert(regUse_[physReg] != 0);
317 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
318 assert(regUse_[*as] != 0);
323 bool isRegAvail(unsigned physReg) const {
324 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
325 "should be physical register!");
326 return regUse_[physReg] == 0;
329 void backUpRegUses() {
330 regUseBackUp_ = regUse_;
333 void restoreRegUses() {
334 regUse_ = regUseBackUp_;
338 /// Register handling helpers.
341 /// getFreePhysReg - return a free physical register for this virtual
342 /// register interval if we have one, otherwise return 0.
343 unsigned getFreePhysReg(LiveInterval* cur);
344 unsigned getFreePhysReg(LiveInterval* cur,
345 const TargetRegisterClass *RC,
346 unsigned MaxInactiveCount,
347 SmallVector<unsigned, 256> &inactiveCounts,
350 /// getFirstNonReservedPhysReg - return the first non-reserved physical
351 /// register in the register class.
352 unsigned getFirstNonReservedPhysReg(const TargetRegisterClass *RC) {
353 TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_);
354 TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_);
355 while (i != aoe && reservedRegs_.test(*i))
357 assert(i != aoe && "All registers reserved?!");
361 void ComputeRelatedRegClasses();
363 template <typename ItTy>
364 void printIntervals(const char* const str, ItTy i, ItTy e) const {
367 dbgs() << str << " intervals:\n";
369 for (; i != e; ++i) {
370 dbgs() << "\t" << *i->first << " -> ";
372 unsigned reg = i->first->reg;
373 if (TargetRegisterInfo::isVirtualRegister(reg))
374 reg = vrm_->getPhys(reg);
376 dbgs() << tri_->getName(reg) << '\n';
381 char RALinScan::ID = 0;
384 INITIALIZE_PASS_BEGIN(RALinScan, "linearscan-regalloc",
385 "Linear Scan Register Allocator", false, false)
386 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
387 INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination)
388 INITIALIZE_PASS_DEPENDENCY(CalculateSpillWeights)
389 INITIALIZE_PASS_DEPENDENCY(PreAllocSplitting)
390 INITIALIZE_PASS_DEPENDENCY(LiveStacks)
391 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
392 INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
393 INITIALIZE_AG_DEPENDENCY(RegisterCoalescer)
394 INITIALIZE_PASS_END(RALinScan, "linearscan-regalloc",
395 "Linear Scan Register Allocator", false, false)
397 void RALinScan::ComputeRelatedRegClasses() {
398 // First pass, add all reg classes to the union, and determine at least one
399 // reg class that each register is in.
400 bool HasAliases = false;
401 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
402 E = tri_->regclass_end(); RCI != E; ++RCI) {
403 RelatedRegClasses.insert(*RCI);
404 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
406 HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
408 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
410 // Already processed this register. Just make sure we know that
411 // multiple register classes share a register.
412 RelatedRegClasses.unionSets(PRC, *RCI);
419 // Second pass, now that we know conservatively what register classes each reg
420 // belongs to, add info about aliases. We don't need to do this for targets
421 // without register aliases.
423 for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
424 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
426 for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
427 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
430 /// attemptTrivialCoalescing - If a simple interval is defined by a copy, try
431 /// allocate the definition the same register as the source register if the
432 /// register is not defined during live time of the interval. If the interval is
433 /// killed by a copy, try to use the destination register. This eliminates a
434 /// copy. This is used to coalesce copies which were not coalesced away before
435 /// allocation either due to dest and src being in different register classes or
436 /// because the coalescer was overly conservative.
437 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
438 unsigned Preference = vrm_->getRegAllocPref(cur.reg);
439 if ((Preference && Preference == Reg) || !cur.containsOneValue())
442 // We cannot handle complicated live ranges. Simple linear stuff only.
443 if (cur.ranges.size() != 1)
446 const LiveRange &range = cur.ranges.front();
448 VNInfo *vni = range.valno;
454 MachineInstr *CopyMI;
455 if ((CopyMI = li_->getInstructionFromIndex(vni->def)) && CopyMI->isCopy())
456 // Defined by a copy, try to extend SrcReg forward
457 CandReg = CopyMI->getOperand(1).getReg();
458 else if (TrivCoalesceEnds &&
459 (CopyMI = li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
460 CopyMI->isCopy() && cur.reg == CopyMI->getOperand(1).getReg())
461 // Only used by a copy, try to extend DstReg backwards
462 CandReg = CopyMI->getOperand(0).getReg();
467 if (TargetRegisterInfo::isVirtualRegister(CandReg)) {
468 if (!vrm_->isAssignedReg(CandReg))
470 CandReg = vrm_->getPhys(CandReg);
475 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
476 if (!RC->contains(CandReg))
479 if (li_->conflictsWithPhysReg(cur, *vrm_, CandReg))
483 DEBUG(dbgs() << "Coalescing: " << cur << " -> " << tri_->getName(CandReg)
485 vrm_->clearVirt(cur.reg);
486 vrm_->assignVirt2Phys(cur.reg, CandReg);
492 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
494 mri_ = &fn.getRegInfo();
495 tm_ = &fn.getTarget();
496 tri_ = tm_->getRegisterInfo();
497 tii_ = tm_->getInstrInfo();
498 allocatableRegs_ = tri_->getAllocatableSet(fn);
499 reservedRegs_ = tri_->getReservedRegs(fn);
500 li_ = &getAnalysis<LiveIntervals>();
501 ls_ = &getAnalysis<LiveStacks>();
502 loopInfo = &getAnalysis<MachineLoopInfo>();
504 // We don't run the coalescer here because we have no reason to
505 // interact with it. If the coalescer requires interaction, it
506 // won't do anything. If it doesn't require interaction, we assume
507 // it was run as a separate pass.
509 // If this is the first function compiled, compute the related reg classes.
510 if (RelatedRegClasses.empty())
511 ComputeRelatedRegClasses();
513 // Also resize register usage trackers.
516 vrm_ = &getAnalysis<VirtRegMap>();
517 if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
519 spiller_.reset(createSpiller(*this, *mf_, *vrm_));
525 // Rewrite spill code and update the PhysRegsUsed set.
526 rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
528 assert(unhandled_.empty() && "Unhandled live intervals remain!");
536 NextReloadMap.clear();
537 DowngradedRegs.clear();
538 DowngradeMap.clear();
544 /// initIntervalSets - initialize the interval sets.
546 void RALinScan::initIntervalSets()
548 assert(unhandled_.empty() && fixed_.empty() &&
549 active_.empty() && inactive_.empty() &&
550 "interval sets should be empty on initialization");
552 handled_.reserve(li_->getNumIntervals());
554 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
555 if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
556 if (!i->second->empty()) {
557 mri_->setPhysRegUsed(i->second->reg);
558 fixed_.push_back(std::make_pair(i->second, i->second->begin()));
561 if (i->second->empty()) {
562 assignRegOrStackSlotAtInterval(i->second);
565 unhandled_.push(i->second);
570 void RALinScan::linearScan() {
571 // linear scan algorithm
573 dbgs() << "********** LINEAR SCAN **********\n"
574 << "********** Function: "
575 << mf_->getFunction()->getName() << '\n';
576 printIntervals("fixed", fixed_.begin(), fixed_.end());
579 while (!unhandled_.empty()) {
580 // pick the interval with the earliest start point
581 LiveInterval* cur = unhandled_.top();
584 DEBUG(dbgs() << "\n*** CURRENT ***: " << *cur << '\n');
586 assert(!cur->empty() && "Empty interval in unhandled set.");
588 processActiveIntervals(cur->beginIndex());
589 processInactiveIntervals(cur->beginIndex());
591 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
592 "Can only allocate virtual registers!");
594 // Allocating a virtual register. try to find a free
595 // physical register or spill an interval (possibly this one) in order to
597 assignRegOrStackSlotAtInterval(cur);
600 printIntervals("active", active_.begin(), active_.end());
601 printIntervals("inactive", inactive_.begin(), inactive_.end());
605 // Expire any remaining active intervals
606 while (!active_.empty()) {
607 IntervalPtr &IP = active_.back();
608 unsigned reg = IP.first->reg;
609 DEBUG(dbgs() << "\tinterval " << *IP.first << " expired\n");
610 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
611 "Can only allocate virtual registers!");
612 reg = vrm_->getPhys(reg);
617 // Expire any remaining inactive intervals
619 for (IntervalPtrs::reverse_iterator
620 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
621 dbgs() << "\tinterval " << *i->first << " expired\n";
625 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
626 MachineFunction::iterator EntryMBB = mf_->begin();
627 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
628 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
629 LiveInterval &cur = *i->second;
631 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
634 else if (vrm_->isAssignedReg(cur.reg))
635 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
638 // Ignore splited live intervals.
639 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
642 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
644 const LiveRange &LR = *I;
645 if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
646 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
647 if (LiveInMBBs[i] != EntryMBB) {
648 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
649 "Adding a virtual register to livein set?");
650 LiveInMBBs[i]->addLiveIn(Reg);
657 DEBUG(dbgs() << *vrm_);
659 // Look for physical registers that end up not being allocated even though
660 // register allocator had to spill other registers in its register class.
661 if (ls_->getNumIntervals() == 0)
663 if (!vrm_->FindUnusedRegisters(li_))
667 /// processActiveIntervals - expire old intervals and move non-overlapping ones
668 /// to the inactive list.
669 void RALinScan::processActiveIntervals(SlotIndex CurPoint)
671 DEBUG(dbgs() << "\tprocessing active intervals:\n");
673 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
674 LiveInterval *Interval = active_[i].first;
675 LiveInterval::iterator IntervalPos = active_[i].second;
676 unsigned reg = Interval->reg;
678 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
680 if (IntervalPos == Interval->end()) { // Remove expired intervals.
681 DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
682 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
683 "Can only allocate virtual registers!");
684 reg = vrm_->getPhys(reg);
687 // Pop off the end of the list.
688 active_[i] = active_.back();
692 } else if (IntervalPos->start > CurPoint) {
693 // Move inactive intervals to inactive list.
694 DEBUG(dbgs() << "\t\tinterval " << *Interval << " inactive\n");
695 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
696 "Can only allocate virtual registers!");
697 reg = vrm_->getPhys(reg);
700 inactive_.push_back(std::make_pair(Interval, IntervalPos));
702 // Pop off the end of the list.
703 active_[i] = active_.back();
707 // Otherwise, just update the iterator position.
708 active_[i].second = IntervalPos;
713 /// processInactiveIntervals - expire old intervals and move overlapping
714 /// ones to the active list.
715 void RALinScan::processInactiveIntervals(SlotIndex CurPoint)
717 DEBUG(dbgs() << "\tprocessing inactive intervals:\n");
719 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
720 LiveInterval *Interval = inactive_[i].first;
721 LiveInterval::iterator IntervalPos = inactive_[i].second;
722 unsigned reg = Interval->reg;
724 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
726 if (IntervalPos == Interval->end()) { // remove expired intervals.
727 DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
729 // Pop off the end of the list.
730 inactive_[i] = inactive_.back();
731 inactive_.pop_back();
733 } else if (IntervalPos->start <= CurPoint) {
734 // move re-activated intervals in active list
735 DEBUG(dbgs() << "\t\tinterval " << *Interval << " active\n");
736 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
737 "Can only allocate virtual registers!");
738 reg = vrm_->getPhys(reg);
741 active_.push_back(std::make_pair(Interval, IntervalPos));
743 // Pop off the end of the list.
744 inactive_[i] = inactive_.back();
745 inactive_.pop_back();
748 // Otherwise, just update the iterator position.
749 inactive_[i].second = IntervalPos;
754 /// updateSpillWeights - updates the spill weights of the specifed physical
755 /// register and its weight.
756 void RALinScan::updateSpillWeights(std::vector<float> &Weights,
757 unsigned reg, float weight,
758 const TargetRegisterClass *RC) {
759 SmallSet<unsigned, 4> Processed;
760 SmallSet<unsigned, 4> SuperAdded;
761 SmallVector<unsigned, 4> Supers;
762 Weights[reg] += weight;
763 Processed.insert(reg);
764 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
765 Weights[*as] += weight;
766 Processed.insert(*as);
767 if (tri_->isSubRegister(*as, reg) &&
768 SuperAdded.insert(*as) &&
770 Supers.push_back(*as);
774 // If the alias is a super-register, and the super-register is in the
775 // register class we are trying to allocate. Then add the weight to all
776 // sub-registers of the super-register even if they are not aliases.
777 // e.g. allocating for GR32, bh is not used, updating bl spill weight.
778 // bl should get the same spill weight otherwise it will be choosen
779 // as a spill candidate since spilling bh doesn't make ebx available.
780 for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
781 for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
782 if (!Processed.count(*sr))
783 Weights[*sr] += weight;
788 RALinScan::IntervalPtrs::iterator
789 FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
790 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
792 if (I->first == LI) return I;
796 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V,
798 for (unsigned i = 0, e = V.size(); i != e; ++i) {
799 RALinScan::IntervalPtr &IP = V[i];
800 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
802 if (I != IP.first->begin()) --I;
807 /// addStackInterval - Create a LiveInterval for stack if the specified live
808 /// interval has been spilled.
809 static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
811 MachineRegisterInfo* mri_, VirtRegMap &vrm_) {
812 int SS = vrm_.getStackSlot(cur->reg);
813 if (SS == VirtRegMap::NO_STACK_SLOT)
816 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
817 LiveInterval &SI = ls_->getOrCreateInterval(SS, RC);
820 if (SI.hasAtLeastOneValue())
821 VNI = SI.getValNumInfo(0);
823 VNI = SI.getNextValue(SlotIndex(), 0,
824 ls_->getVNInfoAllocator());
826 LiveInterval &RI = li_->getInterval(cur->reg);
827 // FIXME: This may be overly conservative.
828 SI.MergeRangesInAsValue(RI, VNI);
831 /// getConflictWeight - Return the number of conflicts between cur
832 /// live interval and defs and uses of Reg weighted by loop depthes.
834 float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
835 MachineRegisterInfo *mri_,
836 MachineLoopInfo *loopInfo) {
838 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
839 E = mri_->reg_end(); I != E; ++I) {
840 MachineInstr *MI = &*I;
841 if (cur->liveAt(li_->getInstructionIndex(MI))) {
842 unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
843 Conflicts += std::pow(10.0f, (float)loopDepth);
849 /// findIntervalsToSpill - Determine the intervals to spill for the
850 /// specified interval. It's passed the physical registers whose spill
851 /// weight is the lowest among all the registers whose live intervals
852 /// conflict with the interval.
853 void RALinScan::findIntervalsToSpill(LiveInterval *cur,
854 std::vector<std::pair<unsigned,float> > &Candidates,
856 SmallVector<LiveInterval*, 8> &SpillIntervals) {
857 // We have figured out the *best* register to spill. But there are other
858 // registers that are pretty good as well (spill weight within 3%). Spill
859 // the one that has fewest defs and uses that conflict with cur.
860 float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
861 SmallVector<LiveInterval*, 8> SLIs[3];
864 dbgs() << "\tConsidering " << NumCands << " candidates: ";
865 for (unsigned i = 0; i != NumCands; ++i)
866 dbgs() << tri_->getName(Candidates[i].first) << " ";
870 // Calculate the number of conflicts of each candidate.
871 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
872 unsigned Reg = i->first->reg;
873 unsigned PhysReg = vrm_->getPhys(Reg);
874 if (!cur->overlapsFrom(*i->first, i->second))
876 for (unsigned j = 0; j < NumCands; ++j) {
877 unsigned Candidate = Candidates[j].first;
878 if (tri_->regsOverlap(PhysReg, Candidate)) {
880 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
881 SLIs[j].push_back(i->first);
886 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
887 unsigned Reg = i->first->reg;
888 unsigned PhysReg = vrm_->getPhys(Reg);
889 if (!cur->overlapsFrom(*i->first, i->second-1))
891 for (unsigned j = 0; j < NumCands; ++j) {
892 unsigned Candidate = Candidates[j].first;
893 if (tri_->regsOverlap(PhysReg, Candidate)) {
895 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
896 SLIs[j].push_back(i->first);
901 // Which is the best candidate?
902 unsigned BestCandidate = 0;
903 float MinConflicts = Conflicts[0];
904 for (unsigned i = 1; i != NumCands; ++i) {
905 if (Conflicts[i] < MinConflicts) {
907 MinConflicts = Conflicts[i];
911 std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
912 std::back_inserter(SpillIntervals));
916 struct WeightCompare {
918 const RALinScan &Allocator;
921 WeightCompare(const RALinScan &Alloc) : Allocator(Alloc) {}
923 typedef std::pair<unsigned, float> RegWeightPair;
924 bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
925 return LHS.second < RHS.second && !Allocator.isRecentlyUsed(LHS.first);
930 static bool weightsAreClose(float w1, float w2) {
934 float diff = w1 - w2;
935 if (diff <= 0.02f) // Within 0.02f
937 return (diff / w2) <= 0.05f; // Within 5%.
940 LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
941 DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
942 if (I == NextReloadMap.end())
944 return &li_->getInterval(I->second);
947 void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
948 bool isNew = DowngradedRegs.insert(Reg);
949 isNew = isNew; // Silence compiler warning.
950 assert(isNew && "Multiple reloads holding the same register?");
951 DowngradeMap.insert(std::make_pair(li->reg, Reg));
952 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS) {
953 isNew = DowngradedRegs.insert(*AS);
954 isNew = isNew; // Silence compiler warning.
955 assert(isNew && "Multiple reloads holding the same register?");
956 DowngradeMap.insert(std::make_pair(li->reg, *AS));
961 void RALinScan::UpgradeRegister(unsigned Reg) {
963 DowngradedRegs.erase(Reg);
964 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
965 DowngradedRegs.erase(*AS);
971 bool operator()(LiveInterval* A, LiveInterval* B) {
972 return A->beginIndex() < B->beginIndex();
977 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
979 void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
980 DEBUG(dbgs() << "\tallocating current interval: ");
982 // This is an implicitly defined live interval, just assign any register.
983 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
985 unsigned physReg = vrm_->getRegAllocPref(cur->reg);
987 physReg = getFirstNonReservedPhysReg(RC);
988 DEBUG(dbgs() << tri_->getName(physReg) << '\n');
989 // Note the register is not really in use.
990 vrm_->assignVirt2Phys(cur->reg, physReg);
996 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
997 SlotIndex StartPosition = cur->beginIndex();
998 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1000 // If start of this live interval is defined by a move instruction and its
1001 // source is assigned a physical register that is compatible with the target
1002 // register class, then we should try to assign it the same register.
1003 // This can happen when the move is from a larger register class to a smaller
1004 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
1005 if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
1006 VNInfo *vni = cur->begin()->valno;
1007 if (!vni->isUnused()) {
1008 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
1009 if (CopyMI && CopyMI->isCopy()) {
1010 unsigned DstSubReg = CopyMI->getOperand(0).getSubReg();
1011 unsigned SrcReg = CopyMI->getOperand(1).getReg();
1012 unsigned SrcSubReg = CopyMI->getOperand(1).getSubReg();
1014 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
1016 else if (vrm_->isAssignedReg(SrcReg))
1017 Reg = vrm_->getPhys(SrcReg);
1020 Reg = tri_->getSubReg(Reg, SrcSubReg);
1022 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
1023 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
1024 mri_->setRegAllocationHint(cur->reg, 0, Reg);
1030 // For every interval in inactive we overlap with, mark the
1031 // register as not free and update spill weights.
1032 for (IntervalPtrs::const_iterator i = inactive_.begin(),
1033 e = inactive_.end(); i != e; ++i) {
1034 unsigned Reg = i->first->reg;
1035 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
1036 "Can only allocate virtual registers!");
1037 const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
1038 // If this is not in a related reg class to the register we're allocating,
1040 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1041 cur->overlapsFrom(*i->first, i->second-1)) {
1042 Reg = vrm_->getPhys(Reg);
1044 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
1048 // Speculatively check to see if we can get a register right now. If not,
1049 // we know we won't be able to by adding more constraints. If so, we can
1050 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
1051 // is very bad (it contains all callee clobbered registers for any functions
1052 // with a call), so we want to avoid doing that if possible.
1053 unsigned physReg = getFreePhysReg(cur);
1054 unsigned BestPhysReg = physReg;
1056 // We got a register. However, if it's in the fixed_ list, we might
1057 // conflict with it. Check to see if we conflict with it or any of its
1059 SmallSet<unsigned, 8> RegAliases;
1060 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
1061 RegAliases.insert(*AS);
1063 bool ConflictsWithFixed = false;
1064 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1065 IntervalPtr &IP = fixed_[i];
1066 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
1067 // Okay, this reg is on the fixed list. Check to see if we actually
1069 LiveInterval *I = IP.first;
1070 if (I->endIndex() > StartPosition) {
1071 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1073 if (II != I->begin() && II->start > StartPosition)
1075 if (cur->overlapsFrom(*I, II)) {
1076 ConflictsWithFixed = true;
1083 // Okay, the register picked by our speculative getFreePhysReg call turned
1084 // out to be in use. Actually add all of the conflicting fixed registers to
1085 // regUse_ so we can do an accurate query.
1086 if (ConflictsWithFixed) {
1087 // For every interval in fixed we overlap with, mark the register as not
1088 // free and update spill weights.
1089 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1090 IntervalPtr &IP = fixed_[i];
1091 LiveInterval *I = IP.first;
1093 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
1094 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1095 I->endIndex() > StartPosition) {
1096 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1098 if (II != I->begin() && II->start > StartPosition)
1100 if (cur->overlapsFrom(*I, II)) {
1101 unsigned reg = I->reg;
1103 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
1108 // Using the newly updated regUse_ object, which includes conflicts in the
1109 // future, see if there are any registers available.
1110 physReg = getFreePhysReg(cur);
1114 // Restore the physical register tracker, removing information about the
1118 // If we find a free register, we are done: assign this virtual to
1119 // the free physical register and add this interval to the active
1122 DEBUG(dbgs() << tri_->getName(physReg) << '\n');
1123 vrm_->assignVirt2Phys(cur->reg, physReg);
1125 active_.push_back(std::make_pair(cur, cur->begin()));
1126 handled_.push_back(cur);
1128 // "Upgrade" the physical register since it has been allocated.
1129 UpgradeRegister(physReg);
1130 if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
1131 // "Downgrade" physReg to try to keep physReg from being allocated until
1132 // the next reload from the same SS is allocated.
1133 mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg);
1134 DowngradeRegister(cur, physReg);
1138 DEBUG(dbgs() << "no free registers\n");
1140 // Compile the spill weights into an array that is better for scanning.
1141 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
1142 for (std::vector<std::pair<unsigned, float> >::iterator
1143 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
1144 updateSpillWeights(SpillWeights, I->first, I->second, RC);
1146 // for each interval in active, update spill weights.
1147 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
1149 unsigned reg = i->first->reg;
1150 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1151 "Can only allocate virtual registers!");
1152 reg = vrm_->getPhys(reg);
1153 updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
1156 DEBUG(dbgs() << "\tassigning stack slot at interval "<< *cur << ":\n");
1158 // Find a register to spill.
1159 float minWeight = HUGE_VALF;
1160 unsigned minReg = 0;
1163 std::vector<std::pair<unsigned,float> > RegsWeights;
1164 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
1165 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1166 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1168 float regWeight = SpillWeights[reg];
1169 // Don't even consider reserved regs.
1170 if (reservedRegs_.test(reg))
1172 // Skip recently allocated registers and reserved registers.
1173 if (minWeight > regWeight && !isRecentlyUsed(reg))
1175 RegsWeights.push_back(std::make_pair(reg, regWeight));
1178 // If we didn't find a register that is spillable, try aliases?
1180 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1181 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1183 if (reservedRegs_.test(reg))
1185 // No need to worry about if the alias register size < regsize of RC.
1186 // We are going to spill all registers that alias it anyway.
1187 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
1188 RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
1192 // Sort all potential spill candidates by weight.
1193 std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare(*this));
1194 minReg = RegsWeights[0].first;
1195 minWeight = RegsWeights[0].second;
1196 if (minWeight == HUGE_VALF) {
1197 // All registers must have inf weight. Just grab one!
1198 minReg = BestPhysReg ? BestPhysReg : getFirstNonReservedPhysReg(RC);
1199 if (cur->weight == HUGE_VALF ||
1200 li_->getApproximateInstructionCount(*cur) == 0) {
1201 // Spill a physical register around defs and uses.
1202 if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
1203 // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
1204 // in fixed_. Reset them.
1205 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1206 IntervalPtr &IP = fixed_[i];
1207 LiveInterval *I = IP.first;
1208 if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
1209 IP.second = I->advanceTo(I->begin(), StartPosition);
1212 DowngradedRegs.clear();
1213 assignRegOrStackSlotAtInterval(cur);
1215 assert(false && "Ran out of registers during register allocation!");
1216 report_fatal_error("Ran out of registers during register allocation!");
1222 // Find up to 3 registers to consider as spill candidates.
1223 unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
1224 while (LastCandidate > 1) {
1225 if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
1231 dbgs() << "\t\tregister(s) with min weight(s): ";
1233 for (unsigned i = 0; i != LastCandidate; ++i)
1234 dbgs() << tri_->getName(RegsWeights[i].first)
1235 << " (" << RegsWeights[i].second << ")\n";
1238 // If the current has the minimum weight, we need to spill it and
1239 // add any added intervals back to unhandled, and restart
1241 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
1242 DEBUG(dbgs() << "\t\t\tspilling(c): " << *cur << '\n');
1243 SmallVector<LiveInterval*, 8> spillIs, added;
1244 spiller_->spill(cur, added, spillIs);
1246 std::sort(added.begin(), added.end(), LISorter());
1247 addStackInterval(cur, ls_, li_, mri_, *vrm_);
1249 return; // Early exit if all spills were folded.
1251 // Merge added with unhandled. Note that we have already sorted
1252 // intervals returned by addIntervalsForSpills by their starting
1254 // This also update the NextReloadMap. That is, it adds mapping from a
1255 // register defined by a reload from SS to the next reload from SS in the
1256 // same basic block.
1257 MachineBasicBlock *LastReloadMBB = 0;
1258 LiveInterval *LastReload = 0;
1259 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1260 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1261 LiveInterval *ReloadLi = added[i];
1262 if (ReloadLi->weight == HUGE_VALF &&
1263 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1264 SlotIndex ReloadIdx = ReloadLi->beginIndex();
1265 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1266 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1267 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1268 // Last reload of same SS is in the same MBB. We want to try to
1269 // allocate both reloads the same register and make sure the reg
1270 // isn't clobbered in between if at all possible.
1271 assert(LastReload->beginIndex() < ReloadIdx);
1272 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1274 LastReloadMBB = ReloadMBB;
1275 LastReload = ReloadLi;
1276 LastReloadSS = ReloadSS;
1278 unhandled_.push(ReloadLi);
1285 // Push the current interval back to unhandled since we are going
1286 // to re-run at least this iteration. Since we didn't modify it it
1287 // should go back right in the front of the list
1288 unhandled_.push(cur);
1290 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
1291 "did not choose a register to spill?");
1293 // We spill all intervals aliasing the register with
1294 // minimum weight, rollback to the interval with the earliest
1295 // start point and let the linear scan algorithm run again
1296 SmallVector<LiveInterval*, 8> spillIs;
1298 // Determine which intervals have to be spilled.
1299 findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
1301 // Set of spilled vregs (used later to rollback properly)
1302 SmallSet<unsigned, 8> spilled;
1304 // The earliest start of a Spilled interval indicates up to where
1305 // in handled we need to roll back
1306 assert(!spillIs.empty() && "No spill intervals?");
1307 SlotIndex earliestStart = spillIs[0]->beginIndex();
1309 // Spill live intervals of virtual regs mapped to the physical register we
1310 // want to clear (and its aliases). We only spill those that overlap with the
1311 // current interval as the rest do not affect its allocation. we also keep
1312 // track of the earliest start of all spilled live intervals since this will
1313 // mark our rollback point.
1314 SmallVector<LiveInterval*, 8> added;
1315 while (!spillIs.empty()) {
1316 LiveInterval *sli = spillIs.back();
1318 DEBUG(dbgs() << "\t\t\tspilling(a): " << *sli << '\n');
1319 if (sli->beginIndex() < earliestStart)
1320 earliestStart = sli->beginIndex();
1321 spiller_->spill(sli, added, spillIs);
1322 addStackInterval(sli, ls_, li_, mri_, *vrm_);
1323 spilled.insert(sli->reg);
1326 // Include any added intervals in earliestStart.
1327 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1328 SlotIndex SI = added[i]->beginIndex();
1329 if (SI < earliestStart)
1333 DEBUG(dbgs() << "\t\trolling back to: " << earliestStart << '\n');
1335 // Scan handled in reverse order up to the earliest start of a
1336 // spilled live interval and undo each one, restoring the state of
1338 while (!handled_.empty()) {
1339 LiveInterval* i = handled_.back();
1340 // If this interval starts before t we are done.
1341 if (!i->empty() && i->beginIndex() < earliestStart)
1343 DEBUG(dbgs() << "\t\t\tundo changes for: " << *i << '\n');
1344 handled_.pop_back();
1346 // When undoing a live interval allocation we must know if it is active or
1347 // inactive to properly update regUse_ and the VirtRegMap.
1348 IntervalPtrs::iterator it;
1349 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
1351 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1352 if (!spilled.count(i->reg))
1354 delRegUse(vrm_->getPhys(i->reg));
1355 vrm_->clearVirt(i->reg);
1356 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
1357 inactive_.erase(it);
1358 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1359 if (!spilled.count(i->reg))
1361 vrm_->clearVirt(i->reg);
1363 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
1364 "Can only allocate virtual registers!");
1365 vrm_->clearVirt(i->reg);
1369 DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
1370 if (ii == DowngradeMap.end())
1371 // It interval has a preference, it must be defined by a copy. Clear the
1372 // preference now since the source interval allocation may have been
1374 mri_->setRegAllocationHint(i->reg, 0, 0);
1376 UpgradeRegister(ii->second);
1380 // Rewind the iterators in the active, inactive, and fixed lists back to the
1381 // point we reverted to.
1382 RevertVectorIteratorsTo(active_, earliestStart);
1383 RevertVectorIteratorsTo(inactive_, earliestStart);
1384 RevertVectorIteratorsTo(fixed_, earliestStart);
1386 // Scan the rest and undo each interval that expired after t and
1387 // insert it in active (the next iteration of the algorithm will
1388 // put it in inactive if required)
1389 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
1390 LiveInterval *HI = handled_[i];
1391 if (!HI->expiredAt(earliestStart) &&
1392 HI->expiredAt(cur->beginIndex())) {
1393 DEBUG(dbgs() << "\t\t\tundo changes for: " << *HI << '\n');
1394 active_.push_back(std::make_pair(HI, HI->begin()));
1395 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
1396 addRegUse(vrm_->getPhys(HI->reg));
1400 // Merge added with unhandled.
1401 // This also update the NextReloadMap. That is, it adds mapping from a
1402 // register defined by a reload from SS to the next reload from SS in the
1403 // same basic block.
1404 MachineBasicBlock *LastReloadMBB = 0;
1405 LiveInterval *LastReload = 0;
1406 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1407 std::sort(added.begin(), added.end(), LISorter());
1408 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1409 LiveInterval *ReloadLi = added[i];
1410 if (ReloadLi->weight == HUGE_VALF &&
1411 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1412 SlotIndex ReloadIdx = ReloadLi->beginIndex();
1413 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1414 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1415 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1416 // Last reload of same SS is in the same MBB. We want to try to
1417 // allocate both reloads the same register and make sure the reg
1418 // isn't clobbered in between if at all possible.
1419 assert(LastReload->beginIndex() < ReloadIdx);
1420 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1422 LastReloadMBB = ReloadMBB;
1423 LastReload = ReloadLi;
1424 LastReloadSS = ReloadSS;
1426 unhandled_.push(ReloadLi);
1430 unsigned RALinScan::getFreePhysReg(LiveInterval* cur,
1431 const TargetRegisterClass *RC,
1432 unsigned MaxInactiveCount,
1433 SmallVector<unsigned, 256> &inactiveCounts,
1435 unsigned FreeReg = 0;
1436 unsigned FreeRegInactiveCount = 0;
1438 std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(cur->reg);
1439 // Resolve second part of the hint (if possible) given the current allocation.
1440 unsigned physReg = Hint.second;
1442 TargetRegisterInfo::isVirtualRegister(physReg) && vrm_->hasPhys(physReg))
1443 physReg = vrm_->getPhys(physReg);
1445 TargetRegisterClass::iterator I, E;
1446 tie(I, E) = tri_->getAllocationOrder(RC, Hint.first, physReg, *mf_);
1447 assert(I != E && "No allocatable register in this register class!");
1449 // Scan for the first available register.
1450 for (; I != E; ++I) {
1452 // Ignore "downgraded" registers.
1453 if (SkipDGRegs && DowngradedRegs.count(Reg))
1455 // Skip reserved registers.
1456 if (reservedRegs_.test(Reg))
1458 // Skip recently allocated registers.
1459 if (isRegAvail(Reg) && !isRecentlyUsed(Reg)) {
1461 if (FreeReg < inactiveCounts.size())
1462 FreeRegInactiveCount = inactiveCounts[FreeReg];
1464 FreeRegInactiveCount = 0;
1469 // If there are no free regs, or if this reg has the max inactive count,
1470 // return this register.
1471 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount) {
1472 // Remember what register we picked so we can skip it next time.
1473 if (FreeReg != 0) recordRecentlyUsed(FreeReg);
1477 // Continue scanning the registers, looking for the one with the highest
1478 // inactive count. Alkis found that this reduced register pressure very
1479 // slightly on X86 (in rev 1.94 of this file), though this should probably be
1481 for (; I != E; ++I) {
1483 // Ignore "downgraded" registers.
1484 if (SkipDGRegs && DowngradedRegs.count(Reg))
1486 // Skip reserved registers.
1487 if (reservedRegs_.test(Reg))
1489 if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
1490 FreeRegInactiveCount < inactiveCounts[Reg] && !isRecentlyUsed(Reg)) {
1492 FreeRegInactiveCount = inactiveCounts[Reg];
1493 if (FreeRegInactiveCount == MaxInactiveCount)
1494 break; // We found the one with the max inactive count.
1498 // Remember what register we picked so we can skip it next time.
1499 recordRecentlyUsed(FreeReg);
1504 /// getFreePhysReg - return a free physical register for this virtual register
1505 /// interval if we have one, otherwise return 0.
1506 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
1507 SmallVector<unsigned, 256> inactiveCounts;
1508 unsigned MaxInactiveCount = 0;
1510 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
1511 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1513 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
1515 unsigned reg = i->first->reg;
1516 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1517 "Can only allocate virtual registers!");
1519 // If this is not in a related reg class to the register we're allocating,
1521 const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
1522 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
1523 reg = vrm_->getPhys(reg);
1524 if (inactiveCounts.size() <= reg)
1525 inactiveCounts.resize(reg+1);
1526 ++inactiveCounts[reg];
1527 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
1531 // If copy coalescer has assigned a "preferred" register, check if it's
1533 unsigned Preference = vrm_->getRegAllocPref(cur->reg);
1535 DEBUG(dbgs() << "(preferred: " << tri_->getName(Preference) << ") ");
1536 if (isRegAvail(Preference) &&
1537 RC->contains(Preference))
1541 if (!DowngradedRegs.empty()) {
1542 unsigned FreeReg = getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts,
1547 return getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts, false);
1550 FunctionPass* llvm::createLinearScanRegisterAllocator() {
1551 return new RALinScan();