1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
13 #define DEBUG_TYPE "regalloc"
14 #include "llvm/Function.h"
15 #include "llvm/CodeGen/LiveIntervals.h"
16 #include "llvm/CodeGen/LiveVariables.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/Target/MRegisterInfo.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Support/CFG.h"
26 #include "Support/Debug.h"
27 #include "Support/DepthFirstIterator.h"
28 #include "Support/Statistic.h"
29 #include "Support/STLExtras.h"
33 Statistic<> numSpilled ("ra-linearscan", "Number of registers spilled");
34 Statistic<> numReloaded("ra-linearscan", "Number of registers reloaded");
36 class RA : public MachineFunctionPass {
38 typedef std::vector<const LiveIntervals::Interval*> IntervalPtrs;
42 const TargetMachine* tm_;
43 const MRegisterInfo* mri_;
44 MachineBasicBlock* currentMbb_;
45 MachineBasicBlock::iterator currentInstr_;
46 typedef LiveIntervals::Intervals Intervals;
48 IntervalPtrs active_, inactive_;
50 typedef std::vector<unsigned> Regs;
51 Regs tempUseOperands_;
52 Regs tempDefOperands_;
54 typedef std::vector<bool> RegMask;
57 unsigned regUse_[MRegisterInfo::FirstVirtualRegister];
58 unsigned regUseBackup_[MRegisterInfo::FirstVirtualRegister];
60 typedef LiveIntervals::MachineBasicBlockPtrs MachineBasicBlockPtrs;
61 MachineBasicBlockPtrs mbbs_;
63 typedef std::map<unsigned, unsigned> Virt2PhysMap;
66 typedef std::map<unsigned, int> Virt2StackSlotMap;
67 Virt2StackSlotMap v2ssMap_;
72 virtual const char* getPassName() const {
73 return "Linear Scan Register Allocator";
76 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
77 AU.addRequired<LiveVariables>();
78 AU.addRequired<LiveIntervals>();
79 MachineFunctionPass::getAnalysisUsage(AU);
83 /// runOnMachineFunction - register allocate the whole function
84 bool runOnMachineFunction(MachineFunction&);
86 /// verifyIntervals - verify that we have no inconsistencies
87 /// in the register assignments we have in active and inactive
89 bool verifyIntervals();
91 /// processActiveIntervals - expire old intervals and move
92 /// non-overlapping ones to the incative list
93 void processActiveIntervals(Intervals::const_iterator cur);
95 /// processInactiveIntervals - expire old intervals and move
96 /// overlapping ones to the active list
97 void processInactiveIntervals(Intervals::const_iterator cur);
99 /// assignStackSlotAtInterval - choose and spill
100 /// interval. Currently we spill the interval with the last
101 /// end point in the active and inactive lists and the current
103 void assignStackSlotAtInterval(Intervals::const_iterator cur);
106 /// register handling helpers
109 /// getFreePhysReg - return a free physical register for this
110 /// virtual register interval if we have one, otherwise return
112 unsigned getFreePhysReg(Intervals::const_iterator cur);
114 /// physRegAvailable - returns true if the specifed physical
115 /// register is available
116 bool physRegAvailable(unsigned physReg);
118 /// tempPhysRegAvailable - returns true if the specifed
119 /// temporary physical register is available
120 bool tempPhysRegAvailable(unsigned physReg);
122 /// getFreeTempPhysReg - return a free temprorary physical
123 /// register for this virtual register if we have one (should
125 unsigned getFreeTempPhysReg(unsigned virtReg);
127 /// assignVirt2PhysReg - assigns the free physical register to
128 /// the virtual register passed as arguments
129 void assignVirt2PhysReg(unsigned virtReg, unsigned physReg);
131 /// clearVirtReg - free the physical register associated with this
132 /// virtual register and disassociate virtual->physical and
133 /// physical->virtual mappings
134 void clearVirtReg(unsigned virtReg);
136 /// assignVirt2StackSlot - assigns this virtual register to a
138 void assignVirt2StackSlot(unsigned virtReg);
140 /// getStackSlot - returns the offset of the specified
141 /// register on the stack
142 int getStackSlot(unsigned virtReg);
144 /// spillVirtReg - spills the virtual register
145 void spillVirtReg(unsigned virtReg);
147 /// loadPhysReg - loads to the physical register the value of
148 /// the virtual register specifed. Virtual register must have
149 /// an assigned stack slot
150 void loadVirt2PhysReg(unsigned virtReg, unsigned physReg);
152 void markPhysRegFree(unsigned physReg);
153 void markPhysRegNotFree(unsigned physReg);
155 void backupRegUse() {
156 memcpy(regUseBackup_, regUse_, sizeof(regUseBackup_));
159 void restoreRegUse() {
160 memcpy(regUse_, regUseBackup_, sizeof(regUseBackup_));
163 void printVirt2PhysMap() const {
164 std::cerr << "allocated registers:\n";
165 for (Virt2PhysMap::const_iterator
166 i = v2pMap_.begin(), e = v2pMap_.end(); i != e; ++i) {
167 std::cerr << '[' << i->first << ','
168 << mri_->getName(i->second) << "]\n";
172 void printIntervals(const char* const str,
173 RA::IntervalPtrs::const_iterator i,
174 RA::IntervalPtrs::const_iterator e) const {
175 if (str) std::cerr << str << " intervals:\n";
176 for (; i != e; ++i) {
177 std::cerr << "\t\t" << **i << " -> ";
178 if ((*i)->reg < MRegisterInfo::FirstVirtualRegister) {
179 std::cerr << mri_->getName((*i)->reg);
182 std::cerr << mri_->getName(v2pMap_.find((*i)->reg)->second);
187 void printFreeRegs(const char* const str,
188 const TargetRegisterClass* rc) const {
189 if (str) std::cerr << str << ':';
190 for (TargetRegisterClass::iterator i =
191 rc->allocation_order_begin(*mf_);
192 i != rc->allocation_order_end(*mf_); ++i) {
195 std::cerr << ' ' << mri_->getName(reg);
196 if (reserved_[reg]) std::cerr << "*";
204 bool RA::runOnMachineFunction(MachineFunction &fn) {
206 tm_ = &fn.getTarget();
207 mri_ = tm_->getRegisterInfo();
208 li_ = &getAnalysis<LiveIntervals>().getIntervals();
212 mbbs_ = getAnalysis<LiveIntervals>().getOrderedMachineBasicBlockPtrs();
215 memset(regUse_, 0, sizeof(regUse_));
216 memset(regUseBackup_, 0, sizeof(regUseBackup_));
220 for (MachineBasicBlockPtrs::iterator
221 mbbi = mbbs_.begin(), mbbe = mbbs_.end();
222 mbbi != mbbe; ++mbbi) {
223 MachineBasicBlock* mbb = *mbbi;
224 std::cerr << mbb->getBasicBlock()->getName() << '\n';
225 for (MachineBasicBlock::iterator
226 ii = mbb->begin(), ie = mbb->end();
228 MachineInstr* instr = *ii;
230 std::cerr << i++ << "\t";
231 instr->print(std::cerr, *tm_);
236 // FIXME: this will work only for the X86 backend. I need to
237 // device an algorthm to select the minimal (considering register
238 // aliasing) number of temp registers to reserve so that we have 2
239 // registers for each register class available.
241 // reserve R32: EDI, EBX,
245 reserved_.assign(MRegisterInfo::FirstVirtualRegister, false);
246 reserved_[19] = true; /* EDI */
247 reserved_[17] = true; /* EBX */
248 reserved_[12] = true; /* DI */
249 reserved_[ 7] = true; /* BX */
250 reserved_[ 4] = true; /* BH */
251 reserved_[ 5] = true; /* BL */
252 reserved_[28] = true; /* FP5 */
253 reserved_[29] = true; /* FP6 */
255 // liner scan algorithm
256 for (Intervals::const_iterator
257 i = li_->begin(), e = li_->end(); i != e; ++i) {
258 DEBUG(std::cerr << "processing current interval: " << *i << '\n');
260 DEBUG(printIntervals("\tactive", active_.begin(), active_.end()));
261 DEBUG(printIntervals("\tinactive", inactive_.begin(), inactive_.end()));
262 processActiveIntervals(i);
263 processInactiveIntervals(i);
267 // for every interval in inactive we overlap mark the register
269 for (IntervalPtrs::iterator j = inactive_.begin();
270 j != inactive_.end(); ++j) {
271 unsigned reg = (*j)->reg;
272 if (reg >= MRegisterInfo::FirstVirtualRegister)
275 if (i->overlaps(**j)) {
276 markPhysRegNotFree(reg);
280 // for every pre-allocated interval in unhandled we overlap
281 // mark the register as not free
282 for (Intervals::const_iterator j = i + 1; j != e; ++j) {
283 if (j->reg < MRegisterInfo::FirstVirtualRegister &&
285 markPhysRegNotFree(j->reg);
288 DEBUG(std::cerr << "\tallocating current interval:\n");
289 // if this register is preallocated reserve it
290 if (i->reg < MRegisterInfo::FirstVirtualRegister) {
292 markPhysRegNotFree(i->reg);
293 active_.push_back(&*i);
295 // otherwise we are allocating a virtual register. try to find
296 // a free physical register or spill an interval in order to
297 // assign it one (we could spill the current though).
299 unsigned physReg = getFreePhysReg(i);
301 assignStackSlotAtInterval(i);
305 assignVirt2PhysReg(i->reg, physReg);
306 active_.push_back(&*i);
310 // expire any remaining active intervals
311 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
312 unsigned reg = (*i)->reg;
313 DEBUG(std::cerr << "\t\tinterval " << **i << " expired\n");
314 if (reg >= MRegisterInfo::FirstVirtualRegister) {
317 markPhysRegFree(reg);
320 DEBUG(std::cerr << "finished register allocation\n");
321 DEBUG(printVirt2PhysMap());
323 DEBUG(std::cerr << "Rewrite machine code:\n");
324 for (MachineBasicBlockPtrs::iterator
325 mbbi = mbbs_.begin(), mbbe = mbbs_.end(); mbbi != mbbe; ++mbbi) {
329 for (currentInstr_ = currentMbb_->begin();
330 currentInstr_ != currentMbb_->end(); ++currentInstr_) {
332 DEBUG(std::cerr << "\tinstruction: ";
333 (*currentInstr_)->print(std::cerr, *tm_););
335 // use our current mapping and actually replace and
336 // virtual register with its allocated physical registers
337 DEBUG(std::cerr << "\t\treplacing virtual registers with mapped "
338 "physical registers:\n");
339 for (unsigned i = 0, e = (*currentInstr_)->getNumOperands();
341 MachineOperand& op = (*currentInstr_)->getOperand(i);
342 if (op.isVirtualRegister()) {
343 unsigned virtReg = op.getAllocatedRegNum();
344 unsigned physReg = v2pMap_[virtReg];
346 DEBUG(std::cerr << "\t\t\t%reg" << virtReg
347 << " -> " << mri_->getName(physReg) << '\n');
348 (*currentInstr_)->SetMachineOperandReg(i, physReg);
353 DEBUG(std::cerr << "\t\tloading temporarily used operands to "
355 for (unsigned i = 0, e = (*currentInstr_)->getNumOperands();
357 MachineOperand& op = (*currentInstr_)->getOperand(i);
358 if (op.isVirtualRegister() && op.isUse() && !op.isDef()) {
359 unsigned virtReg = op.getAllocatedRegNum();
360 unsigned physReg = v2pMap_[virtReg];
362 physReg = getFreeTempPhysReg(virtReg);
363 loadVirt2PhysReg(virtReg, physReg);
364 tempUseOperands_.push_back(virtReg);
366 (*currentInstr_)->SetMachineOperandReg(i, physReg);
370 DEBUG(std::cerr << "\t\tclearing temporarily used operands:\n");
371 for (unsigned i = 0, e = tempUseOperands_.size(); i != e; ++i) {
372 clearVirtReg(tempUseOperands_[i]);
374 tempUseOperands_.clear();
376 DEBUG(std::cerr << "\t\tassigning temporarily defined operands to "
378 for (unsigned i = 0, e = (*currentInstr_)->getNumOperands();
380 MachineOperand& op = (*currentInstr_)->getOperand(i);
381 if (op.isVirtualRegister() && op.isDef()) {
382 unsigned virtReg = op.getAllocatedRegNum();
383 unsigned physReg = v2pMap_[virtReg];
385 physReg = getFreeTempPhysReg(virtReg);
387 if (op.isUse()) { // def and use
388 loadVirt2PhysReg(virtReg, physReg);
391 assignVirt2PhysReg(virtReg, physReg);
393 tempDefOperands_.push_back(virtReg);
394 (*currentInstr_)->SetMachineOperandReg(i, physReg);
398 DEBUG(std::cerr << "\t\tspilling temporarily defined operands "
399 "of this instruction:\n");
400 ++currentInstr_; // we want to insert after this instruction
401 for (unsigned i = 0, e = tempDefOperands_.size(); i != e; ++i) {
402 spillVirtReg(tempDefOperands_[i]);
404 --currentInstr_; // restore currentInstr_ iterator
405 tempDefOperands_.clear();
412 void RA::processActiveIntervals(Intervals::const_iterator cur)
414 DEBUG(std::cerr << "\tprocessing active intervals:\n");
415 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end();) {
416 unsigned reg = (*i)->reg;
417 // remove expired intervals. we expire earlier because this if
418 // an interval expires this is going to be the last use. in
419 // this case we can reuse the register for a def in the same
421 if ((*i)->expiredAt(cur->start() + 1)) {
422 DEBUG(std::cerr << "\t\tinterval " << **i << " expired\n");
423 if (reg >= MRegisterInfo::FirstVirtualRegister) {
426 markPhysRegFree(reg);
427 // remove from active
428 i = active_.erase(i);
430 // move inactive intervals to inactive list
431 else if (!(*i)->liveAt(cur->start())) {
432 DEBUG(std::cerr << "\t\t\tinterval " << **i << " inactive\n");
433 if (reg >= MRegisterInfo::FirstVirtualRegister) {
436 markPhysRegFree(reg);
438 inactive_.push_back(*i);
439 // remove from active
440 i = active_.erase(i);
448 void RA::processInactiveIntervals(Intervals::const_iterator cur)
450 DEBUG(std::cerr << "\tprocessing inactive intervals:\n");
451 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end();) {
452 unsigned reg = (*i)->reg;
454 // remove expired intervals. we expire earlier because this if
455 // an interval expires this is going to be the last use. in
456 // this case we can reuse the register for a def in the same
458 if ((*i)->expiredAt(cur->start() + 1)) {
459 DEBUG(std::cerr << "\t\t\tinterval " << **i << " expired\n");
460 // remove from inactive
461 i = inactive_.erase(i);
463 // move re-activated intervals in active list
464 else if ((*i)->liveAt(cur->start())) {
465 DEBUG(std::cerr << "\t\t\tinterval " << **i << " active\n");
466 if (reg >= MRegisterInfo::FirstVirtualRegister) {
469 markPhysRegNotFree(reg);
471 active_.push_back(*i);
472 // remove from inactive
473 i = inactive_.erase(i);
482 template <typename T>
483 void updateWeight(T rw[], int reg, T w)
485 if (rw[reg] == std::numeric_limits<T>::max() ||
486 w == std::numeric_limits<T>::max())
487 rw[reg] = std::numeric_limits<T>::max();
493 void RA::assignStackSlotAtInterval(Intervals::const_iterator cur)
495 DEBUG(std::cerr << "\t\tassigning stack slot at interval "
498 // set all weights to zero
499 float regWeight[MRegisterInfo::FirstVirtualRegister];
500 for (unsigned i = 0; i < MRegisterInfo::FirstVirtualRegister; ++i)
503 // for each interval in active that overlaps
504 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
505 if (!cur->overlaps(**i))
508 unsigned reg = (*i)->reg;
509 if (reg >= MRegisterInfo::FirstVirtualRegister) {
512 updateWeight(regWeight, reg, (*i)->weight);
513 for (const unsigned* as = mri_->getAliasSet(reg); *as; ++as)
514 updateWeight(regWeight, *as, (*i)->weight);
517 // for each interval in inactive that overlaps
518 for (IntervalPtrs::iterator i = inactive_.begin();
519 i != inactive_.end(); ++i) {
520 if (!cur->overlaps(**i))
523 unsigned reg = (*i)->reg;
524 if (reg >= MRegisterInfo::FirstVirtualRegister) {
527 updateWeight(regWeight, reg, (*i)->weight);
528 for (const unsigned* as = mri_->getAliasSet(reg); *as; ++as)
529 updateWeight(regWeight, *as, (*i)->weight);
532 // for each fixed interval in unhandled that overlaps
533 for (Intervals::const_iterator j = cur + 1; j != li_->end(); ++j) {
534 if (j->reg >= MRegisterInfo::FirstVirtualRegister)
536 updateWeight(regWeight, j->reg, j->weight);
537 for (const unsigned* as = mri_->getAliasSet(j->reg); *as; ++as)
538 updateWeight(regWeight, *as, j->weight);
541 float minWeight = std::numeric_limits<float>::max();
543 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(cur->reg);
544 for (TargetRegisterClass::iterator i = rc->allocation_order_begin(*mf_);
545 i != rc->allocation_order_end(*mf_); ++i) {
547 if (!reserved_[reg] && minWeight > regWeight[reg]) {
548 minWeight = regWeight[reg];
553 if (cur->weight < minWeight) {
555 DEBUG(std::cerr << "\t\t\t\tspilling : " << mri_->getName(minReg)
556 << ", weight: " << cur->weight << '\n');
557 assignVirt2StackSlot(cur->reg);
560 std::set<unsigned> toSpill;
561 toSpill.insert(minReg);
562 for (const unsigned* as = mri_->getAliasSet(minReg); *as; ++as)
565 std::vector<unsigned> spilled;
566 for (IntervalPtrs::iterator i = active_.begin();
567 i != active_.end(); ) {
568 unsigned reg = (*i)->reg;
569 if (reg >= MRegisterInfo::FirstVirtualRegister &&
570 toSpill.find(v2pMap_[reg]) != toSpill.end() &&
571 cur->overlaps(**i)) {
572 spilled.push_back(v2pMap_[reg]);
573 DEBUG(std::cerr << "\t\t\t\tspilling : "
574 << mri_->getName(minReg) << ", weight: "
575 << (*i)->weight << '\n');
576 assignVirt2StackSlot(reg);
577 i = active_.erase(i);
583 for (IntervalPtrs::iterator i = inactive_.begin();
584 i != inactive_.end(); ) {
585 unsigned reg = (*i)->reg;
586 if (reg >= MRegisterInfo::FirstVirtualRegister &&
587 toSpill.find(v2pMap_[reg]) != toSpill.end() &&
588 cur->overlaps(**i)) {
589 DEBUG(std::cerr << "\t\t\t\tspilling : "
590 << mri_->getName(minReg) << ", weight: "
591 << (*i)->weight << '\n');
592 assignVirt2StackSlot(reg);
593 i = inactive_.erase(i);
600 unsigned physReg = getFreePhysReg(cur);
601 assert(physReg && "no free physical register after spill?");
604 for (unsigned i = 0; i < spilled.size(); ++i)
605 markPhysRegFree(spilled[i]);
607 assignVirt2PhysReg(cur->reg, physReg);
608 active_.push_back(&*cur);
612 bool RA::physRegAvailable(unsigned physReg)
614 assert(!reserved_[physReg] &&
615 "cannot call this method with a reserved register");
617 return !regUse_[physReg];
620 unsigned RA::getFreePhysReg(Intervals::const_iterator cur)
622 DEBUG(std::cerr << "\t\tgetting free physical register: ");
624 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(cur->reg);
625 for (TargetRegisterClass::iterator i = rc->allocation_order_begin(*mf_);
626 i != rc->allocation_order_end(*mf_); ++i) {
628 if (!reserved_[reg] && !regUse_[reg]) {
629 DEBUG(std::cerr << mri_->getName(reg) << '\n');
634 DEBUG(std::cerr << "no free register\n");
638 bool RA::tempPhysRegAvailable(unsigned physReg)
640 assert(reserved_[physReg] &&
641 "cannot call this method with a not reserved temp register");
643 return !regUse_[physReg];
646 unsigned RA::getFreeTempPhysReg(unsigned virtReg)
648 DEBUG(std::cerr << "\t\tgetting free temporary physical register: ");
650 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(virtReg);
651 // go in reverse allocation order for the temp registers
652 for (TargetRegisterClass::iterator i = rc->allocation_order_end(*mf_) - 1;
653 i != rc->allocation_order_begin(*mf_) - 1; --i) {
655 if (reserved_[reg] && !regUse_[reg]) {
656 DEBUG(std::cerr << mri_->getName(reg) << '\n');
661 assert(0 && "no free temporary physical register?");
665 void RA::assignVirt2PhysReg(unsigned virtReg, unsigned physReg)
667 v2pMap_[virtReg] = physReg;
668 markPhysRegNotFree(physReg);
671 void RA::clearVirtReg(unsigned virtReg)
673 Virt2PhysMap::iterator it = v2pMap_.find(virtReg);
674 assert(it != v2pMap_.end() &&
675 "attempting to clear a not allocated virtual register");
676 unsigned physReg = it->second;
677 markPhysRegFree(physReg);
678 v2pMap_[virtReg] = 0; // this marks that this virtual register
679 // lives on the stack
680 DEBUG(std::cerr << "\t\t\tcleared register " << mri_->getName(physReg)
684 void RA::assignVirt2StackSlot(unsigned virtReg)
686 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(virtReg);
687 int frameIndex = mf_->getFrameInfo()->CreateStackObject(rc);
689 bool inserted = v2ssMap_.insert(std::make_pair(virtReg, frameIndex)).second;
691 "attempt to assign stack slot to already assigned register?");
692 // if the virtual register was previously assigned clear the mapping
693 // and free the virtual register
694 if (v2pMap_.find(virtReg) != v2pMap_.end()) {
695 clearVirtReg(virtReg);
698 v2pMap_[virtReg] = 0; // this marks that this virtual register
699 // lives on the stack
703 int RA::getStackSlot(unsigned virtReg)
705 // use lower_bound so that we can do a possibly O(1) insert later
707 Virt2StackSlotMap::iterator it = v2ssMap_.find(virtReg);
708 assert(it != v2ssMap_.end() &&
709 "attempt to get stack slot on register that does not live on the stack");
713 void RA::spillVirtReg(unsigned virtReg)
715 DEBUG(std::cerr << "\t\t\tspilling register: " << virtReg);
716 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(virtReg);
717 int frameIndex = getStackSlot(virtReg);
718 DEBUG(std::cerr << " to stack slot #" << frameIndex << '\n');
720 instrAdded_ += mri_->storeRegToStackSlot(*currentMbb_, currentInstr_,
721 v2pMap_[virtReg], frameIndex, rc);
722 clearVirtReg(virtReg);
725 void RA::loadVirt2PhysReg(unsigned virtReg, unsigned physReg)
727 DEBUG(std::cerr << "\t\t\tloading register: " << virtReg);
728 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(virtReg);
729 int frameIndex = getStackSlot(virtReg);
730 DEBUG(std::cerr << " from stack slot #" << frameIndex << '\n');
732 instrAdded_ += mri_->loadRegFromStackSlot(*currentMbb_, currentInstr_,
733 physReg, frameIndex, rc);
734 assignVirt2PhysReg(virtReg, physReg);
737 void RA::markPhysRegFree(unsigned physReg)
739 assert(regUse_[physReg] != 0);
741 for (const unsigned* as = mri_->getAliasSet(physReg); *as; ++as) {
743 assert(regUse_[physReg] != 0);
748 void RA::markPhysRegNotFree(unsigned physReg)
751 for (const unsigned* as = mri_->getAliasSet(physReg); *as; ++as) {
757 FunctionPass* llvm::createLinearScanRegisterAllocator() {