1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "VirtRegMap.h"
16 #include "VirtRegRewriter.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/CalcSpillWeights.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/LiveStackAnalysis.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/MachineLoopInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/RegAllocRegistry.h"
28 #include "llvm/CodeGen/RegisterCoalescer.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/ADT/EquivalenceClasses.h"
34 #include "llvm/ADT/SmallSet.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/ADT/STLExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
48 STATISTIC(NumIters , "Number of iterations performed");
49 STATISTIC(NumBacktracks, "Number of times we had to backtrack");
50 STATISTIC(NumCoalesce, "Number of copies coalesced");
51 STATISTIC(NumDowngrade, "Number of registers downgraded");
54 NewHeuristic("new-spilling-heuristic",
55 cl::desc("Use new spilling heuristic"),
56 cl::init(false), cl::Hidden);
59 PreSplitIntervals("pre-alloc-split",
60 cl::desc("Pre-register allocation live interval splitting"),
61 cl::init(false), cl::Hidden);
64 TrivCoalesceEnds("trivial-coalesce-ends",
65 cl::desc("Attempt trivial coalescing of interval ends"),
66 cl::init(false), cl::Hidden);
68 static RegisterRegAlloc
69 linearscanRegAlloc("linearscan", "linear scan register allocator",
70 createLinearScanRegisterAllocator);
73 // When we allocate a register, add it to a fixed-size queue of
74 // registers to skip in subsequent allocations. This trades a small
75 // amount of register pressure and increased spills for flexibility in
76 // the post-pass scheduler.
78 // Note that in a the number of registers used for reloading spills
79 // will be one greater than the value of this option.
81 // One big limitation of this is that it doesn't differentiate between
82 // different register classes. So on x86-64, if there is xmm register
83 // pressure, it can caused fewer GPRs to be held in the queue.
84 static cl::opt<unsigned>
85 NumRecentlyUsedRegs("linearscan-skip-count",
86 cl::desc("Number of registers for linearscan to remember to skip."),
90 struct RALinScan : public MachineFunctionPass {
92 RALinScan() : MachineFunctionPass(&ID) {
93 // Initialize the queue to record recently-used registers.
94 if (NumRecentlyUsedRegs > 0)
95 RecentRegs.resize(NumRecentlyUsedRegs, 0);
96 RecentNext = RecentRegs.begin();
99 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
100 typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
102 /// RelatedRegClasses - This structure is built the first time a function is
103 /// compiled, and keeps track of which register classes have registers that
104 /// belong to multiple classes or have aliases that are in other classes.
105 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
106 DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
108 // NextReloadMap - For each register in the map, it maps to the another
109 // register which is defined by a reload from the same stack slot and
110 // both reloads are in the same basic block.
111 DenseMap<unsigned, unsigned> NextReloadMap;
113 // DowngradedRegs - A set of registers which are being "downgraded", i.e.
114 // un-favored for allocation.
115 SmallSet<unsigned, 8> DowngradedRegs;
117 // DowngradeMap - A map from virtual registers to physical registers being
118 // downgraded for the virtual registers.
119 DenseMap<unsigned, unsigned> DowngradeMap;
121 MachineFunction* mf_;
122 MachineRegisterInfo* mri_;
123 const TargetMachine* tm_;
124 const TargetRegisterInfo* tri_;
125 const TargetInstrInfo* tii_;
126 BitVector allocatableRegs_;
129 const MachineLoopInfo *loopInfo;
131 /// handled_ - Intervals are added to the handled_ set in the order of their
132 /// start value. This is uses for backtracking.
133 std::vector<LiveInterval*> handled_;
135 /// fixed_ - Intervals that correspond to machine registers.
139 /// active_ - Intervals that are currently being processed, and which have a
140 /// live range active for the current point.
141 IntervalPtrs active_;
143 /// inactive_ - Intervals that are currently being processed, but which have
144 /// a hold at the current point.
145 IntervalPtrs inactive_;
147 typedef std::priority_queue<LiveInterval*,
148 SmallVector<LiveInterval*, 64>,
149 greater_ptr<LiveInterval> > IntervalHeap;
150 IntervalHeap unhandled_;
152 /// regUse_ - Tracks register usage.
153 SmallVector<unsigned, 32> regUse_;
154 SmallVector<unsigned, 32> regUseBackUp_;
156 /// vrm_ - Tracks register assignments.
159 std::auto_ptr<VirtRegRewriter> rewriter_;
161 std::auto_ptr<Spiller> spiller_;
163 // The queue of recently-used registers.
164 SmallVector<unsigned, 4> RecentRegs;
165 SmallVector<unsigned, 4>::iterator RecentNext;
167 // Record that we just picked this register.
168 void recordRecentlyUsed(unsigned reg) {
169 assert(reg != 0 && "Recently used register is NOREG!");
170 if (!RecentRegs.empty()) {
172 if (RecentNext == RecentRegs.end())
173 RecentNext = RecentRegs.begin();
178 virtual const char* getPassName() const {
179 return "Linear Scan Register Allocator";
182 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
183 AU.setPreservesCFG();
184 AU.addRequired<LiveIntervals>();
185 AU.addPreserved<SlotIndexes>();
187 AU.addRequiredID(StrongPHIEliminationID);
188 // Make sure PassManager knows which analyses to make available
189 // to coalescing and which analyses coalescing invalidates.
190 AU.addRequiredTransitive<RegisterCoalescer>();
191 AU.addRequired<CalculateSpillWeights>();
192 if (PreSplitIntervals)
193 AU.addRequiredID(PreAllocSplittingID);
194 AU.addRequired<LiveStacks>();
195 AU.addPreserved<LiveStacks>();
196 AU.addRequired<MachineLoopInfo>();
197 AU.addPreserved<MachineLoopInfo>();
198 AU.addRequired<VirtRegMap>();
199 AU.addPreserved<VirtRegMap>();
200 AU.addPreservedID(MachineDominatorsID);
201 MachineFunctionPass::getAnalysisUsage(AU);
204 /// runOnMachineFunction - register allocate the whole function
205 bool runOnMachineFunction(MachineFunction&);
207 // Determine if we skip this register due to its being recently used.
208 bool isRecentlyUsed(unsigned reg) const {
209 return std::find(RecentRegs.begin(), RecentRegs.end(), reg) !=
214 /// linearScan - the linear scan algorithm
217 /// initIntervalSets - initialize the interval sets.
219 void initIntervalSets();
221 /// processActiveIntervals - expire old intervals and move non-overlapping
222 /// ones to the inactive list.
223 void processActiveIntervals(SlotIndex CurPoint);
225 /// processInactiveIntervals - expire old intervals and move overlapping
226 /// ones to the active list.
227 void processInactiveIntervals(SlotIndex CurPoint);
229 /// hasNextReloadInterval - Return the next liveinterval that's being
230 /// defined by a reload from the same SS as the specified one.
231 LiveInterval *hasNextReloadInterval(LiveInterval *cur);
233 /// DowngradeRegister - Downgrade a register for allocation.
234 void DowngradeRegister(LiveInterval *li, unsigned Reg);
236 /// UpgradeRegister - Upgrade a register for allocation.
237 void UpgradeRegister(unsigned Reg);
239 /// assignRegOrStackSlotAtInterval - assign a register if one
240 /// is available, or spill.
241 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
243 void updateSpillWeights(std::vector<float> &Weights,
244 unsigned reg, float weight,
245 const TargetRegisterClass *RC);
247 /// findIntervalsToSpill - Determine the intervals to spill for the
248 /// specified interval. It's passed the physical registers whose spill
249 /// weight is the lowest among all the registers whose live intervals
250 /// conflict with the interval.
251 void findIntervalsToSpill(LiveInterval *cur,
252 std::vector<std::pair<unsigned,float> > &Candidates,
254 SmallVector<LiveInterval*, 8> &SpillIntervals);
256 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
257 /// try allocate the definition the same register as the source register
258 /// if the register is not defined during live time of the interval. This
259 /// eliminate a copy. This is used to coalesce copies which were not
260 /// coalesced away before allocation either due to dest and src being in
261 /// different register classes or because the coalescer was overly
263 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
266 /// Register usage / availability tracking helpers.
270 regUse_.resize(tri_->getNumRegs(), 0);
271 regUseBackUp_.resize(tri_->getNumRegs(), 0);
274 void finalizeRegUses() {
276 // Verify all the registers are "freed".
278 for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
279 if (regUse_[i] != 0) {
280 dbgs() << tri_->getName(i) << " is still in use!\n";
288 regUseBackUp_.clear();
291 void addRegUse(unsigned physReg) {
292 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
293 "should be physical register!");
295 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
299 void delRegUse(unsigned physReg) {
300 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
301 "should be physical register!");
302 assert(regUse_[physReg] != 0);
304 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
305 assert(regUse_[*as] != 0);
310 bool isRegAvail(unsigned physReg) const {
311 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
312 "should be physical register!");
313 return regUse_[physReg] == 0;
316 void backUpRegUses() {
317 regUseBackUp_ = regUse_;
320 void restoreRegUses() {
321 regUse_ = regUseBackUp_;
325 /// Register handling helpers.
328 /// getFreePhysReg - return a free physical register for this virtual
329 /// register interval if we have one, otherwise return 0.
330 unsigned getFreePhysReg(LiveInterval* cur);
331 unsigned getFreePhysReg(LiveInterval* cur,
332 const TargetRegisterClass *RC,
333 unsigned MaxInactiveCount,
334 SmallVector<unsigned, 256> &inactiveCounts,
337 /// assignVirt2StackSlot - assigns this virtual register to a
338 /// stack slot. returns the stack slot
339 int assignVirt2StackSlot(unsigned virtReg);
341 void ComputeRelatedRegClasses();
343 template <typename ItTy>
344 void printIntervals(const char* const str, ItTy i, ItTy e) const {
347 dbgs() << str << " intervals:\n";
349 for (; i != e; ++i) {
350 dbgs() << "\t" << *i->first << " -> ";
352 unsigned reg = i->first->reg;
353 if (TargetRegisterInfo::isVirtualRegister(reg))
354 reg = vrm_->getPhys(reg);
356 dbgs() << tri_->getName(reg) << '\n';
361 char RALinScan::ID = 0;
364 static RegisterPass<RALinScan>
365 X("linearscan-regalloc", "Linear Scan Register Allocator");
367 void RALinScan::ComputeRelatedRegClasses() {
368 // First pass, add all reg classes to the union, and determine at least one
369 // reg class that each register is in.
370 bool HasAliases = false;
371 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
372 E = tri_->regclass_end(); RCI != E; ++RCI) {
373 RelatedRegClasses.insert(*RCI);
374 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
376 HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
378 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
380 // Already processed this register. Just make sure we know that
381 // multiple register classes share a register.
382 RelatedRegClasses.unionSets(PRC, *RCI);
389 // Second pass, now that we know conservatively what register classes each reg
390 // belongs to, add info about aliases. We don't need to do this for targets
391 // without register aliases.
393 for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
394 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
396 for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
397 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
400 /// attemptTrivialCoalescing - If a simple interval is defined by a copy, try
401 /// allocate the definition the same register as the source register if the
402 /// register is not defined during live time of the interval. If the interval is
403 /// killed by a copy, try to use the destination register. This eliminates a
404 /// copy. This is used to coalesce copies which were not coalesced away before
405 /// allocation either due to dest and src being in different register classes or
406 /// because the coalescer was overly conservative.
407 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
408 unsigned Preference = vrm_->getRegAllocPref(cur.reg);
409 if ((Preference && Preference == Reg) || !cur.containsOneValue())
412 // We cannot handle complicated live ranges. Simple linear stuff only.
413 if (cur.ranges.size() != 1)
416 const LiveRange &range = cur.ranges.front();
418 VNInfo *vni = range.valno;
424 MachineInstr *CopyMI;
425 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
426 if (vni->def != SlotIndex() && vni->isDefAccurate() &&
427 (CopyMI = li_->getInstructionFromIndex(vni->def)) &&
428 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
429 // Defined by a copy, try to extend SrcReg forward
431 else if (TrivCoalesceEnds &&
433 li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
434 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
436 // Only used by a copy, try to extend DstReg backwards
442 if (TargetRegisterInfo::isVirtualRegister(CandReg)) {
443 if (!vrm_->isAssignedReg(CandReg))
445 CandReg = vrm_->getPhys(CandReg);
450 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
451 if (!RC->contains(CandReg))
454 if (li_->conflictsWithPhysReg(cur, *vrm_, CandReg))
458 DEBUG(dbgs() << "Coalescing: " << cur << " -> " << tri_->getName(CandReg)
460 vrm_->clearVirt(cur.reg);
461 vrm_->assignVirt2Phys(cur.reg, CandReg);
467 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
469 mri_ = &fn.getRegInfo();
470 tm_ = &fn.getTarget();
471 tri_ = tm_->getRegisterInfo();
472 tii_ = tm_->getInstrInfo();
473 allocatableRegs_ = tri_->getAllocatableSet(fn);
474 li_ = &getAnalysis<LiveIntervals>();
475 ls_ = &getAnalysis<LiveStacks>();
476 loopInfo = &getAnalysis<MachineLoopInfo>();
478 // We don't run the coalescer here because we have no reason to
479 // interact with it. If the coalescer requires interaction, it
480 // won't do anything. If it doesn't require interaction, we assume
481 // it was run as a separate pass.
483 // If this is the first function compiled, compute the related reg classes.
484 if (RelatedRegClasses.empty())
485 ComputeRelatedRegClasses();
487 // Also resize register usage trackers.
490 vrm_ = &getAnalysis<VirtRegMap>();
491 if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
493 spiller_.reset(createSpiller(mf_, li_, loopInfo, vrm_));
499 // Rewrite spill code and update the PhysRegsUsed set.
500 rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
502 assert(unhandled_.empty() && "Unhandled live intervals remain!");
510 NextReloadMap.clear();
511 DowngradedRegs.clear();
512 DowngradeMap.clear();
518 /// initIntervalSets - initialize the interval sets.
520 void RALinScan::initIntervalSets()
522 assert(unhandled_.empty() && fixed_.empty() &&
523 active_.empty() && inactive_.empty() &&
524 "interval sets should be empty on initialization");
526 handled_.reserve(li_->getNumIntervals());
528 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
529 if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
530 if (!i->second->empty()) {
531 mri_->setPhysRegUsed(i->second->reg);
532 fixed_.push_back(std::make_pair(i->second, i->second->begin()));
535 if (i->second->empty()) {
536 assignRegOrStackSlotAtInterval(i->second);
539 unhandled_.push(i->second);
544 void RALinScan::linearScan() {
545 // linear scan algorithm
547 dbgs() << "********** LINEAR SCAN **********\n"
548 << "********** Function: "
549 << mf_->getFunction()->getName() << '\n';
550 printIntervals("fixed", fixed_.begin(), fixed_.end());
553 while (!unhandled_.empty()) {
554 // pick the interval with the earliest start point
555 LiveInterval* cur = unhandled_.top();
558 DEBUG(dbgs() << "\n*** CURRENT ***: " << *cur << '\n');
560 assert(!cur->empty() && "Empty interval in unhandled set.");
562 processActiveIntervals(cur->beginIndex());
563 processInactiveIntervals(cur->beginIndex());
565 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
566 "Can only allocate virtual registers!");
568 // Allocating a virtual register. try to find a free
569 // physical register or spill an interval (possibly this one) in order to
571 assignRegOrStackSlotAtInterval(cur);
574 printIntervals("active", active_.begin(), active_.end());
575 printIntervals("inactive", inactive_.begin(), inactive_.end());
579 // Expire any remaining active intervals
580 while (!active_.empty()) {
581 IntervalPtr &IP = active_.back();
582 unsigned reg = IP.first->reg;
583 DEBUG(dbgs() << "\tinterval " << *IP.first << " expired\n");
584 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
585 "Can only allocate virtual registers!");
586 reg = vrm_->getPhys(reg);
591 // Expire any remaining inactive intervals
593 for (IntervalPtrs::reverse_iterator
594 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
595 dbgs() << "\tinterval " << *i->first << " expired\n";
599 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
600 MachineFunction::iterator EntryMBB = mf_->begin();
601 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
602 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
603 LiveInterval &cur = *i->second;
605 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
608 else if (vrm_->isAssignedReg(cur.reg))
609 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
612 // Ignore splited live intervals.
613 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
616 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
618 const LiveRange &LR = *I;
619 if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
620 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
621 if (LiveInMBBs[i] != EntryMBB) {
622 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
623 "Adding a virtual register to livein set?");
624 LiveInMBBs[i]->addLiveIn(Reg);
631 DEBUG(dbgs() << *vrm_);
633 // Look for physical registers that end up not being allocated even though
634 // register allocator had to spill other registers in its register class.
635 if (ls_->getNumIntervals() == 0)
637 if (!vrm_->FindUnusedRegisters(li_))
641 /// processActiveIntervals - expire old intervals and move non-overlapping ones
642 /// to the inactive list.
643 void RALinScan::processActiveIntervals(SlotIndex CurPoint)
645 DEBUG(dbgs() << "\tprocessing active intervals:\n");
647 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
648 LiveInterval *Interval = active_[i].first;
649 LiveInterval::iterator IntervalPos = active_[i].second;
650 unsigned reg = Interval->reg;
652 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
654 if (IntervalPos == Interval->end()) { // Remove expired intervals.
655 DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
656 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
657 "Can only allocate virtual registers!");
658 reg = vrm_->getPhys(reg);
661 // Pop off the end of the list.
662 active_[i] = active_.back();
666 } else if (IntervalPos->start > CurPoint) {
667 // Move inactive intervals to inactive list.
668 DEBUG(dbgs() << "\t\tinterval " << *Interval << " inactive\n");
669 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
670 "Can only allocate virtual registers!");
671 reg = vrm_->getPhys(reg);
674 inactive_.push_back(std::make_pair(Interval, IntervalPos));
676 // Pop off the end of the list.
677 active_[i] = active_.back();
681 // Otherwise, just update the iterator position.
682 active_[i].second = IntervalPos;
687 /// processInactiveIntervals - expire old intervals and move overlapping
688 /// ones to the active list.
689 void RALinScan::processInactiveIntervals(SlotIndex CurPoint)
691 DEBUG(dbgs() << "\tprocessing inactive intervals:\n");
693 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
694 LiveInterval *Interval = inactive_[i].first;
695 LiveInterval::iterator IntervalPos = inactive_[i].second;
696 unsigned reg = Interval->reg;
698 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
700 if (IntervalPos == Interval->end()) { // remove expired intervals.
701 DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
703 // Pop off the end of the list.
704 inactive_[i] = inactive_.back();
705 inactive_.pop_back();
707 } else if (IntervalPos->start <= CurPoint) {
708 // move re-activated intervals in active list
709 DEBUG(dbgs() << "\t\tinterval " << *Interval << " active\n");
710 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
711 "Can only allocate virtual registers!");
712 reg = vrm_->getPhys(reg);
715 active_.push_back(std::make_pair(Interval, IntervalPos));
717 // Pop off the end of the list.
718 inactive_[i] = inactive_.back();
719 inactive_.pop_back();
722 // Otherwise, just update the iterator position.
723 inactive_[i].second = IntervalPos;
728 /// updateSpillWeights - updates the spill weights of the specifed physical
729 /// register and its weight.
730 void RALinScan::updateSpillWeights(std::vector<float> &Weights,
731 unsigned reg, float weight,
732 const TargetRegisterClass *RC) {
733 SmallSet<unsigned, 4> Processed;
734 SmallSet<unsigned, 4> SuperAdded;
735 SmallVector<unsigned, 4> Supers;
736 Weights[reg] += weight;
737 Processed.insert(reg);
738 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
739 Weights[*as] += weight;
740 Processed.insert(*as);
741 if (tri_->isSubRegister(*as, reg) &&
742 SuperAdded.insert(*as) &&
744 Supers.push_back(*as);
748 // If the alias is a super-register, and the super-register is in the
749 // register class we are trying to allocate. Then add the weight to all
750 // sub-registers of the super-register even if they are not aliases.
751 // e.g. allocating for GR32, bh is not used, updating bl spill weight.
752 // bl should get the same spill weight otherwise it will be choosen
753 // as a spill candidate since spilling bh doesn't make ebx available.
754 for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
755 for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
756 if (!Processed.count(*sr))
757 Weights[*sr] += weight;
762 RALinScan::IntervalPtrs::iterator
763 FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
764 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
766 if (I->first == LI) return I;
770 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, SlotIndex Point){
771 for (unsigned i = 0, e = V.size(); i != e; ++i) {
772 RALinScan::IntervalPtr &IP = V[i];
773 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
775 if (I != IP.first->begin()) --I;
780 /// addStackInterval - Create a LiveInterval for stack if the specified live
781 /// interval has been spilled.
782 static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
784 MachineRegisterInfo* mri_, VirtRegMap &vrm_) {
785 int SS = vrm_.getStackSlot(cur->reg);
786 if (SS == VirtRegMap::NO_STACK_SLOT)
789 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
790 LiveInterval &SI = ls_->getOrCreateInterval(SS, RC);
793 if (SI.hasAtLeastOneValue())
794 VNI = SI.getValNumInfo(0);
796 VNI = SI.getNextValue(SlotIndex(), 0, false,
797 ls_->getVNInfoAllocator());
799 LiveInterval &RI = li_->getInterval(cur->reg);
800 // FIXME: This may be overly conservative.
801 SI.MergeRangesInAsValue(RI, VNI);
804 /// getConflictWeight - Return the number of conflicts between cur
805 /// live interval and defs and uses of Reg weighted by loop depthes.
807 float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
808 MachineRegisterInfo *mri_,
809 const MachineLoopInfo *loopInfo) {
811 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
812 E = mri_->reg_end(); I != E; ++I) {
813 MachineInstr *MI = &*I;
814 if (cur->liveAt(li_->getInstructionIndex(MI))) {
815 unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
816 Conflicts += powf(10.0f, (float)loopDepth);
822 /// findIntervalsToSpill - Determine the intervals to spill for the
823 /// specified interval. It's passed the physical registers whose spill
824 /// weight is the lowest among all the registers whose live intervals
825 /// conflict with the interval.
826 void RALinScan::findIntervalsToSpill(LiveInterval *cur,
827 std::vector<std::pair<unsigned,float> > &Candidates,
829 SmallVector<LiveInterval*, 8> &SpillIntervals) {
830 // We have figured out the *best* register to spill. But there are other
831 // registers that are pretty good as well (spill weight within 3%). Spill
832 // the one that has fewest defs and uses that conflict with cur.
833 float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
834 SmallVector<LiveInterval*, 8> SLIs[3];
837 dbgs() << "\tConsidering " << NumCands << " candidates: ";
838 for (unsigned i = 0; i != NumCands; ++i)
839 dbgs() << tri_->getName(Candidates[i].first) << " ";
843 // Calculate the number of conflicts of each candidate.
844 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
845 unsigned Reg = i->first->reg;
846 unsigned PhysReg = vrm_->getPhys(Reg);
847 if (!cur->overlapsFrom(*i->first, i->second))
849 for (unsigned j = 0; j < NumCands; ++j) {
850 unsigned Candidate = Candidates[j].first;
851 if (tri_->regsOverlap(PhysReg, Candidate)) {
853 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
854 SLIs[j].push_back(i->first);
859 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
860 unsigned Reg = i->first->reg;
861 unsigned PhysReg = vrm_->getPhys(Reg);
862 if (!cur->overlapsFrom(*i->first, i->second-1))
864 for (unsigned j = 0; j < NumCands; ++j) {
865 unsigned Candidate = Candidates[j].first;
866 if (tri_->regsOverlap(PhysReg, Candidate)) {
868 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
869 SLIs[j].push_back(i->first);
874 // Which is the best candidate?
875 unsigned BestCandidate = 0;
876 float MinConflicts = Conflicts[0];
877 for (unsigned i = 1; i != NumCands; ++i) {
878 if (Conflicts[i] < MinConflicts) {
880 MinConflicts = Conflicts[i];
884 std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
885 std::back_inserter(SpillIntervals));
889 struct WeightCompare {
891 const RALinScan &Allocator;
894 WeightCompare(const RALinScan &Alloc) : Allocator(Alloc) {}
896 typedef std::pair<unsigned, float> RegWeightPair;
897 bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
898 return LHS.second < RHS.second && !Allocator.isRecentlyUsed(LHS.first);
903 static bool weightsAreClose(float w1, float w2) {
907 float diff = w1 - w2;
908 if (diff <= 0.02f) // Within 0.02f
910 return (diff / w2) <= 0.05f; // Within 5%.
913 LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
914 DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
915 if (I == NextReloadMap.end())
917 return &li_->getInterval(I->second);
920 void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
921 bool isNew = DowngradedRegs.insert(Reg);
922 isNew = isNew; // Silence compiler warning.
923 assert(isNew && "Multiple reloads holding the same register?");
924 DowngradeMap.insert(std::make_pair(li->reg, Reg));
925 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS) {
926 isNew = DowngradedRegs.insert(*AS);
927 isNew = isNew; // Silence compiler warning.
928 assert(isNew && "Multiple reloads holding the same register?");
929 DowngradeMap.insert(std::make_pair(li->reg, *AS));
934 void RALinScan::UpgradeRegister(unsigned Reg) {
936 DowngradedRegs.erase(Reg);
937 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
938 DowngradedRegs.erase(*AS);
944 bool operator()(LiveInterval* A, LiveInterval* B) {
945 return A->beginIndex() < B->beginIndex();
950 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
952 void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
953 DEBUG(dbgs() << "\tallocating current interval: ");
955 // This is an implicitly defined live interval, just assign any register.
956 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
958 unsigned physReg = vrm_->getRegAllocPref(cur->reg);
960 physReg = *RC->allocation_order_begin(*mf_);
961 DEBUG(dbgs() << tri_->getName(physReg) << '\n');
962 // Note the register is not really in use.
963 vrm_->assignVirt2Phys(cur->reg, physReg);
969 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
970 SlotIndex StartPosition = cur->beginIndex();
971 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
973 // If start of this live interval is defined by a move instruction and its
974 // source is assigned a physical register that is compatible with the target
975 // register class, then we should try to assign it the same register.
976 // This can happen when the move is from a larger register class to a smaller
977 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
978 if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
979 VNInfo *vni = cur->begin()->valno;
980 if ((vni->def != SlotIndex()) && !vni->isUnused() &&
981 vni->isDefAccurate()) {
982 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
983 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
985 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
987 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
989 else if (vrm_->isAssignedReg(SrcReg))
990 Reg = vrm_->getPhys(SrcReg);
993 Reg = tri_->getSubReg(Reg, SrcSubReg);
995 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
996 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
997 mri_->setRegAllocationHint(cur->reg, 0, Reg);
1003 // For every interval in inactive we overlap with, mark the
1004 // register as not free and update spill weights.
1005 for (IntervalPtrs::const_iterator i = inactive_.begin(),
1006 e = inactive_.end(); i != e; ++i) {
1007 unsigned Reg = i->first->reg;
1008 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
1009 "Can only allocate virtual registers!");
1010 const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
1011 // If this is not in a related reg class to the register we're allocating,
1013 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1014 cur->overlapsFrom(*i->first, i->second-1)) {
1015 Reg = vrm_->getPhys(Reg);
1017 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
1021 // Speculatively check to see if we can get a register right now. If not,
1022 // we know we won't be able to by adding more constraints. If so, we can
1023 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
1024 // is very bad (it contains all callee clobbered registers for any functions
1025 // with a call), so we want to avoid doing that if possible.
1026 unsigned physReg = getFreePhysReg(cur);
1027 unsigned BestPhysReg = physReg;
1029 // We got a register. However, if it's in the fixed_ list, we might
1030 // conflict with it. Check to see if we conflict with it or any of its
1032 SmallSet<unsigned, 8> RegAliases;
1033 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
1034 RegAliases.insert(*AS);
1036 bool ConflictsWithFixed = false;
1037 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1038 IntervalPtr &IP = fixed_[i];
1039 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
1040 // Okay, this reg is on the fixed list. Check to see if we actually
1042 LiveInterval *I = IP.first;
1043 if (I->endIndex() > StartPosition) {
1044 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1046 if (II != I->begin() && II->start > StartPosition)
1048 if (cur->overlapsFrom(*I, II)) {
1049 ConflictsWithFixed = true;
1056 // Okay, the register picked by our speculative getFreePhysReg call turned
1057 // out to be in use. Actually add all of the conflicting fixed registers to
1058 // regUse_ so we can do an accurate query.
1059 if (ConflictsWithFixed) {
1060 // For every interval in fixed we overlap with, mark the register as not
1061 // free and update spill weights.
1062 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1063 IntervalPtr &IP = fixed_[i];
1064 LiveInterval *I = IP.first;
1066 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
1067 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1068 I->endIndex() > StartPosition) {
1069 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1071 if (II != I->begin() && II->start > StartPosition)
1073 if (cur->overlapsFrom(*I, II)) {
1074 unsigned reg = I->reg;
1076 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
1081 // Using the newly updated regUse_ object, which includes conflicts in the
1082 // future, see if there are any registers available.
1083 physReg = getFreePhysReg(cur);
1087 // Restore the physical register tracker, removing information about the
1091 // If we find a free register, we are done: assign this virtual to
1092 // the free physical register and add this interval to the active
1095 DEBUG(dbgs() << tri_->getName(physReg) << '\n');
1096 vrm_->assignVirt2Phys(cur->reg, physReg);
1098 active_.push_back(std::make_pair(cur, cur->begin()));
1099 handled_.push_back(cur);
1101 // "Upgrade" the physical register since it has been allocated.
1102 UpgradeRegister(physReg);
1103 if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
1104 // "Downgrade" physReg to try to keep physReg from being allocated until
1105 // the next reload from the same SS is allocated.
1106 mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg);
1107 DowngradeRegister(cur, physReg);
1111 DEBUG(dbgs() << "no free registers\n");
1113 // Compile the spill weights into an array that is better for scanning.
1114 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
1115 for (std::vector<std::pair<unsigned, float> >::iterator
1116 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
1117 updateSpillWeights(SpillWeights, I->first, I->second, RC);
1119 // for each interval in active, update spill weights.
1120 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
1122 unsigned reg = i->first->reg;
1123 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1124 "Can only allocate virtual registers!");
1125 reg = vrm_->getPhys(reg);
1126 updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
1129 DEBUG(dbgs() << "\tassigning stack slot at interval "<< *cur << ":\n");
1131 // Find a register to spill.
1132 float minWeight = HUGE_VALF;
1133 unsigned minReg = 0;
1136 std::vector<std::pair<unsigned,float> > RegsWeights;
1137 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
1138 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1139 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1141 float regWeight = SpillWeights[reg];
1142 // Skip recently allocated registers.
1143 if (minWeight > regWeight && !isRecentlyUsed(reg))
1145 RegsWeights.push_back(std::make_pair(reg, regWeight));
1148 // If we didn't find a register that is spillable, try aliases?
1150 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1151 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1153 // No need to worry about if the alias register size < regsize of RC.
1154 // We are going to spill all registers that alias it anyway.
1155 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
1156 RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
1160 // Sort all potential spill candidates by weight.
1161 std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare(*this));
1162 minReg = RegsWeights[0].first;
1163 minWeight = RegsWeights[0].second;
1164 if (minWeight == HUGE_VALF) {
1165 // All registers must have inf weight. Just grab one!
1166 minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
1167 if (cur->weight == HUGE_VALF ||
1168 li_->getApproximateInstructionCount(*cur) == 0) {
1169 // Spill a physical register around defs and uses.
1170 if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
1171 // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
1172 // in fixed_. Reset them.
1173 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1174 IntervalPtr &IP = fixed_[i];
1175 LiveInterval *I = IP.first;
1176 if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
1177 IP.second = I->advanceTo(I->begin(), StartPosition);
1180 DowngradedRegs.clear();
1181 assignRegOrStackSlotAtInterval(cur);
1183 assert(false && "Ran out of registers during register allocation!");
1184 llvm_report_error("Ran out of registers during register allocation!");
1190 // Find up to 3 registers to consider as spill candidates.
1191 unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
1192 while (LastCandidate > 1) {
1193 if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
1199 dbgs() << "\t\tregister(s) with min weight(s): ";
1201 for (unsigned i = 0; i != LastCandidate; ++i)
1202 dbgs() << tri_->getName(RegsWeights[i].first)
1203 << " (" << RegsWeights[i].second << ")\n";
1206 // If the current has the minimum weight, we need to spill it and
1207 // add any added intervals back to unhandled, and restart
1209 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
1210 DEBUG(dbgs() << "\t\t\tspilling(c): " << *cur << '\n');
1211 SmallVector<LiveInterval*, 8> spillIs;
1212 std::vector<LiveInterval*> added;
1214 added = spiller_->spill(cur, spillIs);
1216 std::sort(added.begin(), added.end(), LISorter());
1217 addStackInterval(cur, ls_, li_, mri_, *vrm_);
1219 return; // Early exit if all spills were folded.
1221 // Merge added with unhandled. Note that we have already sorted
1222 // intervals returned by addIntervalsForSpills by their starting
1224 // This also update the NextReloadMap. That is, it adds mapping from a
1225 // register defined by a reload from SS to the next reload from SS in the
1226 // same basic block.
1227 MachineBasicBlock *LastReloadMBB = 0;
1228 LiveInterval *LastReload = 0;
1229 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1230 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1231 LiveInterval *ReloadLi = added[i];
1232 if (ReloadLi->weight == HUGE_VALF &&
1233 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1234 SlotIndex ReloadIdx = ReloadLi->beginIndex();
1235 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1236 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1237 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1238 // Last reload of same SS is in the same MBB. We want to try to
1239 // allocate both reloads the same register and make sure the reg
1240 // isn't clobbered in between if at all possible.
1241 assert(LastReload->beginIndex() < ReloadIdx);
1242 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1244 LastReloadMBB = ReloadMBB;
1245 LastReload = ReloadLi;
1246 LastReloadSS = ReloadSS;
1248 unhandled_.push(ReloadLi);
1255 // Push the current interval back to unhandled since we are going
1256 // to re-run at least this iteration. Since we didn't modify it it
1257 // should go back right in the front of the list
1258 unhandled_.push(cur);
1260 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
1261 "did not choose a register to spill?");
1263 // We spill all intervals aliasing the register with
1264 // minimum weight, rollback to the interval with the earliest
1265 // start point and let the linear scan algorithm run again
1266 SmallVector<LiveInterval*, 8> spillIs;
1268 // Determine which intervals have to be spilled.
1269 findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
1271 // Set of spilled vregs (used later to rollback properly)
1272 SmallSet<unsigned, 8> spilled;
1274 // The earliest start of a Spilled interval indicates up to where
1275 // in handled we need to roll back
1276 assert(!spillIs.empty() && "No spill intervals?");
1277 SlotIndex earliestStart = spillIs[0]->beginIndex();
1279 // Spill live intervals of virtual regs mapped to the physical register we
1280 // want to clear (and its aliases). We only spill those that overlap with the
1281 // current interval as the rest do not affect its allocation. we also keep
1282 // track of the earliest start of all spilled live intervals since this will
1283 // mark our rollback point.
1284 std::vector<LiveInterval*> added;
1285 while (!spillIs.empty()) {
1286 LiveInterval *sli = spillIs.back();
1288 DEBUG(dbgs() << "\t\t\tspilling(a): " << *sli << '\n');
1289 if (sli->beginIndex() < earliestStart)
1290 earliestStart = sli->beginIndex();
1292 std::vector<LiveInterval*> newIs;
1293 newIs = spiller_->spill(sli, spillIs, &earliestStart);
1294 addStackInterval(sli, ls_, li_, mri_, *vrm_);
1295 std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
1296 spilled.insert(sli->reg);
1299 DEBUG(dbgs() << "\t\trolling back to: " << earliestStart << '\n');
1301 // Scan handled in reverse order up to the earliest start of a
1302 // spilled live interval and undo each one, restoring the state of
1304 while (!handled_.empty()) {
1305 LiveInterval* i = handled_.back();
1306 // If this interval starts before t we are done.
1307 if (!i->empty() && i->beginIndex() < earliestStart)
1309 DEBUG(dbgs() << "\t\t\tundo changes for: " << *i << '\n');
1310 handled_.pop_back();
1312 // When undoing a live interval allocation we must know if it is active or
1313 // inactive to properly update regUse_ and the VirtRegMap.
1314 IntervalPtrs::iterator it;
1315 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
1317 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1318 if (!spilled.count(i->reg))
1320 delRegUse(vrm_->getPhys(i->reg));
1321 vrm_->clearVirt(i->reg);
1322 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
1323 inactive_.erase(it);
1324 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1325 if (!spilled.count(i->reg))
1327 vrm_->clearVirt(i->reg);
1329 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
1330 "Can only allocate virtual registers!");
1331 vrm_->clearVirt(i->reg);
1335 DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
1336 if (ii == DowngradeMap.end())
1337 // It interval has a preference, it must be defined by a copy. Clear the
1338 // preference now since the source interval allocation may have been
1340 mri_->setRegAllocationHint(i->reg, 0, 0);
1342 UpgradeRegister(ii->second);
1346 // Rewind the iterators in the active, inactive, and fixed lists back to the
1347 // point we reverted to.
1348 RevertVectorIteratorsTo(active_, earliestStart);
1349 RevertVectorIteratorsTo(inactive_, earliestStart);
1350 RevertVectorIteratorsTo(fixed_, earliestStart);
1352 // Scan the rest and undo each interval that expired after t and
1353 // insert it in active (the next iteration of the algorithm will
1354 // put it in inactive if required)
1355 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
1356 LiveInterval *HI = handled_[i];
1357 if (!HI->expiredAt(earliestStart) &&
1358 HI->expiredAt(cur->beginIndex())) {
1359 DEBUG(dbgs() << "\t\t\tundo changes for: " << *HI << '\n');
1360 active_.push_back(std::make_pair(HI, HI->begin()));
1361 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
1362 addRegUse(vrm_->getPhys(HI->reg));
1366 // Merge added with unhandled.
1367 // This also update the NextReloadMap. That is, it adds mapping from a
1368 // register defined by a reload from SS to the next reload from SS in the
1369 // same basic block.
1370 MachineBasicBlock *LastReloadMBB = 0;
1371 LiveInterval *LastReload = 0;
1372 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1373 std::sort(added.begin(), added.end(), LISorter());
1374 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1375 LiveInterval *ReloadLi = added[i];
1376 if (ReloadLi->weight == HUGE_VALF &&
1377 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1378 SlotIndex ReloadIdx = ReloadLi->beginIndex();
1379 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1380 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1381 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1382 // Last reload of same SS is in the same MBB. We want to try to
1383 // allocate both reloads the same register and make sure the reg
1384 // isn't clobbered in between if at all possible.
1385 assert(LastReload->beginIndex() < ReloadIdx);
1386 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1388 LastReloadMBB = ReloadMBB;
1389 LastReload = ReloadLi;
1390 LastReloadSS = ReloadSS;
1392 unhandled_.push(ReloadLi);
1396 unsigned RALinScan::getFreePhysReg(LiveInterval* cur,
1397 const TargetRegisterClass *RC,
1398 unsigned MaxInactiveCount,
1399 SmallVector<unsigned, 256> &inactiveCounts,
1401 unsigned FreeReg = 0;
1402 unsigned FreeRegInactiveCount = 0;
1404 std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(cur->reg);
1405 // Resolve second part of the hint (if possible) given the current allocation.
1406 unsigned physReg = Hint.second;
1408 TargetRegisterInfo::isVirtualRegister(physReg) && vrm_->hasPhys(physReg))
1409 physReg = vrm_->getPhys(physReg);
1411 TargetRegisterClass::iterator I, E;
1412 tie(I, E) = tri_->getAllocationOrder(RC, Hint.first, physReg, *mf_);
1413 assert(I != E && "No allocatable register in this register class!");
1415 // Scan for the first available register.
1416 for (; I != E; ++I) {
1418 // Ignore "downgraded" registers.
1419 if (SkipDGRegs && DowngradedRegs.count(Reg))
1421 // Skip recently allocated registers.
1422 if (isRegAvail(Reg) && !isRecentlyUsed(Reg)) {
1424 if (FreeReg < inactiveCounts.size())
1425 FreeRegInactiveCount = inactiveCounts[FreeReg];
1427 FreeRegInactiveCount = 0;
1432 // If there are no free regs, or if this reg has the max inactive count,
1433 // return this register.
1434 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount) {
1435 // Remember what register we picked so we can skip it next time.
1436 if (FreeReg != 0) recordRecentlyUsed(FreeReg);
1440 // Continue scanning the registers, looking for the one with the highest
1441 // inactive count. Alkis found that this reduced register pressure very
1442 // slightly on X86 (in rev 1.94 of this file), though this should probably be
1444 for (; I != E; ++I) {
1446 // Ignore "downgraded" registers.
1447 if (SkipDGRegs && DowngradedRegs.count(Reg))
1449 if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
1450 FreeRegInactiveCount < inactiveCounts[Reg] && !isRecentlyUsed(Reg)) {
1452 FreeRegInactiveCount = inactiveCounts[Reg];
1453 if (FreeRegInactiveCount == MaxInactiveCount)
1454 break; // We found the one with the max inactive count.
1458 // Remember what register we picked so we can skip it next time.
1459 recordRecentlyUsed(FreeReg);
1464 /// getFreePhysReg - return a free physical register for this virtual register
1465 /// interval if we have one, otherwise return 0.
1466 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
1467 SmallVector<unsigned, 256> inactiveCounts;
1468 unsigned MaxInactiveCount = 0;
1470 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
1471 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1473 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
1475 unsigned reg = i->first->reg;
1476 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1477 "Can only allocate virtual registers!");
1479 // If this is not in a related reg class to the register we're allocating,
1481 const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
1482 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
1483 reg = vrm_->getPhys(reg);
1484 if (inactiveCounts.size() <= reg)
1485 inactiveCounts.resize(reg+1);
1486 ++inactiveCounts[reg];
1487 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
1491 // If copy coalescer has assigned a "preferred" register, check if it's
1493 unsigned Preference = vrm_->getRegAllocPref(cur->reg);
1495 DEBUG(dbgs() << "(preferred: " << tri_->getName(Preference) << ") ");
1496 if (isRegAvail(Preference) &&
1497 RC->contains(Preference))
1501 if (!DowngradedRegs.empty()) {
1502 unsigned FreeReg = getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts,
1507 return getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts, false);
1510 FunctionPass* llvm::createLinearScanRegisterAllocator() {
1511 return new RALinScan();