1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "VirtRegMap.h"
16 #include "VirtRegRewriter.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/CalcSpillWeights.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/LiveStackAnalysis.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/MachineLoopInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/RegAllocRegistry.h"
28 #include "llvm/CodeGen/RegisterCoalescer.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/ADT/EquivalenceClasses.h"
34 #include "llvm/ADT/SmallSet.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/ADT/STLExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
48 STATISTIC(NumIters , "Number of iterations performed");
49 STATISTIC(NumBacktracks, "Number of times we had to backtrack");
50 STATISTIC(NumCoalesce, "Number of copies coalesced");
51 STATISTIC(NumDowngrade, "Number of registers downgraded");
54 NewHeuristic("new-spilling-heuristic",
55 cl::desc("Use new spilling heuristic"),
56 cl::init(false), cl::Hidden);
59 PreSplitIntervals("pre-alloc-split",
60 cl::desc("Pre-register allocation live interval splitting"),
61 cl::init(false), cl::Hidden);
64 TrivCoalesceEnds("trivial-coalesce-ends",
65 cl::desc("Attempt trivial coalescing of interval ends"),
66 cl::init(false), cl::Hidden);
68 static RegisterRegAlloc
69 linearscanRegAlloc("linearscan", "linear scan register allocator",
70 createLinearScanRegisterAllocator);
73 // When we allocate a register, add it to a fixed-size queue of
74 // registers to skip in subsequent allocations. This trades a small
75 // amount of register pressure and increased spills for flexibility in
76 // the post-pass scheduler.
78 // Note that in a the number of registers used for reloading spills
79 // will be one greater than the value of this option.
81 // One big limitation of this is that it doesn't differentiate between
82 // different register classes. So on x86-64, if there is xmm register
83 // pressure, it can caused fewer GPRs to be held in the queue.
84 static cl::opt<unsigned>
85 NumRecentlyUsedRegs("linearscan-skip-count",
86 cl::desc("Number of registers for linearscan to remember"
91 struct RALinScan : public MachineFunctionPass {
93 RALinScan() : MachineFunctionPass(ID) {
94 // Initialize the queue to record recently-used registers.
95 if (NumRecentlyUsedRegs > 0)
96 RecentRegs.resize(NumRecentlyUsedRegs, 0);
97 RecentNext = RecentRegs.begin();
100 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
101 typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
103 /// RelatedRegClasses - This structure is built the first time a function is
104 /// compiled, and keeps track of which register classes have registers that
105 /// belong to multiple classes or have aliases that are in other classes.
106 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
107 DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
109 // NextReloadMap - For each register in the map, it maps to the another
110 // register which is defined by a reload from the same stack slot and
111 // both reloads are in the same basic block.
112 DenseMap<unsigned, unsigned> NextReloadMap;
114 // DowngradedRegs - A set of registers which are being "downgraded", i.e.
115 // un-favored for allocation.
116 SmallSet<unsigned, 8> DowngradedRegs;
118 // DowngradeMap - A map from virtual registers to physical registers being
119 // downgraded for the virtual registers.
120 DenseMap<unsigned, unsigned> DowngradeMap;
122 MachineFunction* mf_;
123 MachineRegisterInfo* mri_;
124 const TargetMachine* tm_;
125 const TargetRegisterInfo* tri_;
126 const TargetInstrInfo* tii_;
127 BitVector allocatableRegs_;
128 BitVector reservedRegs_;
131 MachineLoopInfo *loopInfo;
133 /// handled_ - Intervals are added to the handled_ set in the order of their
134 /// start value. This is uses for backtracking.
135 std::vector<LiveInterval*> handled_;
137 /// fixed_ - Intervals that correspond to machine registers.
141 /// active_ - Intervals that are currently being processed, and which have a
142 /// live range active for the current point.
143 IntervalPtrs active_;
145 /// inactive_ - Intervals that are currently being processed, but which have
146 /// a hold at the current point.
147 IntervalPtrs inactive_;
149 typedef std::priority_queue<LiveInterval*,
150 SmallVector<LiveInterval*, 64>,
151 greater_ptr<LiveInterval> > IntervalHeap;
152 IntervalHeap unhandled_;
154 /// regUse_ - Tracks register usage.
155 SmallVector<unsigned, 32> regUse_;
156 SmallVector<unsigned, 32> regUseBackUp_;
158 /// vrm_ - Tracks register assignments.
161 std::auto_ptr<VirtRegRewriter> rewriter_;
163 std::auto_ptr<Spiller> spiller_;
165 // The queue of recently-used registers.
166 SmallVector<unsigned, 4> RecentRegs;
167 SmallVector<unsigned, 4>::iterator RecentNext;
169 // Record that we just picked this register.
170 void recordRecentlyUsed(unsigned reg) {
171 assert(reg != 0 && "Recently used register is NOREG!");
172 if (!RecentRegs.empty()) {
174 if (RecentNext == RecentRegs.end())
175 RecentNext = RecentRegs.begin();
180 virtual const char* getPassName() const {
181 return "Linear Scan Register Allocator";
184 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
185 AU.setPreservesCFG();
186 AU.addRequired<LiveIntervals>();
187 AU.addPreserved<SlotIndexes>();
189 AU.addRequiredID(StrongPHIEliminationID);
190 // Make sure PassManager knows which analyses to make available
191 // to coalescing and which analyses coalescing invalidates.
192 AU.addRequiredTransitive<RegisterCoalescer>();
193 AU.addRequired<CalculateSpillWeights>();
194 if (PreSplitIntervals)
195 AU.addRequiredID(PreAllocSplittingID);
196 AU.addRequired<LiveStacks>();
197 AU.addPreserved<LiveStacks>();
198 AU.addRequired<MachineLoopInfo>();
199 AU.addPreserved<MachineLoopInfo>();
200 AU.addRequired<VirtRegMap>();
201 AU.addPreserved<VirtRegMap>();
202 AU.addPreservedID(MachineDominatorsID);
203 MachineFunctionPass::getAnalysisUsage(AU);
206 /// runOnMachineFunction - register allocate the whole function
207 bool runOnMachineFunction(MachineFunction&);
209 // Determine if we skip this register due to its being recently used.
210 bool isRecentlyUsed(unsigned reg) const {
211 return std::find(RecentRegs.begin(), RecentRegs.end(), reg) !=
216 /// linearScan - the linear scan algorithm
219 /// initIntervalSets - initialize the interval sets.
221 void initIntervalSets();
223 /// processActiveIntervals - expire old intervals and move non-overlapping
224 /// ones to the inactive list.
225 void processActiveIntervals(SlotIndex CurPoint);
227 /// processInactiveIntervals - expire old intervals and move overlapping
228 /// ones to the active list.
229 void processInactiveIntervals(SlotIndex CurPoint);
231 /// hasNextReloadInterval - Return the next liveinterval that's being
232 /// defined by a reload from the same SS as the specified one.
233 LiveInterval *hasNextReloadInterval(LiveInterval *cur);
235 /// DowngradeRegister - Downgrade a register for allocation.
236 void DowngradeRegister(LiveInterval *li, unsigned Reg);
238 /// UpgradeRegister - Upgrade a register for allocation.
239 void UpgradeRegister(unsigned Reg);
241 /// assignRegOrStackSlotAtInterval - assign a register if one
242 /// is available, or spill.
243 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
245 void updateSpillWeights(std::vector<float> &Weights,
246 unsigned reg, float weight,
247 const TargetRegisterClass *RC);
249 /// findIntervalsToSpill - Determine the intervals to spill for the
250 /// specified interval. It's passed the physical registers whose spill
251 /// weight is the lowest among all the registers whose live intervals
252 /// conflict with the interval.
253 void findIntervalsToSpill(LiveInterval *cur,
254 std::vector<std::pair<unsigned,float> > &Candidates,
256 SmallVector<LiveInterval*, 8> &SpillIntervals);
258 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
259 /// try to allocate the definition to the same register as the source,
260 /// if the register is not defined during the life time of the interval.
261 /// This eliminates a copy, and is used to coalesce copies which were not
262 /// coalesced away before allocation either due to dest and src being in
263 /// different register classes or because the coalescer was overly
265 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
268 /// Register usage / availability tracking helpers.
272 regUse_.resize(tri_->getNumRegs(), 0);
273 regUseBackUp_.resize(tri_->getNumRegs(), 0);
276 void finalizeRegUses() {
278 // Verify all the registers are "freed".
280 for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
281 if (regUse_[i] != 0) {
282 dbgs() << tri_->getName(i) << " is still in use!\n";
290 regUseBackUp_.clear();
293 void addRegUse(unsigned physReg) {
294 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
295 "should be physical register!");
297 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
301 void delRegUse(unsigned physReg) {
302 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
303 "should be physical register!");
304 assert(regUse_[physReg] != 0);
306 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
307 assert(regUse_[*as] != 0);
312 bool isRegAvail(unsigned physReg) const {
313 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
314 "should be physical register!");
315 return regUse_[physReg] == 0;
318 void backUpRegUses() {
319 regUseBackUp_ = regUse_;
322 void restoreRegUses() {
323 regUse_ = regUseBackUp_;
327 /// Register handling helpers.
330 /// getFreePhysReg - return a free physical register for this virtual
331 /// register interval if we have one, otherwise return 0.
332 unsigned getFreePhysReg(LiveInterval* cur);
333 unsigned getFreePhysReg(LiveInterval* cur,
334 const TargetRegisterClass *RC,
335 unsigned MaxInactiveCount,
336 SmallVector<unsigned, 256> &inactiveCounts,
339 void ComputeRelatedRegClasses();
341 template <typename ItTy>
342 void printIntervals(const char* const str, ItTy i, ItTy e) const {
345 dbgs() << str << " intervals:\n";
347 for (; i != e; ++i) {
348 dbgs() << "\t" << *i->first << " -> ";
350 unsigned reg = i->first->reg;
351 if (TargetRegisterInfo::isVirtualRegister(reg))
352 reg = vrm_->getPhys(reg);
354 dbgs() << tri_->getName(reg) << '\n';
359 char RALinScan::ID = 0;
362 INITIALIZE_PASS(RALinScan, "linearscan-regalloc",
363 "Linear Scan Register Allocator", false, false);
365 void RALinScan::ComputeRelatedRegClasses() {
366 // First pass, add all reg classes to the union, and determine at least one
367 // reg class that each register is in.
368 bool HasAliases = false;
369 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
370 E = tri_->regclass_end(); RCI != E; ++RCI) {
371 RelatedRegClasses.insert(*RCI);
372 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
374 HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
376 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
378 // Already processed this register. Just make sure we know that
379 // multiple register classes share a register.
380 RelatedRegClasses.unionSets(PRC, *RCI);
387 // Second pass, now that we know conservatively what register classes each reg
388 // belongs to, add info about aliases. We don't need to do this for targets
389 // without register aliases.
391 for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
392 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
394 for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
395 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
398 /// attemptTrivialCoalescing - If a simple interval is defined by a copy, try
399 /// allocate the definition the same register as the source register if the
400 /// register is not defined during live time of the interval. If the interval is
401 /// killed by a copy, try to use the destination register. This eliminates a
402 /// copy. This is used to coalesce copies which were not coalesced away before
403 /// allocation either due to dest and src being in different register classes or
404 /// because the coalescer was overly conservative.
405 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
406 unsigned Preference = vrm_->getRegAllocPref(cur.reg);
407 if ((Preference && Preference == Reg) || !cur.containsOneValue())
410 // We cannot handle complicated live ranges. Simple linear stuff only.
411 if (cur.ranges.size() != 1)
414 const LiveRange &range = cur.ranges.front();
416 VNInfo *vni = range.valno;
422 MachineInstr *CopyMI;
423 if (vni->def != SlotIndex() && vni->isDefAccurate() &&
424 (CopyMI = li_->getInstructionFromIndex(vni->def)) && CopyMI->isCopy())
425 // Defined by a copy, try to extend SrcReg forward
426 CandReg = CopyMI->getOperand(1).getReg();
427 else if (TrivCoalesceEnds &&
428 (CopyMI = li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
429 CopyMI->isCopy() && cur.reg == CopyMI->getOperand(1).getReg())
430 // Only used by a copy, try to extend DstReg backwards
431 CandReg = CopyMI->getOperand(0).getReg();
436 if (TargetRegisterInfo::isVirtualRegister(CandReg)) {
437 if (!vrm_->isAssignedReg(CandReg))
439 CandReg = vrm_->getPhys(CandReg);
444 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
445 if (!RC->contains(CandReg))
448 if (li_->conflictsWithPhysReg(cur, *vrm_, CandReg))
452 DEBUG(dbgs() << "Coalescing: " << cur << " -> " << tri_->getName(CandReg)
454 vrm_->clearVirt(cur.reg);
455 vrm_->assignVirt2Phys(cur.reg, CandReg);
461 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
463 mri_ = &fn.getRegInfo();
464 tm_ = &fn.getTarget();
465 tri_ = tm_->getRegisterInfo();
466 tii_ = tm_->getInstrInfo();
467 allocatableRegs_ = tri_->getAllocatableSet(fn);
468 reservedRegs_ = tri_->getReservedRegs(fn);
469 li_ = &getAnalysis<LiveIntervals>();
470 ls_ = &getAnalysis<LiveStacks>();
471 loopInfo = &getAnalysis<MachineLoopInfo>();
473 // We don't run the coalescer here because we have no reason to
474 // interact with it. If the coalescer requires interaction, it
475 // won't do anything. If it doesn't require interaction, we assume
476 // it was run as a separate pass.
478 // If this is the first function compiled, compute the related reg classes.
479 if (RelatedRegClasses.empty())
480 ComputeRelatedRegClasses();
482 // Also resize register usage trackers.
485 vrm_ = &getAnalysis<VirtRegMap>();
486 if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
488 spiller_.reset(createSpiller(*this, *mf_, *vrm_));
494 // Rewrite spill code and update the PhysRegsUsed set.
495 rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
497 assert(unhandled_.empty() && "Unhandled live intervals remain!");
505 NextReloadMap.clear();
506 DowngradedRegs.clear();
507 DowngradeMap.clear();
513 /// initIntervalSets - initialize the interval sets.
515 void RALinScan::initIntervalSets()
517 assert(unhandled_.empty() && fixed_.empty() &&
518 active_.empty() && inactive_.empty() &&
519 "interval sets should be empty on initialization");
521 handled_.reserve(li_->getNumIntervals());
523 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
524 if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
525 if (!i->second->empty()) {
526 mri_->setPhysRegUsed(i->second->reg);
527 fixed_.push_back(std::make_pair(i->second, i->second->begin()));
530 if (i->second->empty()) {
531 assignRegOrStackSlotAtInterval(i->second);
534 unhandled_.push(i->second);
539 void RALinScan::linearScan() {
540 // linear scan algorithm
542 dbgs() << "********** LINEAR SCAN **********\n"
543 << "********** Function: "
544 << mf_->getFunction()->getName() << '\n';
545 printIntervals("fixed", fixed_.begin(), fixed_.end());
548 while (!unhandled_.empty()) {
549 // pick the interval with the earliest start point
550 LiveInterval* cur = unhandled_.top();
553 DEBUG(dbgs() << "\n*** CURRENT ***: " << *cur << '\n');
555 assert(!cur->empty() && "Empty interval in unhandled set.");
557 processActiveIntervals(cur->beginIndex());
558 processInactiveIntervals(cur->beginIndex());
560 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
561 "Can only allocate virtual registers!");
563 // Allocating a virtual register. try to find a free
564 // physical register or spill an interval (possibly this one) in order to
566 assignRegOrStackSlotAtInterval(cur);
569 printIntervals("active", active_.begin(), active_.end());
570 printIntervals("inactive", inactive_.begin(), inactive_.end());
574 // Expire any remaining active intervals
575 while (!active_.empty()) {
576 IntervalPtr &IP = active_.back();
577 unsigned reg = IP.first->reg;
578 DEBUG(dbgs() << "\tinterval " << *IP.first << " expired\n");
579 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
580 "Can only allocate virtual registers!");
581 reg = vrm_->getPhys(reg);
586 // Expire any remaining inactive intervals
588 for (IntervalPtrs::reverse_iterator
589 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
590 dbgs() << "\tinterval " << *i->first << " expired\n";
594 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
595 MachineFunction::iterator EntryMBB = mf_->begin();
596 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
597 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
598 LiveInterval &cur = *i->second;
600 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
603 else if (vrm_->isAssignedReg(cur.reg))
604 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
607 // Ignore splited live intervals.
608 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
611 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
613 const LiveRange &LR = *I;
614 if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
615 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
616 if (LiveInMBBs[i] != EntryMBB) {
617 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
618 "Adding a virtual register to livein set?");
619 LiveInMBBs[i]->addLiveIn(Reg);
626 DEBUG(dbgs() << *vrm_);
628 // Look for physical registers that end up not being allocated even though
629 // register allocator had to spill other registers in its register class.
630 if (ls_->getNumIntervals() == 0)
632 if (!vrm_->FindUnusedRegisters(li_))
636 /// processActiveIntervals - expire old intervals and move non-overlapping ones
637 /// to the inactive list.
638 void RALinScan::processActiveIntervals(SlotIndex CurPoint)
640 DEBUG(dbgs() << "\tprocessing active intervals:\n");
642 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
643 LiveInterval *Interval = active_[i].first;
644 LiveInterval::iterator IntervalPos = active_[i].second;
645 unsigned reg = Interval->reg;
647 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
649 if (IntervalPos == Interval->end()) { // Remove expired intervals.
650 DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
651 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
652 "Can only allocate virtual registers!");
653 reg = vrm_->getPhys(reg);
656 // Pop off the end of the list.
657 active_[i] = active_.back();
661 } else if (IntervalPos->start > CurPoint) {
662 // Move inactive intervals to inactive list.
663 DEBUG(dbgs() << "\t\tinterval " << *Interval << " inactive\n");
664 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
665 "Can only allocate virtual registers!");
666 reg = vrm_->getPhys(reg);
669 inactive_.push_back(std::make_pair(Interval, IntervalPos));
671 // Pop off the end of the list.
672 active_[i] = active_.back();
676 // Otherwise, just update the iterator position.
677 active_[i].second = IntervalPos;
682 /// processInactiveIntervals - expire old intervals and move overlapping
683 /// ones to the active list.
684 void RALinScan::processInactiveIntervals(SlotIndex CurPoint)
686 DEBUG(dbgs() << "\tprocessing inactive intervals:\n");
688 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
689 LiveInterval *Interval = inactive_[i].first;
690 LiveInterval::iterator IntervalPos = inactive_[i].second;
691 unsigned reg = Interval->reg;
693 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
695 if (IntervalPos == Interval->end()) { // remove expired intervals.
696 DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
698 // Pop off the end of the list.
699 inactive_[i] = inactive_.back();
700 inactive_.pop_back();
702 } else if (IntervalPos->start <= CurPoint) {
703 // move re-activated intervals in active list
704 DEBUG(dbgs() << "\t\tinterval " << *Interval << " active\n");
705 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
706 "Can only allocate virtual registers!");
707 reg = vrm_->getPhys(reg);
710 active_.push_back(std::make_pair(Interval, IntervalPos));
712 // Pop off the end of the list.
713 inactive_[i] = inactive_.back();
714 inactive_.pop_back();
717 // Otherwise, just update the iterator position.
718 inactive_[i].second = IntervalPos;
723 /// updateSpillWeights - updates the spill weights of the specifed physical
724 /// register and its weight.
725 void RALinScan::updateSpillWeights(std::vector<float> &Weights,
726 unsigned reg, float weight,
727 const TargetRegisterClass *RC) {
728 SmallSet<unsigned, 4> Processed;
729 SmallSet<unsigned, 4> SuperAdded;
730 SmallVector<unsigned, 4> Supers;
731 Weights[reg] += weight;
732 Processed.insert(reg);
733 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
734 Weights[*as] += weight;
735 Processed.insert(*as);
736 if (tri_->isSubRegister(*as, reg) &&
737 SuperAdded.insert(*as) &&
739 Supers.push_back(*as);
743 // If the alias is a super-register, and the super-register is in the
744 // register class we are trying to allocate. Then add the weight to all
745 // sub-registers of the super-register even if they are not aliases.
746 // e.g. allocating for GR32, bh is not used, updating bl spill weight.
747 // bl should get the same spill weight otherwise it will be choosen
748 // as a spill candidate since spilling bh doesn't make ebx available.
749 for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
750 for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
751 if (!Processed.count(*sr))
752 Weights[*sr] += weight;
757 RALinScan::IntervalPtrs::iterator
758 FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
759 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
761 if (I->first == LI) return I;
765 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, SlotIndex Point){
766 for (unsigned i = 0, e = V.size(); i != e; ++i) {
767 RALinScan::IntervalPtr &IP = V[i];
768 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
770 if (I != IP.first->begin()) --I;
775 /// addStackInterval - Create a LiveInterval for stack if the specified live
776 /// interval has been spilled.
777 static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
779 MachineRegisterInfo* mri_, VirtRegMap &vrm_) {
780 int SS = vrm_.getStackSlot(cur->reg);
781 if (SS == VirtRegMap::NO_STACK_SLOT)
784 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
785 LiveInterval &SI = ls_->getOrCreateInterval(SS, RC);
788 if (SI.hasAtLeastOneValue())
789 VNI = SI.getValNumInfo(0);
791 VNI = SI.getNextValue(SlotIndex(), 0, false,
792 ls_->getVNInfoAllocator());
794 LiveInterval &RI = li_->getInterval(cur->reg);
795 // FIXME: This may be overly conservative.
796 SI.MergeRangesInAsValue(RI, VNI);
799 /// getConflictWeight - Return the number of conflicts between cur
800 /// live interval and defs and uses of Reg weighted by loop depthes.
802 float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
803 MachineRegisterInfo *mri_,
804 MachineLoopInfo *loopInfo) {
806 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
807 E = mri_->reg_end(); I != E; ++I) {
808 MachineInstr *MI = &*I;
809 if (cur->liveAt(li_->getInstructionIndex(MI))) {
810 unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
811 Conflicts += std::pow(10.0f, (float)loopDepth);
817 /// findIntervalsToSpill - Determine the intervals to spill for the
818 /// specified interval. It's passed the physical registers whose spill
819 /// weight is the lowest among all the registers whose live intervals
820 /// conflict with the interval.
821 void RALinScan::findIntervalsToSpill(LiveInterval *cur,
822 std::vector<std::pair<unsigned,float> > &Candidates,
824 SmallVector<LiveInterval*, 8> &SpillIntervals) {
825 // We have figured out the *best* register to spill. But there are other
826 // registers that are pretty good as well (spill weight within 3%). Spill
827 // the one that has fewest defs and uses that conflict with cur.
828 float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
829 SmallVector<LiveInterval*, 8> SLIs[3];
832 dbgs() << "\tConsidering " << NumCands << " candidates: ";
833 for (unsigned i = 0; i != NumCands; ++i)
834 dbgs() << tri_->getName(Candidates[i].first) << " ";
838 // Calculate the number of conflicts of each candidate.
839 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
840 unsigned Reg = i->first->reg;
841 unsigned PhysReg = vrm_->getPhys(Reg);
842 if (!cur->overlapsFrom(*i->first, i->second))
844 for (unsigned j = 0; j < NumCands; ++j) {
845 unsigned Candidate = Candidates[j].first;
846 if (tri_->regsOverlap(PhysReg, Candidate)) {
848 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
849 SLIs[j].push_back(i->first);
854 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
855 unsigned Reg = i->first->reg;
856 unsigned PhysReg = vrm_->getPhys(Reg);
857 if (!cur->overlapsFrom(*i->first, i->second-1))
859 for (unsigned j = 0; j < NumCands; ++j) {
860 unsigned Candidate = Candidates[j].first;
861 if (tri_->regsOverlap(PhysReg, Candidate)) {
863 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
864 SLIs[j].push_back(i->first);
869 // Which is the best candidate?
870 unsigned BestCandidate = 0;
871 float MinConflicts = Conflicts[0];
872 for (unsigned i = 1; i != NumCands; ++i) {
873 if (Conflicts[i] < MinConflicts) {
875 MinConflicts = Conflicts[i];
879 std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
880 std::back_inserter(SpillIntervals));
884 struct WeightCompare {
886 const RALinScan &Allocator;
889 WeightCompare(const RALinScan &Alloc) : Allocator(Alloc) {}
891 typedef std::pair<unsigned, float> RegWeightPair;
892 bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
893 return LHS.second < RHS.second && !Allocator.isRecentlyUsed(LHS.first);
898 static bool weightsAreClose(float w1, float w2) {
902 float diff = w1 - w2;
903 if (diff <= 0.02f) // Within 0.02f
905 return (diff / w2) <= 0.05f; // Within 5%.
908 LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
909 DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
910 if (I == NextReloadMap.end())
912 return &li_->getInterval(I->second);
915 void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
916 bool isNew = DowngradedRegs.insert(Reg);
917 isNew = isNew; // Silence compiler warning.
918 assert(isNew && "Multiple reloads holding the same register?");
919 DowngradeMap.insert(std::make_pair(li->reg, Reg));
920 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS) {
921 isNew = DowngradedRegs.insert(*AS);
922 isNew = isNew; // Silence compiler warning.
923 assert(isNew && "Multiple reloads holding the same register?");
924 DowngradeMap.insert(std::make_pair(li->reg, *AS));
929 void RALinScan::UpgradeRegister(unsigned Reg) {
931 DowngradedRegs.erase(Reg);
932 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
933 DowngradedRegs.erase(*AS);
939 bool operator()(LiveInterval* A, LiveInterval* B) {
940 return A->beginIndex() < B->beginIndex();
945 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
947 void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
948 DEBUG(dbgs() << "\tallocating current interval: ");
950 // This is an implicitly defined live interval, just assign any register.
951 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
953 unsigned physReg = vrm_->getRegAllocPref(cur->reg);
955 TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_);
956 TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_);
957 while (reservedRegs_.test(*i) && i != aoe)
959 assert(i != aoe && "All registers reserved?!");
962 DEBUG(dbgs() << tri_->getName(physReg) << '\n');
963 // Note the register is not really in use.
964 vrm_->assignVirt2Phys(cur->reg, physReg);
970 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
971 SlotIndex StartPosition = cur->beginIndex();
972 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
974 // If start of this live interval is defined by a move instruction and its
975 // source is assigned a physical register that is compatible with the target
976 // register class, then we should try to assign it the same register.
977 // This can happen when the move is from a larger register class to a smaller
978 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
979 if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
980 VNInfo *vni = cur->begin()->valno;
981 if ((vni->def != SlotIndex()) && !vni->isUnused() &&
982 vni->isDefAccurate()) {
983 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
984 if (CopyMI && CopyMI->isCopy()) {
985 unsigned DstSubReg = CopyMI->getOperand(0).getSubReg();
986 unsigned SrcReg = CopyMI->getOperand(1).getReg();
987 unsigned SrcSubReg = CopyMI->getOperand(1).getSubReg();
989 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
991 else if (vrm_->isAssignedReg(SrcReg))
992 Reg = vrm_->getPhys(SrcReg);
995 Reg = tri_->getSubReg(Reg, SrcSubReg);
997 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
998 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
999 mri_->setRegAllocationHint(cur->reg, 0, Reg);
1005 // For every interval in inactive we overlap with, mark the
1006 // register as not free and update spill weights.
1007 for (IntervalPtrs::const_iterator i = inactive_.begin(),
1008 e = inactive_.end(); i != e; ++i) {
1009 unsigned Reg = i->first->reg;
1010 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
1011 "Can only allocate virtual registers!");
1012 const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
1013 // If this is not in a related reg class to the register we're allocating,
1015 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1016 cur->overlapsFrom(*i->first, i->second-1)) {
1017 Reg = vrm_->getPhys(Reg);
1019 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
1023 // Speculatively check to see if we can get a register right now. If not,
1024 // we know we won't be able to by adding more constraints. If so, we can
1025 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
1026 // is very bad (it contains all callee clobbered registers for any functions
1027 // with a call), so we want to avoid doing that if possible.
1028 unsigned physReg = getFreePhysReg(cur);
1029 unsigned BestPhysReg = physReg;
1031 // We got a register. However, if it's in the fixed_ list, we might
1032 // conflict with it. Check to see if we conflict with it or any of its
1034 SmallSet<unsigned, 8> RegAliases;
1035 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
1036 RegAliases.insert(*AS);
1038 bool ConflictsWithFixed = false;
1039 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1040 IntervalPtr &IP = fixed_[i];
1041 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
1042 // Okay, this reg is on the fixed list. Check to see if we actually
1044 LiveInterval *I = IP.first;
1045 if (I->endIndex() > StartPosition) {
1046 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1048 if (II != I->begin() && II->start > StartPosition)
1050 if (cur->overlapsFrom(*I, II)) {
1051 ConflictsWithFixed = true;
1058 // Okay, the register picked by our speculative getFreePhysReg call turned
1059 // out to be in use. Actually add all of the conflicting fixed registers to
1060 // regUse_ so we can do an accurate query.
1061 if (ConflictsWithFixed) {
1062 // For every interval in fixed we overlap with, mark the register as not
1063 // free and update spill weights.
1064 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1065 IntervalPtr &IP = fixed_[i];
1066 LiveInterval *I = IP.first;
1068 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
1069 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1070 I->endIndex() > StartPosition) {
1071 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1073 if (II != I->begin() && II->start > StartPosition)
1075 if (cur->overlapsFrom(*I, II)) {
1076 unsigned reg = I->reg;
1078 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
1083 // Using the newly updated regUse_ object, which includes conflicts in the
1084 // future, see if there are any registers available.
1085 physReg = getFreePhysReg(cur);
1089 // Restore the physical register tracker, removing information about the
1093 // If we find a free register, we are done: assign this virtual to
1094 // the free physical register and add this interval to the active
1097 DEBUG(dbgs() << tri_->getName(physReg) << '\n');
1098 vrm_->assignVirt2Phys(cur->reg, physReg);
1100 active_.push_back(std::make_pair(cur, cur->begin()));
1101 handled_.push_back(cur);
1103 // "Upgrade" the physical register since it has been allocated.
1104 UpgradeRegister(physReg);
1105 if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
1106 // "Downgrade" physReg to try to keep physReg from being allocated until
1107 // the next reload from the same SS is allocated.
1108 mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg);
1109 DowngradeRegister(cur, physReg);
1113 DEBUG(dbgs() << "no free registers\n");
1115 // Compile the spill weights into an array that is better for scanning.
1116 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
1117 for (std::vector<std::pair<unsigned, float> >::iterator
1118 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
1119 updateSpillWeights(SpillWeights, I->first, I->second, RC);
1121 // for each interval in active, update spill weights.
1122 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
1124 unsigned reg = i->first->reg;
1125 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1126 "Can only allocate virtual registers!");
1127 reg = vrm_->getPhys(reg);
1128 updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
1131 DEBUG(dbgs() << "\tassigning stack slot at interval "<< *cur << ":\n");
1133 // Find a register to spill.
1134 float minWeight = HUGE_VALF;
1135 unsigned minReg = 0;
1138 std::vector<std::pair<unsigned,float> > RegsWeights;
1139 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
1140 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1141 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1143 float regWeight = SpillWeights[reg];
1144 // Skip recently allocated registers and reserved registers.
1145 if (minWeight > regWeight && !isRecentlyUsed(reg) &&
1146 !reservedRegs_.test(reg))
1148 RegsWeights.push_back(std::make_pair(reg, regWeight));
1151 // If we didn't find a register that is spillable, try aliases?
1153 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1154 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1156 if (reservedRegs_.test(reg))
1158 // No need to worry about if the alias register size < regsize of RC.
1159 // We are going to spill all registers that alias it anyway.
1160 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
1161 RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
1165 // Sort all potential spill candidates by weight.
1166 std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare(*this));
1167 minReg = RegsWeights[0].first;
1168 minWeight = RegsWeights[0].second;
1169 if (minWeight == HUGE_VALF) {
1170 // All registers must have inf weight. Just grab one!
1171 if (BestPhysReg == 0) {
1172 TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_);
1173 TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_);
1174 while (reservedRegs_.test(*i) && i != aoe)
1176 assert(i != aoe && "All registers reserved?!");
1179 minReg = BestPhysReg;
1180 if (cur->weight == HUGE_VALF ||
1181 li_->getApproximateInstructionCount(*cur) == 0) {
1182 // Spill a physical register around defs and uses.
1183 if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
1184 // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
1185 // in fixed_. Reset them.
1186 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1187 IntervalPtr &IP = fixed_[i];
1188 LiveInterval *I = IP.first;
1189 if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
1190 IP.second = I->advanceTo(I->begin(), StartPosition);
1193 DowngradedRegs.clear();
1194 assignRegOrStackSlotAtInterval(cur);
1196 assert(false && "Ran out of registers during register allocation!");
1197 report_fatal_error("Ran out of registers during register allocation!");
1203 // Find up to 3 registers to consider as spill candidates.
1204 unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
1205 while (LastCandidate > 1) {
1206 if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
1212 dbgs() << "\t\tregister(s) with min weight(s): ";
1214 for (unsigned i = 0; i != LastCandidate; ++i)
1215 dbgs() << tri_->getName(RegsWeights[i].first)
1216 << " (" << RegsWeights[i].second << ")\n";
1219 // If the current has the minimum weight, we need to spill it and
1220 // add any added intervals back to unhandled, and restart
1222 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
1223 DEBUG(dbgs() << "\t\t\tspilling(c): " << *cur << '\n');
1224 SmallVector<LiveInterval*, 8> spillIs, added;
1225 spiller_->spill(cur, added, spillIs);
1227 std::sort(added.begin(), added.end(), LISorter());
1228 addStackInterval(cur, ls_, li_, mri_, *vrm_);
1230 return; // Early exit if all spills were folded.
1232 // Merge added with unhandled. Note that we have already sorted
1233 // intervals returned by addIntervalsForSpills by their starting
1235 // This also update the NextReloadMap. That is, it adds mapping from a
1236 // register defined by a reload from SS to the next reload from SS in the
1237 // same basic block.
1238 MachineBasicBlock *LastReloadMBB = 0;
1239 LiveInterval *LastReload = 0;
1240 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1241 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1242 LiveInterval *ReloadLi = added[i];
1243 if (ReloadLi->weight == HUGE_VALF &&
1244 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1245 SlotIndex ReloadIdx = ReloadLi->beginIndex();
1246 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1247 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1248 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1249 // Last reload of same SS is in the same MBB. We want to try to
1250 // allocate both reloads the same register and make sure the reg
1251 // isn't clobbered in between if at all possible.
1252 assert(LastReload->beginIndex() < ReloadIdx);
1253 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1255 LastReloadMBB = ReloadMBB;
1256 LastReload = ReloadLi;
1257 LastReloadSS = ReloadSS;
1259 unhandled_.push(ReloadLi);
1266 // Push the current interval back to unhandled since we are going
1267 // to re-run at least this iteration. Since we didn't modify it it
1268 // should go back right in the front of the list
1269 unhandled_.push(cur);
1271 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
1272 "did not choose a register to spill?");
1274 // We spill all intervals aliasing the register with
1275 // minimum weight, rollback to the interval with the earliest
1276 // start point and let the linear scan algorithm run again
1277 SmallVector<LiveInterval*, 8> spillIs;
1279 // Determine which intervals have to be spilled.
1280 findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
1282 // Set of spilled vregs (used later to rollback properly)
1283 SmallSet<unsigned, 8> spilled;
1285 // The earliest start of a Spilled interval indicates up to where
1286 // in handled we need to roll back
1287 assert(!spillIs.empty() && "No spill intervals?");
1288 SlotIndex earliestStart = spillIs[0]->beginIndex();
1290 // Spill live intervals of virtual regs mapped to the physical register we
1291 // want to clear (and its aliases). We only spill those that overlap with the
1292 // current interval as the rest do not affect its allocation. we also keep
1293 // track of the earliest start of all spilled live intervals since this will
1294 // mark our rollback point.
1295 SmallVector<LiveInterval*, 8> added;
1296 while (!spillIs.empty()) {
1297 LiveInterval *sli = spillIs.back();
1299 DEBUG(dbgs() << "\t\t\tspilling(a): " << *sli << '\n');
1300 if (sli->beginIndex() < earliestStart)
1301 earliestStart = sli->beginIndex();
1302 spiller_->spill(sli, added, spillIs);
1303 addStackInterval(sli, ls_, li_, mri_, *vrm_);
1304 spilled.insert(sli->reg);
1307 // Include any added intervals in earliestStart.
1308 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1309 SlotIndex SI = added[i]->beginIndex();
1310 if (SI < earliestStart)
1314 DEBUG(dbgs() << "\t\trolling back to: " << earliestStart << '\n');
1316 // Scan handled in reverse order up to the earliest start of a
1317 // spilled live interval and undo each one, restoring the state of
1319 while (!handled_.empty()) {
1320 LiveInterval* i = handled_.back();
1321 // If this interval starts before t we are done.
1322 if (!i->empty() && i->beginIndex() < earliestStart)
1324 DEBUG(dbgs() << "\t\t\tundo changes for: " << *i << '\n');
1325 handled_.pop_back();
1327 // When undoing a live interval allocation we must know if it is active or
1328 // inactive to properly update regUse_ and the VirtRegMap.
1329 IntervalPtrs::iterator it;
1330 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
1332 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1333 if (!spilled.count(i->reg))
1335 delRegUse(vrm_->getPhys(i->reg));
1336 vrm_->clearVirt(i->reg);
1337 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
1338 inactive_.erase(it);
1339 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1340 if (!spilled.count(i->reg))
1342 vrm_->clearVirt(i->reg);
1344 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
1345 "Can only allocate virtual registers!");
1346 vrm_->clearVirt(i->reg);
1350 DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
1351 if (ii == DowngradeMap.end())
1352 // It interval has a preference, it must be defined by a copy. Clear the
1353 // preference now since the source interval allocation may have been
1355 mri_->setRegAllocationHint(i->reg, 0, 0);
1357 UpgradeRegister(ii->second);
1361 // Rewind the iterators in the active, inactive, and fixed lists back to the
1362 // point we reverted to.
1363 RevertVectorIteratorsTo(active_, earliestStart);
1364 RevertVectorIteratorsTo(inactive_, earliestStart);
1365 RevertVectorIteratorsTo(fixed_, earliestStart);
1367 // Scan the rest and undo each interval that expired after t and
1368 // insert it in active (the next iteration of the algorithm will
1369 // put it in inactive if required)
1370 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
1371 LiveInterval *HI = handled_[i];
1372 if (!HI->expiredAt(earliestStart) &&
1373 HI->expiredAt(cur->beginIndex())) {
1374 DEBUG(dbgs() << "\t\t\tundo changes for: " << *HI << '\n');
1375 active_.push_back(std::make_pair(HI, HI->begin()));
1376 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
1377 addRegUse(vrm_->getPhys(HI->reg));
1381 // Merge added with unhandled.
1382 // This also update the NextReloadMap. That is, it adds mapping from a
1383 // register defined by a reload from SS to the next reload from SS in the
1384 // same basic block.
1385 MachineBasicBlock *LastReloadMBB = 0;
1386 LiveInterval *LastReload = 0;
1387 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1388 std::sort(added.begin(), added.end(), LISorter());
1389 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1390 LiveInterval *ReloadLi = added[i];
1391 if (ReloadLi->weight == HUGE_VALF &&
1392 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1393 SlotIndex ReloadIdx = ReloadLi->beginIndex();
1394 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1395 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1396 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1397 // Last reload of same SS is in the same MBB. We want to try to
1398 // allocate both reloads the same register and make sure the reg
1399 // isn't clobbered in between if at all possible.
1400 assert(LastReload->beginIndex() < ReloadIdx);
1401 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1403 LastReloadMBB = ReloadMBB;
1404 LastReload = ReloadLi;
1405 LastReloadSS = ReloadSS;
1407 unhandled_.push(ReloadLi);
1411 unsigned RALinScan::getFreePhysReg(LiveInterval* cur,
1412 const TargetRegisterClass *RC,
1413 unsigned MaxInactiveCount,
1414 SmallVector<unsigned, 256> &inactiveCounts,
1416 unsigned FreeReg = 0;
1417 unsigned FreeRegInactiveCount = 0;
1419 std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(cur->reg);
1420 // Resolve second part of the hint (if possible) given the current allocation.
1421 unsigned physReg = Hint.second;
1423 TargetRegisterInfo::isVirtualRegister(physReg) && vrm_->hasPhys(physReg))
1424 physReg = vrm_->getPhys(physReg);
1426 TargetRegisterClass::iterator I, E;
1427 tie(I, E) = tri_->getAllocationOrder(RC, Hint.first, physReg, *mf_);
1428 assert(I != E && "No allocatable register in this register class!");
1430 // Scan for the first available register.
1431 for (; I != E; ++I) {
1433 // Ignore "downgraded" registers.
1434 if (SkipDGRegs && DowngradedRegs.count(Reg))
1436 // Skip reserved registers.
1437 if (reservedRegs_.test(Reg))
1439 // Skip recently allocated registers.
1440 if (isRegAvail(Reg) && !isRecentlyUsed(Reg)) {
1442 if (FreeReg < inactiveCounts.size())
1443 FreeRegInactiveCount = inactiveCounts[FreeReg];
1445 FreeRegInactiveCount = 0;
1450 // If there are no free regs, or if this reg has the max inactive count,
1451 // return this register.
1452 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount) {
1453 // Remember what register we picked so we can skip it next time.
1454 if (FreeReg != 0) recordRecentlyUsed(FreeReg);
1458 // Continue scanning the registers, looking for the one with the highest
1459 // inactive count. Alkis found that this reduced register pressure very
1460 // slightly on X86 (in rev 1.94 of this file), though this should probably be
1462 for (; I != E; ++I) {
1464 // Ignore "downgraded" registers.
1465 if (SkipDGRegs && DowngradedRegs.count(Reg))
1467 // Skip reserved registers.
1468 if (reservedRegs_.test(Reg))
1470 if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
1471 FreeRegInactiveCount < inactiveCounts[Reg] && !isRecentlyUsed(Reg)) {
1473 FreeRegInactiveCount = inactiveCounts[Reg];
1474 if (FreeRegInactiveCount == MaxInactiveCount)
1475 break; // We found the one with the max inactive count.
1479 // Remember what register we picked so we can skip it next time.
1480 recordRecentlyUsed(FreeReg);
1485 /// getFreePhysReg - return a free physical register for this virtual register
1486 /// interval if we have one, otherwise return 0.
1487 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
1488 SmallVector<unsigned, 256> inactiveCounts;
1489 unsigned MaxInactiveCount = 0;
1491 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
1492 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1494 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
1496 unsigned reg = i->first->reg;
1497 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1498 "Can only allocate virtual registers!");
1500 // If this is not in a related reg class to the register we're allocating,
1502 const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
1503 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
1504 reg = vrm_->getPhys(reg);
1505 if (inactiveCounts.size() <= reg)
1506 inactiveCounts.resize(reg+1);
1507 ++inactiveCounts[reg];
1508 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
1512 // If copy coalescer has assigned a "preferred" register, check if it's
1514 unsigned Preference = vrm_->getRegAllocPref(cur->reg);
1516 DEBUG(dbgs() << "(preferred: " << tri_->getName(Preference) << ") ");
1517 if (isRegAvail(Preference) &&
1518 RC->contains(Preference))
1522 if (!DowngradedRegs.empty()) {
1523 unsigned FreeReg = getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts,
1528 return getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts, false);
1531 FunctionPass* llvm::createLinearScanRegisterAllocator() {
1532 return new RALinScan();