1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "PhysRegTracker.h"
16 #include "VirtRegMap.h"
17 #include "llvm/Function.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/LiveStackAnalysis.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/RegAllocRegistry.h"
26 #include "llvm/CodeGen/RegisterCoalescer.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/ADT/EquivalenceClasses.h"
32 #include "llvm/ADT/SmallSet.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/Compiler.h"
44 STATISTIC(NumIters , "Number of iterations performed");
45 STATISTIC(NumBacktracks, "Number of times we had to backtrack");
46 STATISTIC(NumCoalesce, "Number of copies coalesced");
49 NewHeuristic("new-spilling-heuristic",
50 cl::desc("Use new spilling heuristic"),
51 cl::init(false), cl::Hidden);
54 PreSplitIntervals("pre-alloc-split",
55 cl::desc("Pre-register allocation live interval splitting"),
56 cl::init(false), cl::Hidden);
58 static RegisterRegAlloc
59 linearscanRegAlloc("linearscan", "linear scan register allocator",
60 createLinearScanRegisterAllocator);
63 struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass {
65 RALinScan() : MachineFunctionPass(&ID) {}
67 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
68 typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
70 /// RelatedRegClasses - This structure is built the first time a function is
71 /// compiled, and keeps track of which register classes have registers that
72 /// belong to multiple classes or have aliases that are in other classes.
73 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
74 DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
77 MachineRegisterInfo* mri_;
78 const TargetMachine* tm_;
79 const TargetRegisterInfo* tri_;
80 const TargetInstrInfo* tii_;
81 BitVector allocatableRegs_;
84 const MachineLoopInfo *loopInfo;
86 /// handled_ - Intervals are added to the handled_ set in the order of their
87 /// start value. This is uses for backtracking.
88 std::vector<LiveInterval*> handled_;
90 /// fixed_ - Intervals that correspond to machine registers.
94 /// active_ - Intervals that are currently being processed, and which have a
95 /// live range active for the current point.
98 /// inactive_ - Intervals that are currently being processed, but which have
99 /// a hold at the current point.
100 IntervalPtrs inactive_;
102 typedef std::priority_queue<LiveInterval*,
103 SmallVector<LiveInterval*, 64>,
104 greater_ptr<LiveInterval> > IntervalHeap;
105 IntervalHeap unhandled_;
106 std::auto_ptr<PhysRegTracker> prt_;
107 std::auto_ptr<VirtRegMap> vrm_;
108 std::auto_ptr<Spiller> spiller_;
111 virtual const char* getPassName() const {
112 return "Linear Scan Register Allocator";
115 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
116 AU.addRequired<LiveIntervals>();
118 AU.addRequiredID(StrongPHIEliminationID);
119 // Make sure PassManager knows which analyses to make available
120 // to coalescing and which analyses coalescing invalidates.
121 AU.addRequiredTransitive<RegisterCoalescer>();
122 if (PreSplitIntervals)
123 AU.addRequiredID(PreAllocSplittingID);
124 AU.addRequired<LiveStacks>();
125 AU.addPreserved<LiveStacks>();
126 AU.addRequired<MachineLoopInfo>();
127 AU.addPreserved<MachineLoopInfo>();
128 AU.addPreservedID(MachineDominatorsID);
129 MachineFunctionPass::getAnalysisUsage(AU);
132 /// runOnMachineFunction - register allocate the whole function
133 bool runOnMachineFunction(MachineFunction&);
136 /// linearScan - the linear scan algorithm
139 /// initIntervalSets - initialize the interval sets.
141 void initIntervalSets();
143 /// processActiveIntervals - expire old intervals and move non-overlapping
144 /// ones to the inactive list.
145 void processActiveIntervals(unsigned CurPoint);
147 /// processInactiveIntervals - expire old intervals and move overlapping
148 /// ones to the active list.
149 void processInactiveIntervals(unsigned CurPoint);
151 /// assignRegOrStackSlotAtInterval - assign a register if one
152 /// is available, or spill.
153 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
155 /// findIntervalsToSpill - Determine the intervals to spill for the
156 /// specified interval. It's passed the physical registers whose spill
157 /// weight is the lowest among all the registers whose live intervals
158 /// conflict with the interval.
159 void findIntervalsToSpill(LiveInterval *cur,
160 std::vector<std::pair<unsigned,float> > &Candidates,
162 SmallVector<LiveInterval*, 8> &SpillIntervals);
164 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
165 /// try allocate the definition the same register as the source register
166 /// if the register is not defined during live time of the interval. This
167 /// eliminate a copy. This is used to coalesce copies which were not
168 /// coalesced away before allocation either due to dest and src being in
169 /// different register classes or because the coalescer was overly
171 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
174 /// register handling helpers
177 /// getFreePhysReg - return a free physical register for this virtual
178 /// register interval if we have one, otherwise return 0.
179 unsigned getFreePhysReg(LiveInterval* cur);
181 /// assignVirt2StackSlot - assigns this virtual register to a
182 /// stack slot. returns the stack slot
183 int assignVirt2StackSlot(unsigned virtReg);
185 void ComputeRelatedRegClasses();
187 template <typename ItTy>
188 void printIntervals(const char* const str, ItTy i, ItTy e) const {
189 if (str) DOUT << str << " intervals:\n";
190 for (; i != e; ++i) {
191 DOUT << "\t" << *i->first << " -> ";
192 unsigned reg = i->first->reg;
193 if (TargetRegisterInfo::isVirtualRegister(reg)) {
194 reg = vrm_->getPhys(reg);
196 DOUT << tri_->getName(reg) << '\n';
200 char RALinScan::ID = 0;
203 static RegisterPass<RALinScan>
204 X("linearscan-regalloc", "Linear Scan Register Allocator");
206 void RALinScan::ComputeRelatedRegClasses() {
207 const TargetRegisterInfo &TRI = *tri_;
209 // First pass, add all reg classes to the union, and determine at least one
210 // reg class that each register is in.
211 bool HasAliases = false;
212 for (TargetRegisterInfo::regclass_iterator RCI = TRI.regclass_begin(),
213 E = TRI.regclass_end(); RCI != E; ++RCI) {
214 RelatedRegClasses.insert(*RCI);
215 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
217 HasAliases = HasAliases || *TRI.getAliasSet(*I) != 0;
219 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
221 // Already processed this register. Just make sure we know that
222 // multiple register classes share a register.
223 RelatedRegClasses.unionSets(PRC, *RCI);
230 // Second pass, now that we know conservatively what register classes each reg
231 // belongs to, add info about aliases. We don't need to do this for targets
232 // without register aliases.
234 for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
235 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
237 for (const unsigned *AS = TRI.getAliasSet(I->first); *AS; ++AS)
238 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
241 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
242 /// try allocate the definition the same register as the source register
243 /// if the register is not defined during live time of the interval. This
244 /// eliminate a copy. This is used to coalesce copies which were not
245 /// coalesced away before allocation either due to dest and src being in
246 /// different register classes or because the coalescer was overly
248 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
249 if ((cur.preference && cur.preference == Reg) || !cur.containsOneValue())
252 VNInfo *vni = cur.begin()->valno;
253 if (!vni->def || vni->def == ~1U || vni->def == ~0U)
255 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
256 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
258 !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
260 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
261 if (!vrm_->isAssignedReg(SrcReg))
264 SrcReg = vrm_->getPhys(SrcReg);
269 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
270 if (!RC->contains(SrcReg))
274 if (!li_->conflictsWithPhysRegDef(cur, *vrm_, SrcReg)) {
275 DOUT << "Coalescing: " << cur << " -> " << tri_->getName(SrcReg)
277 vrm_->clearVirt(cur.reg);
278 vrm_->assignVirt2Phys(cur.reg, SrcReg);
286 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
288 mri_ = &fn.getRegInfo();
289 tm_ = &fn.getTarget();
290 tri_ = tm_->getRegisterInfo();
291 tii_ = tm_->getInstrInfo();
292 allocatableRegs_ = tri_->getAllocatableSet(fn);
293 li_ = &getAnalysis<LiveIntervals>();
294 ls_ = &getAnalysis<LiveStacks>();
295 loopInfo = &getAnalysis<MachineLoopInfo>();
297 // We don't run the coalescer here because we have no reason to
298 // interact with it. If the coalescer requires interaction, it
299 // won't do anything. If it doesn't require interaction, we assume
300 // it was run as a separate pass.
302 // If this is the first function compiled, compute the related reg classes.
303 if (RelatedRegClasses.empty())
304 ComputeRelatedRegClasses();
306 if (!prt_.get()) prt_.reset(new PhysRegTracker(*tri_));
307 vrm_.reset(new VirtRegMap(*mf_));
308 if (!spiller_.get()) spiller_.reset(createSpiller());
314 // Rewrite spill code and update the PhysRegsUsed set.
315 spiller_->runOnMachineFunction(*mf_, *vrm_);
316 vrm_.reset(); // Free the VirtRegMap
318 assert(unhandled_.empty() && "Unhandled live intervals remain!");
327 /// initIntervalSets - initialize the interval sets.
329 void RALinScan::initIntervalSets()
331 assert(unhandled_.empty() && fixed_.empty() &&
332 active_.empty() && inactive_.empty() &&
333 "interval sets should be empty on initialization");
335 handled_.reserve(li_->getNumIntervals());
337 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
338 if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
339 mri_->setPhysRegUsed(i->second->reg);
340 fixed_.push_back(std::make_pair(i->second, i->second->begin()));
342 unhandled_.push(i->second);
346 void RALinScan::linearScan()
348 // linear scan algorithm
349 DOUT << "********** LINEAR SCAN **********\n";
350 DOUT << "********** Function: " << mf_->getFunction()->getName() << '\n';
352 DEBUG(printIntervals("fixed", fixed_.begin(), fixed_.end()));
354 while (!unhandled_.empty()) {
355 // pick the interval with the earliest start point
356 LiveInterval* cur = unhandled_.top();
359 DOUT << "\n*** CURRENT ***: " << *cur << '\n';
362 processActiveIntervals(cur->beginNumber());
363 processInactiveIntervals(cur->beginNumber());
365 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
366 "Can only allocate virtual registers!");
369 // Allocating a virtual register. try to find a free
370 // physical register or spill an interval (possibly this one) in order to
372 assignRegOrStackSlotAtInterval(cur);
374 DEBUG(printIntervals("active", active_.begin(), active_.end()));
375 DEBUG(printIntervals("inactive", inactive_.begin(), inactive_.end()));
378 // expire any remaining active intervals
379 while (!active_.empty()) {
380 IntervalPtr &IP = active_.back();
381 unsigned reg = IP.first->reg;
382 DOUT << "\tinterval " << *IP.first << " expired\n";
383 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
384 "Can only allocate virtual registers!");
385 reg = vrm_->getPhys(reg);
386 prt_->delRegUse(reg);
390 // expire any remaining inactive intervals
391 DEBUG(for (IntervalPtrs::reverse_iterator
392 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
393 DOUT << "\tinterval " << *i->first << " expired\n");
396 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
397 MachineFunction::iterator EntryMBB = mf_->begin();
398 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
399 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
400 LiveInterval &cur = *i->second;
402 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
405 else if (vrm_->isAssignedReg(cur.reg))
406 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
409 // Ignore splited live intervals.
410 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
412 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
414 const LiveRange &LR = *I;
415 if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
416 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
417 if (LiveInMBBs[i] != EntryMBB)
418 LiveInMBBs[i]->addLiveIn(Reg);
427 /// processActiveIntervals - expire old intervals and move non-overlapping ones
428 /// to the inactive list.
429 void RALinScan::processActiveIntervals(unsigned CurPoint)
431 DOUT << "\tprocessing active intervals:\n";
433 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
434 LiveInterval *Interval = active_[i].first;
435 LiveInterval::iterator IntervalPos = active_[i].second;
436 unsigned reg = Interval->reg;
438 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
440 if (IntervalPos == Interval->end()) { // Remove expired intervals.
441 DOUT << "\t\tinterval " << *Interval << " expired\n";
442 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
443 "Can only allocate virtual registers!");
444 reg = vrm_->getPhys(reg);
445 prt_->delRegUse(reg);
447 // Pop off the end of the list.
448 active_[i] = active_.back();
452 } else if (IntervalPos->start > CurPoint) {
453 // Move inactive intervals to inactive list.
454 DOUT << "\t\tinterval " << *Interval << " inactive\n";
455 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
456 "Can only allocate virtual registers!");
457 reg = vrm_->getPhys(reg);
458 prt_->delRegUse(reg);
460 inactive_.push_back(std::make_pair(Interval, IntervalPos));
462 // Pop off the end of the list.
463 active_[i] = active_.back();
467 // Otherwise, just update the iterator position.
468 active_[i].second = IntervalPos;
473 /// processInactiveIntervals - expire old intervals and move overlapping
474 /// ones to the active list.
475 void RALinScan::processInactiveIntervals(unsigned CurPoint)
477 DOUT << "\tprocessing inactive intervals:\n";
479 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
480 LiveInterval *Interval = inactive_[i].first;
481 LiveInterval::iterator IntervalPos = inactive_[i].second;
482 unsigned reg = Interval->reg;
484 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
486 if (IntervalPos == Interval->end()) { // remove expired intervals.
487 DOUT << "\t\tinterval " << *Interval << " expired\n";
489 // Pop off the end of the list.
490 inactive_[i] = inactive_.back();
491 inactive_.pop_back();
493 } else if (IntervalPos->start <= CurPoint) {
494 // move re-activated intervals in active list
495 DOUT << "\t\tinterval " << *Interval << " active\n";
496 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
497 "Can only allocate virtual registers!");
498 reg = vrm_->getPhys(reg);
499 prt_->addRegUse(reg);
501 active_.push_back(std::make_pair(Interval, IntervalPos));
503 // Pop off the end of the list.
504 inactive_[i] = inactive_.back();
505 inactive_.pop_back();
508 // Otherwise, just update the iterator position.
509 inactive_[i].second = IntervalPos;
514 /// updateSpillWeights - updates the spill weights of the specifed physical
515 /// register and its weight.
516 static void updateSpillWeights(std::vector<float> &Weights,
517 unsigned reg, float weight,
518 const TargetRegisterInfo *TRI) {
519 Weights[reg] += weight;
520 for (const unsigned* as = TRI->getAliasSet(reg); *as; ++as)
521 Weights[*as] += weight;
525 RALinScan::IntervalPtrs::iterator
526 FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
527 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
529 if (I->first == LI) return I;
533 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, unsigned Point){
534 for (unsigned i = 0, e = V.size(); i != e; ++i) {
535 RALinScan::IntervalPtr &IP = V[i];
536 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
538 if (I != IP.first->begin()) --I;
543 /// addStackInterval - Create a LiveInterval for stack if the specified live
544 /// interval has been spilled.
545 static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
546 LiveIntervals *li_, float &Weight,
548 int SS = vrm_.getStackSlot(cur->reg);
549 if (SS == VirtRegMap::NO_STACK_SLOT)
551 LiveInterval &SI = ls_->getOrCreateInterval(SS);
555 if (SI.hasAtLeastOneValue())
556 VNI = SI.getValNumInfo(0);
558 VNI = SI.getNextValue(~0U, 0, ls_->getVNInfoAllocator());
560 LiveInterval &RI = li_->getInterval(cur->reg);
561 // FIXME: This may be overly conservative.
562 SI.MergeRangesInAsValue(RI, VNI);
565 /// getConflictWeight - Return the number of conflicts between cur
566 /// live interval and defs and uses of Reg weighted by loop depthes.
567 static float getConflictWeight(LiveInterval *cur, unsigned Reg,
569 MachineRegisterInfo *mri_,
570 const MachineLoopInfo *loopInfo) {
572 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
573 E = mri_->reg_end(); I != E; ++I) {
574 MachineInstr *MI = &*I;
575 if (cur->liveAt(li_->getInstructionIndex(MI))) {
576 unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
577 Conflicts += powf(10.0f, (float)loopDepth);
583 /// findIntervalsToSpill - Determine the intervals to spill for the
584 /// specified interval. It's passed the physical registers whose spill
585 /// weight is the lowest among all the registers whose live intervals
586 /// conflict with the interval.
587 void RALinScan::findIntervalsToSpill(LiveInterval *cur,
588 std::vector<std::pair<unsigned,float> > &Candidates,
590 SmallVector<LiveInterval*, 8> &SpillIntervals) {
591 // We have figured out the *best* register to spill. But there are other
592 // registers that are pretty good as well (spill weight within 3%). Spill
593 // the one that has fewest defs and uses that conflict with cur.
594 float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
595 SmallVector<LiveInterval*, 8> SLIs[3];
597 DOUT << "\tConsidering " << NumCands << " candidates: ";
598 DEBUG(for (unsigned i = 0; i != NumCands; ++i)
599 DOUT << tri_->getName(Candidates[i].first) << " ";
602 // Calculate the number of conflicts of each candidate.
603 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
604 unsigned Reg = i->first->reg;
605 unsigned PhysReg = vrm_->getPhys(Reg);
606 if (!cur->overlapsFrom(*i->first, i->second))
608 for (unsigned j = 0; j < NumCands; ++j) {
609 unsigned Candidate = Candidates[j].first;
610 if (tri_->regsOverlap(PhysReg, Candidate)) {
612 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
613 SLIs[j].push_back(i->first);
618 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
619 unsigned Reg = i->first->reg;
620 unsigned PhysReg = vrm_->getPhys(Reg);
621 if (!cur->overlapsFrom(*i->first, i->second-1))
623 for (unsigned j = 0; j < NumCands; ++j) {
624 unsigned Candidate = Candidates[j].first;
625 if (tri_->regsOverlap(PhysReg, Candidate)) {
627 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
628 SLIs[j].push_back(i->first);
633 // Which is the best candidate?
634 unsigned BestCandidate = 0;
635 float MinConflicts = Conflicts[0];
636 for (unsigned i = 1; i != NumCands; ++i) {
637 if (Conflicts[i] < MinConflicts) {
639 MinConflicts = Conflicts[i];
643 std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
644 std::back_inserter(SpillIntervals));
648 struct WeightCompare {
649 typedef std::pair<unsigned, float> RegWeightPair;
650 bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
651 return LHS.second < RHS.second;
656 static bool weightsAreClose(float w1, float w2) {
660 float diff = w1 - w2;
661 if (diff <= 0.02f) // Within 0.02f
663 return (diff / w2) <= 0.05f; // Within 5%.
666 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
668 void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
670 DOUT << "\tallocating current interval: ";
672 // This is an implicitly defined live interval, just assign any register.
673 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
675 unsigned physReg = cur->preference;
677 physReg = *RC->allocation_order_begin(*mf_);
678 DOUT << tri_->getName(physReg) << '\n';
679 // Note the register is not really in use.
680 vrm_->assignVirt2Phys(cur->reg, physReg);
684 PhysRegTracker backupPrt = *prt_;
686 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
687 unsigned StartPosition = cur->beginNumber();
688 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
690 // If start of this live interval is defined by a move instruction and its
691 // source is assigned a physical register that is compatible with the target
692 // register class, then we should try to assign it the same register.
693 // This can happen when the move is from a larger register class to a smaller
694 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
695 if (!cur->preference && cur->hasAtLeastOneValue()) {
696 VNInfo *vni = cur->begin()->valno;
697 if (vni->def && vni->def != ~1U && vni->def != ~0U) {
698 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
699 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
701 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
703 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
705 else if (vrm_->isAssignedReg(SrcReg))
706 Reg = vrm_->getPhys(SrcReg);
707 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
708 cur->preference = Reg;
713 // for every interval in inactive we overlap with, mark the
714 // register as not free and update spill weights.
715 for (IntervalPtrs::const_iterator i = inactive_.begin(),
716 e = inactive_.end(); i != e; ++i) {
717 unsigned Reg = i->first->reg;
718 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
719 "Can only allocate virtual registers!");
720 const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
721 // If this is not in a related reg class to the register we're allocating,
723 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
724 cur->overlapsFrom(*i->first, i->second-1)) {
725 Reg = vrm_->getPhys(Reg);
726 prt_->addRegUse(Reg);
727 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
731 // Speculatively check to see if we can get a register right now. If not,
732 // we know we won't be able to by adding more constraints. If so, we can
733 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
734 // is very bad (it contains all callee clobbered registers for any functions
735 // with a call), so we want to avoid doing that if possible.
736 unsigned physReg = getFreePhysReg(cur);
737 unsigned BestPhysReg = physReg;
739 // We got a register. However, if it's in the fixed_ list, we might
740 // conflict with it. Check to see if we conflict with it or any of its
742 SmallSet<unsigned, 8> RegAliases;
743 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
744 RegAliases.insert(*AS);
746 bool ConflictsWithFixed = false;
747 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
748 IntervalPtr &IP = fixed_[i];
749 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
750 // Okay, this reg is on the fixed list. Check to see if we actually
752 LiveInterval *I = IP.first;
753 if (I->endNumber() > StartPosition) {
754 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
756 if (II != I->begin() && II->start > StartPosition)
758 if (cur->overlapsFrom(*I, II)) {
759 ConflictsWithFixed = true;
766 // Okay, the register picked by our speculative getFreePhysReg call turned
767 // out to be in use. Actually add all of the conflicting fixed registers to
768 // prt so we can do an accurate query.
769 if (ConflictsWithFixed) {
770 // For every interval in fixed we overlap with, mark the register as not
771 // free and update spill weights.
772 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
773 IntervalPtr &IP = fixed_[i];
774 LiveInterval *I = IP.first;
776 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
777 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
778 I->endNumber() > StartPosition) {
779 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
781 if (II != I->begin() && II->start > StartPosition)
783 if (cur->overlapsFrom(*I, II)) {
784 unsigned reg = I->reg;
785 prt_->addRegUse(reg);
786 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
791 // Using the newly updated prt_ object, which includes conflicts in the
792 // future, see if there are any registers available.
793 physReg = getFreePhysReg(cur);
797 // Restore the physical register tracker, removing information about the
801 // if we find a free register, we are done: assign this virtual to
802 // the free physical register and add this interval to the active
805 DOUT << tri_->getName(physReg) << '\n';
806 vrm_->assignVirt2Phys(cur->reg, physReg);
807 prt_->addRegUse(physReg);
808 active_.push_back(std::make_pair(cur, cur->begin()));
809 handled_.push_back(cur);
812 DOUT << "no free registers\n";
814 // Compile the spill weights into an array that is better for scanning.
815 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
816 for (std::vector<std::pair<unsigned, float> >::iterator
817 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
818 updateSpillWeights(SpillWeights, I->first, I->second, tri_);
820 // for each interval in active, update spill weights.
821 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
823 unsigned reg = i->first->reg;
824 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
825 "Can only allocate virtual registers!");
826 reg = vrm_->getPhys(reg);
827 updateSpillWeights(SpillWeights, reg, i->first->weight, tri_);
830 DOUT << "\tassigning stack slot at interval "<< *cur << ":\n";
832 // Find a register to spill.
833 float minWeight = HUGE_VALF;
834 unsigned minReg = 0; /*cur->preference*/; // Try the preferred register first.
837 std::vector<std::pair<unsigned,float> > RegsWeights;
838 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
839 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
840 e = RC->allocation_order_end(*mf_); i != e; ++i) {
842 float regWeight = SpillWeights[reg];
843 if (minWeight > regWeight)
845 RegsWeights.push_back(std::make_pair(reg, regWeight));
848 // If we didn't find a register that is spillable, try aliases?
850 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
851 e = RC->allocation_order_end(*mf_); i != e; ++i) {
853 // No need to worry about if the alias register size < regsize of RC.
854 // We are going to spill all registers that alias it anyway.
855 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
856 RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
860 // Sort all potential spill candidates by weight.
861 std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare());
862 minReg = RegsWeights[0].first;
863 minWeight = RegsWeights[0].second;
864 if (minWeight == HUGE_VALF) {
865 // All registers must have inf weight. Just grab one!
866 minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
867 if (cur->weight == HUGE_VALF ||
868 li_->getApproximateInstructionCount(*cur) == 0) {
869 // Spill a physical register around defs and uses.
870 li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_);
871 assignRegOrStackSlotAtInterval(cur);
876 // Find up to 3 registers to consider as spill candidates.
877 unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
878 while (LastCandidate > 1) {
879 if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
884 DOUT << "\t\tregister(s) with min weight(s): ";
885 DEBUG(for (unsigned i = 0; i != LastCandidate; ++i)
886 DOUT << tri_->getName(RegsWeights[i].first)
887 << " (" << RegsWeights[i].second << ")\n");
889 // if the current has the minimum weight, we need to spill it and
890 // add any added intervals back to unhandled, and restart
892 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
893 DOUT << "\t\t\tspilling(c): " << *cur << '\n';
895 SmallVector<LiveInterval*, 8> spillIs;
896 std::vector<LiveInterval*> added =
897 li_->addIntervalsForSpills(*cur, spillIs, loopInfo, *vrm_, SSWeight);
898 addStackInterval(cur, ls_, li_, SSWeight, *vrm_);
900 return; // Early exit if all spills were folded.
902 // Merge added with unhandled. Note that we know that
903 // addIntervalsForSpills returns intervals sorted by their starting
905 for (unsigned i = 0, e = added.size(); i != e; ++i)
906 unhandled_.push(added[i]);
912 // push the current interval back to unhandled since we are going
913 // to re-run at least this iteration. Since we didn't modify it it
914 // should go back right in the front of the list
915 unhandled_.push(cur);
917 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
918 "did not choose a register to spill?");
920 // We spill all intervals aliasing the register with
921 // minimum weight, rollback to the interval with the earliest
922 // start point and let the linear scan algorithm run again
923 SmallVector<LiveInterval*, 8> spillIs;
925 // Determine which intervals have to be spilled.
926 findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
928 // Set of spilled vregs (used later to rollback properly)
929 SmallSet<unsigned, 8> spilled;
931 // The earliest start of a Spilled interval indicates up to where
932 // in handled we need to roll back
933 unsigned earliestStart = cur->beginNumber();
935 // Spill live intervals of virtual regs mapped to the physical register we
936 // want to clear (and its aliases). We only spill those that overlap with the
937 // current interval as the rest do not affect its allocation. we also keep
938 // track of the earliest start of all spilled live intervals since this will
939 // mark our rollback point.
940 std::vector<LiveInterval*> added;
941 while (!spillIs.empty()) {
942 LiveInterval *sli = spillIs.back();
944 DOUT << "\t\t\tspilling(a): " << *sli << '\n';
945 earliestStart = std::min(earliestStart, sli->beginNumber());
947 std::vector<LiveInterval*> newIs =
948 li_->addIntervalsForSpills(*sli, spillIs, loopInfo, *vrm_, SSWeight);
949 addStackInterval(sli, ls_, li_, SSWeight, *vrm_);
950 std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
951 spilled.insert(sli->reg);
954 DOUT << "\t\trolling back to: " << earliestStart << '\n';
956 // Scan handled in reverse order up to the earliest start of a
957 // spilled live interval and undo each one, restoring the state of
959 while (!handled_.empty()) {
960 LiveInterval* i = handled_.back();
961 // If this interval starts before t we are done.
962 if (i->beginNumber() < earliestStart)
964 DOUT << "\t\t\tundo changes for: " << *i << '\n';
967 // When undoing a live interval allocation we must know if it is active or
968 // inactive to properly update the PhysRegTracker and the VirtRegMap.
969 IntervalPtrs::iterator it;
970 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
972 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
973 if (!spilled.count(i->reg))
975 prt_->delRegUse(vrm_->getPhys(i->reg));
976 vrm_->clearVirt(i->reg);
977 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
979 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
980 if (!spilled.count(i->reg))
982 vrm_->clearVirt(i->reg);
984 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
985 "Can only allocate virtual registers!");
986 vrm_->clearVirt(i->reg);
990 // It interval has a preference, it must be defined by a copy. Clear the
991 // preference now since the source interval allocation may have been undone
996 // Rewind the iterators in the active, inactive, and fixed lists back to the
997 // point we reverted to.
998 RevertVectorIteratorsTo(active_, earliestStart);
999 RevertVectorIteratorsTo(inactive_, earliestStart);
1000 RevertVectorIteratorsTo(fixed_, earliestStart);
1002 // scan the rest and undo each interval that expired after t and
1003 // insert it in active (the next iteration of the algorithm will
1004 // put it in inactive if required)
1005 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
1006 LiveInterval *HI = handled_[i];
1007 if (!HI->expiredAt(earliestStart) &&
1008 HI->expiredAt(cur->beginNumber())) {
1009 DOUT << "\t\t\tundo changes for: " << *HI << '\n';
1010 active_.push_back(std::make_pair(HI, HI->begin()));
1011 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
1012 prt_->addRegUse(vrm_->getPhys(HI->reg));
1016 // merge added with unhandled
1017 for (unsigned i = 0, e = added.size(); i != e; ++i)
1018 unhandled_.push(added[i]);
1021 /// getFreePhysReg - return a free physical register for this virtual register
1022 /// interval if we have one, otherwise return 0.
1023 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
1024 SmallVector<unsigned, 256> inactiveCounts;
1025 unsigned MaxInactiveCount = 0;
1027 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
1028 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1030 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
1032 unsigned reg = i->first->reg;
1033 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1034 "Can only allocate virtual registers!");
1036 // If this is not in a related reg class to the register we're allocating,
1038 const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
1039 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
1040 reg = vrm_->getPhys(reg);
1041 if (inactiveCounts.size() <= reg)
1042 inactiveCounts.resize(reg+1);
1043 ++inactiveCounts[reg];
1044 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
1048 unsigned FreeReg = 0;
1049 unsigned FreeRegInactiveCount = 0;
1051 // If copy coalescer has assigned a "preferred" register, check if it's
1053 if (cur->preference) {
1054 if (prt_->isRegAvail(cur->preference) &&
1055 RC->contains(cur->preference)) {
1056 DOUT << "\t\tassigned the preferred register: "
1057 << tri_->getName(cur->preference) << "\n";
1058 return cur->preference;
1060 DOUT << "\t\tunable to assign the preferred register: "
1061 << tri_->getName(cur->preference) << "\n";
1064 // Scan for the first available register.
1065 TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_);
1066 TargetRegisterClass::iterator E = RC->allocation_order_end(*mf_);
1067 assert(I != E && "No allocatable register in this register class!");
1069 if (prt_->isRegAvail(*I)) {
1071 if (FreeReg < inactiveCounts.size())
1072 FreeRegInactiveCount = inactiveCounts[FreeReg];
1074 FreeRegInactiveCount = 0;
1078 // If there are no free regs, or if this reg has the max inactive count,
1079 // return this register.
1080 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount) return FreeReg;
1082 // Continue scanning the registers, looking for the one with the highest
1083 // inactive count. Alkis found that this reduced register pressure very
1084 // slightly on X86 (in rev 1.94 of this file), though this should probably be
1086 for (; I != E; ++I) {
1088 if (prt_->isRegAvail(Reg) && Reg < inactiveCounts.size() &&
1089 FreeRegInactiveCount < inactiveCounts[Reg]) {
1091 FreeRegInactiveCount = inactiveCounts[Reg];
1092 if (FreeRegInactiveCount == MaxInactiveCount)
1093 break; // We found the one with the max inactive count.
1100 FunctionPass* llvm::createLinearScanRegisterAllocator() {
1101 return new RALinScan();