1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "VirtRegMap.h"
16 #include "VirtRegRewriter.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/LiveStackAnalysis.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegAllocRegistry.h"
27 #include "llvm/CodeGen/RegisterCoalescer.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/ADT/EquivalenceClasses.h"
33 #include "llvm/ADT/SmallSet.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/Compiler.h"
45 STATISTIC(NumIters , "Number of iterations performed");
46 STATISTIC(NumBacktracks, "Number of times we had to backtrack");
47 STATISTIC(NumCoalesce, "Number of copies coalesced");
48 STATISTIC(NumDowngrade, "Number of registers downgraded");
51 NewHeuristic("new-spilling-heuristic",
52 cl::desc("Use new spilling heuristic"),
53 cl::init(false), cl::Hidden);
56 PreSplitIntervals("pre-alloc-split",
57 cl::desc("Pre-register allocation live interval splitting"),
58 cl::init(false), cl::Hidden);
61 NewSpillFramework("new-spill-framework",
62 cl::desc("New spilling framework"),
63 cl::init(false), cl::Hidden);
65 static RegisterRegAlloc
66 linearscanRegAlloc("linearscan", "linear scan register allocator",
67 createLinearScanRegisterAllocator);
70 struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass {
72 RALinScan() : MachineFunctionPass(&ID) {}
74 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
75 typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
77 /// RelatedRegClasses - This structure is built the first time a function is
78 /// compiled, and keeps track of which register classes have registers that
79 /// belong to multiple classes or have aliases that are in other classes.
80 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
81 DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
83 // NextReloadMap - For each register in the map, it maps to the another
84 // register which is defined by a reload from the same stack slot and
85 // both reloads are in the same basic block.
86 DenseMap<unsigned, unsigned> NextReloadMap;
88 // DowngradedRegs - A set of registers which are being "downgraded", i.e.
89 // un-favored for allocation.
90 SmallSet<unsigned, 8> DowngradedRegs;
92 // DowngradeMap - A map from virtual registers to physical registers being
93 // downgraded for the virtual registers.
94 DenseMap<unsigned, unsigned> DowngradeMap;
97 MachineRegisterInfo* mri_;
98 const TargetMachine* tm_;
99 const TargetRegisterInfo* tri_;
100 const TargetInstrInfo* tii_;
101 BitVector allocatableRegs_;
104 const MachineLoopInfo *loopInfo;
106 /// handled_ - Intervals are added to the handled_ set in the order of their
107 /// start value. This is uses for backtracking.
108 std::vector<LiveInterval*> handled_;
110 /// fixed_ - Intervals that correspond to machine registers.
114 /// active_ - Intervals that are currently being processed, and which have a
115 /// live range active for the current point.
116 IntervalPtrs active_;
118 /// inactive_ - Intervals that are currently being processed, but which have
119 /// a hold at the current point.
120 IntervalPtrs inactive_;
122 typedef std::priority_queue<LiveInterval*,
123 SmallVector<LiveInterval*, 64>,
124 greater_ptr<LiveInterval> > IntervalHeap;
125 IntervalHeap unhandled_;
127 /// regUse_ - Tracks register usage.
128 SmallVector<unsigned, 32> regUse_;
129 SmallVector<unsigned, 32> regUseBackUp_;
131 /// vrm_ - Tracks register assignments.
134 std::auto_ptr<VirtRegRewriter> rewriter_;
136 std::auto_ptr<Spiller> spiller_;
139 virtual const char* getPassName() const {
140 return "Linear Scan Register Allocator";
143 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
144 AU.addRequired<LiveIntervals>();
146 AU.addRequiredID(StrongPHIEliminationID);
147 // Make sure PassManager knows which analyses to make available
148 // to coalescing and which analyses coalescing invalidates.
149 AU.addRequiredTransitive<RegisterCoalescer>();
150 if (PreSplitIntervals)
151 AU.addRequiredID(PreAllocSplittingID);
152 AU.addRequired<LiveStacks>();
153 AU.addPreserved<LiveStacks>();
154 AU.addRequired<MachineLoopInfo>();
155 AU.addPreserved<MachineLoopInfo>();
156 AU.addRequired<VirtRegMap>();
157 AU.addPreserved<VirtRegMap>();
158 AU.addPreservedID(MachineDominatorsID);
159 MachineFunctionPass::getAnalysisUsage(AU);
162 /// runOnMachineFunction - register allocate the whole function
163 bool runOnMachineFunction(MachineFunction&);
166 /// linearScan - the linear scan algorithm
169 /// initIntervalSets - initialize the interval sets.
171 void initIntervalSets();
173 /// processActiveIntervals - expire old intervals and move non-overlapping
174 /// ones to the inactive list.
175 void processActiveIntervals(unsigned CurPoint);
177 /// processInactiveIntervals - expire old intervals and move overlapping
178 /// ones to the active list.
179 void processInactiveIntervals(unsigned CurPoint);
181 /// hasNextReloadInterval - Return the next liveinterval that's being
182 /// defined by a reload from the same SS as the specified one.
183 LiveInterval *hasNextReloadInterval(LiveInterval *cur);
185 /// DowngradeRegister - Downgrade a register for allocation.
186 void DowngradeRegister(LiveInterval *li, unsigned Reg);
188 /// UpgradeRegister - Upgrade a register for allocation.
189 void UpgradeRegister(unsigned Reg);
191 /// assignRegOrStackSlotAtInterval - assign a register if one
192 /// is available, or spill.
193 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
195 void updateSpillWeights(std::vector<float> &Weights,
196 unsigned reg, float weight,
197 const TargetRegisterClass *RC);
199 /// findIntervalsToSpill - Determine the intervals to spill for the
200 /// specified interval. It's passed the physical registers whose spill
201 /// weight is the lowest among all the registers whose live intervals
202 /// conflict with the interval.
203 void findIntervalsToSpill(LiveInterval *cur,
204 std::vector<std::pair<unsigned,float> > &Candidates,
206 SmallVector<LiveInterval*, 8> &SpillIntervals);
208 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
209 /// try allocate the definition the same register as the source register
210 /// if the register is not defined during live time of the interval. This
211 /// eliminate a copy. This is used to coalesce copies which were not
212 /// coalesced away before allocation either due to dest and src being in
213 /// different register classes or because the coalescer was overly
215 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
218 /// Register usage / availability tracking helpers.
222 regUse_.resize(tri_->getNumRegs(), 0);
223 regUseBackUp_.resize(tri_->getNumRegs(), 0);
226 void finalizeRegUses() {
228 // Verify all the registers are "freed".
230 for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
231 if (regUse_[i] != 0) {
232 cerr << tri_->getName(i) << " is still in use!\n";
240 regUseBackUp_.clear();
243 void addRegUse(unsigned physReg) {
244 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
245 "should be physical register!");
247 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
251 void delRegUse(unsigned physReg) {
252 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
253 "should be physical register!");
254 assert(regUse_[physReg] != 0);
256 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
257 assert(regUse_[*as] != 0);
262 bool isRegAvail(unsigned physReg) const {
263 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
264 "should be physical register!");
265 return regUse_[physReg] == 0;
268 void backUpRegUses() {
269 regUseBackUp_ = regUse_;
272 void restoreRegUses() {
273 regUse_ = regUseBackUp_;
277 /// Register handling helpers.
280 /// getFreePhysReg - return a free physical register for this virtual
281 /// register interval if we have one, otherwise return 0.
282 unsigned getFreePhysReg(LiveInterval* cur);
283 unsigned getFreePhysReg(const TargetRegisterClass *RC,
284 unsigned MaxInactiveCount,
285 SmallVector<unsigned, 256> &inactiveCounts,
288 /// assignVirt2StackSlot - assigns this virtual register to a
289 /// stack slot. returns the stack slot
290 int assignVirt2StackSlot(unsigned virtReg);
292 void ComputeRelatedRegClasses();
294 template <typename ItTy>
295 void printIntervals(const char* const str, ItTy i, ItTy e) const {
296 if (str) DOUT << str << " intervals:\n";
297 for (; i != e; ++i) {
298 DOUT << "\t" << *i->first << " -> ";
299 unsigned reg = i->first->reg;
300 if (TargetRegisterInfo::isVirtualRegister(reg)) {
301 reg = vrm_->getPhys(reg);
303 DOUT << tri_->getName(reg) << '\n';
307 char RALinScan::ID = 0;
310 static RegisterPass<RALinScan>
311 X("linearscan-regalloc", "Linear Scan Register Allocator");
313 void RALinScan::ComputeRelatedRegClasses() {
314 // First pass, add all reg classes to the union, and determine at least one
315 // reg class that each register is in.
316 bool HasAliases = false;
317 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
318 E = tri_->regclass_end(); RCI != E; ++RCI) {
319 RelatedRegClasses.insert(*RCI);
320 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
322 HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
324 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
326 // Already processed this register. Just make sure we know that
327 // multiple register classes share a register.
328 RelatedRegClasses.unionSets(PRC, *RCI);
335 // Second pass, now that we know conservatively what register classes each reg
336 // belongs to, add info about aliases. We don't need to do this for targets
337 // without register aliases.
339 for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
340 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
342 for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
343 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
346 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
347 /// try allocate the definition the same register as the source register
348 /// if the register is not defined during live time of the interval. This
349 /// eliminate a copy. This is used to coalesce copies which were not
350 /// coalesced away before allocation either due to dest and src being in
351 /// different register classes or because the coalescer was overly
353 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
354 if ((cur.preference && cur.preference == Reg) || !cur.containsOneValue())
357 VNInfo *vni = cur.begin()->valno;
358 if (!vni->def || vni->def == ~1U || vni->def == ~0U)
360 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
361 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg, PhysReg;
363 !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
366 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
367 if (!vrm_->isAssignedReg(SrcReg))
369 PhysReg = vrm_->getPhys(SrcReg);
374 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
375 if (!RC->contains(PhysReg))
379 if (!li_->conflictsWithPhysRegDef(cur, *vrm_, PhysReg)) {
380 DOUT << "Coalescing: " << cur << " -> " << tri_->getName(PhysReg)
382 vrm_->clearVirt(cur.reg);
383 vrm_->assignVirt2Phys(cur.reg, PhysReg);
385 // Remove unnecessary kills since a copy does not clobber the register.
386 if (li_->hasInterval(SrcReg)) {
387 LiveInterval &SrcLI = li_->getInterval(SrcReg);
388 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(cur.reg),
389 E = mri_->reg_end(); I != E; ++I) {
390 MachineOperand &O = I.getOperand();
391 if (!O.isUse() || !O.isKill())
393 MachineInstr *MI = &*I;
394 if (SrcLI.liveAt(li_->getDefIndex(li_->getInstructionIndex(MI))))
406 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
408 mri_ = &fn.getRegInfo();
409 tm_ = &fn.getTarget();
410 tri_ = tm_->getRegisterInfo();
411 tii_ = tm_->getInstrInfo();
412 allocatableRegs_ = tri_->getAllocatableSet(fn);
413 li_ = &getAnalysis<LiveIntervals>();
414 ls_ = &getAnalysis<LiveStacks>();
415 loopInfo = &getAnalysis<MachineLoopInfo>();
417 // We don't run the coalescer here because we have no reason to
418 // interact with it. If the coalescer requires interaction, it
419 // won't do anything. If it doesn't require interaction, we assume
420 // it was run as a separate pass.
422 // If this is the first function compiled, compute the related reg classes.
423 if (RelatedRegClasses.empty())
424 ComputeRelatedRegClasses();
426 // Also resize register usage trackers.
429 vrm_ = &getAnalysis<VirtRegMap>();
430 if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
432 if (NewSpillFramework) {
433 spiller_.reset(createSpiller(mf_, li_, vrm_));
443 // Rewrite spill code and update the PhysRegsUsed set.
444 rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
446 assert(unhandled_.empty() && "Unhandled live intervals remain!");
454 NextReloadMap.clear();
455 DowngradedRegs.clear();
456 DowngradeMap.clear();
461 /// initIntervalSets - initialize the interval sets.
463 void RALinScan::initIntervalSets()
465 assert(unhandled_.empty() && fixed_.empty() &&
466 active_.empty() && inactive_.empty() &&
467 "interval sets should be empty on initialization");
469 handled_.reserve(li_->getNumIntervals());
471 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
472 if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
473 mri_->setPhysRegUsed(i->second->reg);
474 fixed_.push_back(std::make_pair(i->second, i->second->begin()));
476 unhandled_.push(i->second);
480 void RALinScan::linearScan()
482 // linear scan algorithm
483 DOUT << "********** LINEAR SCAN **********\n";
484 DOUT << "********** Function: " << mf_->getFunction()->getName() << '\n';
486 DEBUG(printIntervals("fixed", fixed_.begin(), fixed_.end()));
488 while (!unhandled_.empty()) {
489 // pick the interval with the earliest start point
490 LiveInterval* cur = unhandled_.top();
493 DOUT << "\n*** CURRENT ***: " << *cur << '\n';
496 processActiveIntervals(cur->beginNumber());
497 processInactiveIntervals(cur->beginNumber());
499 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
500 "Can only allocate virtual registers!");
503 // Allocating a virtual register. try to find a free
504 // physical register or spill an interval (possibly this one) in order to
506 assignRegOrStackSlotAtInterval(cur);
508 DEBUG(printIntervals("active", active_.begin(), active_.end()));
509 DEBUG(printIntervals("inactive", inactive_.begin(), inactive_.end()));
512 // Expire any remaining active intervals
513 while (!active_.empty()) {
514 IntervalPtr &IP = active_.back();
515 unsigned reg = IP.first->reg;
516 DOUT << "\tinterval " << *IP.first << " expired\n";
517 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
518 "Can only allocate virtual registers!");
519 reg = vrm_->getPhys(reg);
524 // Expire any remaining inactive intervals
525 DEBUG(for (IntervalPtrs::reverse_iterator
526 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
527 DOUT << "\tinterval " << *i->first << " expired\n");
530 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
531 MachineFunction::iterator EntryMBB = mf_->begin();
532 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
533 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
534 LiveInterval &cur = *i->second;
536 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
539 else if (vrm_->isAssignedReg(cur.reg))
540 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
543 // Ignore splited live intervals.
544 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
546 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
548 const LiveRange &LR = *I;
549 if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
550 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
551 if (LiveInMBBs[i] != EntryMBB)
552 LiveInMBBs[i]->addLiveIn(Reg);
560 // Look for physical registers that end up not being allocated even though
561 // register allocator had to spill other registers in its register class.
562 if (ls_->getNumIntervals() == 0)
564 if (!vrm_->FindUnusedRegisters(tri_, li_))
568 /// processActiveIntervals - expire old intervals and move non-overlapping ones
569 /// to the inactive list.
570 void RALinScan::processActiveIntervals(unsigned CurPoint)
572 DOUT << "\tprocessing active intervals:\n";
574 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
575 LiveInterval *Interval = active_[i].first;
576 LiveInterval::iterator IntervalPos = active_[i].second;
577 unsigned reg = Interval->reg;
579 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
581 if (IntervalPos == Interval->end()) { // Remove expired intervals.
582 DOUT << "\t\tinterval " << *Interval << " expired\n";
583 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
584 "Can only allocate virtual registers!");
585 reg = vrm_->getPhys(reg);
588 // Pop off the end of the list.
589 active_[i] = active_.back();
593 } else if (IntervalPos->start > CurPoint) {
594 // Move inactive intervals to inactive list.
595 DOUT << "\t\tinterval " << *Interval << " inactive\n";
596 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
597 "Can only allocate virtual registers!");
598 reg = vrm_->getPhys(reg);
601 inactive_.push_back(std::make_pair(Interval, IntervalPos));
603 // Pop off the end of the list.
604 active_[i] = active_.back();
608 // Otherwise, just update the iterator position.
609 active_[i].second = IntervalPos;
614 /// processInactiveIntervals - expire old intervals and move overlapping
615 /// ones to the active list.
616 void RALinScan::processInactiveIntervals(unsigned CurPoint)
618 DOUT << "\tprocessing inactive intervals:\n";
620 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
621 LiveInterval *Interval = inactive_[i].first;
622 LiveInterval::iterator IntervalPos = inactive_[i].second;
623 unsigned reg = Interval->reg;
625 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
627 if (IntervalPos == Interval->end()) { // remove expired intervals.
628 DOUT << "\t\tinterval " << *Interval << " expired\n";
630 // Pop off the end of the list.
631 inactive_[i] = inactive_.back();
632 inactive_.pop_back();
634 } else if (IntervalPos->start <= CurPoint) {
635 // move re-activated intervals in active list
636 DOUT << "\t\tinterval " << *Interval << " active\n";
637 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
638 "Can only allocate virtual registers!");
639 reg = vrm_->getPhys(reg);
642 active_.push_back(std::make_pair(Interval, IntervalPos));
644 // Pop off the end of the list.
645 inactive_[i] = inactive_.back();
646 inactive_.pop_back();
649 // Otherwise, just update the iterator position.
650 inactive_[i].second = IntervalPos;
655 /// updateSpillWeights - updates the spill weights of the specifed physical
656 /// register and its weight.
657 void RALinScan::updateSpillWeights(std::vector<float> &Weights,
658 unsigned reg, float weight,
659 const TargetRegisterClass *RC) {
660 SmallSet<unsigned, 4> Processed;
661 SmallSet<unsigned, 4> SuperAdded;
662 SmallVector<unsigned, 4> Supers;
663 Weights[reg] += weight;
664 Processed.insert(reg);
665 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
666 Weights[*as] += weight;
667 Processed.insert(*as);
668 if (tri_->isSubRegister(*as, reg) &&
669 SuperAdded.insert(*as) &&
671 Supers.push_back(*as);
675 // If the alias is a super-register, and the super-register is in the
676 // register class we are trying to allocate. Then add the weight to all
677 // sub-registers of the super-register even if they are not aliases.
678 // e.g. allocating for GR32, bh is not used, updating bl spill weight.
679 // bl should get the same spill weight otherwise it will be choosen
680 // as a spill candidate since spilling bh doesn't make ebx available.
681 for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
682 for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
683 if (!Processed.count(*sr))
684 Weights[*sr] += weight;
689 RALinScan::IntervalPtrs::iterator
690 FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
691 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
693 if (I->first == LI) return I;
697 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, unsigned Point){
698 for (unsigned i = 0, e = V.size(); i != e; ++i) {
699 RALinScan::IntervalPtr &IP = V[i];
700 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
702 if (I != IP.first->begin()) --I;
707 /// addStackInterval - Create a LiveInterval for stack if the specified live
708 /// interval has been spilled.
709 static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
711 MachineRegisterInfo* mri_, VirtRegMap &vrm_) {
712 int SS = vrm_.getStackSlot(cur->reg);
713 if (SS == VirtRegMap::NO_STACK_SLOT)
716 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
717 LiveInterval &SI = ls_->getOrCreateInterval(SS, RC);
720 if (SI.hasAtLeastOneValue())
721 VNI = SI.getValNumInfo(0);
723 VNI = SI.getNextValue(~0U, 0, ls_->getVNInfoAllocator());
725 LiveInterval &RI = li_->getInterval(cur->reg);
726 // FIXME: This may be overly conservative.
727 SI.MergeRangesInAsValue(RI, VNI);
730 /// getConflictWeight - Return the number of conflicts between cur
731 /// live interval and defs and uses of Reg weighted by loop depthes.
733 float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
734 MachineRegisterInfo *mri_,
735 const MachineLoopInfo *loopInfo) {
737 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
738 E = mri_->reg_end(); I != E; ++I) {
739 MachineInstr *MI = &*I;
740 if (cur->liveAt(li_->getInstructionIndex(MI))) {
741 unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
742 Conflicts += powf(10.0f, (float)loopDepth);
748 /// findIntervalsToSpill - Determine the intervals to spill for the
749 /// specified interval. It's passed the physical registers whose spill
750 /// weight is the lowest among all the registers whose live intervals
751 /// conflict with the interval.
752 void RALinScan::findIntervalsToSpill(LiveInterval *cur,
753 std::vector<std::pair<unsigned,float> > &Candidates,
755 SmallVector<LiveInterval*, 8> &SpillIntervals) {
756 // We have figured out the *best* register to spill. But there are other
757 // registers that are pretty good as well (spill weight within 3%). Spill
758 // the one that has fewest defs and uses that conflict with cur.
759 float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
760 SmallVector<LiveInterval*, 8> SLIs[3];
762 DOUT << "\tConsidering " << NumCands << " candidates: ";
763 DEBUG(for (unsigned i = 0; i != NumCands; ++i)
764 DOUT << tri_->getName(Candidates[i].first) << " ";
767 // Calculate the number of conflicts of each candidate.
768 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
769 unsigned Reg = i->first->reg;
770 unsigned PhysReg = vrm_->getPhys(Reg);
771 if (!cur->overlapsFrom(*i->first, i->second))
773 for (unsigned j = 0; j < NumCands; ++j) {
774 unsigned Candidate = Candidates[j].first;
775 if (tri_->regsOverlap(PhysReg, Candidate)) {
777 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
778 SLIs[j].push_back(i->first);
783 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
784 unsigned Reg = i->first->reg;
785 unsigned PhysReg = vrm_->getPhys(Reg);
786 if (!cur->overlapsFrom(*i->first, i->second-1))
788 for (unsigned j = 0; j < NumCands; ++j) {
789 unsigned Candidate = Candidates[j].first;
790 if (tri_->regsOverlap(PhysReg, Candidate)) {
792 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
793 SLIs[j].push_back(i->first);
798 // Which is the best candidate?
799 unsigned BestCandidate = 0;
800 float MinConflicts = Conflicts[0];
801 for (unsigned i = 1; i != NumCands; ++i) {
802 if (Conflicts[i] < MinConflicts) {
804 MinConflicts = Conflicts[i];
808 std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
809 std::back_inserter(SpillIntervals));
813 struct WeightCompare {
814 typedef std::pair<unsigned, float> RegWeightPair;
815 bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
816 return LHS.second < RHS.second;
821 static bool weightsAreClose(float w1, float w2) {
825 float diff = w1 - w2;
826 if (diff <= 0.02f) // Within 0.02f
828 return (diff / w2) <= 0.05f; // Within 5%.
831 LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
832 DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
833 if (I == NextReloadMap.end())
835 return &li_->getInterval(I->second);
838 void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
839 bool isNew = DowngradedRegs.insert(Reg);
840 isNew = isNew; // Silence compiler warning.
841 assert(isNew && "Multiple reloads holding the same register?");
842 DowngradeMap.insert(std::make_pair(li->reg, Reg));
843 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS) {
844 isNew = DowngradedRegs.insert(*AS);
845 isNew = isNew; // Silence compiler warning.
846 assert(isNew && "Multiple reloads holding the same register?");
847 DowngradeMap.insert(std::make_pair(li->reg, *AS));
852 void RALinScan::UpgradeRegister(unsigned Reg) {
854 DowngradedRegs.erase(Reg);
855 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
856 DowngradedRegs.erase(*AS);
862 bool operator()(LiveInterval* A, LiveInterval* B) {
863 return A->beginNumber() < B->beginNumber();
868 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
870 void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
872 DOUT << "\tallocating current interval: ";
874 // This is an implicitly defined live interval, just assign any register.
875 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
877 unsigned physReg = cur->preference;
879 physReg = *RC->allocation_order_begin(*mf_);
880 DOUT << tri_->getName(physReg) << '\n';
881 // Note the register is not really in use.
882 vrm_->assignVirt2Phys(cur->reg, physReg);
888 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
889 unsigned StartPosition = cur->beginNumber();
890 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
892 // If start of this live interval is defined by a move instruction and its
893 // source is assigned a physical register that is compatible with the target
894 // register class, then we should try to assign it the same register.
895 // This can happen when the move is from a larger register class to a smaller
896 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
897 if (!cur->preference && cur->hasAtLeastOneValue()) {
898 VNInfo *vni = cur->begin()->valno;
899 if (vni->def && vni->def != ~1U && vni->def != ~0U) {
900 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
901 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
903 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
905 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
907 else if (vrm_->isAssignedReg(SrcReg))
908 Reg = vrm_->getPhys(SrcReg);
911 Reg = tri_->getSubReg(Reg, SrcSubReg);
913 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
914 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
915 cur->preference = Reg;
921 // For every interval in inactive we overlap with, mark the
922 // register as not free and update spill weights.
923 for (IntervalPtrs::const_iterator i = inactive_.begin(),
924 e = inactive_.end(); i != e; ++i) {
925 unsigned Reg = i->first->reg;
926 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
927 "Can only allocate virtual registers!");
928 const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
929 // If this is not in a related reg class to the register we're allocating,
931 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
932 cur->overlapsFrom(*i->first, i->second-1)) {
933 Reg = vrm_->getPhys(Reg);
935 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
939 // Speculatively check to see if we can get a register right now. If not,
940 // we know we won't be able to by adding more constraints. If so, we can
941 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
942 // is very bad (it contains all callee clobbered registers for any functions
943 // with a call), so we want to avoid doing that if possible.
944 unsigned physReg = getFreePhysReg(cur);
945 unsigned BestPhysReg = physReg;
947 // We got a register. However, if it's in the fixed_ list, we might
948 // conflict with it. Check to see if we conflict with it or any of its
950 SmallSet<unsigned, 8> RegAliases;
951 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
952 RegAliases.insert(*AS);
954 bool ConflictsWithFixed = false;
955 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
956 IntervalPtr &IP = fixed_[i];
957 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
958 // Okay, this reg is on the fixed list. Check to see if we actually
960 LiveInterval *I = IP.first;
961 if (I->endNumber() > StartPosition) {
962 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
964 if (II != I->begin() && II->start > StartPosition)
966 if (cur->overlapsFrom(*I, II)) {
967 ConflictsWithFixed = true;
974 // Okay, the register picked by our speculative getFreePhysReg call turned
975 // out to be in use. Actually add all of the conflicting fixed registers to
976 // regUse_ so we can do an accurate query.
977 if (ConflictsWithFixed) {
978 // For every interval in fixed we overlap with, mark the register as not
979 // free and update spill weights.
980 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
981 IntervalPtr &IP = fixed_[i];
982 LiveInterval *I = IP.first;
984 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
985 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
986 I->endNumber() > StartPosition) {
987 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
989 if (II != I->begin() && II->start > StartPosition)
991 if (cur->overlapsFrom(*I, II)) {
992 unsigned reg = I->reg;
994 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
999 // Using the newly updated regUse_ object, which includes conflicts in the
1000 // future, see if there are any registers available.
1001 physReg = getFreePhysReg(cur);
1005 // Restore the physical register tracker, removing information about the
1009 // If we find a free register, we are done: assign this virtual to
1010 // the free physical register and add this interval to the active
1013 DOUT << tri_->getName(physReg) << '\n';
1014 vrm_->assignVirt2Phys(cur->reg, physReg);
1016 active_.push_back(std::make_pair(cur, cur->begin()));
1017 handled_.push_back(cur);
1019 // "Upgrade" the physical register since it has been allocated.
1020 UpgradeRegister(physReg);
1021 if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
1022 // "Downgrade" physReg to try to keep physReg from being allocated until
1023 // the next reload from the same SS is allocated.
1024 NextReloadLI->preference = physReg;
1025 DowngradeRegister(cur, physReg);
1029 DOUT << "no free registers\n";
1031 // Compile the spill weights into an array that is better for scanning.
1032 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
1033 for (std::vector<std::pair<unsigned, float> >::iterator
1034 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
1035 updateSpillWeights(SpillWeights, I->first, I->second, RC);
1037 // for each interval in active, update spill weights.
1038 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
1040 unsigned reg = i->first->reg;
1041 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1042 "Can only allocate virtual registers!");
1043 reg = vrm_->getPhys(reg);
1044 updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
1047 DOUT << "\tassigning stack slot at interval "<< *cur << ":\n";
1049 // Find a register to spill.
1050 float minWeight = HUGE_VALF;
1051 unsigned minReg = 0; /*cur->preference*/; // Try the pref register first.
1054 std::vector<std::pair<unsigned,float> > RegsWeights;
1055 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
1056 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1057 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1059 float regWeight = SpillWeights[reg];
1060 if (minWeight > regWeight)
1062 RegsWeights.push_back(std::make_pair(reg, regWeight));
1065 // If we didn't find a register that is spillable, try aliases?
1067 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1068 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1070 // No need to worry about if the alias register size < regsize of RC.
1071 // We are going to spill all registers that alias it anyway.
1072 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
1073 RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
1077 // Sort all potential spill candidates by weight.
1078 std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare());
1079 minReg = RegsWeights[0].first;
1080 minWeight = RegsWeights[0].second;
1081 if (minWeight == HUGE_VALF) {
1082 // All registers must have inf weight. Just grab one!
1083 minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
1084 if (cur->weight == HUGE_VALF ||
1085 li_->getApproximateInstructionCount(*cur) == 0) {
1086 // Spill a physical register around defs and uses.
1087 if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
1088 // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
1089 // in fixed_. Reset them.
1090 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1091 IntervalPtr &IP = fixed_[i];
1092 LiveInterval *I = IP.first;
1093 if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
1094 IP.second = I->advanceTo(I->begin(), StartPosition);
1097 DowngradedRegs.clear();
1098 assignRegOrStackSlotAtInterval(cur);
1100 cerr << "Ran out of registers during register allocation!\n";
1107 // Find up to 3 registers to consider as spill candidates.
1108 unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
1109 while (LastCandidate > 1) {
1110 if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
1115 DOUT << "\t\tregister(s) with min weight(s): ";
1116 DEBUG(for (unsigned i = 0; i != LastCandidate; ++i)
1117 DOUT << tri_->getName(RegsWeights[i].first)
1118 << " (" << RegsWeights[i].second << ")\n");
1120 // If the current has the minimum weight, we need to spill it and
1121 // add any added intervals back to unhandled, and restart
1123 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
1124 DOUT << "\t\t\tspilling(c): " << *cur << '\n';
1125 SmallVector<LiveInterval*, 8> spillIs;
1126 std::vector<LiveInterval*> added;
1128 if (!NewSpillFramework) {
1129 added = li_->addIntervalsForSpills(*cur, spillIs, loopInfo, *vrm_);
1132 added = spiller_->spill(cur);
1135 std::sort(added.begin(), added.end(), LISorter());
1136 addStackInterval(cur, ls_, li_, mri_, *vrm_);
1138 return; // Early exit if all spills were folded.
1140 // Merge added with unhandled. Note that we have already sorted
1141 // intervals returned by addIntervalsForSpills by their starting
1143 // This also update the NextReloadMap. That is, it adds mapping from a
1144 // register defined by a reload from SS to the next reload from SS in the
1145 // same basic block.
1146 MachineBasicBlock *LastReloadMBB = 0;
1147 LiveInterval *LastReload = 0;
1148 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1149 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1150 LiveInterval *ReloadLi = added[i];
1151 if (ReloadLi->weight == HUGE_VALF &&
1152 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1153 unsigned ReloadIdx = ReloadLi->beginNumber();
1154 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1155 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1156 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1157 // Last reload of same SS is in the same MBB. We want to try to
1158 // allocate both reloads the same register and make sure the reg
1159 // isn't clobbered in between if at all possible.
1160 assert(LastReload->beginNumber() < ReloadIdx);
1161 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1163 LastReloadMBB = ReloadMBB;
1164 LastReload = ReloadLi;
1165 LastReloadSS = ReloadSS;
1167 unhandled_.push(ReloadLi);
1174 // Push the current interval back to unhandled since we are going
1175 // to re-run at least this iteration. Since we didn't modify it it
1176 // should go back right in the front of the list
1177 unhandled_.push(cur);
1179 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
1180 "did not choose a register to spill?");
1182 // We spill all intervals aliasing the register with
1183 // minimum weight, rollback to the interval with the earliest
1184 // start point and let the linear scan algorithm run again
1185 SmallVector<LiveInterval*, 8> spillIs;
1187 // Determine which intervals have to be spilled.
1188 findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
1190 // Set of spilled vregs (used later to rollback properly)
1191 SmallSet<unsigned, 8> spilled;
1193 // The earliest start of a Spilled interval indicates up to where
1194 // in handled we need to roll back
1195 unsigned earliestStart = cur->beginNumber();
1197 // Spill live intervals of virtual regs mapped to the physical register we
1198 // want to clear (and its aliases). We only spill those that overlap with the
1199 // current interval as the rest do not affect its allocation. we also keep
1200 // track of the earliest start of all spilled live intervals since this will
1201 // mark our rollback point.
1202 std::vector<LiveInterval*> added;
1203 while (!spillIs.empty()) {
1204 LiveInterval *sli = spillIs.back();
1206 DOUT << "\t\t\tspilling(a): " << *sli << '\n';
1207 earliestStart = std::min(earliestStart, sli->beginNumber());
1208 std::vector<LiveInterval*> newIs =
1209 li_->addIntervalsForSpills(*sli, spillIs, loopInfo, *vrm_);
1210 addStackInterval(sli, ls_, li_, mri_, *vrm_);
1211 std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
1212 spilled.insert(sli->reg);
1215 DOUT << "\t\trolling back to: " << earliestStart << '\n';
1217 // Scan handled in reverse order up to the earliest start of a
1218 // spilled live interval and undo each one, restoring the state of
1220 while (!handled_.empty()) {
1221 LiveInterval* i = handled_.back();
1222 // If this interval starts before t we are done.
1223 if (i->beginNumber() < earliestStart)
1225 DOUT << "\t\t\tundo changes for: " << *i << '\n';
1226 handled_.pop_back();
1228 // When undoing a live interval allocation we must know if it is active or
1229 // inactive to properly update regUse_ and the VirtRegMap.
1230 IntervalPtrs::iterator it;
1231 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
1233 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1234 if (!spilled.count(i->reg))
1236 delRegUse(vrm_->getPhys(i->reg));
1237 vrm_->clearVirt(i->reg);
1238 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
1239 inactive_.erase(it);
1240 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1241 if (!spilled.count(i->reg))
1243 vrm_->clearVirt(i->reg);
1245 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
1246 "Can only allocate virtual registers!");
1247 vrm_->clearVirt(i->reg);
1251 DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
1252 if (ii == DowngradeMap.end())
1253 // It interval has a preference, it must be defined by a copy. Clear the
1254 // preference now since the source interval allocation may have been
1258 UpgradeRegister(ii->second);
1262 // Rewind the iterators in the active, inactive, and fixed lists back to the
1263 // point we reverted to.
1264 RevertVectorIteratorsTo(active_, earliestStart);
1265 RevertVectorIteratorsTo(inactive_, earliestStart);
1266 RevertVectorIteratorsTo(fixed_, earliestStart);
1268 // Scan the rest and undo each interval that expired after t and
1269 // insert it in active (the next iteration of the algorithm will
1270 // put it in inactive if required)
1271 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
1272 LiveInterval *HI = handled_[i];
1273 if (!HI->expiredAt(earliestStart) &&
1274 HI->expiredAt(cur->beginNumber())) {
1275 DOUT << "\t\t\tundo changes for: " << *HI << '\n';
1276 active_.push_back(std::make_pair(HI, HI->begin()));
1277 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
1278 addRegUse(vrm_->getPhys(HI->reg));
1282 // Merge added with unhandled.
1283 // This also update the NextReloadMap. That is, it adds mapping from a
1284 // register defined by a reload from SS to the next reload from SS in the
1285 // same basic block.
1286 MachineBasicBlock *LastReloadMBB = 0;
1287 LiveInterval *LastReload = 0;
1288 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1289 std::sort(added.begin(), added.end(), LISorter());
1290 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1291 LiveInterval *ReloadLi = added[i];
1292 if (ReloadLi->weight == HUGE_VALF &&
1293 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1294 unsigned ReloadIdx = ReloadLi->beginNumber();
1295 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1296 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1297 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1298 // Last reload of same SS is in the same MBB. We want to try to
1299 // allocate both reloads the same register and make sure the reg
1300 // isn't clobbered in between if at all possible.
1301 assert(LastReload->beginNumber() < ReloadIdx);
1302 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1304 LastReloadMBB = ReloadMBB;
1305 LastReload = ReloadLi;
1306 LastReloadSS = ReloadSS;
1308 unhandled_.push(ReloadLi);
1312 unsigned RALinScan::getFreePhysReg(const TargetRegisterClass *RC,
1313 unsigned MaxInactiveCount,
1314 SmallVector<unsigned, 256> &inactiveCounts,
1316 unsigned FreeReg = 0;
1317 unsigned FreeRegInactiveCount = 0;
1319 TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_);
1320 TargetRegisterClass::iterator E = RC->allocation_order_end(*mf_);
1321 assert(I != E && "No allocatable register in this register class!");
1323 // Scan for the first available register.
1324 for (; I != E; ++I) {
1326 // Ignore "downgraded" registers.
1327 if (SkipDGRegs && DowngradedRegs.count(Reg))
1329 if (isRegAvail(Reg)) {
1331 if (FreeReg < inactiveCounts.size())
1332 FreeRegInactiveCount = inactiveCounts[FreeReg];
1334 FreeRegInactiveCount = 0;
1339 // If there are no free regs, or if this reg has the max inactive count,
1340 // return this register.
1341 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount)
1344 // Continue scanning the registers, looking for the one with the highest
1345 // inactive count. Alkis found that this reduced register pressure very
1346 // slightly on X86 (in rev 1.94 of this file), though this should probably be
1348 for (; I != E; ++I) {
1350 // Ignore "downgraded" registers.
1351 if (SkipDGRegs && DowngradedRegs.count(Reg))
1353 if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
1354 FreeRegInactiveCount < inactiveCounts[Reg]) {
1356 FreeRegInactiveCount = inactiveCounts[Reg];
1357 if (FreeRegInactiveCount == MaxInactiveCount)
1358 break; // We found the one with the max inactive count.
1365 /// getFreePhysReg - return a free physical register for this virtual register
1366 /// interval if we have one, otherwise return 0.
1367 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
1368 SmallVector<unsigned, 256> inactiveCounts;
1369 unsigned MaxInactiveCount = 0;
1371 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
1372 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1374 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
1376 unsigned reg = i->first->reg;
1377 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1378 "Can only allocate virtual registers!");
1380 // If this is not in a related reg class to the register we're allocating,
1382 const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
1383 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
1384 reg = vrm_->getPhys(reg);
1385 if (inactiveCounts.size() <= reg)
1386 inactiveCounts.resize(reg+1);
1387 ++inactiveCounts[reg];
1388 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
1392 // If copy coalescer has assigned a "preferred" register, check if it's
1394 if (cur->preference) {
1395 DOUT << "(preferred: " << tri_->getName(cur->preference) << ") ";
1396 if (isRegAvail(cur->preference) &&
1397 RC->contains(cur->preference))
1398 return cur->preference;
1401 if (!DowngradedRegs.empty()) {
1402 unsigned FreeReg = getFreePhysReg(RC, MaxInactiveCount, inactiveCounts,
1407 return getFreePhysReg(RC, MaxInactiveCount, inactiveCounts, false);
1410 FunctionPass* llvm::createLinearScanRegisterAllocator() {
1411 return new RALinScan();