1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "VirtRegMap.h"
16 #include "VirtRegRewriter.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/LiveStackAnalysis.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegAllocRegistry.h"
27 #include "llvm/CodeGen/RegisterCoalescer.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/ADT/EquivalenceClasses.h"
33 #include "llvm/ADT/SmallSet.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/Compiler.h"
39 #include "llvm/Support/ErrorHandling.h"
48 STATISTIC(NumIters , "Number of iterations performed");
49 STATISTIC(NumBacktracks, "Number of times we had to backtrack");
50 STATISTIC(NumCoalesce, "Number of copies coalesced");
51 STATISTIC(NumDowngrade, "Number of registers downgraded");
54 NewHeuristic("new-spilling-heuristic",
55 cl::desc("Use new spilling heuristic"),
56 cl::init(false), cl::Hidden);
59 PreSplitIntervals("pre-alloc-split",
60 cl::desc("Pre-register allocation live interval splitting"),
61 cl::init(false), cl::Hidden);
64 NewSpillFramework("new-spill-framework",
65 cl::desc("New spilling framework"),
66 cl::init(false), cl::Hidden);
68 static RegisterRegAlloc
69 linearscanRegAlloc("linearscan", "linear scan register allocator",
70 createLinearScanRegisterAllocator);
73 struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass {
75 RALinScan() : MachineFunctionPass(&ID) {}
77 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
78 typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
80 /// RelatedRegClasses - This structure is built the first time a function is
81 /// compiled, and keeps track of which register classes have registers that
82 /// belong to multiple classes or have aliases that are in other classes.
83 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
84 DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
86 // NextReloadMap - For each register in the map, it maps to the another
87 // register which is defined by a reload from the same stack slot and
88 // both reloads are in the same basic block.
89 DenseMap<unsigned, unsigned> NextReloadMap;
91 // DowngradedRegs - A set of registers which are being "downgraded", i.e.
92 // un-favored for allocation.
93 SmallSet<unsigned, 8> DowngradedRegs;
95 // DowngradeMap - A map from virtual registers to physical registers being
96 // downgraded for the virtual registers.
97 DenseMap<unsigned, unsigned> DowngradeMap;
100 MachineRegisterInfo* mri_;
101 const TargetMachine* tm_;
102 const TargetRegisterInfo* tri_;
103 const TargetInstrInfo* tii_;
104 BitVector allocatableRegs_;
107 const MachineLoopInfo *loopInfo;
109 /// handled_ - Intervals are added to the handled_ set in the order of their
110 /// start value. This is uses for backtracking.
111 std::vector<LiveInterval*> handled_;
113 /// fixed_ - Intervals that correspond to machine registers.
117 /// active_ - Intervals that are currently being processed, and which have a
118 /// live range active for the current point.
119 IntervalPtrs active_;
121 /// inactive_ - Intervals that are currently being processed, but which have
122 /// a hold at the current point.
123 IntervalPtrs inactive_;
125 typedef std::priority_queue<LiveInterval*,
126 SmallVector<LiveInterval*, 64>,
127 greater_ptr<LiveInterval> > IntervalHeap;
128 IntervalHeap unhandled_;
130 /// regUse_ - Tracks register usage.
131 SmallVector<unsigned, 32> regUse_;
132 SmallVector<unsigned, 32> regUseBackUp_;
134 /// vrm_ - Tracks register assignments.
137 std::auto_ptr<VirtRegRewriter> rewriter_;
139 std::auto_ptr<Spiller> spiller_;
142 virtual const char* getPassName() const {
143 return "Linear Scan Register Allocator";
146 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
147 AU.addRequired<LiveIntervals>();
149 AU.addRequiredID(StrongPHIEliminationID);
150 // Make sure PassManager knows which analyses to make available
151 // to coalescing and which analyses coalescing invalidates.
152 AU.addRequiredTransitive<RegisterCoalescer>();
153 if (PreSplitIntervals)
154 AU.addRequiredID(PreAllocSplittingID);
155 AU.addRequired<LiveStacks>();
156 AU.addPreserved<LiveStacks>();
157 AU.addRequired<MachineLoopInfo>();
158 AU.addPreserved<MachineLoopInfo>();
159 AU.addRequired<VirtRegMap>();
160 AU.addPreserved<VirtRegMap>();
161 AU.addPreservedID(MachineDominatorsID);
162 MachineFunctionPass::getAnalysisUsage(AU);
165 /// runOnMachineFunction - register allocate the whole function
166 bool runOnMachineFunction(MachineFunction&);
169 /// linearScan - the linear scan algorithm
172 /// initIntervalSets - initialize the interval sets.
174 void initIntervalSets();
176 /// processActiveIntervals - expire old intervals and move non-overlapping
177 /// ones to the inactive list.
178 void processActiveIntervals(unsigned CurPoint);
180 /// processInactiveIntervals - expire old intervals and move overlapping
181 /// ones to the active list.
182 void processInactiveIntervals(unsigned CurPoint);
184 /// hasNextReloadInterval - Return the next liveinterval that's being
185 /// defined by a reload from the same SS as the specified one.
186 LiveInterval *hasNextReloadInterval(LiveInterval *cur);
188 /// DowngradeRegister - Downgrade a register for allocation.
189 void DowngradeRegister(LiveInterval *li, unsigned Reg);
191 /// UpgradeRegister - Upgrade a register for allocation.
192 void UpgradeRegister(unsigned Reg);
194 /// assignRegOrStackSlotAtInterval - assign a register if one
195 /// is available, or spill.
196 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
198 void updateSpillWeights(std::vector<float> &Weights,
199 unsigned reg, float weight,
200 const TargetRegisterClass *RC);
202 /// findIntervalsToSpill - Determine the intervals to spill for the
203 /// specified interval. It's passed the physical registers whose spill
204 /// weight is the lowest among all the registers whose live intervals
205 /// conflict with the interval.
206 void findIntervalsToSpill(LiveInterval *cur,
207 std::vector<std::pair<unsigned,float> > &Candidates,
209 SmallVector<LiveInterval*, 8> &SpillIntervals);
211 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
212 /// try allocate the definition the same register as the source register
213 /// if the register is not defined during live time of the interval. This
214 /// eliminate a copy. This is used to coalesce copies which were not
215 /// coalesced away before allocation either due to dest and src being in
216 /// different register classes or because the coalescer was overly
218 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
221 /// Register usage / availability tracking helpers.
225 regUse_.resize(tri_->getNumRegs(), 0);
226 regUseBackUp_.resize(tri_->getNumRegs(), 0);
229 void finalizeRegUses() {
231 // Verify all the registers are "freed".
233 for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
234 if (regUse_[i] != 0) {
235 cerr << tri_->getName(i) << " is still in use!\n";
243 regUseBackUp_.clear();
246 void addRegUse(unsigned physReg) {
247 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
248 "should be physical register!");
250 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
254 void delRegUse(unsigned physReg) {
255 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
256 "should be physical register!");
257 assert(regUse_[physReg] != 0);
259 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
260 assert(regUse_[*as] != 0);
265 bool isRegAvail(unsigned physReg) const {
266 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
267 "should be physical register!");
268 return regUse_[physReg] == 0;
271 void backUpRegUses() {
272 regUseBackUp_ = regUse_;
275 void restoreRegUses() {
276 regUse_ = regUseBackUp_;
280 /// Register handling helpers.
283 /// getFreePhysReg - return a free physical register for this virtual
284 /// register interval if we have one, otherwise return 0.
285 unsigned getFreePhysReg(LiveInterval* cur);
286 unsigned getFreePhysReg(LiveInterval* cur,
287 const TargetRegisterClass *RC,
288 unsigned MaxInactiveCount,
289 SmallVector<unsigned, 256> &inactiveCounts,
292 /// assignVirt2StackSlot - assigns this virtual register to a
293 /// stack slot. returns the stack slot
294 int assignVirt2StackSlot(unsigned virtReg);
296 void ComputeRelatedRegClasses();
298 template <typename ItTy>
299 void printIntervals(const char* const str, ItTy i, ItTy e) const {
300 if (str) DOUT << str << " intervals:\n";
301 for (; i != e; ++i) {
302 DOUT << "\t" << *i->first << " -> ";
303 unsigned reg = i->first->reg;
304 if (TargetRegisterInfo::isVirtualRegister(reg)) {
305 reg = vrm_->getPhys(reg);
307 DOUT << tri_->getName(reg) << '\n';
311 char RALinScan::ID = 0;
314 static RegisterPass<RALinScan>
315 X("linearscan-regalloc", "Linear Scan Register Allocator");
317 void RALinScan::ComputeRelatedRegClasses() {
318 // First pass, add all reg classes to the union, and determine at least one
319 // reg class that each register is in.
320 bool HasAliases = false;
321 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
322 E = tri_->regclass_end(); RCI != E; ++RCI) {
323 RelatedRegClasses.insert(*RCI);
324 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
326 HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
328 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
330 // Already processed this register. Just make sure we know that
331 // multiple register classes share a register.
332 RelatedRegClasses.unionSets(PRC, *RCI);
339 // Second pass, now that we know conservatively what register classes each reg
340 // belongs to, add info about aliases. We don't need to do this for targets
341 // without register aliases.
343 for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
344 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
346 for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
347 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
350 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
351 /// try allocate the definition the same register as the source register
352 /// if the register is not defined during live time of the interval. This
353 /// eliminate a copy. This is used to coalesce copies which were not
354 /// coalesced away before allocation either due to dest and src being in
355 /// different register classes or because the coalescer was overly
357 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
358 unsigned Preference = vrm_->getRegAllocPref(cur.reg);
359 if ((Preference && Preference == Reg) || !cur.containsOneValue())
362 VNInfo *vni = cur.begin()->valno;
363 if (!vni->def || vni->isUnused() || !vni->isDefAccurate())
365 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
366 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg, PhysReg;
368 !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
371 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
372 if (!vrm_->isAssignedReg(SrcReg))
374 PhysReg = vrm_->getPhys(SrcReg);
379 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
380 if (!RC->contains(PhysReg))
384 if (!li_->conflictsWithPhysRegDef(cur, *vrm_, PhysReg)) {
385 DOUT << "Coalescing: " << cur << " -> " << tri_->getName(PhysReg)
387 vrm_->clearVirt(cur.reg);
388 vrm_->assignVirt2Phys(cur.reg, PhysReg);
390 // Remove unnecessary kills since a copy does not clobber the register.
391 if (li_->hasInterval(SrcReg)) {
392 LiveInterval &SrcLI = li_->getInterval(SrcReg);
393 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(cur.reg),
394 E = mri_->reg_end(); I != E; ++I) {
395 MachineOperand &O = I.getOperand();
396 if (!O.isUse() || !O.isKill())
398 MachineInstr *MI = &*I;
399 if (SrcLI.liveAt(li_->getDefIndex(li_->getInstructionIndex(MI))))
411 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
413 mri_ = &fn.getRegInfo();
414 tm_ = &fn.getTarget();
415 tri_ = tm_->getRegisterInfo();
416 tii_ = tm_->getInstrInfo();
417 allocatableRegs_ = tri_->getAllocatableSet(fn);
418 li_ = &getAnalysis<LiveIntervals>();
419 ls_ = &getAnalysis<LiveStacks>();
420 loopInfo = &getAnalysis<MachineLoopInfo>();
422 // We don't run the coalescer here because we have no reason to
423 // interact with it. If the coalescer requires interaction, it
424 // won't do anything. If it doesn't require interaction, we assume
425 // it was run as a separate pass.
427 // If this is the first function compiled, compute the related reg classes.
428 if (RelatedRegClasses.empty())
429 ComputeRelatedRegClasses();
431 // Also resize register usage trackers.
434 vrm_ = &getAnalysis<VirtRegMap>();
435 if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
437 if (NewSpillFramework) {
438 spiller_.reset(createSpiller(mf_, li_, ls_, vrm_));
445 // Rewrite spill code and update the PhysRegsUsed set.
446 rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
448 assert(unhandled_.empty() && "Unhandled live intervals remain!");
456 NextReloadMap.clear();
457 DowngradedRegs.clear();
458 DowngradeMap.clear();
464 /// initIntervalSets - initialize the interval sets.
466 void RALinScan::initIntervalSets()
468 assert(unhandled_.empty() && fixed_.empty() &&
469 active_.empty() && inactive_.empty() &&
470 "interval sets should be empty on initialization");
472 handled_.reserve(li_->getNumIntervals());
474 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
475 if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
476 mri_->setPhysRegUsed(i->second->reg);
477 fixed_.push_back(std::make_pair(i->second, i->second->begin()));
479 unhandled_.push(i->second);
483 void RALinScan::linearScan()
485 // linear scan algorithm
486 DOUT << "********** LINEAR SCAN **********\n";
487 DOUT << "********** Function: " << mf_->getFunction()->getName() << '\n';
489 DEBUG(printIntervals("fixed", fixed_.begin(), fixed_.end()));
491 while (!unhandled_.empty()) {
492 // pick the interval with the earliest start point
493 LiveInterval* cur = unhandled_.top();
496 DOUT << "\n*** CURRENT ***: " << *cur << '\n';
499 processActiveIntervals(cur->beginNumber());
500 processInactiveIntervals(cur->beginNumber());
502 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
503 "Can only allocate virtual registers!");
506 // Allocating a virtual register. try to find a free
507 // physical register or spill an interval (possibly this one) in order to
509 assignRegOrStackSlotAtInterval(cur);
511 DEBUG(printIntervals("active", active_.begin(), active_.end()));
512 DEBUG(printIntervals("inactive", inactive_.begin(), inactive_.end()));
515 // Expire any remaining active intervals
516 while (!active_.empty()) {
517 IntervalPtr &IP = active_.back();
518 unsigned reg = IP.first->reg;
519 DOUT << "\tinterval " << *IP.first << " expired\n";
520 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
521 "Can only allocate virtual registers!");
522 reg = vrm_->getPhys(reg);
527 // Expire any remaining inactive intervals
528 DEBUG(for (IntervalPtrs::reverse_iterator
529 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
530 DOUT << "\tinterval " << *i->first << " expired\n");
533 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
534 MachineFunction::iterator EntryMBB = mf_->begin();
535 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
536 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
537 LiveInterval &cur = *i->second;
539 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
542 else if (vrm_->isAssignedReg(cur.reg))
543 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
546 // Ignore splited live intervals.
547 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
550 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
552 const LiveRange &LR = *I;
553 if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
554 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
555 if (LiveInMBBs[i] != EntryMBB) {
556 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
557 "Adding a virtual register to livein set?");
558 LiveInMBBs[i]->addLiveIn(Reg);
567 // Look for physical registers that end up not being allocated even though
568 // register allocator had to spill other registers in its register class.
569 if (ls_->getNumIntervals() == 0)
571 if (!vrm_->FindUnusedRegisters(li_))
575 /// processActiveIntervals - expire old intervals and move non-overlapping ones
576 /// to the inactive list.
577 void RALinScan::processActiveIntervals(unsigned CurPoint)
579 DOUT << "\tprocessing active intervals:\n";
581 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
582 LiveInterval *Interval = active_[i].first;
583 LiveInterval::iterator IntervalPos = active_[i].second;
584 unsigned reg = Interval->reg;
586 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
588 if (IntervalPos == Interval->end()) { // Remove expired intervals.
589 DOUT << "\t\tinterval " << *Interval << " expired\n";
590 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
591 "Can only allocate virtual registers!");
592 reg = vrm_->getPhys(reg);
595 // Pop off the end of the list.
596 active_[i] = active_.back();
600 } else if (IntervalPos->start > CurPoint) {
601 // Move inactive intervals to inactive list.
602 DOUT << "\t\tinterval " << *Interval << " inactive\n";
603 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
604 "Can only allocate virtual registers!");
605 reg = vrm_->getPhys(reg);
608 inactive_.push_back(std::make_pair(Interval, IntervalPos));
610 // Pop off the end of the list.
611 active_[i] = active_.back();
615 // Otherwise, just update the iterator position.
616 active_[i].second = IntervalPos;
621 /// processInactiveIntervals - expire old intervals and move overlapping
622 /// ones to the active list.
623 void RALinScan::processInactiveIntervals(unsigned CurPoint)
625 DOUT << "\tprocessing inactive intervals:\n";
627 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
628 LiveInterval *Interval = inactive_[i].first;
629 LiveInterval::iterator IntervalPos = inactive_[i].second;
630 unsigned reg = Interval->reg;
632 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
634 if (IntervalPos == Interval->end()) { // remove expired intervals.
635 DOUT << "\t\tinterval " << *Interval << " expired\n";
637 // Pop off the end of the list.
638 inactive_[i] = inactive_.back();
639 inactive_.pop_back();
641 } else if (IntervalPos->start <= CurPoint) {
642 // move re-activated intervals in active list
643 DOUT << "\t\tinterval " << *Interval << " active\n";
644 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
645 "Can only allocate virtual registers!");
646 reg = vrm_->getPhys(reg);
649 active_.push_back(std::make_pair(Interval, IntervalPos));
651 // Pop off the end of the list.
652 inactive_[i] = inactive_.back();
653 inactive_.pop_back();
656 // Otherwise, just update the iterator position.
657 inactive_[i].second = IntervalPos;
662 /// updateSpillWeights - updates the spill weights of the specifed physical
663 /// register and its weight.
664 void RALinScan::updateSpillWeights(std::vector<float> &Weights,
665 unsigned reg, float weight,
666 const TargetRegisterClass *RC) {
667 SmallSet<unsigned, 4> Processed;
668 SmallSet<unsigned, 4> SuperAdded;
669 SmallVector<unsigned, 4> Supers;
670 Weights[reg] += weight;
671 Processed.insert(reg);
672 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
673 Weights[*as] += weight;
674 Processed.insert(*as);
675 if (tri_->isSubRegister(*as, reg) &&
676 SuperAdded.insert(*as) &&
678 Supers.push_back(*as);
682 // If the alias is a super-register, and the super-register is in the
683 // register class we are trying to allocate. Then add the weight to all
684 // sub-registers of the super-register even if they are not aliases.
685 // e.g. allocating for GR32, bh is not used, updating bl spill weight.
686 // bl should get the same spill weight otherwise it will be choosen
687 // as a spill candidate since spilling bh doesn't make ebx available.
688 for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
689 for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
690 if (!Processed.count(*sr))
691 Weights[*sr] += weight;
696 RALinScan::IntervalPtrs::iterator
697 FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
698 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
700 if (I->first == LI) return I;
704 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, unsigned Point){
705 for (unsigned i = 0, e = V.size(); i != e; ++i) {
706 RALinScan::IntervalPtr &IP = V[i];
707 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
709 if (I != IP.first->begin()) --I;
714 /// addStackInterval - Create a LiveInterval for stack if the specified live
715 /// interval has been spilled.
716 static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
718 MachineRegisterInfo* mri_, VirtRegMap &vrm_) {
719 int SS = vrm_.getStackSlot(cur->reg);
720 if (SS == VirtRegMap::NO_STACK_SLOT)
723 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
724 LiveInterval &SI = ls_->getOrCreateInterval(SS, RC);
727 if (SI.hasAtLeastOneValue())
728 VNI = SI.getValNumInfo(0);
730 VNI = SI.getNextValue(0, 0, false, ls_->getVNInfoAllocator());
732 LiveInterval &RI = li_->getInterval(cur->reg);
733 // FIXME: This may be overly conservative.
734 SI.MergeRangesInAsValue(RI, VNI);
737 /// getConflictWeight - Return the number of conflicts between cur
738 /// live interval and defs and uses of Reg weighted by loop depthes.
740 float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
741 MachineRegisterInfo *mri_,
742 const MachineLoopInfo *loopInfo) {
744 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
745 E = mri_->reg_end(); I != E; ++I) {
746 MachineInstr *MI = &*I;
747 if (cur->liveAt(li_->getInstructionIndex(MI))) {
748 unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
749 Conflicts += powf(10.0f, (float)loopDepth);
755 /// findIntervalsToSpill - Determine the intervals to spill for the
756 /// specified interval. It's passed the physical registers whose spill
757 /// weight is the lowest among all the registers whose live intervals
758 /// conflict with the interval.
759 void RALinScan::findIntervalsToSpill(LiveInterval *cur,
760 std::vector<std::pair<unsigned,float> > &Candidates,
762 SmallVector<LiveInterval*, 8> &SpillIntervals) {
763 // We have figured out the *best* register to spill. But there are other
764 // registers that are pretty good as well (spill weight within 3%). Spill
765 // the one that has fewest defs and uses that conflict with cur.
766 float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
767 SmallVector<LiveInterval*, 8> SLIs[3];
769 DOUT << "\tConsidering " << NumCands << " candidates: ";
770 DEBUG(for (unsigned i = 0; i != NumCands; ++i)
771 DOUT << tri_->getName(Candidates[i].first) << " ";
774 // Calculate the number of conflicts of each candidate.
775 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
776 unsigned Reg = i->first->reg;
777 unsigned PhysReg = vrm_->getPhys(Reg);
778 if (!cur->overlapsFrom(*i->first, i->second))
780 for (unsigned j = 0; j < NumCands; ++j) {
781 unsigned Candidate = Candidates[j].first;
782 if (tri_->regsOverlap(PhysReg, Candidate)) {
784 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
785 SLIs[j].push_back(i->first);
790 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
791 unsigned Reg = i->first->reg;
792 unsigned PhysReg = vrm_->getPhys(Reg);
793 if (!cur->overlapsFrom(*i->first, i->second-1))
795 for (unsigned j = 0; j < NumCands; ++j) {
796 unsigned Candidate = Candidates[j].first;
797 if (tri_->regsOverlap(PhysReg, Candidate)) {
799 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
800 SLIs[j].push_back(i->first);
805 // Which is the best candidate?
806 unsigned BestCandidate = 0;
807 float MinConflicts = Conflicts[0];
808 for (unsigned i = 1; i != NumCands; ++i) {
809 if (Conflicts[i] < MinConflicts) {
811 MinConflicts = Conflicts[i];
815 std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
816 std::back_inserter(SpillIntervals));
820 struct WeightCompare {
821 typedef std::pair<unsigned, float> RegWeightPair;
822 bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
823 return LHS.second < RHS.second;
828 static bool weightsAreClose(float w1, float w2) {
832 float diff = w1 - w2;
833 if (diff <= 0.02f) // Within 0.02f
835 return (diff / w2) <= 0.05f; // Within 5%.
838 LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
839 DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
840 if (I == NextReloadMap.end())
842 return &li_->getInterval(I->second);
845 void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
846 bool isNew = DowngradedRegs.insert(Reg);
847 isNew = isNew; // Silence compiler warning.
848 assert(isNew && "Multiple reloads holding the same register?");
849 DowngradeMap.insert(std::make_pair(li->reg, Reg));
850 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS) {
851 isNew = DowngradedRegs.insert(*AS);
852 isNew = isNew; // Silence compiler warning.
853 assert(isNew && "Multiple reloads holding the same register?");
854 DowngradeMap.insert(std::make_pair(li->reg, *AS));
859 void RALinScan::UpgradeRegister(unsigned Reg) {
861 DowngradedRegs.erase(Reg);
862 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
863 DowngradedRegs.erase(*AS);
869 bool operator()(LiveInterval* A, LiveInterval* B) {
870 return A->beginNumber() < B->beginNumber();
875 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
877 void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
879 DOUT << "\tallocating current interval: ";
881 // This is an implicitly defined live interval, just assign any register.
882 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
884 unsigned physReg = vrm_->getRegAllocPref(cur->reg);
886 physReg = *RC->allocation_order_begin(*mf_);
887 DOUT << tri_->getName(physReg) << '\n';
888 // Note the register is not really in use.
889 vrm_->assignVirt2Phys(cur->reg, physReg);
895 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
896 unsigned StartPosition = cur->beginNumber();
897 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
899 // If start of this live interval is defined by a move instruction and its
900 // source is assigned a physical register that is compatible with the target
901 // register class, then we should try to assign it the same register.
902 // This can happen when the move is from a larger register class to a smaller
903 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
904 if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
905 VNInfo *vni = cur->begin()->valno;
906 if (vni->def && !vni->isUnused() && vni->isDefAccurate()) {
907 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
908 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
910 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
912 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
914 else if (vrm_->isAssignedReg(SrcReg))
915 Reg = vrm_->getPhys(SrcReg);
918 Reg = tri_->getSubReg(Reg, SrcSubReg);
920 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
921 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
922 mri_->setRegAllocationHint(cur->reg, 0, Reg);
928 // For every interval in inactive we overlap with, mark the
929 // register as not free and update spill weights.
930 for (IntervalPtrs::const_iterator i = inactive_.begin(),
931 e = inactive_.end(); i != e; ++i) {
932 unsigned Reg = i->first->reg;
933 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
934 "Can only allocate virtual registers!");
935 const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
936 // If this is not in a related reg class to the register we're allocating,
938 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
939 cur->overlapsFrom(*i->first, i->second-1)) {
940 Reg = vrm_->getPhys(Reg);
942 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
946 // Speculatively check to see if we can get a register right now. If not,
947 // we know we won't be able to by adding more constraints. If so, we can
948 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
949 // is very bad (it contains all callee clobbered registers for any functions
950 // with a call), so we want to avoid doing that if possible.
951 unsigned physReg = getFreePhysReg(cur);
952 unsigned BestPhysReg = physReg;
954 // We got a register. However, if it's in the fixed_ list, we might
955 // conflict with it. Check to see if we conflict with it or any of its
957 SmallSet<unsigned, 8> RegAliases;
958 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
959 RegAliases.insert(*AS);
961 bool ConflictsWithFixed = false;
962 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
963 IntervalPtr &IP = fixed_[i];
964 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
965 // Okay, this reg is on the fixed list. Check to see if we actually
967 LiveInterval *I = IP.first;
968 if (I->endNumber() > StartPosition) {
969 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
971 if (II != I->begin() && II->start > StartPosition)
973 if (cur->overlapsFrom(*I, II)) {
974 ConflictsWithFixed = true;
981 // Okay, the register picked by our speculative getFreePhysReg call turned
982 // out to be in use. Actually add all of the conflicting fixed registers to
983 // regUse_ so we can do an accurate query.
984 if (ConflictsWithFixed) {
985 // For every interval in fixed we overlap with, mark the register as not
986 // free and update spill weights.
987 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
988 IntervalPtr &IP = fixed_[i];
989 LiveInterval *I = IP.first;
991 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
992 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
993 I->endNumber() > StartPosition) {
994 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
996 if (II != I->begin() && II->start > StartPosition)
998 if (cur->overlapsFrom(*I, II)) {
999 unsigned reg = I->reg;
1001 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
1006 // Using the newly updated regUse_ object, which includes conflicts in the
1007 // future, see if there are any registers available.
1008 physReg = getFreePhysReg(cur);
1012 // Restore the physical register tracker, removing information about the
1016 // If we find a free register, we are done: assign this virtual to
1017 // the free physical register and add this interval to the active
1020 DOUT << tri_->getName(physReg) << '\n';
1021 vrm_->assignVirt2Phys(cur->reg, physReg);
1023 active_.push_back(std::make_pair(cur, cur->begin()));
1024 handled_.push_back(cur);
1026 // "Upgrade" the physical register since it has been allocated.
1027 UpgradeRegister(physReg);
1028 if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
1029 // "Downgrade" physReg to try to keep physReg from being allocated until
1030 // the next reload from the same SS is allocated.
1031 mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg);
1032 DowngradeRegister(cur, physReg);
1036 DOUT << "no free registers\n";
1038 // Compile the spill weights into an array that is better for scanning.
1039 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
1040 for (std::vector<std::pair<unsigned, float> >::iterator
1041 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
1042 updateSpillWeights(SpillWeights, I->first, I->second, RC);
1044 // for each interval in active, update spill weights.
1045 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
1047 unsigned reg = i->first->reg;
1048 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1049 "Can only allocate virtual registers!");
1050 reg = vrm_->getPhys(reg);
1051 updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
1054 DOUT << "\tassigning stack slot at interval "<< *cur << ":\n";
1056 // Find a register to spill.
1057 float minWeight = HUGE_VALF;
1058 unsigned minReg = 0;
1061 std::vector<std::pair<unsigned,float> > RegsWeights;
1062 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
1063 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1064 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1066 float regWeight = SpillWeights[reg];
1067 if (minWeight > regWeight)
1069 RegsWeights.push_back(std::make_pair(reg, regWeight));
1072 // If we didn't find a register that is spillable, try aliases?
1074 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1075 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1077 // No need to worry about if the alias register size < regsize of RC.
1078 // We are going to spill all registers that alias it anyway.
1079 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
1080 RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
1084 // Sort all potential spill candidates by weight.
1085 std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare());
1086 minReg = RegsWeights[0].first;
1087 minWeight = RegsWeights[0].second;
1088 if (minWeight == HUGE_VALF) {
1089 // All registers must have inf weight. Just grab one!
1090 minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
1091 if (cur->weight == HUGE_VALF ||
1092 li_->getApproximateInstructionCount(*cur) == 0) {
1093 // Spill a physical register around defs and uses.
1094 if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
1095 // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
1096 // in fixed_. Reset them.
1097 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1098 IntervalPtr &IP = fixed_[i];
1099 LiveInterval *I = IP.first;
1100 if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
1101 IP.second = I->advanceTo(I->begin(), StartPosition);
1104 DowngradedRegs.clear();
1105 assignRegOrStackSlotAtInterval(cur);
1107 llvm_report_error("Ran out of registers during register allocation!");
1113 // Find up to 3 registers to consider as spill candidates.
1114 unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
1115 while (LastCandidate > 1) {
1116 if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
1121 DOUT << "\t\tregister(s) with min weight(s): ";
1122 DEBUG(for (unsigned i = 0; i != LastCandidate; ++i)
1123 DOUT << tri_->getName(RegsWeights[i].first)
1124 << " (" << RegsWeights[i].second << ")\n");
1126 // If the current has the minimum weight, we need to spill it and
1127 // add any added intervals back to unhandled, and restart
1129 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
1130 DOUT << "\t\t\tspilling(c): " << *cur << '\n';
1131 SmallVector<LiveInterval*, 8> spillIs;
1132 std::vector<LiveInterval*> added;
1134 if (!NewSpillFramework) {
1135 added = li_->addIntervalsForSpills(*cur, spillIs, loopInfo, *vrm_);
1137 added = spiller_->spill(cur);
1140 std::sort(added.begin(), added.end(), LISorter());
1141 addStackInterval(cur, ls_, li_, mri_, *vrm_);
1143 return; // Early exit if all spills were folded.
1145 // Merge added with unhandled. Note that we have already sorted
1146 // intervals returned by addIntervalsForSpills by their starting
1148 // This also update the NextReloadMap. That is, it adds mapping from a
1149 // register defined by a reload from SS to the next reload from SS in the
1150 // same basic block.
1151 MachineBasicBlock *LastReloadMBB = 0;
1152 LiveInterval *LastReload = 0;
1153 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1154 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1155 LiveInterval *ReloadLi = added[i];
1156 if (ReloadLi->weight == HUGE_VALF &&
1157 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1158 unsigned ReloadIdx = ReloadLi->beginNumber();
1159 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1160 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1161 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1162 // Last reload of same SS is in the same MBB. We want to try to
1163 // allocate both reloads the same register and make sure the reg
1164 // isn't clobbered in between if at all possible.
1165 assert(LastReload->beginNumber() < ReloadIdx);
1166 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1168 LastReloadMBB = ReloadMBB;
1169 LastReload = ReloadLi;
1170 LastReloadSS = ReloadSS;
1172 unhandled_.push(ReloadLi);
1179 // Push the current interval back to unhandled since we are going
1180 // to re-run at least this iteration. Since we didn't modify it it
1181 // should go back right in the front of the list
1182 unhandled_.push(cur);
1184 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
1185 "did not choose a register to spill?");
1187 // We spill all intervals aliasing the register with
1188 // minimum weight, rollback to the interval with the earliest
1189 // start point and let the linear scan algorithm run again
1190 SmallVector<LiveInterval*, 8> spillIs;
1192 // Determine which intervals have to be spilled.
1193 findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
1195 // Set of spilled vregs (used later to rollback properly)
1196 SmallSet<unsigned, 8> spilled;
1198 // The earliest start of a Spilled interval indicates up to where
1199 // in handled we need to roll back
1201 LiveInterval *earliestStartInterval = cur;
1203 // Spill live intervals of virtual regs mapped to the physical register we
1204 // want to clear (and its aliases). We only spill those that overlap with the
1205 // current interval as the rest do not affect its allocation. we also keep
1206 // track of the earliest start of all spilled live intervals since this will
1207 // mark our rollback point.
1208 std::vector<LiveInterval*> added;
1209 while (!spillIs.empty()) {
1210 bool epicFail = false;
1211 LiveInterval *sli = spillIs.back();
1213 DOUT << "\t\t\tspilling(a): " << *sli << '\n';
1214 earliestStartInterval =
1215 (earliestStartInterval->beginNumber() < sli->beginNumber()) ?
1216 earliestStartInterval : sli;
1218 std::vector<LiveInterval*> newIs;
1219 if (!NewSpillFramework) {
1220 newIs = li_->addIntervalsForSpills(*sli, spillIs, loopInfo, *vrm_);
1222 newIs = spiller_->spill(sli);
1224 addStackInterval(sli, ls_, li_, mri_, *vrm_);
1225 std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
1226 spilled.insert(sli->reg);
1233 unsigned earliestStart = earliestStartInterval->beginNumber();
1235 DOUT << "\t\trolling back to: " << earliestStart << '\n';
1237 // Scan handled in reverse order up to the earliest start of a
1238 // spilled live interval and undo each one, restoring the state of
1240 while (!handled_.empty()) {
1241 LiveInterval* i = handled_.back();
1242 // If this interval starts before t we are done.
1243 if (i->beginNumber() < earliestStart)
1245 DOUT << "\t\t\tundo changes for: " << *i << '\n';
1246 handled_.pop_back();
1248 // When undoing a live interval allocation we must know if it is active or
1249 // inactive to properly update regUse_ and the VirtRegMap.
1250 IntervalPtrs::iterator it;
1251 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
1253 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1254 if (!spilled.count(i->reg))
1256 delRegUse(vrm_->getPhys(i->reg));
1257 vrm_->clearVirt(i->reg);
1258 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
1259 inactive_.erase(it);
1260 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1261 if (!spilled.count(i->reg))
1263 vrm_->clearVirt(i->reg);
1265 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
1266 "Can only allocate virtual registers!");
1267 vrm_->clearVirt(i->reg);
1271 DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
1272 if (ii == DowngradeMap.end())
1273 // It interval has a preference, it must be defined by a copy. Clear the
1274 // preference now since the source interval allocation may have been
1276 mri_->setRegAllocationHint(i->reg, 0, 0);
1278 UpgradeRegister(ii->second);
1282 // Rewind the iterators in the active, inactive, and fixed lists back to the
1283 // point we reverted to.
1284 RevertVectorIteratorsTo(active_, earliestStart);
1285 RevertVectorIteratorsTo(inactive_, earliestStart);
1286 RevertVectorIteratorsTo(fixed_, earliestStart);
1288 // Scan the rest and undo each interval that expired after t and
1289 // insert it in active (the next iteration of the algorithm will
1290 // put it in inactive if required)
1291 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
1292 LiveInterval *HI = handled_[i];
1293 if (!HI->expiredAt(earliestStart) &&
1294 HI->expiredAt(cur->beginNumber())) {
1295 DOUT << "\t\t\tundo changes for: " << *HI << '\n';
1296 active_.push_back(std::make_pair(HI, HI->begin()));
1297 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
1298 addRegUse(vrm_->getPhys(HI->reg));
1302 // Merge added with unhandled.
1303 // This also update the NextReloadMap. That is, it adds mapping from a
1304 // register defined by a reload from SS to the next reload from SS in the
1305 // same basic block.
1306 MachineBasicBlock *LastReloadMBB = 0;
1307 LiveInterval *LastReload = 0;
1308 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1309 std::sort(added.begin(), added.end(), LISorter());
1310 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1311 LiveInterval *ReloadLi = added[i];
1312 if (ReloadLi->weight == HUGE_VALF &&
1313 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1314 unsigned ReloadIdx = ReloadLi->beginNumber();
1315 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1316 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1317 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1318 // Last reload of same SS is in the same MBB. We want to try to
1319 // allocate both reloads the same register and make sure the reg
1320 // isn't clobbered in between if at all possible.
1321 assert(LastReload->beginNumber() < ReloadIdx);
1322 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1324 LastReloadMBB = ReloadMBB;
1325 LastReload = ReloadLi;
1326 LastReloadSS = ReloadSS;
1328 unhandled_.push(ReloadLi);
1332 unsigned RALinScan::getFreePhysReg(LiveInterval* cur,
1333 const TargetRegisterClass *RC,
1334 unsigned MaxInactiveCount,
1335 SmallVector<unsigned, 256> &inactiveCounts,
1337 unsigned FreeReg = 0;
1338 unsigned FreeRegInactiveCount = 0;
1340 std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(cur->reg);
1341 // Resolve second part of the hint (if possible) given the current allocation.
1342 unsigned physReg = Hint.second;
1344 TargetRegisterInfo::isVirtualRegister(physReg) && vrm_->hasPhys(physReg))
1345 physReg = vrm_->getPhys(physReg);
1347 TargetRegisterClass::iterator I, E;
1348 tie(I, E) = tri_->getAllocationOrder(RC, Hint.first, physReg, *mf_);
1349 assert(I != E && "No allocatable register in this register class!");
1351 // Scan for the first available register.
1352 for (; I != E; ++I) {
1354 // Ignore "downgraded" registers.
1355 if (SkipDGRegs && DowngradedRegs.count(Reg))
1357 if (isRegAvail(Reg)) {
1359 if (FreeReg < inactiveCounts.size())
1360 FreeRegInactiveCount = inactiveCounts[FreeReg];
1362 FreeRegInactiveCount = 0;
1367 // If there are no free regs, or if this reg has the max inactive count,
1368 // return this register.
1369 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount)
1372 // Continue scanning the registers, looking for the one with the highest
1373 // inactive count. Alkis found that this reduced register pressure very
1374 // slightly on X86 (in rev 1.94 of this file), though this should probably be
1376 for (; I != E; ++I) {
1378 // Ignore "downgraded" registers.
1379 if (SkipDGRegs && DowngradedRegs.count(Reg))
1381 if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
1382 FreeRegInactiveCount < inactiveCounts[Reg]) {
1384 FreeRegInactiveCount = inactiveCounts[Reg];
1385 if (FreeRegInactiveCount == MaxInactiveCount)
1386 break; // We found the one with the max inactive count.
1393 /// getFreePhysReg - return a free physical register for this virtual register
1394 /// interval if we have one, otherwise return 0.
1395 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
1396 SmallVector<unsigned, 256> inactiveCounts;
1397 unsigned MaxInactiveCount = 0;
1399 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
1400 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1402 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
1404 unsigned reg = i->first->reg;
1405 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1406 "Can only allocate virtual registers!");
1408 // If this is not in a related reg class to the register we're allocating,
1410 const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
1411 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
1412 reg = vrm_->getPhys(reg);
1413 if (inactiveCounts.size() <= reg)
1414 inactiveCounts.resize(reg+1);
1415 ++inactiveCounts[reg];
1416 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
1420 // If copy coalescer has assigned a "preferred" register, check if it's
1422 unsigned Preference = vrm_->getRegAllocPref(cur->reg);
1424 DOUT << "(preferred: " << tri_->getName(Preference) << ") ";
1425 if (isRegAvail(Preference) &&
1426 RC->contains(Preference))
1430 if (!DowngradedRegs.empty()) {
1431 unsigned FreeReg = getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts,
1436 return getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts, false);
1439 FunctionPass* llvm::createLinearScanRegisterAllocator() {
1440 return new RALinScan();