1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "VirtRegMap.h"
16 #include "VirtRegRewriter.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/LiveStackAnalysis.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegAllocRegistry.h"
27 #include "llvm/CodeGen/RegisterCoalescer.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/ADT/EquivalenceClasses.h"
33 #include "llvm/ADT/SmallSet.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/Compiler.h"
46 STATISTIC(NumIters , "Number of iterations performed");
47 STATISTIC(NumBacktracks, "Number of times we had to backtrack");
48 STATISTIC(NumCoalesce, "Number of copies coalesced");
49 STATISTIC(NumDowngrade, "Number of registers downgraded");
52 NewHeuristic("new-spilling-heuristic",
53 cl::desc("Use new spilling heuristic"),
54 cl::init(false), cl::Hidden);
57 PreSplitIntervals("pre-alloc-split",
58 cl::desc("Pre-register allocation live interval splitting"),
59 cl::init(false), cl::Hidden);
62 NewSpillFramework("new-spill-framework",
63 cl::desc("New spilling framework"),
64 cl::init(false), cl::Hidden);
66 static RegisterRegAlloc
67 linearscanRegAlloc("linearscan", "linear scan register allocator",
68 createLinearScanRegisterAllocator);
71 struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass {
73 RALinScan() : MachineFunctionPass(&ID) {}
75 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
76 typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
78 /// RelatedRegClasses - This structure is built the first time a function is
79 /// compiled, and keeps track of which register classes have registers that
80 /// belong to multiple classes or have aliases that are in other classes.
81 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
82 DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
84 // NextReloadMap - For each register in the map, it maps to the another
85 // register which is defined by a reload from the same stack slot and
86 // both reloads are in the same basic block.
87 DenseMap<unsigned, unsigned> NextReloadMap;
89 // DowngradedRegs - A set of registers which are being "downgraded", i.e.
90 // un-favored for allocation.
91 SmallSet<unsigned, 8> DowngradedRegs;
93 // DowngradeMap - A map from virtual registers to physical registers being
94 // downgraded for the virtual registers.
95 DenseMap<unsigned, unsigned> DowngradeMap;
98 MachineRegisterInfo* mri_;
99 const TargetMachine* tm_;
100 const TargetRegisterInfo* tri_;
101 const TargetInstrInfo* tii_;
102 BitVector allocatableRegs_;
105 const MachineLoopInfo *loopInfo;
107 /// handled_ - Intervals are added to the handled_ set in the order of their
108 /// start value. This is uses for backtracking.
109 std::vector<LiveInterval*> handled_;
111 /// fixed_ - Intervals that correspond to machine registers.
115 /// active_ - Intervals that are currently being processed, and which have a
116 /// live range active for the current point.
117 IntervalPtrs active_;
119 /// inactive_ - Intervals that are currently being processed, but which have
120 /// a hold at the current point.
121 IntervalPtrs inactive_;
123 typedef std::priority_queue<LiveInterval*,
124 SmallVector<LiveInterval*, 64>,
125 greater_ptr<LiveInterval> > IntervalHeap;
126 IntervalHeap unhandled_;
128 /// regUse_ - Tracks register usage.
129 SmallVector<unsigned, 32> regUse_;
130 SmallVector<unsigned, 32> regUseBackUp_;
132 /// vrm_ - Tracks register assignments.
135 std::auto_ptr<VirtRegRewriter> rewriter_;
137 std::auto_ptr<Spiller> spiller_;
140 virtual const char* getPassName() const {
141 return "Linear Scan Register Allocator";
144 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
145 AU.addRequired<LiveIntervals>();
147 AU.addRequiredID(StrongPHIEliminationID);
148 // Make sure PassManager knows which analyses to make available
149 // to coalescing and which analyses coalescing invalidates.
150 AU.addRequiredTransitive<RegisterCoalescer>();
151 if (PreSplitIntervals)
152 AU.addRequiredID(PreAllocSplittingID);
153 AU.addRequired<LiveStacks>();
154 AU.addPreserved<LiveStacks>();
155 AU.addRequired<MachineLoopInfo>();
156 AU.addPreserved<MachineLoopInfo>();
157 AU.addRequired<VirtRegMap>();
158 AU.addPreserved<VirtRegMap>();
159 AU.addPreservedID(MachineDominatorsID);
160 MachineFunctionPass::getAnalysisUsage(AU);
163 /// runOnMachineFunction - register allocate the whole function
164 bool runOnMachineFunction(MachineFunction&);
167 /// linearScan - the linear scan algorithm
170 /// initIntervalSets - initialize the interval sets.
172 void initIntervalSets();
174 /// processActiveIntervals - expire old intervals and move non-overlapping
175 /// ones to the inactive list.
176 void processActiveIntervals(unsigned CurPoint);
178 /// processInactiveIntervals - expire old intervals and move overlapping
179 /// ones to the active list.
180 void processInactiveIntervals(unsigned CurPoint);
182 /// hasNextReloadInterval - Return the next liveinterval that's being
183 /// defined by a reload from the same SS as the specified one.
184 LiveInterval *hasNextReloadInterval(LiveInterval *cur);
186 /// DowngradeRegister - Downgrade a register for allocation.
187 void DowngradeRegister(LiveInterval *li, unsigned Reg);
189 /// UpgradeRegister - Upgrade a register for allocation.
190 void UpgradeRegister(unsigned Reg);
192 /// assignRegOrStackSlotAtInterval - assign a register if one
193 /// is available, or spill.
194 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
196 void updateSpillWeights(std::vector<float> &Weights,
197 unsigned reg, float weight,
198 const TargetRegisterClass *RC);
200 /// findIntervalsToSpill - Determine the intervals to spill for the
201 /// specified interval. It's passed the physical registers whose spill
202 /// weight is the lowest among all the registers whose live intervals
203 /// conflict with the interval.
204 void findIntervalsToSpill(LiveInterval *cur,
205 std::vector<std::pair<unsigned,float> > &Candidates,
207 SmallVector<LiveInterval*, 8> &SpillIntervals);
209 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
210 /// try allocate the definition the same register as the source register
211 /// if the register is not defined during live time of the interval. This
212 /// eliminate a copy. This is used to coalesce copies which were not
213 /// coalesced away before allocation either due to dest and src being in
214 /// different register classes or because the coalescer was overly
216 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
219 /// Register usage / availability tracking helpers.
223 regUse_.resize(tri_->getNumRegs(), 0);
224 regUseBackUp_.resize(tri_->getNumRegs(), 0);
227 void finalizeRegUses() {
229 // Verify all the registers are "freed".
231 for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
232 if (regUse_[i] != 0) {
233 cerr << tri_->getName(i) << " is still in use!\n";
241 regUseBackUp_.clear();
244 void addRegUse(unsigned physReg) {
245 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
246 "should be physical register!");
248 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
252 void delRegUse(unsigned physReg) {
253 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
254 "should be physical register!");
255 assert(regUse_[physReg] != 0);
257 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
258 assert(regUse_[*as] != 0);
263 bool isRegAvail(unsigned physReg) const {
264 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
265 "should be physical register!");
266 return regUse_[physReg] == 0;
269 void backUpRegUses() {
270 regUseBackUp_ = regUse_;
273 void restoreRegUses() {
274 regUse_ = regUseBackUp_;
278 /// Register handling helpers.
281 /// getFreePhysReg - return a free physical register for this virtual
282 /// register interval if we have one, otherwise return 0.
283 unsigned getFreePhysReg(LiveInterval* cur);
284 unsigned getFreePhysReg(LiveInterval* cur,
285 const TargetRegisterClass *RC,
286 unsigned MaxInactiveCount,
287 SmallVector<unsigned, 256> &inactiveCounts,
290 /// assignVirt2StackSlot - assigns this virtual register to a
291 /// stack slot. returns the stack slot
292 int assignVirt2StackSlot(unsigned virtReg);
294 void ComputeRelatedRegClasses();
296 template <typename ItTy>
297 void printIntervals(const char* const str, ItTy i, ItTy e) const {
298 if (str) DOUT << str << " intervals:\n";
299 for (; i != e; ++i) {
300 DOUT << "\t" << *i->first << " -> ";
301 unsigned reg = i->first->reg;
302 if (TargetRegisterInfo::isVirtualRegister(reg)) {
303 reg = vrm_->getPhys(reg);
305 DOUT << tri_->getName(reg) << '\n';
309 char RALinScan::ID = 0;
312 static RegisterPass<RALinScan>
313 X("linearscan-regalloc", "Linear Scan Register Allocator");
315 void RALinScan::ComputeRelatedRegClasses() {
316 // First pass, add all reg classes to the union, and determine at least one
317 // reg class that each register is in.
318 bool HasAliases = false;
319 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
320 E = tri_->regclass_end(); RCI != E; ++RCI) {
321 RelatedRegClasses.insert(*RCI);
322 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
324 HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
326 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
328 // Already processed this register. Just make sure we know that
329 // multiple register classes share a register.
330 RelatedRegClasses.unionSets(PRC, *RCI);
337 // Second pass, now that we know conservatively what register classes each reg
338 // belongs to, add info about aliases. We don't need to do this for targets
339 // without register aliases.
341 for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
342 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
344 for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
345 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
348 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
349 /// try allocate the definition the same register as the source register
350 /// if the register is not defined during live time of the interval. This
351 /// eliminate a copy. This is used to coalesce copies which were not
352 /// coalesced away before allocation either due to dest and src being in
353 /// different register classes or because the coalescer was overly
355 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
356 unsigned Preference = vrm_->getRegAllocPref(cur.reg);
357 if ((Preference && Preference == Reg) || !cur.containsOneValue())
360 VNInfo *vni = cur.begin()->valno;
361 if (!vni->def || vni->isUnused() || !vni->isDefAccurate())
363 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
364 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg, PhysReg;
366 !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
369 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
370 if (!vrm_->isAssignedReg(SrcReg))
372 PhysReg = vrm_->getPhys(SrcReg);
377 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
378 if (!RC->contains(PhysReg))
382 if (!li_->conflictsWithPhysRegDef(cur, *vrm_, PhysReg)) {
383 DOUT << "Coalescing: " << cur << " -> " << tri_->getName(PhysReg)
385 vrm_->clearVirt(cur.reg);
386 vrm_->assignVirt2Phys(cur.reg, PhysReg);
388 // Remove unnecessary kills since a copy does not clobber the register.
389 if (li_->hasInterval(SrcReg)) {
390 LiveInterval &SrcLI = li_->getInterval(SrcReg);
391 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(cur.reg),
392 E = mri_->reg_end(); I != E; ++I) {
393 MachineOperand &O = I.getOperand();
394 if (!O.isUse() || !O.isKill())
396 MachineInstr *MI = &*I;
397 if (SrcLI.liveAt(li_->getDefIndex(li_->getInstructionIndex(MI))))
409 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
411 mri_ = &fn.getRegInfo();
412 tm_ = &fn.getTarget();
413 tri_ = tm_->getRegisterInfo();
414 tii_ = tm_->getInstrInfo();
415 allocatableRegs_ = tri_->getAllocatableSet(fn);
416 li_ = &getAnalysis<LiveIntervals>();
417 ls_ = &getAnalysis<LiveStacks>();
418 loopInfo = &getAnalysis<MachineLoopInfo>();
420 // We don't run the coalescer here because we have no reason to
421 // interact with it. If the coalescer requires interaction, it
422 // won't do anything. If it doesn't require interaction, we assume
423 // it was run as a separate pass.
425 // If this is the first function compiled, compute the related reg classes.
426 if (RelatedRegClasses.empty())
427 ComputeRelatedRegClasses();
429 // Also resize register usage trackers.
432 vrm_ = &getAnalysis<VirtRegMap>();
433 if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
435 if (NewSpillFramework) {
436 spiller_.reset(createSpiller(mf_, li_, ls_, vrm_));
443 // Rewrite spill code and update the PhysRegsUsed set.
444 rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
446 assert(unhandled_.empty() && "Unhandled live intervals remain!");
454 NextReloadMap.clear();
455 DowngradedRegs.clear();
456 DowngradeMap.clear();
462 /// initIntervalSets - initialize the interval sets.
464 void RALinScan::initIntervalSets()
466 assert(unhandled_.empty() && fixed_.empty() &&
467 active_.empty() && inactive_.empty() &&
468 "interval sets should be empty on initialization");
470 handled_.reserve(li_->getNumIntervals());
472 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
473 if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
474 mri_->setPhysRegUsed(i->second->reg);
475 fixed_.push_back(std::make_pair(i->second, i->second->begin()));
477 unhandled_.push(i->second);
481 void RALinScan::linearScan()
483 // linear scan algorithm
484 DOUT << "********** LINEAR SCAN **********\n";
485 DOUT << "********** Function: " << mf_->getFunction()->getName() << '\n';
487 DEBUG(printIntervals("fixed", fixed_.begin(), fixed_.end()));
489 while (!unhandled_.empty()) {
490 // pick the interval with the earliest start point
491 LiveInterval* cur = unhandled_.top();
494 DOUT << "\n*** CURRENT ***: " << *cur << '\n';
497 processActiveIntervals(cur->beginNumber());
498 processInactiveIntervals(cur->beginNumber());
500 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
501 "Can only allocate virtual registers!");
504 // Allocating a virtual register. try to find a free
505 // physical register or spill an interval (possibly this one) in order to
507 assignRegOrStackSlotAtInterval(cur);
509 DEBUG(printIntervals("active", active_.begin(), active_.end()));
510 DEBUG(printIntervals("inactive", inactive_.begin(), inactive_.end()));
513 // Expire any remaining active intervals
514 while (!active_.empty()) {
515 IntervalPtr &IP = active_.back();
516 unsigned reg = IP.first->reg;
517 DOUT << "\tinterval " << *IP.first << " expired\n";
518 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
519 "Can only allocate virtual registers!");
520 reg = vrm_->getPhys(reg);
525 // Expire any remaining inactive intervals
526 DEBUG(for (IntervalPtrs::reverse_iterator
527 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
528 DOUT << "\tinterval " << *i->first << " expired\n");
531 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
532 MachineFunction::iterator EntryMBB = mf_->begin();
533 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
534 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
535 LiveInterval &cur = *i->second;
537 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
540 else if (vrm_->isAssignedReg(cur.reg))
541 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
544 // Ignore splited live intervals.
545 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
548 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
550 const LiveRange &LR = *I;
551 if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
552 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
553 if (LiveInMBBs[i] != EntryMBB) {
554 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
555 "Adding a virtual register to livein set?");
556 LiveInMBBs[i]->addLiveIn(Reg);
565 // Look for physical registers that end up not being allocated even though
566 // register allocator had to spill other registers in its register class.
567 if (ls_->getNumIntervals() == 0)
569 if (!vrm_->FindUnusedRegisters(li_))
573 /// processActiveIntervals - expire old intervals and move non-overlapping ones
574 /// to the inactive list.
575 void RALinScan::processActiveIntervals(unsigned CurPoint)
577 DOUT << "\tprocessing active intervals:\n";
579 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
580 LiveInterval *Interval = active_[i].first;
581 LiveInterval::iterator IntervalPos = active_[i].second;
582 unsigned reg = Interval->reg;
584 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
586 if (IntervalPos == Interval->end()) { // Remove expired intervals.
587 DOUT << "\t\tinterval " << *Interval << " expired\n";
588 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
589 "Can only allocate virtual registers!");
590 reg = vrm_->getPhys(reg);
593 // Pop off the end of the list.
594 active_[i] = active_.back();
598 } else if (IntervalPos->start > CurPoint) {
599 // Move inactive intervals to inactive list.
600 DOUT << "\t\tinterval " << *Interval << " inactive\n";
601 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
602 "Can only allocate virtual registers!");
603 reg = vrm_->getPhys(reg);
606 inactive_.push_back(std::make_pair(Interval, IntervalPos));
608 // Pop off the end of the list.
609 active_[i] = active_.back();
613 // Otherwise, just update the iterator position.
614 active_[i].second = IntervalPos;
619 /// processInactiveIntervals - expire old intervals and move overlapping
620 /// ones to the active list.
621 void RALinScan::processInactiveIntervals(unsigned CurPoint)
623 DOUT << "\tprocessing inactive intervals:\n";
625 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
626 LiveInterval *Interval = inactive_[i].first;
627 LiveInterval::iterator IntervalPos = inactive_[i].second;
628 unsigned reg = Interval->reg;
630 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
632 if (IntervalPos == Interval->end()) { // remove expired intervals.
633 DOUT << "\t\tinterval " << *Interval << " expired\n";
635 // Pop off the end of the list.
636 inactive_[i] = inactive_.back();
637 inactive_.pop_back();
639 } else if (IntervalPos->start <= CurPoint) {
640 // move re-activated intervals in active list
641 DOUT << "\t\tinterval " << *Interval << " active\n";
642 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
643 "Can only allocate virtual registers!");
644 reg = vrm_->getPhys(reg);
647 active_.push_back(std::make_pair(Interval, IntervalPos));
649 // Pop off the end of the list.
650 inactive_[i] = inactive_.back();
651 inactive_.pop_back();
654 // Otherwise, just update the iterator position.
655 inactive_[i].second = IntervalPos;
660 /// updateSpillWeights - updates the spill weights of the specifed physical
661 /// register and its weight.
662 void RALinScan::updateSpillWeights(std::vector<float> &Weights,
663 unsigned reg, float weight,
664 const TargetRegisterClass *RC) {
665 SmallSet<unsigned, 4> Processed;
666 SmallSet<unsigned, 4> SuperAdded;
667 SmallVector<unsigned, 4> Supers;
668 Weights[reg] += weight;
669 Processed.insert(reg);
670 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
671 Weights[*as] += weight;
672 Processed.insert(*as);
673 if (tri_->isSubRegister(*as, reg) &&
674 SuperAdded.insert(*as) &&
676 Supers.push_back(*as);
680 // If the alias is a super-register, and the super-register is in the
681 // register class we are trying to allocate. Then add the weight to all
682 // sub-registers of the super-register even if they are not aliases.
683 // e.g. allocating for GR32, bh is not used, updating bl spill weight.
684 // bl should get the same spill weight otherwise it will be choosen
685 // as a spill candidate since spilling bh doesn't make ebx available.
686 for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
687 for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
688 if (!Processed.count(*sr))
689 Weights[*sr] += weight;
694 RALinScan::IntervalPtrs::iterator
695 FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
696 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
698 if (I->first == LI) return I;
702 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, unsigned Point){
703 for (unsigned i = 0, e = V.size(); i != e; ++i) {
704 RALinScan::IntervalPtr &IP = V[i];
705 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
707 if (I != IP.first->begin()) --I;
712 /// addStackInterval - Create a LiveInterval for stack if the specified live
713 /// interval has been spilled.
714 static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
716 MachineRegisterInfo* mri_, VirtRegMap &vrm_) {
717 int SS = vrm_.getStackSlot(cur->reg);
718 if (SS == VirtRegMap::NO_STACK_SLOT)
721 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
722 LiveInterval &SI = ls_->getOrCreateInterval(SS, RC);
725 if (SI.hasAtLeastOneValue())
726 VNI = SI.getValNumInfo(0);
728 VNI = SI.getNextValue(0, 0, false, ls_->getVNInfoAllocator());
730 LiveInterval &RI = li_->getInterval(cur->reg);
731 // FIXME: This may be overly conservative.
732 SI.MergeRangesInAsValue(RI, VNI);
735 /// getConflictWeight - Return the number of conflicts between cur
736 /// live interval and defs and uses of Reg weighted by loop depthes.
738 float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
739 MachineRegisterInfo *mri_,
740 const MachineLoopInfo *loopInfo) {
742 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
743 E = mri_->reg_end(); I != E; ++I) {
744 MachineInstr *MI = &*I;
745 if (cur->liveAt(li_->getInstructionIndex(MI))) {
746 unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
747 Conflicts += powf(10.0f, (float)loopDepth);
753 /// findIntervalsToSpill - Determine the intervals to spill for the
754 /// specified interval. It's passed the physical registers whose spill
755 /// weight is the lowest among all the registers whose live intervals
756 /// conflict with the interval.
757 void RALinScan::findIntervalsToSpill(LiveInterval *cur,
758 std::vector<std::pair<unsigned,float> > &Candidates,
760 SmallVector<LiveInterval*, 8> &SpillIntervals) {
761 // We have figured out the *best* register to spill. But there are other
762 // registers that are pretty good as well (spill weight within 3%). Spill
763 // the one that has fewest defs and uses that conflict with cur.
764 float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
765 SmallVector<LiveInterval*, 8> SLIs[3];
767 DOUT << "\tConsidering " << NumCands << " candidates: ";
768 DEBUG(for (unsigned i = 0; i != NumCands; ++i)
769 DOUT << tri_->getName(Candidates[i].first) << " ";
772 // Calculate the number of conflicts of each candidate.
773 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
774 unsigned Reg = i->first->reg;
775 unsigned PhysReg = vrm_->getPhys(Reg);
776 if (!cur->overlapsFrom(*i->first, i->second))
778 for (unsigned j = 0; j < NumCands; ++j) {
779 unsigned Candidate = Candidates[j].first;
780 if (tri_->regsOverlap(PhysReg, Candidate)) {
782 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
783 SLIs[j].push_back(i->first);
788 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
789 unsigned Reg = i->first->reg;
790 unsigned PhysReg = vrm_->getPhys(Reg);
791 if (!cur->overlapsFrom(*i->first, i->second-1))
793 for (unsigned j = 0; j < NumCands; ++j) {
794 unsigned Candidate = Candidates[j].first;
795 if (tri_->regsOverlap(PhysReg, Candidate)) {
797 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
798 SLIs[j].push_back(i->first);
803 // Which is the best candidate?
804 unsigned BestCandidate = 0;
805 float MinConflicts = Conflicts[0];
806 for (unsigned i = 1; i != NumCands; ++i) {
807 if (Conflicts[i] < MinConflicts) {
809 MinConflicts = Conflicts[i];
813 std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
814 std::back_inserter(SpillIntervals));
818 struct WeightCompare {
819 typedef std::pair<unsigned, float> RegWeightPair;
820 bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
821 return LHS.second < RHS.second;
826 static bool weightsAreClose(float w1, float w2) {
830 float diff = w1 - w2;
831 if (diff <= 0.02f) // Within 0.02f
833 return (diff / w2) <= 0.05f; // Within 5%.
836 LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
837 DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
838 if (I == NextReloadMap.end())
840 return &li_->getInterval(I->second);
843 void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
844 bool isNew = DowngradedRegs.insert(Reg);
845 isNew = isNew; // Silence compiler warning.
846 assert(isNew && "Multiple reloads holding the same register?");
847 DowngradeMap.insert(std::make_pair(li->reg, Reg));
848 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS) {
849 isNew = DowngradedRegs.insert(*AS);
850 isNew = isNew; // Silence compiler warning.
851 assert(isNew && "Multiple reloads holding the same register?");
852 DowngradeMap.insert(std::make_pair(li->reg, *AS));
857 void RALinScan::UpgradeRegister(unsigned Reg) {
859 DowngradedRegs.erase(Reg);
860 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
861 DowngradedRegs.erase(*AS);
867 bool operator()(LiveInterval* A, LiveInterval* B) {
868 return A->beginNumber() < B->beginNumber();
873 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
875 void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
877 DOUT << "\tallocating current interval: ";
879 // This is an implicitly defined live interval, just assign any register.
880 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
882 unsigned physReg = vrm_->getRegAllocPref(cur->reg);
884 physReg = *RC->allocation_order_begin(*mf_);
885 DOUT << tri_->getName(physReg) << '\n';
886 // Note the register is not really in use.
887 vrm_->assignVirt2Phys(cur->reg, physReg);
893 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
894 unsigned StartPosition = cur->beginNumber();
895 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
897 // If start of this live interval is defined by a move instruction and its
898 // source is assigned a physical register that is compatible with the target
899 // register class, then we should try to assign it the same register.
900 // This can happen when the move is from a larger register class to a smaller
901 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
902 if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
903 VNInfo *vni = cur->begin()->valno;
904 if (vni->def && !vni->isUnused() && vni->isDefAccurate()) {
905 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
906 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
908 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
910 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
912 else if (vrm_->isAssignedReg(SrcReg))
913 Reg = vrm_->getPhys(SrcReg);
916 Reg = tri_->getSubReg(Reg, SrcSubReg);
918 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
919 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
920 mri_->setRegAllocationHint(cur->reg, 0, Reg);
926 // For every interval in inactive we overlap with, mark the
927 // register as not free and update spill weights.
928 for (IntervalPtrs::const_iterator i = inactive_.begin(),
929 e = inactive_.end(); i != e; ++i) {
930 unsigned Reg = i->first->reg;
931 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
932 "Can only allocate virtual registers!");
933 const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
934 // If this is not in a related reg class to the register we're allocating,
936 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
937 cur->overlapsFrom(*i->first, i->second-1)) {
938 Reg = vrm_->getPhys(Reg);
940 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
944 // Speculatively check to see if we can get a register right now. If not,
945 // we know we won't be able to by adding more constraints. If so, we can
946 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
947 // is very bad (it contains all callee clobbered registers for any functions
948 // with a call), so we want to avoid doing that if possible.
949 unsigned physReg = getFreePhysReg(cur);
950 unsigned BestPhysReg = physReg;
952 // We got a register. However, if it's in the fixed_ list, we might
953 // conflict with it. Check to see if we conflict with it or any of its
955 SmallSet<unsigned, 8> RegAliases;
956 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
957 RegAliases.insert(*AS);
959 bool ConflictsWithFixed = false;
960 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
961 IntervalPtr &IP = fixed_[i];
962 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
963 // Okay, this reg is on the fixed list. Check to see if we actually
965 LiveInterval *I = IP.first;
966 if (I->endNumber() > StartPosition) {
967 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
969 if (II != I->begin() && II->start > StartPosition)
971 if (cur->overlapsFrom(*I, II)) {
972 ConflictsWithFixed = true;
979 // Okay, the register picked by our speculative getFreePhysReg call turned
980 // out to be in use. Actually add all of the conflicting fixed registers to
981 // regUse_ so we can do an accurate query.
982 if (ConflictsWithFixed) {
983 // For every interval in fixed we overlap with, mark the register as not
984 // free and update spill weights.
985 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
986 IntervalPtr &IP = fixed_[i];
987 LiveInterval *I = IP.first;
989 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
990 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
991 I->endNumber() > StartPosition) {
992 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
994 if (II != I->begin() && II->start > StartPosition)
996 if (cur->overlapsFrom(*I, II)) {
997 unsigned reg = I->reg;
999 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
1004 // Using the newly updated regUse_ object, which includes conflicts in the
1005 // future, see if there are any registers available.
1006 physReg = getFreePhysReg(cur);
1010 // Restore the physical register tracker, removing information about the
1014 // If we find a free register, we are done: assign this virtual to
1015 // the free physical register and add this interval to the active
1018 DOUT << tri_->getName(physReg) << '\n';
1019 vrm_->assignVirt2Phys(cur->reg, physReg);
1021 active_.push_back(std::make_pair(cur, cur->begin()));
1022 handled_.push_back(cur);
1024 // "Upgrade" the physical register since it has been allocated.
1025 UpgradeRegister(physReg);
1026 if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
1027 // "Downgrade" physReg to try to keep physReg from being allocated until
1028 // the next reload from the same SS is allocated.
1029 mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg);
1030 DowngradeRegister(cur, physReg);
1034 DOUT << "no free registers\n";
1036 // Compile the spill weights into an array that is better for scanning.
1037 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
1038 for (std::vector<std::pair<unsigned, float> >::iterator
1039 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
1040 updateSpillWeights(SpillWeights, I->first, I->second, RC);
1042 // for each interval in active, update spill weights.
1043 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
1045 unsigned reg = i->first->reg;
1046 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1047 "Can only allocate virtual registers!");
1048 reg = vrm_->getPhys(reg);
1049 updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
1052 DOUT << "\tassigning stack slot at interval "<< *cur << ":\n";
1054 // Find a register to spill.
1055 float minWeight = HUGE_VALF;
1056 unsigned minReg = 0;
1059 std::vector<std::pair<unsigned,float> > RegsWeights;
1060 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
1061 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1062 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1064 float regWeight = SpillWeights[reg];
1065 if (minWeight > regWeight)
1067 RegsWeights.push_back(std::make_pair(reg, regWeight));
1070 // If we didn't find a register that is spillable, try aliases?
1072 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1073 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1075 // No need to worry about if the alias register size < regsize of RC.
1076 // We are going to spill all registers that alias it anyway.
1077 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
1078 RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
1082 // Sort all potential spill candidates by weight.
1083 std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare());
1084 minReg = RegsWeights[0].first;
1085 minWeight = RegsWeights[0].second;
1086 if (minWeight == HUGE_VALF) {
1087 // All registers must have inf weight. Just grab one!
1088 minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
1089 if (cur->weight == HUGE_VALF ||
1090 li_->getApproximateInstructionCount(*cur) == 0) {
1091 // Spill a physical register around defs and uses.
1092 if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
1093 // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
1094 // in fixed_. Reset them.
1095 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1096 IntervalPtr &IP = fixed_[i];
1097 LiveInterval *I = IP.first;
1098 if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
1099 IP.second = I->advanceTo(I->begin(), StartPosition);
1102 DowngradedRegs.clear();
1103 assignRegOrStackSlotAtInterval(cur);
1105 cerr << "Ran out of registers during register allocation!\n";
1112 // Find up to 3 registers to consider as spill candidates.
1113 unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
1114 while (LastCandidate > 1) {
1115 if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
1120 DOUT << "\t\tregister(s) with min weight(s): ";
1121 DEBUG(for (unsigned i = 0; i != LastCandidate; ++i)
1122 DOUT << tri_->getName(RegsWeights[i].first)
1123 << " (" << RegsWeights[i].second << ")\n");
1125 // If the current has the minimum weight, we need to spill it and
1126 // add any added intervals back to unhandled, and restart
1128 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
1129 DOUT << "\t\t\tspilling(c): " << *cur << '\n';
1130 SmallVector<LiveInterval*, 8> spillIs;
1131 std::vector<LiveInterval*> added;
1133 if (!NewSpillFramework) {
1134 added = li_->addIntervalsForSpills(*cur, spillIs, loopInfo, *vrm_);
1136 added = spiller_->spill(cur);
1139 std::sort(added.begin(), added.end(), LISorter());
1140 addStackInterval(cur, ls_, li_, mri_, *vrm_);
1142 return; // Early exit if all spills were folded.
1144 // Merge added with unhandled. Note that we have already sorted
1145 // intervals returned by addIntervalsForSpills by their starting
1147 // This also update the NextReloadMap. That is, it adds mapping from a
1148 // register defined by a reload from SS to the next reload from SS in the
1149 // same basic block.
1150 MachineBasicBlock *LastReloadMBB = 0;
1151 LiveInterval *LastReload = 0;
1152 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1153 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1154 LiveInterval *ReloadLi = added[i];
1155 if (ReloadLi->weight == HUGE_VALF &&
1156 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1157 unsigned ReloadIdx = ReloadLi->beginNumber();
1158 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1159 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1160 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1161 // Last reload of same SS is in the same MBB. We want to try to
1162 // allocate both reloads the same register and make sure the reg
1163 // isn't clobbered in between if at all possible.
1164 assert(LastReload->beginNumber() < ReloadIdx);
1165 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1167 LastReloadMBB = ReloadMBB;
1168 LastReload = ReloadLi;
1169 LastReloadSS = ReloadSS;
1171 unhandled_.push(ReloadLi);
1178 // Push the current interval back to unhandled since we are going
1179 // to re-run at least this iteration. Since we didn't modify it it
1180 // should go back right in the front of the list
1181 unhandled_.push(cur);
1183 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
1184 "did not choose a register to spill?");
1186 // We spill all intervals aliasing the register with
1187 // minimum weight, rollback to the interval with the earliest
1188 // start point and let the linear scan algorithm run again
1189 SmallVector<LiveInterval*, 8> spillIs;
1191 // Determine which intervals have to be spilled.
1192 findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
1194 // Set of spilled vregs (used later to rollback properly)
1195 SmallSet<unsigned, 8> spilled;
1197 // The earliest start of a Spilled interval indicates up to where
1198 // in handled we need to roll back
1200 LiveInterval *earliestStartInterval = cur;
1202 // Spill live intervals of virtual regs mapped to the physical register we
1203 // want to clear (and its aliases). We only spill those that overlap with the
1204 // current interval as the rest do not affect its allocation. we also keep
1205 // track of the earliest start of all spilled live intervals since this will
1206 // mark our rollback point.
1207 std::vector<LiveInterval*> added;
1208 while (!spillIs.empty()) {
1209 bool epicFail = false;
1210 LiveInterval *sli = spillIs.back();
1212 DOUT << "\t\t\tspilling(a): " << *sli << '\n';
1213 earliestStartInterval =
1214 (earliestStartInterval->beginNumber() < sli->beginNumber()) ?
1215 earliestStartInterval : sli;
1217 std::vector<LiveInterval*> newIs;
1218 if (!NewSpillFramework) {
1219 newIs = li_->addIntervalsForSpills(*sli, spillIs, loopInfo, *vrm_);
1221 newIs = spiller_->spill(sli);
1223 addStackInterval(sli, ls_, li_, mri_, *vrm_);
1224 std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
1225 spilled.insert(sli->reg);
1232 unsigned earliestStart = earliestStartInterval->beginNumber();
1234 DOUT << "\t\trolling back to: " << earliestStart << '\n';
1236 // Scan handled in reverse order up to the earliest start of a
1237 // spilled live interval and undo each one, restoring the state of
1239 while (!handled_.empty()) {
1240 LiveInterval* i = handled_.back();
1241 // If this interval starts before t we are done.
1242 if (i->beginNumber() < earliestStart)
1244 DOUT << "\t\t\tundo changes for: " << *i << '\n';
1245 handled_.pop_back();
1247 // When undoing a live interval allocation we must know if it is active or
1248 // inactive to properly update regUse_ and the VirtRegMap.
1249 IntervalPtrs::iterator it;
1250 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
1252 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1253 if (!spilled.count(i->reg))
1255 delRegUse(vrm_->getPhys(i->reg));
1256 vrm_->clearVirt(i->reg);
1257 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
1258 inactive_.erase(it);
1259 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1260 if (!spilled.count(i->reg))
1262 vrm_->clearVirt(i->reg);
1264 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
1265 "Can only allocate virtual registers!");
1266 vrm_->clearVirt(i->reg);
1270 DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
1271 if (ii == DowngradeMap.end())
1272 // It interval has a preference, it must be defined by a copy. Clear the
1273 // preference now since the source interval allocation may have been
1275 mri_->setRegAllocationHint(i->reg, 0, 0);
1277 UpgradeRegister(ii->second);
1281 // Rewind the iterators in the active, inactive, and fixed lists back to the
1282 // point we reverted to.
1283 RevertVectorIteratorsTo(active_, earliestStart);
1284 RevertVectorIteratorsTo(inactive_, earliestStart);
1285 RevertVectorIteratorsTo(fixed_, earliestStart);
1287 // Scan the rest and undo each interval that expired after t and
1288 // insert it in active (the next iteration of the algorithm will
1289 // put it in inactive if required)
1290 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
1291 LiveInterval *HI = handled_[i];
1292 if (!HI->expiredAt(earliestStart) &&
1293 HI->expiredAt(cur->beginNumber())) {
1294 DOUT << "\t\t\tundo changes for: " << *HI << '\n';
1295 active_.push_back(std::make_pair(HI, HI->begin()));
1296 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
1297 addRegUse(vrm_->getPhys(HI->reg));
1301 // Merge added with unhandled.
1302 // This also update the NextReloadMap. That is, it adds mapping from a
1303 // register defined by a reload from SS to the next reload from SS in the
1304 // same basic block.
1305 MachineBasicBlock *LastReloadMBB = 0;
1306 LiveInterval *LastReload = 0;
1307 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1308 std::sort(added.begin(), added.end(), LISorter());
1309 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1310 LiveInterval *ReloadLi = added[i];
1311 if (ReloadLi->weight == HUGE_VALF &&
1312 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1313 unsigned ReloadIdx = ReloadLi->beginNumber();
1314 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1315 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1316 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1317 // Last reload of same SS is in the same MBB. We want to try to
1318 // allocate both reloads the same register and make sure the reg
1319 // isn't clobbered in between if at all possible.
1320 assert(LastReload->beginNumber() < ReloadIdx);
1321 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1323 LastReloadMBB = ReloadMBB;
1324 LastReload = ReloadLi;
1325 LastReloadSS = ReloadSS;
1327 unhandled_.push(ReloadLi);
1331 unsigned RALinScan::getFreePhysReg(LiveInterval* cur,
1332 const TargetRegisterClass *RC,
1333 unsigned MaxInactiveCount,
1334 SmallVector<unsigned, 256> &inactiveCounts,
1336 unsigned FreeReg = 0;
1337 unsigned FreeRegInactiveCount = 0;
1339 std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(cur->reg);
1340 // Resolve second part of the hint (if possible) given the current allocation.
1341 unsigned physReg = Hint.second;
1343 TargetRegisterInfo::isVirtualRegister(physReg) && vrm_->hasPhys(physReg))
1344 physReg = vrm_->getPhys(physReg);
1346 TargetRegisterClass::iterator I, E;
1347 tie(I, E) = tri_->getAllocationOrder(RC, Hint.first, physReg, *mf_);
1348 assert(I != E && "No allocatable register in this register class!");
1350 // Scan for the first available register.
1351 for (; I != E; ++I) {
1353 // Ignore "downgraded" registers.
1354 if (SkipDGRegs && DowngradedRegs.count(Reg))
1356 if (isRegAvail(Reg)) {
1358 if (FreeReg < inactiveCounts.size())
1359 FreeRegInactiveCount = inactiveCounts[FreeReg];
1361 FreeRegInactiveCount = 0;
1366 // If there are no free regs, or if this reg has the max inactive count,
1367 // return this register.
1368 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount)
1371 // Continue scanning the registers, looking for the one with the highest
1372 // inactive count. Alkis found that this reduced register pressure very
1373 // slightly on X86 (in rev 1.94 of this file), though this should probably be
1375 for (; I != E; ++I) {
1377 // Ignore "downgraded" registers.
1378 if (SkipDGRegs && DowngradedRegs.count(Reg))
1380 if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
1381 FreeRegInactiveCount < inactiveCounts[Reg]) {
1383 FreeRegInactiveCount = inactiveCounts[Reg];
1384 if (FreeRegInactiveCount == MaxInactiveCount)
1385 break; // We found the one with the max inactive count.
1392 /// getFreePhysReg - return a free physical register for this virtual register
1393 /// interval if we have one, otherwise return 0.
1394 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
1395 SmallVector<unsigned, 256> inactiveCounts;
1396 unsigned MaxInactiveCount = 0;
1398 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
1399 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1401 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
1403 unsigned reg = i->first->reg;
1404 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1405 "Can only allocate virtual registers!");
1407 // If this is not in a related reg class to the register we're allocating,
1409 const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
1410 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
1411 reg = vrm_->getPhys(reg);
1412 if (inactiveCounts.size() <= reg)
1413 inactiveCounts.resize(reg+1);
1414 ++inactiveCounts[reg];
1415 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
1419 // If copy coalescer has assigned a "preferred" register, check if it's
1421 unsigned Preference = vrm_->getRegAllocPref(cur->reg);
1423 DOUT << "(preferred: " << tri_->getName(Preference) << ") ";
1424 if (isRegAvail(Preference) &&
1425 RC->contains(Preference))
1429 if (!DowngradedRegs.empty()) {
1430 unsigned FreeReg = getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts,
1435 return getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts, false);
1438 FunctionPass* llvm::createLinearScanRegisterAllocator() {
1439 return new RALinScan();