1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "VirtRegMap.h"
16 #include "VirtRegRewriter.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/LiveStackAnalysis.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegAllocRegistry.h"
27 #include "llvm/CodeGen/RegisterCoalescer.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/ADT/EquivalenceClasses.h"
33 #include "llvm/ADT/SmallSet.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
47 STATISTIC(NumIters , "Number of iterations performed");
48 STATISTIC(NumBacktracks, "Number of times we had to backtrack");
49 STATISTIC(NumCoalesce, "Number of copies coalesced");
50 STATISTIC(NumDowngrade, "Number of registers downgraded");
53 NewHeuristic("new-spilling-heuristic",
54 cl::desc("Use new spilling heuristic"),
55 cl::init(false), cl::Hidden);
58 PreSplitIntervals("pre-alloc-split",
59 cl::desc("Pre-register allocation live interval splitting"),
60 cl::init(false), cl::Hidden);
62 static RegisterRegAlloc
63 linearscanRegAlloc("linearscan", "linear scan register allocator",
64 createLinearScanRegisterAllocator);
67 // When we allocate a register, add it to a fixed-size queue of
68 // registers to skip in subsequent allocations. This trades a small
69 // amount of register pressure and increased spills for flexibility in
70 // the post-pass scheduler.
72 // Note that in a the number of registers used for reloading spills
73 // will be one greater than the value of this option.
75 // One big limitation of this is that it doesn't differentiate between
76 // different register classes. So on x86-64, if there is xmm register
77 // pressure, it can caused fewer GPRs to be held in the queue.
78 static cl::opt<unsigned>
79 NumRecentlyUsedRegs("linearscan-skip-count",
80 cl::desc("Number of registers for linearscan to remember to skip."),
84 struct RALinScan : public MachineFunctionPass {
86 RALinScan() : MachineFunctionPass(&ID) {
87 // Initialize the queue to record recently-used registers.
88 if (NumRecentlyUsedRegs > 0)
89 RecentRegs.resize(NumRecentlyUsedRegs, 0);
92 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
93 typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
95 /// RelatedRegClasses - This structure is built the first time a function is
96 /// compiled, and keeps track of which register classes have registers that
97 /// belong to multiple classes or have aliases that are in other classes.
98 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
99 DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
101 // NextReloadMap - For each register in the map, it maps to the another
102 // register which is defined by a reload from the same stack slot and
103 // both reloads are in the same basic block.
104 DenseMap<unsigned, unsigned> NextReloadMap;
106 // DowngradedRegs - A set of registers which are being "downgraded", i.e.
107 // un-favored for allocation.
108 SmallSet<unsigned, 8> DowngradedRegs;
110 // DowngradeMap - A map from virtual registers to physical registers being
111 // downgraded for the virtual registers.
112 DenseMap<unsigned, unsigned> DowngradeMap;
114 MachineFunction* mf_;
115 MachineRegisterInfo* mri_;
116 const TargetMachine* tm_;
117 const TargetRegisterInfo* tri_;
118 const TargetInstrInfo* tii_;
119 BitVector allocatableRegs_;
122 const MachineLoopInfo *loopInfo;
124 /// handled_ - Intervals are added to the handled_ set in the order of their
125 /// start value. This is uses for backtracking.
126 std::vector<LiveInterval*> handled_;
128 /// fixed_ - Intervals that correspond to machine registers.
132 /// active_ - Intervals that are currently being processed, and which have a
133 /// live range active for the current point.
134 IntervalPtrs active_;
136 /// inactive_ - Intervals that are currently being processed, but which have
137 /// a hold at the current point.
138 IntervalPtrs inactive_;
140 typedef std::priority_queue<LiveInterval*,
141 SmallVector<LiveInterval*, 64>,
142 greater_ptr<LiveInterval> > IntervalHeap;
143 IntervalHeap unhandled_;
145 /// regUse_ - Tracks register usage.
146 SmallVector<unsigned, 32> regUse_;
147 SmallVector<unsigned, 32> regUseBackUp_;
149 /// vrm_ - Tracks register assignments.
152 std::auto_ptr<VirtRegRewriter> rewriter_;
154 std::auto_ptr<Spiller> spiller_;
156 // The queue of recently-used registers.
157 SmallVector<unsigned, 3> RecentRegs;
159 // Record that we just picked this register.
160 void recordRecentlyUsed(unsigned reg) {
161 assert(reg != 0 && "Recently used register is NOREG!");
162 if (!RecentRegs.empty()) {
163 std::copy(RecentRegs.begin() + 1, RecentRegs.end(), RecentRegs.begin());
164 RecentRegs.back() = reg;
169 virtual const char* getPassName() const {
170 return "Linear Scan Register Allocator";
173 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
174 AU.setPreservesCFG();
175 AU.addRequired<LiveIntervals>();
176 AU.addPreserved<SlotIndexes>();
178 AU.addRequiredID(StrongPHIEliminationID);
179 // Make sure PassManager knows which analyses to make available
180 // to coalescing and which analyses coalescing invalidates.
181 AU.addRequiredTransitive<RegisterCoalescer>();
182 if (PreSplitIntervals)
183 AU.addRequiredID(PreAllocSplittingID);
184 AU.addRequired<LiveStacks>();
185 AU.addPreserved<LiveStacks>();
186 AU.addRequired<MachineLoopInfo>();
187 AU.addPreserved<MachineLoopInfo>();
188 AU.addRequired<VirtRegMap>();
189 AU.addPreserved<VirtRegMap>();
190 AU.addPreservedID(MachineDominatorsID);
191 MachineFunctionPass::getAnalysisUsage(AU);
194 /// runOnMachineFunction - register allocate the whole function
195 bool runOnMachineFunction(MachineFunction&);
197 // Determine if we skip this register due to its being recently used.
198 bool isRecentlyUsed(unsigned reg) const {
199 return std::find(RecentRegs.begin(), RecentRegs.end(), reg) !=
204 /// linearScan - the linear scan algorithm
207 /// initIntervalSets - initialize the interval sets.
209 void initIntervalSets();
211 /// processActiveIntervals - expire old intervals and move non-overlapping
212 /// ones to the inactive list.
213 void processActiveIntervals(SlotIndex CurPoint);
215 /// processInactiveIntervals - expire old intervals and move overlapping
216 /// ones to the active list.
217 void processInactiveIntervals(SlotIndex CurPoint);
219 /// hasNextReloadInterval - Return the next liveinterval that's being
220 /// defined by a reload from the same SS as the specified one.
221 LiveInterval *hasNextReloadInterval(LiveInterval *cur);
223 /// DowngradeRegister - Downgrade a register for allocation.
224 void DowngradeRegister(LiveInterval *li, unsigned Reg);
226 /// UpgradeRegister - Upgrade a register for allocation.
227 void UpgradeRegister(unsigned Reg);
229 /// assignRegOrStackSlotAtInterval - assign a register if one
230 /// is available, or spill.
231 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
233 void updateSpillWeights(std::vector<float> &Weights,
234 unsigned reg, float weight,
235 const TargetRegisterClass *RC);
237 /// findIntervalsToSpill - Determine the intervals to spill for the
238 /// specified interval. It's passed the physical registers whose spill
239 /// weight is the lowest among all the registers whose live intervals
240 /// conflict with the interval.
241 void findIntervalsToSpill(LiveInterval *cur,
242 std::vector<std::pair<unsigned,float> > &Candidates,
244 SmallVector<LiveInterval*, 8> &SpillIntervals);
246 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
247 /// try allocate the definition the same register as the source register
248 /// if the register is not defined during live time of the interval. This
249 /// eliminate a copy. This is used to coalesce copies which were not
250 /// coalesced away before allocation either due to dest and src being in
251 /// different register classes or because the coalescer was overly
253 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
256 /// Register usage / availability tracking helpers.
260 regUse_.resize(tri_->getNumRegs(), 0);
261 regUseBackUp_.resize(tri_->getNumRegs(), 0);
264 void finalizeRegUses() {
266 // Verify all the registers are "freed".
268 for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
269 if (regUse_[i] != 0) {
270 errs() << tri_->getName(i) << " is still in use!\n";
278 regUseBackUp_.clear();
281 void addRegUse(unsigned physReg) {
282 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
283 "should be physical register!");
285 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
289 void delRegUse(unsigned physReg) {
290 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
291 "should be physical register!");
292 assert(regUse_[physReg] != 0);
294 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
295 assert(regUse_[*as] != 0);
300 bool isRegAvail(unsigned physReg) const {
301 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
302 "should be physical register!");
303 return regUse_[physReg] == 0;
306 void backUpRegUses() {
307 regUseBackUp_ = regUse_;
310 void restoreRegUses() {
311 regUse_ = regUseBackUp_;
315 /// Register handling helpers.
318 /// getFreePhysReg - return a free physical register for this virtual
319 /// register interval if we have one, otherwise return 0.
320 unsigned getFreePhysReg(LiveInterval* cur);
321 unsigned getFreePhysReg(LiveInterval* cur,
322 const TargetRegisterClass *RC,
323 unsigned MaxInactiveCount,
324 SmallVector<unsigned, 256> &inactiveCounts,
327 /// assignVirt2StackSlot - assigns this virtual register to a
328 /// stack slot. returns the stack slot
329 int assignVirt2StackSlot(unsigned virtReg);
331 void ComputeRelatedRegClasses();
333 template <typename ItTy>
334 void printIntervals(const char* const str, ItTy i, ItTy e) const {
337 errs() << str << " intervals:\n";
339 for (; i != e; ++i) {
340 errs() << "\t" << *i->first << " -> ";
342 unsigned reg = i->first->reg;
343 if (TargetRegisterInfo::isVirtualRegister(reg))
344 reg = vrm_->getPhys(reg);
346 errs() << tri_->getName(reg) << '\n';
351 char RALinScan::ID = 0;
354 static RegisterPass<RALinScan>
355 X("linearscan-regalloc", "Linear Scan Register Allocator");
357 void RALinScan::ComputeRelatedRegClasses() {
358 // First pass, add all reg classes to the union, and determine at least one
359 // reg class that each register is in.
360 bool HasAliases = false;
361 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
362 E = tri_->regclass_end(); RCI != E; ++RCI) {
363 RelatedRegClasses.insert(*RCI);
364 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
366 HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
368 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
370 // Already processed this register. Just make sure we know that
371 // multiple register classes share a register.
372 RelatedRegClasses.unionSets(PRC, *RCI);
379 // Second pass, now that we know conservatively what register classes each reg
380 // belongs to, add info about aliases. We don't need to do this for targets
381 // without register aliases.
383 for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
384 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
386 for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
387 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
390 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
391 /// try allocate the definition the same register as the source register
392 /// if the register is not defined during live time of the interval. This
393 /// eliminate a copy. This is used to coalesce copies which were not
394 /// coalesced away before allocation either due to dest and src being in
395 /// different register classes or because the coalescer was overly
397 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
398 unsigned Preference = vrm_->getRegAllocPref(cur.reg);
399 if ((Preference && Preference == Reg) || !cur.containsOneValue())
402 VNInfo *vni = cur.begin()->valno;
403 if ((vni->def == SlotIndex()) ||
404 vni->isUnused() || !vni->isDefAccurate())
406 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
407 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg, PhysReg;
409 !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
412 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
413 if (!vrm_->isAssignedReg(SrcReg))
415 PhysReg = vrm_->getPhys(SrcReg);
420 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
421 if (!RC->contains(PhysReg))
425 if (!li_->conflictsWithPhysRegDef(cur, *vrm_, PhysReg)) {
426 DEBUG(errs() << "Coalescing: " << cur << " -> " << tri_->getName(PhysReg)
428 vrm_->clearVirt(cur.reg);
429 vrm_->assignVirt2Phys(cur.reg, PhysReg);
431 // Remove unnecessary kills since a copy does not clobber the register.
432 if (li_->hasInterval(SrcReg)) {
433 LiveInterval &SrcLI = li_->getInterval(SrcReg);
434 for (MachineRegisterInfo::use_iterator I = mri_->use_begin(cur.reg),
435 E = mri_->use_end(); I != E; ++I) {
436 MachineOperand &O = I.getOperand();
439 MachineInstr *MI = &*I;
440 if (SrcLI.liveAt(li_->getInstructionIndex(MI).getDefIndex()))
452 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
454 mri_ = &fn.getRegInfo();
455 tm_ = &fn.getTarget();
456 tri_ = tm_->getRegisterInfo();
457 tii_ = tm_->getInstrInfo();
458 allocatableRegs_ = tri_->getAllocatableSet(fn);
459 li_ = &getAnalysis<LiveIntervals>();
460 ls_ = &getAnalysis<LiveStacks>();
461 loopInfo = &getAnalysis<MachineLoopInfo>();
463 // We don't run the coalescer here because we have no reason to
464 // interact with it. If the coalescer requires interaction, it
465 // won't do anything. If it doesn't require interaction, we assume
466 // it was run as a separate pass.
468 // If this is the first function compiled, compute the related reg classes.
469 if (RelatedRegClasses.empty())
470 ComputeRelatedRegClasses();
472 // Also resize register usage trackers.
475 vrm_ = &getAnalysis<VirtRegMap>();
476 if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
478 spiller_.reset(createSpiller(mf_, li_, loopInfo, vrm_));
484 // Rewrite spill code and update the PhysRegsUsed set.
485 rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
487 assert(unhandled_.empty() && "Unhandled live intervals remain!");
495 NextReloadMap.clear();
496 DowngradedRegs.clear();
497 DowngradeMap.clear();
503 /// initIntervalSets - initialize the interval sets.
505 void RALinScan::initIntervalSets()
507 assert(unhandled_.empty() && fixed_.empty() &&
508 active_.empty() && inactive_.empty() &&
509 "interval sets should be empty on initialization");
511 handled_.reserve(li_->getNumIntervals());
513 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
514 if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
515 if (!i->second->empty()) {
516 mri_->setPhysRegUsed(i->second->reg);
517 fixed_.push_back(std::make_pair(i->second, i->second->begin()));
520 if (i->second->empty()) {
521 assignRegOrStackSlotAtInterval(i->second);
524 unhandled_.push(i->second);
529 void RALinScan::linearScan() {
530 // linear scan algorithm
532 errs() << "********** LINEAR SCAN **********\n"
533 << "********** Function: "
534 << mf_->getFunction()->getName() << '\n';
535 printIntervals("fixed", fixed_.begin(), fixed_.end());
538 while (!unhandled_.empty()) {
539 // pick the interval with the earliest start point
540 LiveInterval* cur = unhandled_.top();
543 DEBUG(errs() << "\n*** CURRENT ***: " << *cur << '\n');
545 assert(!cur->empty() && "Empty interval in unhandled set.");
547 processActiveIntervals(cur->beginIndex());
548 processInactiveIntervals(cur->beginIndex());
550 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
551 "Can only allocate virtual registers!");
553 // Allocating a virtual register. try to find a free
554 // physical register or spill an interval (possibly this one) in order to
556 assignRegOrStackSlotAtInterval(cur);
559 printIntervals("active", active_.begin(), active_.end());
560 printIntervals("inactive", inactive_.begin(), inactive_.end());
564 // Expire any remaining active intervals
565 while (!active_.empty()) {
566 IntervalPtr &IP = active_.back();
567 unsigned reg = IP.first->reg;
568 DEBUG(errs() << "\tinterval " << *IP.first << " expired\n");
569 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
570 "Can only allocate virtual registers!");
571 reg = vrm_->getPhys(reg);
576 // Expire any remaining inactive intervals
578 for (IntervalPtrs::reverse_iterator
579 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
580 errs() << "\tinterval " << *i->first << " expired\n";
584 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
585 MachineFunction::iterator EntryMBB = mf_->begin();
586 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
587 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
588 LiveInterval &cur = *i->second;
590 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
593 else if (vrm_->isAssignedReg(cur.reg))
594 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
597 // Ignore splited live intervals.
598 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
601 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
603 const LiveRange &LR = *I;
604 if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
605 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
606 if (LiveInMBBs[i] != EntryMBB) {
607 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
608 "Adding a virtual register to livein set?");
609 LiveInMBBs[i]->addLiveIn(Reg);
616 DEBUG(errs() << *vrm_);
618 // Look for physical registers that end up not being allocated even though
619 // register allocator had to spill other registers in its register class.
620 if (ls_->getNumIntervals() == 0)
622 if (!vrm_->FindUnusedRegisters(li_))
626 /// processActiveIntervals - expire old intervals and move non-overlapping ones
627 /// to the inactive list.
628 void RALinScan::processActiveIntervals(SlotIndex CurPoint)
630 DEBUG(errs() << "\tprocessing active intervals:\n");
632 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
633 LiveInterval *Interval = active_[i].first;
634 LiveInterval::iterator IntervalPos = active_[i].second;
635 unsigned reg = Interval->reg;
637 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
639 if (IntervalPos == Interval->end()) { // Remove expired intervals.
640 DEBUG(errs() << "\t\tinterval " << *Interval << " expired\n");
641 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
642 "Can only allocate virtual registers!");
643 reg = vrm_->getPhys(reg);
646 // Pop off the end of the list.
647 active_[i] = active_.back();
651 } else if (IntervalPos->start > CurPoint) {
652 // Move inactive intervals to inactive list.
653 DEBUG(errs() << "\t\tinterval " << *Interval << " inactive\n");
654 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
655 "Can only allocate virtual registers!");
656 reg = vrm_->getPhys(reg);
659 inactive_.push_back(std::make_pair(Interval, IntervalPos));
661 // Pop off the end of the list.
662 active_[i] = active_.back();
666 // Otherwise, just update the iterator position.
667 active_[i].second = IntervalPos;
672 /// processInactiveIntervals - expire old intervals and move overlapping
673 /// ones to the active list.
674 void RALinScan::processInactiveIntervals(SlotIndex CurPoint)
676 DEBUG(errs() << "\tprocessing inactive intervals:\n");
678 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
679 LiveInterval *Interval = inactive_[i].first;
680 LiveInterval::iterator IntervalPos = inactive_[i].second;
681 unsigned reg = Interval->reg;
683 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
685 if (IntervalPos == Interval->end()) { // remove expired intervals.
686 DEBUG(errs() << "\t\tinterval " << *Interval << " expired\n");
688 // Pop off the end of the list.
689 inactive_[i] = inactive_.back();
690 inactive_.pop_back();
692 } else if (IntervalPos->start <= CurPoint) {
693 // move re-activated intervals in active list
694 DEBUG(errs() << "\t\tinterval " << *Interval << " active\n");
695 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
696 "Can only allocate virtual registers!");
697 reg = vrm_->getPhys(reg);
700 active_.push_back(std::make_pair(Interval, IntervalPos));
702 // Pop off the end of the list.
703 inactive_[i] = inactive_.back();
704 inactive_.pop_back();
707 // Otherwise, just update the iterator position.
708 inactive_[i].second = IntervalPos;
713 /// updateSpillWeights - updates the spill weights of the specifed physical
714 /// register and its weight.
715 void RALinScan::updateSpillWeights(std::vector<float> &Weights,
716 unsigned reg, float weight,
717 const TargetRegisterClass *RC) {
718 SmallSet<unsigned, 4> Processed;
719 SmallSet<unsigned, 4> SuperAdded;
720 SmallVector<unsigned, 4> Supers;
721 Weights[reg] += weight;
722 Processed.insert(reg);
723 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
724 Weights[*as] += weight;
725 Processed.insert(*as);
726 if (tri_->isSubRegister(*as, reg) &&
727 SuperAdded.insert(*as) &&
729 Supers.push_back(*as);
733 // If the alias is a super-register, and the super-register is in the
734 // register class we are trying to allocate. Then add the weight to all
735 // sub-registers of the super-register even if they are not aliases.
736 // e.g. allocating for GR32, bh is not used, updating bl spill weight.
737 // bl should get the same spill weight otherwise it will be choosen
738 // as a spill candidate since spilling bh doesn't make ebx available.
739 for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
740 for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
741 if (!Processed.count(*sr))
742 Weights[*sr] += weight;
747 RALinScan::IntervalPtrs::iterator
748 FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
749 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
751 if (I->first == LI) return I;
755 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, SlotIndex Point){
756 for (unsigned i = 0, e = V.size(); i != e; ++i) {
757 RALinScan::IntervalPtr &IP = V[i];
758 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
760 if (I != IP.first->begin()) --I;
765 /// addStackInterval - Create a LiveInterval for stack if the specified live
766 /// interval has been spilled.
767 static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
769 MachineRegisterInfo* mri_, VirtRegMap &vrm_) {
770 int SS = vrm_.getStackSlot(cur->reg);
771 if (SS == VirtRegMap::NO_STACK_SLOT)
774 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
775 LiveInterval &SI = ls_->getOrCreateInterval(SS, RC);
778 if (SI.hasAtLeastOneValue())
779 VNI = SI.getValNumInfo(0);
781 VNI = SI.getNextValue(SlotIndex(), 0, false,
782 ls_->getVNInfoAllocator());
784 LiveInterval &RI = li_->getInterval(cur->reg);
785 // FIXME: This may be overly conservative.
786 SI.MergeRangesInAsValue(RI, VNI);
789 /// getConflictWeight - Return the number of conflicts between cur
790 /// live interval and defs and uses of Reg weighted by loop depthes.
792 float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
793 MachineRegisterInfo *mri_,
794 const MachineLoopInfo *loopInfo) {
796 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
797 E = mri_->reg_end(); I != E; ++I) {
798 MachineInstr *MI = &*I;
799 if (cur->liveAt(li_->getInstructionIndex(MI))) {
800 unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
801 Conflicts += powf(10.0f, (float)loopDepth);
807 /// findIntervalsToSpill - Determine the intervals to spill for the
808 /// specified interval. It's passed the physical registers whose spill
809 /// weight is the lowest among all the registers whose live intervals
810 /// conflict with the interval.
811 void RALinScan::findIntervalsToSpill(LiveInterval *cur,
812 std::vector<std::pair<unsigned,float> > &Candidates,
814 SmallVector<LiveInterval*, 8> &SpillIntervals) {
815 // We have figured out the *best* register to spill. But there are other
816 // registers that are pretty good as well (spill weight within 3%). Spill
817 // the one that has fewest defs and uses that conflict with cur.
818 float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
819 SmallVector<LiveInterval*, 8> SLIs[3];
822 errs() << "\tConsidering " << NumCands << " candidates: ";
823 for (unsigned i = 0; i != NumCands; ++i)
824 errs() << tri_->getName(Candidates[i].first) << " ";
828 // Calculate the number of conflicts of each candidate.
829 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
830 unsigned Reg = i->first->reg;
831 unsigned PhysReg = vrm_->getPhys(Reg);
832 if (!cur->overlapsFrom(*i->first, i->second))
834 for (unsigned j = 0; j < NumCands; ++j) {
835 unsigned Candidate = Candidates[j].first;
836 if (tri_->regsOverlap(PhysReg, Candidate)) {
838 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
839 SLIs[j].push_back(i->first);
844 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
845 unsigned Reg = i->first->reg;
846 unsigned PhysReg = vrm_->getPhys(Reg);
847 if (!cur->overlapsFrom(*i->first, i->second-1))
849 for (unsigned j = 0; j < NumCands; ++j) {
850 unsigned Candidate = Candidates[j].first;
851 if (tri_->regsOverlap(PhysReg, Candidate)) {
853 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
854 SLIs[j].push_back(i->first);
859 // Which is the best candidate?
860 unsigned BestCandidate = 0;
861 float MinConflicts = Conflicts[0];
862 for (unsigned i = 1; i != NumCands; ++i) {
863 if (Conflicts[i] < MinConflicts) {
865 MinConflicts = Conflicts[i];
869 std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
870 std::back_inserter(SpillIntervals));
874 struct WeightCompare {
876 const RALinScan &Allocator;
879 WeightCompare(const RALinScan &Alloc) : Allocator(Alloc) {};
881 typedef std::pair<unsigned, float> RegWeightPair;
882 bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
883 return LHS.second < RHS.second && !Allocator.isRecentlyUsed(LHS.first);
888 static bool weightsAreClose(float w1, float w2) {
892 float diff = w1 - w2;
893 if (diff <= 0.02f) // Within 0.02f
895 return (diff / w2) <= 0.05f; // Within 5%.
898 LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
899 DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
900 if (I == NextReloadMap.end())
902 return &li_->getInterval(I->second);
905 void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
906 bool isNew = DowngradedRegs.insert(Reg);
907 isNew = isNew; // Silence compiler warning.
908 assert(isNew && "Multiple reloads holding the same register?");
909 DowngradeMap.insert(std::make_pair(li->reg, Reg));
910 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS) {
911 isNew = DowngradedRegs.insert(*AS);
912 isNew = isNew; // Silence compiler warning.
913 assert(isNew && "Multiple reloads holding the same register?");
914 DowngradeMap.insert(std::make_pair(li->reg, *AS));
919 void RALinScan::UpgradeRegister(unsigned Reg) {
921 DowngradedRegs.erase(Reg);
922 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
923 DowngradedRegs.erase(*AS);
929 bool operator()(LiveInterval* A, LiveInterval* B) {
930 return A->beginIndex() < B->beginIndex();
935 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
937 void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
938 DEBUG(errs() << "\tallocating current interval: ");
940 // This is an implicitly defined live interval, just assign any register.
941 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
943 unsigned physReg = vrm_->getRegAllocPref(cur->reg);
945 physReg = *RC->allocation_order_begin(*mf_);
946 DEBUG(errs() << tri_->getName(physReg) << '\n');
947 // Note the register is not really in use.
948 vrm_->assignVirt2Phys(cur->reg, physReg);
954 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
955 SlotIndex StartPosition = cur->beginIndex();
956 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
958 // If start of this live interval is defined by a move instruction and its
959 // source is assigned a physical register that is compatible with the target
960 // register class, then we should try to assign it the same register.
961 // This can happen when the move is from a larger register class to a smaller
962 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
963 if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
964 VNInfo *vni = cur->begin()->valno;
965 if ((vni->def != SlotIndex()) && !vni->isUnused() &&
966 vni->isDefAccurate()) {
967 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
968 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
970 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
972 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
974 else if (vrm_->isAssignedReg(SrcReg))
975 Reg = vrm_->getPhys(SrcReg);
978 Reg = tri_->getSubReg(Reg, SrcSubReg);
980 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
981 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
982 mri_->setRegAllocationHint(cur->reg, 0, Reg);
988 // For every interval in inactive we overlap with, mark the
989 // register as not free and update spill weights.
990 for (IntervalPtrs::const_iterator i = inactive_.begin(),
991 e = inactive_.end(); i != e; ++i) {
992 unsigned Reg = i->first->reg;
993 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
994 "Can only allocate virtual registers!");
995 const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
996 // If this is not in a related reg class to the register we're allocating,
998 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
999 cur->overlapsFrom(*i->first, i->second-1)) {
1000 Reg = vrm_->getPhys(Reg);
1002 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
1006 // Speculatively check to see if we can get a register right now. If not,
1007 // we know we won't be able to by adding more constraints. If so, we can
1008 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
1009 // is very bad (it contains all callee clobbered registers for any functions
1010 // with a call), so we want to avoid doing that if possible.
1011 unsigned physReg = getFreePhysReg(cur);
1012 unsigned BestPhysReg = physReg;
1014 // We got a register. However, if it's in the fixed_ list, we might
1015 // conflict with it. Check to see if we conflict with it or any of its
1017 SmallSet<unsigned, 8> RegAliases;
1018 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
1019 RegAliases.insert(*AS);
1021 bool ConflictsWithFixed = false;
1022 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1023 IntervalPtr &IP = fixed_[i];
1024 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
1025 // Okay, this reg is on the fixed list. Check to see if we actually
1027 LiveInterval *I = IP.first;
1028 if (I->endIndex() > StartPosition) {
1029 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1031 if (II != I->begin() && II->start > StartPosition)
1033 if (cur->overlapsFrom(*I, II)) {
1034 ConflictsWithFixed = true;
1041 // Okay, the register picked by our speculative getFreePhysReg call turned
1042 // out to be in use. Actually add all of the conflicting fixed registers to
1043 // regUse_ so we can do an accurate query.
1044 if (ConflictsWithFixed) {
1045 // For every interval in fixed we overlap with, mark the register as not
1046 // free and update spill weights.
1047 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1048 IntervalPtr &IP = fixed_[i];
1049 LiveInterval *I = IP.first;
1051 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
1052 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1053 I->endIndex() > StartPosition) {
1054 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1056 if (II != I->begin() && II->start > StartPosition)
1058 if (cur->overlapsFrom(*I, II)) {
1059 unsigned reg = I->reg;
1061 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
1066 // Using the newly updated regUse_ object, which includes conflicts in the
1067 // future, see if there are any registers available.
1068 physReg = getFreePhysReg(cur);
1072 // Restore the physical register tracker, removing information about the
1076 // If we find a free register, we are done: assign this virtual to
1077 // the free physical register and add this interval to the active
1080 DEBUG(errs() << tri_->getName(physReg) << '\n');
1081 vrm_->assignVirt2Phys(cur->reg, physReg);
1083 active_.push_back(std::make_pair(cur, cur->begin()));
1084 handled_.push_back(cur);
1086 // "Upgrade" the physical register since it has been allocated.
1087 UpgradeRegister(physReg);
1088 if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
1089 // "Downgrade" physReg to try to keep physReg from being allocated until
1090 // the next reload from the same SS is allocated.
1091 mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg);
1092 DowngradeRegister(cur, physReg);
1096 DEBUG(errs() << "no free registers\n");
1098 // Compile the spill weights into an array that is better for scanning.
1099 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
1100 for (std::vector<std::pair<unsigned, float> >::iterator
1101 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
1102 updateSpillWeights(SpillWeights, I->first, I->second, RC);
1104 // for each interval in active, update spill weights.
1105 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
1107 unsigned reg = i->first->reg;
1108 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1109 "Can only allocate virtual registers!");
1110 reg = vrm_->getPhys(reg);
1111 updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
1114 DEBUG(errs() << "\tassigning stack slot at interval "<< *cur << ":\n");
1116 // Find a register to spill.
1117 float minWeight = HUGE_VALF;
1118 unsigned minReg = 0;
1121 std::vector<std::pair<unsigned,float> > RegsWeights;
1122 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
1123 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1124 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1126 float regWeight = SpillWeights[reg];
1127 // Skip recently allocated registers.
1128 if (minWeight > regWeight && !isRecentlyUsed(reg))
1130 RegsWeights.push_back(std::make_pair(reg, regWeight));
1133 // If we didn't find a register that is spillable, try aliases?
1135 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1136 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1138 // No need to worry about if the alias register size < regsize of RC.
1139 // We are going to spill all registers that alias it anyway.
1140 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
1141 RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
1145 // Sort all potential spill candidates by weight.
1146 std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare(*this));
1147 minReg = RegsWeights[0].first;
1148 minWeight = RegsWeights[0].second;
1149 if (minWeight == HUGE_VALF) {
1150 // All registers must have inf weight. Just grab one!
1151 minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
1152 if (cur->weight == HUGE_VALF ||
1153 li_->getApproximateInstructionCount(*cur) == 0) {
1154 // Spill a physical register around defs and uses.
1155 if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
1156 // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
1157 // in fixed_. Reset them.
1158 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1159 IntervalPtr &IP = fixed_[i];
1160 LiveInterval *I = IP.first;
1161 if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
1162 IP.second = I->advanceTo(I->begin(), StartPosition);
1165 DowngradedRegs.clear();
1166 assignRegOrStackSlotAtInterval(cur);
1168 assert(false && "Ran out of registers during register allocation!");
1169 llvm_report_error("Ran out of registers during register allocation!");
1175 // Find up to 3 registers to consider as spill candidates.
1176 unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
1177 while (LastCandidate > 1) {
1178 if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
1184 errs() << "\t\tregister(s) with min weight(s): ";
1186 for (unsigned i = 0; i != LastCandidate; ++i)
1187 errs() << tri_->getName(RegsWeights[i].first)
1188 << " (" << RegsWeights[i].second << ")\n";
1191 // If the current has the minimum weight, we need to spill it and
1192 // add any added intervals back to unhandled, and restart
1194 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
1195 DEBUG(errs() << "\t\t\tspilling(c): " << *cur << '\n');
1196 SmallVector<LiveInterval*, 8> spillIs;
1197 std::vector<LiveInterval*> added;
1199 added = spiller_->spill(cur, spillIs);
1201 std::sort(added.begin(), added.end(), LISorter());
1202 addStackInterval(cur, ls_, li_, mri_, *vrm_);
1204 return; // Early exit if all spills were folded.
1206 // Merge added with unhandled. Note that we have already sorted
1207 // intervals returned by addIntervalsForSpills by their starting
1209 // This also update the NextReloadMap. That is, it adds mapping from a
1210 // register defined by a reload from SS to the next reload from SS in the
1211 // same basic block.
1212 MachineBasicBlock *LastReloadMBB = 0;
1213 LiveInterval *LastReload = 0;
1214 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1215 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1216 LiveInterval *ReloadLi = added[i];
1217 if (ReloadLi->weight == HUGE_VALF &&
1218 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1219 SlotIndex ReloadIdx = ReloadLi->beginIndex();
1220 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1221 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1222 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1223 // Last reload of same SS is in the same MBB. We want to try to
1224 // allocate both reloads the same register and make sure the reg
1225 // isn't clobbered in between if at all possible.
1226 assert(LastReload->beginIndex() < ReloadIdx);
1227 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1229 LastReloadMBB = ReloadMBB;
1230 LastReload = ReloadLi;
1231 LastReloadSS = ReloadSS;
1233 unhandled_.push(ReloadLi);
1240 // Push the current interval back to unhandled since we are going
1241 // to re-run at least this iteration. Since we didn't modify it it
1242 // should go back right in the front of the list
1243 unhandled_.push(cur);
1245 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
1246 "did not choose a register to spill?");
1248 // We spill all intervals aliasing the register with
1249 // minimum weight, rollback to the interval with the earliest
1250 // start point and let the linear scan algorithm run again
1251 SmallVector<LiveInterval*, 8> spillIs;
1253 // Determine which intervals have to be spilled.
1254 findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
1256 // Set of spilled vregs (used later to rollback properly)
1257 SmallSet<unsigned, 8> spilled;
1259 // The earliest start of a Spilled interval indicates up to where
1260 // in handled we need to roll back
1262 LiveInterval *earliestStartInterval = cur;
1264 // Spill live intervals of virtual regs mapped to the physical register we
1265 // want to clear (and its aliases). We only spill those that overlap with the
1266 // current interval as the rest do not affect its allocation. we also keep
1267 // track of the earliest start of all spilled live intervals since this will
1268 // mark our rollback point.
1269 std::vector<LiveInterval*> added;
1270 while (!spillIs.empty()) {
1271 LiveInterval *sli = spillIs.back();
1273 DEBUG(errs() << "\t\t\tspilling(a): " << *sli << '\n');
1274 earliestStartInterval =
1275 (earliestStartInterval->beginIndex() < sli->beginIndex()) ?
1276 earliestStartInterval : sli;
1278 std::vector<LiveInterval*> newIs;
1279 newIs = spiller_->spill(sli, spillIs);
1280 addStackInterval(sli, ls_, li_, mri_, *vrm_);
1281 std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
1282 spilled.insert(sli->reg);
1285 SlotIndex earliestStart = earliestStartInterval->beginIndex();
1287 DEBUG(errs() << "\t\trolling back to: " << earliestStart << '\n');
1289 // Scan handled in reverse order up to the earliest start of a
1290 // spilled live interval and undo each one, restoring the state of
1292 while (!handled_.empty()) {
1293 LiveInterval* i = handled_.back();
1294 // If this interval starts before t we are done.
1295 if (i->beginIndex() < earliestStart)
1297 DEBUG(errs() << "\t\t\tundo changes for: " << *i << '\n');
1298 handled_.pop_back();
1300 // When undoing a live interval allocation we must know if it is active or
1301 // inactive to properly update regUse_ and the VirtRegMap.
1302 IntervalPtrs::iterator it;
1303 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
1305 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1306 if (!spilled.count(i->reg))
1308 delRegUse(vrm_->getPhys(i->reg));
1309 vrm_->clearVirt(i->reg);
1310 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
1311 inactive_.erase(it);
1312 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1313 if (!spilled.count(i->reg))
1315 vrm_->clearVirt(i->reg);
1317 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
1318 "Can only allocate virtual registers!");
1319 vrm_->clearVirt(i->reg);
1323 DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
1324 if (ii == DowngradeMap.end())
1325 // It interval has a preference, it must be defined by a copy. Clear the
1326 // preference now since the source interval allocation may have been
1328 mri_->setRegAllocationHint(i->reg, 0, 0);
1330 UpgradeRegister(ii->second);
1334 // Rewind the iterators in the active, inactive, and fixed lists back to the
1335 // point we reverted to.
1336 RevertVectorIteratorsTo(active_, earliestStart);
1337 RevertVectorIteratorsTo(inactive_, earliestStart);
1338 RevertVectorIteratorsTo(fixed_, earliestStart);
1340 // Scan the rest and undo each interval that expired after t and
1341 // insert it in active (the next iteration of the algorithm will
1342 // put it in inactive if required)
1343 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
1344 LiveInterval *HI = handled_[i];
1345 if (!HI->expiredAt(earliestStart) &&
1346 HI->expiredAt(cur->beginIndex())) {
1347 DEBUG(errs() << "\t\t\tundo changes for: " << *HI << '\n');
1348 active_.push_back(std::make_pair(HI, HI->begin()));
1349 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
1350 addRegUse(vrm_->getPhys(HI->reg));
1354 // Merge added with unhandled.
1355 // This also update the NextReloadMap. That is, it adds mapping from a
1356 // register defined by a reload from SS to the next reload from SS in the
1357 // same basic block.
1358 MachineBasicBlock *LastReloadMBB = 0;
1359 LiveInterval *LastReload = 0;
1360 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1361 std::sort(added.begin(), added.end(), LISorter());
1362 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1363 LiveInterval *ReloadLi = added[i];
1364 if (ReloadLi->weight == HUGE_VALF &&
1365 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1366 SlotIndex ReloadIdx = ReloadLi->beginIndex();
1367 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1368 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1369 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1370 // Last reload of same SS is in the same MBB. We want to try to
1371 // allocate both reloads the same register and make sure the reg
1372 // isn't clobbered in between if at all possible.
1373 assert(LastReload->beginIndex() < ReloadIdx);
1374 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1376 LastReloadMBB = ReloadMBB;
1377 LastReload = ReloadLi;
1378 LastReloadSS = ReloadSS;
1380 unhandled_.push(ReloadLi);
1384 unsigned RALinScan::getFreePhysReg(LiveInterval* cur,
1385 const TargetRegisterClass *RC,
1386 unsigned MaxInactiveCount,
1387 SmallVector<unsigned, 256> &inactiveCounts,
1389 unsigned FreeReg = 0;
1390 unsigned FreeRegInactiveCount = 0;
1392 std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(cur->reg);
1393 // Resolve second part of the hint (if possible) given the current allocation.
1394 unsigned physReg = Hint.second;
1396 TargetRegisterInfo::isVirtualRegister(physReg) && vrm_->hasPhys(physReg))
1397 physReg = vrm_->getPhys(physReg);
1399 TargetRegisterClass::iterator I, E;
1400 tie(I, E) = tri_->getAllocationOrder(RC, Hint.first, physReg, *mf_);
1401 assert(I != E && "No allocatable register in this register class!");
1403 // Scan for the first available register.
1404 for (; I != E; ++I) {
1406 // Ignore "downgraded" registers.
1407 if (SkipDGRegs && DowngradedRegs.count(Reg))
1409 // Skip recently allocated registers.
1410 if (isRegAvail(Reg) && !isRecentlyUsed(Reg)) {
1412 if (FreeReg < inactiveCounts.size())
1413 FreeRegInactiveCount = inactiveCounts[FreeReg];
1415 FreeRegInactiveCount = 0;
1420 // If there are no free regs, or if this reg has the max inactive count,
1421 // return this register.
1422 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount) {
1423 // Remember what register we picked so we can skip it next time.
1424 if (FreeReg != 0) recordRecentlyUsed(FreeReg);
1428 // Continue scanning the registers, looking for the one with the highest
1429 // inactive count. Alkis found that this reduced register pressure very
1430 // slightly on X86 (in rev 1.94 of this file), though this should probably be
1432 for (; I != E; ++I) {
1434 // Ignore "downgraded" registers.
1435 if (SkipDGRegs && DowngradedRegs.count(Reg))
1437 if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
1438 FreeRegInactiveCount < inactiveCounts[Reg] && !isRecentlyUsed(Reg)) {
1440 FreeRegInactiveCount = inactiveCounts[Reg];
1441 if (FreeRegInactiveCount == MaxInactiveCount)
1442 break; // We found the one with the max inactive count.
1446 // Remember what register we picked so we can skip it next time.
1447 recordRecentlyUsed(FreeReg);
1452 /// getFreePhysReg - return a free physical register for this virtual register
1453 /// interval if we have one, otherwise return 0.
1454 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
1455 SmallVector<unsigned, 256> inactiveCounts;
1456 unsigned MaxInactiveCount = 0;
1458 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
1459 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1461 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
1463 unsigned reg = i->first->reg;
1464 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1465 "Can only allocate virtual registers!");
1467 // If this is not in a related reg class to the register we're allocating,
1469 const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
1470 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
1471 reg = vrm_->getPhys(reg);
1472 if (inactiveCounts.size() <= reg)
1473 inactiveCounts.resize(reg+1);
1474 ++inactiveCounts[reg];
1475 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
1479 // If copy coalescer has assigned a "preferred" register, check if it's
1481 unsigned Preference = vrm_->getRegAllocPref(cur->reg);
1483 DEBUG(errs() << "(preferred: " << tri_->getName(Preference) << ") ");
1484 if (isRegAvail(Preference) &&
1485 RC->contains(Preference))
1489 if (!DowngradedRegs.empty()) {
1490 unsigned FreeReg = getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts,
1495 return getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts, false);
1498 FunctionPass* llvm::createLinearScanRegisterAllocator() {
1499 return new RALinScan();