1 //===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a linear scan register allocator.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "VirtRegMap.h"
16 #include "VirtRegRewriter.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/CalcSpillWeights.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/LiveStackAnalysis.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/MachineLoopInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/RegAllocRegistry.h"
28 #include "llvm/CodeGen/RegisterCoalescer.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/ADT/EquivalenceClasses.h"
34 #include "llvm/ADT/SmallSet.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/ADT/STLExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
48 STATISTIC(NumIters , "Number of iterations performed");
49 STATISTIC(NumBacktracks, "Number of times we had to backtrack");
50 STATISTIC(NumCoalesce, "Number of copies coalesced");
51 STATISTIC(NumDowngrade, "Number of registers downgraded");
54 NewHeuristic("new-spilling-heuristic",
55 cl::desc("Use new spilling heuristic"),
56 cl::init(false), cl::Hidden);
59 PreSplitIntervals("pre-alloc-split",
60 cl::desc("Pre-register allocation live interval splitting"),
61 cl::init(false), cl::Hidden);
64 TrivCoalesceEnds("trivial-coalesce-ends",
65 cl::desc("Attempt trivial coalescing of interval ends"),
66 cl::init(false), cl::Hidden);
68 static RegisterRegAlloc
69 linearscanRegAlloc("linearscan", "linear scan register allocator",
70 createLinearScanRegisterAllocator);
73 // When we allocate a register, add it to a fixed-size queue of
74 // registers to skip in subsequent allocations. This trades a small
75 // amount of register pressure and increased spills for flexibility in
76 // the post-pass scheduler.
78 // Note that in a the number of registers used for reloading spills
79 // will be one greater than the value of this option.
81 // One big limitation of this is that it doesn't differentiate between
82 // different register classes. So on x86-64, if there is xmm register
83 // pressure, it can caused fewer GPRs to be held in the queue.
84 static cl::opt<unsigned>
85 NumRecentlyUsedRegs("linearscan-skip-count",
86 cl::desc("Number of registers for linearscan to remember"
91 struct RALinScan : public MachineFunctionPass {
93 RALinScan() : MachineFunctionPass(&ID) {
94 // Initialize the queue to record recently-used registers.
95 if (NumRecentlyUsedRegs > 0)
96 RecentRegs.resize(NumRecentlyUsedRegs, 0);
97 RecentNext = RecentRegs.begin();
100 typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
101 typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
103 /// RelatedRegClasses - This structure is built the first time a function is
104 /// compiled, and keeps track of which register classes have registers that
105 /// belong to multiple classes or have aliases that are in other classes.
106 EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
107 DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
109 // NextReloadMap - For each register in the map, it maps to the another
110 // register which is defined by a reload from the same stack slot and
111 // both reloads are in the same basic block.
112 DenseMap<unsigned, unsigned> NextReloadMap;
114 // DowngradedRegs - A set of registers which are being "downgraded", i.e.
115 // un-favored for allocation.
116 SmallSet<unsigned, 8> DowngradedRegs;
118 // DowngradeMap - A map from virtual registers to physical registers being
119 // downgraded for the virtual registers.
120 DenseMap<unsigned, unsigned> DowngradeMap;
122 MachineFunction* mf_;
123 MachineRegisterInfo* mri_;
124 const TargetMachine* tm_;
125 const TargetRegisterInfo* tri_;
126 const TargetInstrInfo* tii_;
127 BitVector allocatableRegs_;
130 const MachineLoopInfo *loopInfo;
132 /// handled_ - Intervals are added to the handled_ set in the order of their
133 /// start value. This is uses for backtracking.
134 std::vector<LiveInterval*> handled_;
136 /// fixed_ - Intervals that correspond to machine registers.
140 /// active_ - Intervals that are currently being processed, and which have a
141 /// live range active for the current point.
142 IntervalPtrs active_;
144 /// inactive_ - Intervals that are currently being processed, but which have
145 /// a hold at the current point.
146 IntervalPtrs inactive_;
148 typedef std::priority_queue<LiveInterval*,
149 SmallVector<LiveInterval*, 64>,
150 greater_ptr<LiveInterval> > IntervalHeap;
151 IntervalHeap unhandled_;
153 /// regUse_ - Tracks register usage.
154 SmallVector<unsigned, 32> regUse_;
155 SmallVector<unsigned, 32> regUseBackUp_;
157 /// vrm_ - Tracks register assignments.
160 std::auto_ptr<VirtRegRewriter> rewriter_;
162 std::auto_ptr<Spiller> spiller_;
164 // The queue of recently-used registers.
165 SmallVector<unsigned, 4> RecentRegs;
166 SmallVector<unsigned, 4>::iterator RecentNext;
168 // Record that we just picked this register.
169 void recordRecentlyUsed(unsigned reg) {
170 assert(reg != 0 && "Recently used register is NOREG!");
171 if (!RecentRegs.empty()) {
173 if (RecentNext == RecentRegs.end())
174 RecentNext = RecentRegs.begin();
179 virtual const char* getPassName() const {
180 return "Linear Scan Register Allocator";
183 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
184 AU.setPreservesCFG();
185 AU.addRequired<LiveIntervals>();
186 AU.addPreserved<SlotIndexes>();
188 AU.addRequiredID(StrongPHIEliminationID);
189 // Make sure PassManager knows which analyses to make available
190 // to coalescing and which analyses coalescing invalidates.
191 AU.addRequiredTransitive<RegisterCoalescer>();
192 AU.addRequired<CalculateSpillWeights>();
193 if (PreSplitIntervals)
194 AU.addRequiredID(PreAllocSplittingID);
195 AU.addRequired<LiveStacks>();
196 AU.addPreserved<LiveStacks>();
197 AU.addRequired<MachineLoopInfo>();
198 AU.addPreserved<MachineLoopInfo>();
199 AU.addRequired<VirtRegMap>();
200 AU.addPreserved<VirtRegMap>();
201 AU.addPreservedID(MachineDominatorsID);
202 MachineFunctionPass::getAnalysisUsage(AU);
205 /// runOnMachineFunction - register allocate the whole function
206 bool runOnMachineFunction(MachineFunction&);
208 // Determine if we skip this register due to its being recently used.
209 bool isRecentlyUsed(unsigned reg) const {
210 return std::find(RecentRegs.begin(), RecentRegs.end(), reg) !=
215 /// linearScan - the linear scan algorithm
218 /// initIntervalSets - initialize the interval sets.
220 void initIntervalSets();
222 /// processActiveIntervals - expire old intervals and move non-overlapping
223 /// ones to the inactive list.
224 void processActiveIntervals(SlotIndex CurPoint);
226 /// processInactiveIntervals - expire old intervals and move overlapping
227 /// ones to the active list.
228 void processInactiveIntervals(SlotIndex CurPoint);
230 /// hasNextReloadInterval - Return the next liveinterval that's being
231 /// defined by a reload from the same SS as the specified one.
232 LiveInterval *hasNextReloadInterval(LiveInterval *cur);
234 /// DowngradeRegister - Downgrade a register for allocation.
235 void DowngradeRegister(LiveInterval *li, unsigned Reg);
237 /// UpgradeRegister - Upgrade a register for allocation.
238 void UpgradeRegister(unsigned Reg);
240 /// assignRegOrStackSlotAtInterval - assign a register if one
241 /// is available, or spill.
242 void assignRegOrStackSlotAtInterval(LiveInterval* cur);
244 void updateSpillWeights(std::vector<float> &Weights,
245 unsigned reg, float weight,
246 const TargetRegisterClass *RC);
248 /// findIntervalsToSpill - Determine the intervals to spill for the
249 /// specified interval. It's passed the physical registers whose spill
250 /// weight is the lowest among all the registers whose live intervals
251 /// conflict with the interval.
252 void findIntervalsToSpill(LiveInterval *cur,
253 std::vector<std::pair<unsigned,float> > &Candidates,
255 SmallVector<LiveInterval*, 8> &SpillIntervals);
257 /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
258 /// try allocate the definition the same register as the source register
259 /// if the register is not defined during live time of the interval. This
260 /// eliminate a copy. This is used to coalesce copies which were not
261 /// coalesced away before allocation either due to dest and src being in
262 /// different register classes or because the coalescer was overly
264 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
267 /// Register usage / availability tracking helpers.
271 regUse_.resize(tri_->getNumRegs(), 0);
272 regUseBackUp_.resize(tri_->getNumRegs(), 0);
275 void finalizeRegUses() {
277 // Verify all the registers are "freed".
279 for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
280 if (regUse_[i] != 0) {
281 dbgs() << tri_->getName(i) << " is still in use!\n";
289 regUseBackUp_.clear();
292 void addRegUse(unsigned physReg) {
293 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
294 "should be physical register!");
296 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
300 void delRegUse(unsigned physReg) {
301 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
302 "should be physical register!");
303 assert(regUse_[physReg] != 0);
305 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
306 assert(regUse_[*as] != 0);
311 bool isRegAvail(unsigned physReg) const {
312 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
313 "should be physical register!");
314 return regUse_[physReg] == 0;
317 void backUpRegUses() {
318 regUseBackUp_ = regUse_;
321 void restoreRegUses() {
322 regUse_ = regUseBackUp_;
326 /// Register handling helpers.
329 /// getFreePhysReg - return a free physical register for this virtual
330 /// register interval if we have one, otherwise return 0.
331 unsigned getFreePhysReg(LiveInterval* cur);
332 unsigned getFreePhysReg(LiveInterval* cur,
333 const TargetRegisterClass *RC,
334 unsigned MaxInactiveCount,
335 SmallVector<unsigned, 256> &inactiveCounts,
338 void ComputeRelatedRegClasses();
340 template <typename ItTy>
341 void printIntervals(const char* const str, ItTy i, ItTy e) const {
344 dbgs() << str << " intervals:\n";
346 for (; i != e; ++i) {
347 dbgs() << "\t" << *i->first << " -> ";
349 unsigned reg = i->first->reg;
350 if (TargetRegisterInfo::isVirtualRegister(reg))
351 reg = vrm_->getPhys(reg);
353 dbgs() << tri_->getName(reg) << '\n';
358 char RALinScan::ID = 0;
361 static RegisterPass<RALinScan>
362 X("linearscan-regalloc", "Linear Scan Register Allocator");
364 void RALinScan::ComputeRelatedRegClasses() {
365 // First pass, add all reg classes to the union, and determine at least one
366 // reg class that each register is in.
367 bool HasAliases = false;
368 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
369 E = tri_->regclass_end(); RCI != E; ++RCI) {
370 RelatedRegClasses.insert(*RCI);
371 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
373 HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
375 const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
377 // Already processed this register. Just make sure we know that
378 // multiple register classes share a register.
379 RelatedRegClasses.unionSets(PRC, *RCI);
386 // Second pass, now that we know conservatively what register classes each reg
387 // belongs to, add info about aliases. We don't need to do this for targets
388 // without register aliases.
390 for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
391 I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
393 for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
394 RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
397 /// attemptTrivialCoalescing - If a simple interval is defined by a copy, try
398 /// allocate the definition the same register as the source register if the
399 /// register is not defined during live time of the interval. If the interval is
400 /// killed by a copy, try to use the destination register. This eliminates a
401 /// copy. This is used to coalesce copies which were not coalesced away before
402 /// allocation either due to dest and src being in different register classes or
403 /// because the coalescer was overly conservative.
404 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
405 unsigned Preference = vrm_->getRegAllocPref(cur.reg);
406 if ((Preference && Preference == Reg) || !cur.containsOneValue())
409 // We cannot handle complicated live ranges. Simple linear stuff only.
410 if (cur.ranges.size() != 1)
413 const LiveRange &range = cur.ranges.front();
415 VNInfo *vni = range.valno;
421 MachineInstr *CopyMI;
422 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
423 if (vni->def != SlotIndex() && vni->isDefAccurate() &&
424 (CopyMI = li_->getInstructionFromIndex(vni->def)) &&
425 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
426 // Defined by a copy, try to extend SrcReg forward
428 else if (TrivCoalesceEnds &&
430 li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
431 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
433 // Only used by a copy, try to extend DstReg backwards
439 if (TargetRegisterInfo::isVirtualRegister(CandReg)) {
440 if (!vrm_->isAssignedReg(CandReg))
442 CandReg = vrm_->getPhys(CandReg);
447 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
448 if (!RC->contains(CandReg))
451 if (li_->conflictsWithPhysReg(cur, *vrm_, CandReg))
455 DEBUG(dbgs() << "Coalescing: " << cur << " -> " << tri_->getName(CandReg)
457 vrm_->clearVirt(cur.reg);
458 vrm_->assignVirt2Phys(cur.reg, CandReg);
464 bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
466 mri_ = &fn.getRegInfo();
467 tm_ = &fn.getTarget();
468 tri_ = tm_->getRegisterInfo();
469 tii_ = tm_->getInstrInfo();
470 allocatableRegs_ = tri_->getAllocatableSet(fn);
471 li_ = &getAnalysis<LiveIntervals>();
472 ls_ = &getAnalysis<LiveStacks>();
473 loopInfo = &getAnalysis<MachineLoopInfo>();
475 // We don't run the coalescer here because we have no reason to
476 // interact with it. If the coalescer requires interaction, it
477 // won't do anything. If it doesn't require interaction, we assume
478 // it was run as a separate pass.
480 // If this is the first function compiled, compute the related reg classes.
481 if (RelatedRegClasses.empty())
482 ComputeRelatedRegClasses();
484 // Also resize register usage trackers.
487 vrm_ = &getAnalysis<VirtRegMap>();
488 if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
490 spiller_.reset(createSpiller(mf_, li_, loopInfo, vrm_));
496 // Rewrite spill code and update the PhysRegsUsed set.
497 rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
499 assert(unhandled_.empty() && "Unhandled live intervals remain!");
507 NextReloadMap.clear();
508 DowngradedRegs.clear();
509 DowngradeMap.clear();
515 /// initIntervalSets - initialize the interval sets.
517 void RALinScan::initIntervalSets()
519 assert(unhandled_.empty() && fixed_.empty() &&
520 active_.empty() && inactive_.empty() &&
521 "interval sets should be empty on initialization");
523 handled_.reserve(li_->getNumIntervals());
525 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
526 if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
527 if (!i->second->empty()) {
528 mri_->setPhysRegUsed(i->second->reg);
529 fixed_.push_back(std::make_pair(i->second, i->second->begin()));
532 if (i->second->empty()) {
533 assignRegOrStackSlotAtInterval(i->second);
536 unhandled_.push(i->second);
541 void RALinScan::linearScan() {
542 // linear scan algorithm
544 dbgs() << "********** LINEAR SCAN **********\n"
545 << "********** Function: "
546 << mf_->getFunction()->getName() << '\n';
547 printIntervals("fixed", fixed_.begin(), fixed_.end());
550 while (!unhandled_.empty()) {
551 // pick the interval with the earliest start point
552 LiveInterval* cur = unhandled_.top();
555 DEBUG(dbgs() << "\n*** CURRENT ***: " << *cur << '\n');
557 assert(!cur->empty() && "Empty interval in unhandled set.");
559 processActiveIntervals(cur->beginIndex());
560 processInactiveIntervals(cur->beginIndex());
562 assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
563 "Can only allocate virtual registers!");
565 // Allocating a virtual register. try to find a free
566 // physical register or spill an interval (possibly this one) in order to
568 assignRegOrStackSlotAtInterval(cur);
571 printIntervals("active", active_.begin(), active_.end());
572 printIntervals("inactive", inactive_.begin(), inactive_.end());
576 // Expire any remaining active intervals
577 while (!active_.empty()) {
578 IntervalPtr &IP = active_.back();
579 unsigned reg = IP.first->reg;
580 DEBUG(dbgs() << "\tinterval " << *IP.first << " expired\n");
581 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
582 "Can only allocate virtual registers!");
583 reg = vrm_->getPhys(reg);
588 // Expire any remaining inactive intervals
590 for (IntervalPtrs::reverse_iterator
591 i = inactive_.rbegin(); i != inactive_.rend(); ++i)
592 dbgs() << "\tinterval " << *i->first << " expired\n";
596 // Add live-ins to every BB except for entry. Also perform trivial coalescing.
597 MachineFunction::iterator EntryMBB = mf_->begin();
598 SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
599 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
600 LiveInterval &cur = *i->second;
602 bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
605 else if (vrm_->isAssignedReg(cur.reg))
606 Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
609 // Ignore splited live intervals.
610 if (!isPhys && vrm_->getPreSplitReg(cur.reg))
613 for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
615 const LiveRange &LR = *I;
616 if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
617 for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
618 if (LiveInMBBs[i] != EntryMBB) {
619 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
620 "Adding a virtual register to livein set?");
621 LiveInMBBs[i]->addLiveIn(Reg);
628 DEBUG(dbgs() << *vrm_);
630 // Look for physical registers that end up not being allocated even though
631 // register allocator had to spill other registers in its register class.
632 if (ls_->getNumIntervals() == 0)
634 if (!vrm_->FindUnusedRegisters(li_))
638 /// processActiveIntervals - expire old intervals and move non-overlapping ones
639 /// to the inactive list.
640 void RALinScan::processActiveIntervals(SlotIndex CurPoint)
642 DEBUG(dbgs() << "\tprocessing active intervals:\n");
644 for (unsigned i = 0, e = active_.size(); i != e; ++i) {
645 LiveInterval *Interval = active_[i].first;
646 LiveInterval::iterator IntervalPos = active_[i].second;
647 unsigned reg = Interval->reg;
649 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
651 if (IntervalPos == Interval->end()) { // Remove expired intervals.
652 DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
653 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
654 "Can only allocate virtual registers!");
655 reg = vrm_->getPhys(reg);
658 // Pop off the end of the list.
659 active_[i] = active_.back();
663 } else if (IntervalPos->start > CurPoint) {
664 // Move inactive intervals to inactive list.
665 DEBUG(dbgs() << "\t\tinterval " << *Interval << " inactive\n");
666 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
667 "Can only allocate virtual registers!");
668 reg = vrm_->getPhys(reg);
671 inactive_.push_back(std::make_pair(Interval, IntervalPos));
673 // Pop off the end of the list.
674 active_[i] = active_.back();
678 // Otherwise, just update the iterator position.
679 active_[i].second = IntervalPos;
684 /// processInactiveIntervals - expire old intervals and move overlapping
685 /// ones to the active list.
686 void RALinScan::processInactiveIntervals(SlotIndex CurPoint)
688 DEBUG(dbgs() << "\tprocessing inactive intervals:\n");
690 for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
691 LiveInterval *Interval = inactive_[i].first;
692 LiveInterval::iterator IntervalPos = inactive_[i].second;
693 unsigned reg = Interval->reg;
695 IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
697 if (IntervalPos == Interval->end()) { // remove expired intervals.
698 DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
700 // Pop off the end of the list.
701 inactive_[i] = inactive_.back();
702 inactive_.pop_back();
704 } else if (IntervalPos->start <= CurPoint) {
705 // move re-activated intervals in active list
706 DEBUG(dbgs() << "\t\tinterval " << *Interval << " active\n");
707 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
708 "Can only allocate virtual registers!");
709 reg = vrm_->getPhys(reg);
712 active_.push_back(std::make_pair(Interval, IntervalPos));
714 // Pop off the end of the list.
715 inactive_[i] = inactive_.back();
716 inactive_.pop_back();
719 // Otherwise, just update the iterator position.
720 inactive_[i].second = IntervalPos;
725 /// updateSpillWeights - updates the spill weights of the specifed physical
726 /// register and its weight.
727 void RALinScan::updateSpillWeights(std::vector<float> &Weights,
728 unsigned reg, float weight,
729 const TargetRegisterClass *RC) {
730 SmallSet<unsigned, 4> Processed;
731 SmallSet<unsigned, 4> SuperAdded;
732 SmallVector<unsigned, 4> Supers;
733 Weights[reg] += weight;
734 Processed.insert(reg);
735 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
736 Weights[*as] += weight;
737 Processed.insert(*as);
738 if (tri_->isSubRegister(*as, reg) &&
739 SuperAdded.insert(*as) &&
741 Supers.push_back(*as);
745 // If the alias is a super-register, and the super-register is in the
746 // register class we are trying to allocate. Then add the weight to all
747 // sub-registers of the super-register even if they are not aliases.
748 // e.g. allocating for GR32, bh is not used, updating bl spill weight.
749 // bl should get the same spill weight otherwise it will be choosen
750 // as a spill candidate since spilling bh doesn't make ebx available.
751 for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
752 for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
753 if (!Processed.count(*sr))
754 Weights[*sr] += weight;
759 RALinScan::IntervalPtrs::iterator
760 FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
761 for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
763 if (I->first == LI) return I;
767 static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, SlotIndex Point){
768 for (unsigned i = 0, e = V.size(); i != e; ++i) {
769 RALinScan::IntervalPtr &IP = V[i];
770 LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
772 if (I != IP.first->begin()) --I;
777 /// addStackInterval - Create a LiveInterval for stack if the specified live
778 /// interval has been spilled.
779 static void addStackInterval(LiveInterval *cur, LiveStacks *ls_,
781 MachineRegisterInfo* mri_, VirtRegMap &vrm_) {
782 int SS = vrm_.getStackSlot(cur->reg);
783 if (SS == VirtRegMap::NO_STACK_SLOT)
786 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
787 LiveInterval &SI = ls_->getOrCreateInterval(SS, RC);
790 if (SI.hasAtLeastOneValue())
791 VNI = SI.getValNumInfo(0);
793 VNI = SI.getNextValue(SlotIndex(), 0, false,
794 ls_->getVNInfoAllocator());
796 LiveInterval &RI = li_->getInterval(cur->reg);
797 // FIXME: This may be overly conservative.
798 SI.MergeRangesInAsValue(RI, VNI);
801 /// getConflictWeight - Return the number of conflicts between cur
802 /// live interval and defs and uses of Reg weighted by loop depthes.
804 float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
805 MachineRegisterInfo *mri_,
806 const MachineLoopInfo *loopInfo) {
808 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
809 E = mri_->reg_end(); I != E; ++I) {
810 MachineInstr *MI = &*I;
811 if (cur->liveAt(li_->getInstructionIndex(MI))) {
812 unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
813 Conflicts += std::pow(10.0f, (float)loopDepth);
819 /// findIntervalsToSpill - Determine the intervals to spill for the
820 /// specified interval. It's passed the physical registers whose spill
821 /// weight is the lowest among all the registers whose live intervals
822 /// conflict with the interval.
823 void RALinScan::findIntervalsToSpill(LiveInterval *cur,
824 std::vector<std::pair<unsigned,float> > &Candidates,
826 SmallVector<LiveInterval*, 8> &SpillIntervals) {
827 // We have figured out the *best* register to spill. But there are other
828 // registers that are pretty good as well (spill weight within 3%). Spill
829 // the one that has fewest defs and uses that conflict with cur.
830 float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
831 SmallVector<LiveInterval*, 8> SLIs[3];
834 dbgs() << "\tConsidering " << NumCands << " candidates: ";
835 for (unsigned i = 0; i != NumCands; ++i)
836 dbgs() << tri_->getName(Candidates[i].first) << " ";
840 // Calculate the number of conflicts of each candidate.
841 for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
842 unsigned Reg = i->first->reg;
843 unsigned PhysReg = vrm_->getPhys(Reg);
844 if (!cur->overlapsFrom(*i->first, i->second))
846 for (unsigned j = 0; j < NumCands; ++j) {
847 unsigned Candidate = Candidates[j].first;
848 if (tri_->regsOverlap(PhysReg, Candidate)) {
850 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
851 SLIs[j].push_back(i->first);
856 for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
857 unsigned Reg = i->first->reg;
858 unsigned PhysReg = vrm_->getPhys(Reg);
859 if (!cur->overlapsFrom(*i->first, i->second-1))
861 for (unsigned j = 0; j < NumCands; ++j) {
862 unsigned Candidate = Candidates[j].first;
863 if (tri_->regsOverlap(PhysReg, Candidate)) {
865 Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
866 SLIs[j].push_back(i->first);
871 // Which is the best candidate?
872 unsigned BestCandidate = 0;
873 float MinConflicts = Conflicts[0];
874 for (unsigned i = 1; i != NumCands; ++i) {
875 if (Conflicts[i] < MinConflicts) {
877 MinConflicts = Conflicts[i];
881 std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
882 std::back_inserter(SpillIntervals));
886 struct WeightCompare {
888 const RALinScan &Allocator;
891 WeightCompare(const RALinScan &Alloc) : Allocator(Alloc) {}
893 typedef std::pair<unsigned, float> RegWeightPair;
894 bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
895 return LHS.second < RHS.second && !Allocator.isRecentlyUsed(LHS.first);
900 static bool weightsAreClose(float w1, float w2) {
904 float diff = w1 - w2;
905 if (diff <= 0.02f) // Within 0.02f
907 return (diff / w2) <= 0.05f; // Within 5%.
910 LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
911 DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
912 if (I == NextReloadMap.end())
914 return &li_->getInterval(I->second);
917 void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
918 bool isNew = DowngradedRegs.insert(Reg);
919 isNew = isNew; // Silence compiler warning.
920 assert(isNew && "Multiple reloads holding the same register?");
921 DowngradeMap.insert(std::make_pair(li->reg, Reg));
922 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS) {
923 isNew = DowngradedRegs.insert(*AS);
924 isNew = isNew; // Silence compiler warning.
925 assert(isNew && "Multiple reloads holding the same register?");
926 DowngradeMap.insert(std::make_pair(li->reg, *AS));
931 void RALinScan::UpgradeRegister(unsigned Reg) {
933 DowngradedRegs.erase(Reg);
934 for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
935 DowngradedRegs.erase(*AS);
941 bool operator()(LiveInterval* A, LiveInterval* B) {
942 return A->beginIndex() < B->beginIndex();
947 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
949 void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
950 DEBUG(dbgs() << "\tallocating current interval: ");
952 // This is an implicitly defined live interval, just assign any register.
953 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
955 unsigned physReg = vrm_->getRegAllocPref(cur->reg);
957 physReg = *RC->allocation_order_begin(*mf_);
958 DEBUG(dbgs() << tri_->getName(physReg) << '\n');
959 // Note the register is not really in use.
960 vrm_->assignVirt2Phys(cur->reg, physReg);
966 std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
967 SlotIndex StartPosition = cur->beginIndex();
968 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
970 // If start of this live interval is defined by a move instruction and its
971 // source is assigned a physical register that is compatible with the target
972 // register class, then we should try to assign it the same register.
973 // This can happen when the move is from a larger register class to a smaller
974 // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
975 if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
976 VNInfo *vni = cur->begin()->valno;
977 if ((vni->def != SlotIndex()) && !vni->isUnused() &&
978 vni->isDefAccurate()) {
979 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
980 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
982 tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
984 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
986 else if (vrm_->isAssignedReg(SrcReg))
987 Reg = vrm_->getPhys(SrcReg);
990 Reg = tri_->getSubReg(Reg, SrcSubReg);
992 Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
993 if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
994 mri_->setRegAllocationHint(cur->reg, 0, Reg);
1000 // For every interval in inactive we overlap with, mark the
1001 // register as not free and update spill weights.
1002 for (IntervalPtrs::const_iterator i = inactive_.begin(),
1003 e = inactive_.end(); i != e; ++i) {
1004 unsigned Reg = i->first->reg;
1005 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
1006 "Can only allocate virtual registers!");
1007 const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
1008 // If this is not in a related reg class to the register we're allocating,
1010 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1011 cur->overlapsFrom(*i->first, i->second-1)) {
1012 Reg = vrm_->getPhys(Reg);
1014 SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
1018 // Speculatively check to see if we can get a register right now. If not,
1019 // we know we won't be able to by adding more constraints. If so, we can
1020 // check to see if it is valid. Doing an exhaustive search of the fixed_ list
1021 // is very bad (it contains all callee clobbered registers for any functions
1022 // with a call), so we want to avoid doing that if possible.
1023 unsigned physReg = getFreePhysReg(cur);
1024 unsigned BestPhysReg = physReg;
1026 // We got a register. However, if it's in the fixed_ list, we might
1027 // conflict with it. Check to see if we conflict with it or any of its
1029 SmallSet<unsigned, 8> RegAliases;
1030 for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
1031 RegAliases.insert(*AS);
1033 bool ConflictsWithFixed = false;
1034 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1035 IntervalPtr &IP = fixed_[i];
1036 if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
1037 // Okay, this reg is on the fixed list. Check to see if we actually
1039 LiveInterval *I = IP.first;
1040 if (I->endIndex() > StartPosition) {
1041 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1043 if (II != I->begin() && II->start > StartPosition)
1045 if (cur->overlapsFrom(*I, II)) {
1046 ConflictsWithFixed = true;
1053 // Okay, the register picked by our speculative getFreePhysReg call turned
1054 // out to be in use. Actually add all of the conflicting fixed registers to
1055 // regUse_ so we can do an accurate query.
1056 if (ConflictsWithFixed) {
1057 // For every interval in fixed we overlap with, mark the register as not
1058 // free and update spill weights.
1059 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1060 IntervalPtr &IP = fixed_[i];
1061 LiveInterval *I = IP.first;
1063 const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
1064 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
1065 I->endIndex() > StartPosition) {
1066 LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
1068 if (II != I->begin() && II->start > StartPosition)
1070 if (cur->overlapsFrom(*I, II)) {
1071 unsigned reg = I->reg;
1073 SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
1078 // Using the newly updated regUse_ object, which includes conflicts in the
1079 // future, see if there are any registers available.
1080 physReg = getFreePhysReg(cur);
1084 // Restore the physical register tracker, removing information about the
1088 // If we find a free register, we are done: assign this virtual to
1089 // the free physical register and add this interval to the active
1092 DEBUG(dbgs() << tri_->getName(physReg) << '\n');
1093 vrm_->assignVirt2Phys(cur->reg, physReg);
1095 active_.push_back(std::make_pair(cur, cur->begin()));
1096 handled_.push_back(cur);
1098 // "Upgrade" the physical register since it has been allocated.
1099 UpgradeRegister(physReg);
1100 if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
1101 // "Downgrade" physReg to try to keep physReg from being allocated until
1102 // the next reload from the same SS is allocated.
1103 mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg);
1104 DowngradeRegister(cur, physReg);
1108 DEBUG(dbgs() << "no free registers\n");
1110 // Compile the spill weights into an array that is better for scanning.
1111 std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
1112 for (std::vector<std::pair<unsigned, float> >::iterator
1113 I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
1114 updateSpillWeights(SpillWeights, I->first, I->second, RC);
1116 // for each interval in active, update spill weights.
1117 for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
1119 unsigned reg = i->first->reg;
1120 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1121 "Can only allocate virtual registers!");
1122 reg = vrm_->getPhys(reg);
1123 updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
1126 DEBUG(dbgs() << "\tassigning stack slot at interval "<< *cur << ":\n");
1128 // Find a register to spill.
1129 float minWeight = HUGE_VALF;
1130 unsigned minReg = 0;
1133 std::vector<std::pair<unsigned,float> > RegsWeights;
1134 if (!minReg || SpillWeights[minReg] == HUGE_VALF)
1135 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1136 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1138 float regWeight = SpillWeights[reg];
1139 // Skip recently allocated registers.
1140 if (minWeight > regWeight && !isRecentlyUsed(reg))
1142 RegsWeights.push_back(std::make_pair(reg, regWeight));
1145 // If we didn't find a register that is spillable, try aliases?
1147 for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
1148 e = RC->allocation_order_end(*mf_); i != e; ++i) {
1150 // No need to worry about if the alias register size < regsize of RC.
1151 // We are going to spill all registers that alias it anyway.
1152 for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
1153 RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
1157 // Sort all potential spill candidates by weight.
1158 std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare(*this));
1159 minReg = RegsWeights[0].first;
1160 minWeight = RegsWeights[0].second;
1161 if (minWeight == HUGE_VALF) {
1162 // All registers must have inf weight. Just grab one!
1163 minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_);
1164 if (cur->weight == HUGE_VALF ||
1165 li_->getApproximateInstructionCount(*cur) == 0) {
1166 // Spill a physical register around defs and uses.
1167 if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
1168 // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
1169 // in fixed_. Reset them.
1170 for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
1171 IntervalPtr &IP = fixed_[i];
1172 LiveInterval *I = IP.first;
1173 if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
1174 IP.second = I->advanceTo(I->begin(), StartPosition);
1177 DowngradedRegs.clear();
1178 assignRegOrStackSlotAtInterval(cur);
1180 assert(false && "Ran out of registers during register allocation!");
1181 report_fatal_error("Ran out of registers during register allocation!");
1187 // Find up to 3 registers to consider as spill candidates.
1188 unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
1189 while (LastCandidate > 1) {
1190 if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
1196 dbgs() << "\t\tregister(s) with min weight(s): ";
1198 for (unsigned i = 0; i != LastCandidate; ++i)
1199 dbgs() << tri_->getName(RegsWeights[i].first)
1200 << " (" << RegsWeights[i].second << ")\n";
1203 // If the current has the minimum weight, we need to spill it and
1204 // add any added intervals back to unhandled, and restart
1206 if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
1207 DEBUG(dbgs() << "\t\t\tspilling(c): " << *cur << '\n');
1208 SmallVector<LiveInterval*, 8> spillIs;
1209 std::vector<LiveInterval*> added;
1210 spiller_->spill(cur, added, spillIs);
1212 std::sort(added.begin(), added.end(), LISorter());
1213 addStackInterval(cur, ls_, li_, mri_, *vrm_);
1215 return; // Early exit if all spills were folded.
1217 // Merge added with unhandled. Note that we have already sorted
1218 // intervals returned by addIntervalsForSpills by their starting
1220 // This also update the NextReloadMap. That is, it adds mapping from a
1221 // register defined by a reload from SS to the next reload from SS in the
1222 // same basic block.
1223 MachineBasicBlock *LastReloadMBB = 0;
1224 LiveInterval *LastReload = 0;
1225 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1226 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1227 LiveInterval *ReloadLi = added[i];
1228 if (ReloadLi->weight == HUGE_VALF &&
1229 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1230 SlotIndex ReloadIdx = ReloadLi->beginIndex();
1231 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1232 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1233 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1234 // Last reload of same SS is in the same MBB. We want to try to
1235 // allocate both reloads the same register and make sure the reg
1236 // isn't clobbered in between if at all possible.
1237 assert(LastReload->beginIndex() < ReloadIdx);
1238 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1240 LastReloadMBB = ReloadMBB;
1241 LastReload = ReloadLi;
1242 LastReloadSS = ReloadSS;
1244 unhandled_.push(ReloadLi);
1251 // Push the current interval back to unhandled since we are going
1252 // to re-run at least this iteration. Since we didn't modify it it
1253 // should go back right in the front of the list
1254 unhandled_.push(cur);
1256 assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
1257 "did not choose a register to spill?");
1259 // We spill all intervals aliasing the register with
1260 // minimum weight, rollback to the interval with the earliest
1261 // start point and let the linear scan algorithm run again
1262 SmallVector<LiveInterval*, 8> spillIs;
1264 // Determine which intervals have to be spilled.
1265 findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
1267 // Set of spilled vregs (used later to rollback properly)
1268 SmallSet<unsigned, 8> spilled;
1270 // The earliest start of a Spilled interval indicates up to where
1271 // in handled we need to roll back
1272 assert(!spillIs.empty() && "No spill intervals?");
1273 SlotIndex earliestStart = spillIs[0]->beginIndex();
1275 // Spill live intervals of virtual regs mapped to the physical register we
1276 // want to clear (and its aliases). We only spill those that overlap with the
1277 // current interval as the rest do not affect its allocation. we also keep
1278 // track of the earliest start of all spilled live intervals since this will
1279 // mark our rollback point.
1280 std::vector<LiveInterval*> added;
1281 while (!spillIs.empty()) {
1282 LiveInterval *sli = spillIs.back();
1284 DEBUG(dbgs() << "\t\t\tspilling(a): " << *sli << '\n');
1285 if (sli->beginIndex() < earliestStart)
1286 earliestStart = sli->beginIndex();
1288 spiller_->spill(sli, added, spillIs, &earliestStart);
1289 addStackInterval(sli, ls_, li_, mri_, *vrm_);
1290 spilled.insert(sli->reg);
1293 DEBUG(dbgs() << "\t\trolling back to: " << earliestStart << '\n');
1295 // Scan handled in reverse order up to the earliest start of a
1296 // spilled live interval and undo each one, restoring the state of
1298 while (!handled_.empty()) {
1299 LiveInterval* i = handled_.back();
1300 // If this interval starts before t we are done.
1301 if (!i->empty() && i->beginIndex() < earliestStart)
1303 DEBUG(dbgs() << "\t\t\tundo changes for: " << *i << '\n');
1304 handled_.pop_back();
1306 // When undoing a live interval allocation we must know if it is active or
1307 // inactive to properly update regUse_ and the VirtRegMap.
1308 IntervalPtrs::iterator it;
1309 if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
1311 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1312 if (!spilled.count(i->reg))
1314 delRegUse(vrm_->getPhys(i->reg));
1315 vrm_->clearVirt(i->reg);
1316 } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
1317 inactive_.erase(it);
1318 assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
1319 if (!spilled.count(i->reg))
1321 vrm_->clearVirt(i->reg);
1323 assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
1324 "Can only allocate virtual registers!");
1325 vrm_->clearVirt(i->reg);
1329 DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
1330 if (ii == DowngradeMap.end())
1331 // It interval has a preference, it must be defined by a copy. Clear the
1332 // preference now since the source interval allocation may have been
1334 mri_->setRegAllocationHint(i->reg, 0, 0);
1336 UpgradeRegister(ii->second);
1340 // Rewind the iterators in the active, inactive, and fixed lists back to the
1341 // point we reverted to.
1342 RevertVectorIteratorsTo(active_, earliestStart);
1343 RevertVectorIteratorsTo(inactive_, earliestStart);
1344 RevertVectorIteratorsTo(fixed_, earliestStart);
1346 // Scan the rest and undo each interval that expired after t and
1347 // insert it in active (the next iteration of the algorithm will
1348 // put it in inactive if required)
1349 for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
1350 LiveInterval *HI = handled_[i];
1351 if (!HI->expiredAt(earliestStart) &&
1352 HI->expiredAt(cur->beginIndex())) {
1353 DEBUG(dbgs() << "\t\t\tundo changes for: " << *HI << '\n');
1354 active_.push_back(std::make_pair(HI, HI->begin()));
1355 assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
1356 addRegUse(vrm_->getPhys(HI->reg));
1360 // Merge added with unhandled.
1361 // This also update the NextReloadMap. That is, it adds mapping from a
1362 // register defined by a reload from SS to the next reload from SS in the
1363 // same basic block.
1364 MachineBasicBlock *LastReloadMBB = 0;
1365 LiveInterval *LastReload = 0;
1366 int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
1367 std::sort(added.begin(), added.end(), LISorter());
1368 for (unsigned i = 0, e = added.size(); i != e; ++i) {
1369 LiveInterval *ReloadLi = added[i];
1370 if (ReloadLi->weight == HUGE_VALF &&
1371 li_->getApproximateInstructionCount(*ReloadLi) == 0) {
1372 SlotIndex ReloadIdx = ReloadLi->beginIndex();
1373 MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
1374 int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
1375 if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
1376 // Last reload of same SS is in the same MBB. We want to try to
1377 // allocate both reloads the same register and make sure the reg
1378 // isn't clobbered in between if at all possible.
1379 assert(LastReload->beginIndex() < ReloadIdx);
1380 NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
1382 LastReloadMBB = ReloadMBB;
1383 LastReload = ReloadLi;
1384 LastReloadSS = ReloadSS;
1386 unhandled_.push(ReloadLi);
1390 unsigned RALinScan::getFreePhysReg(LiveInterval* cur,
1391 const TargetRegisterClass *RC,
1392 unsigned MaxInactiveCount,
1393 SmallVector<unsigned, 256> &inactiveCounts,
1395 unsigned FreeReg = 0;
1396 unsigned FreeRegInactiveCount = 0;
1398 std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(cur->reg);
1399 // Resolve second part of the hint (if possible) given the current allocation.
1400 unsigned physReg = Hint.second;
1402 TargetRegisterInfo::isVirtualRegister(physReg) && vrm_->hasPhys(physReg))
1403 physReg = vrm_->getPhys(physReg);
1405 TargetRegisterClass::iterator I, E;
1406 tie(I, E) = tri_->getAllocationOrder(RC, Hint.first, physReg, *mf_);
1407 assert(I != E && "No allocatable register in this register class!");
1409 // Scan for the first available register.
1410 for (; I != E; ++I) {
1412 // Ignore "downgraded" registers.
1413 if (SkipDGRegs && DowngradedRegs.count(Reg))
1415 // Skip recently allocated registers.
1416 if (isRegAvail(Reg) && !isRecentlyUsed(Reg)) {
1418 if (FreeReg < inactiveCounts.size())
1419 FreeRegInactiveCount = inactiveCounts[FreeReg];
1421 FreeRegInactiveCount = 0;
1426 // If there are no free regs, or if this reg has the max inactive count,
1427 // return this register.
1428 if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount) {
1429 // Remember what register we picked so we can skip it next time.
1430 if (FreeReg != 0) recordRecentlyUsed(FreeReg);
1434 // Continue scanning the registers, looking for the one with the highest
1435 // inactive count. Alkis found that this reduced register pressure very
1436 // slightly on X86 (in rev 1.94 of this file), though this should probably be
1438 for (; I != E; ++I) {
1440 // Ignore "downgraded" registers.
1441 if (SkipDGRegs && DowngradedRegs.count(Reg))
1443 if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
1444 FreeRegInactiveCount < inactiveCounts[Reg] && !isRecentlyUsed(Reg)) {
1446 FreeRegInactiveCount = inactiveCounts[Reg];
1447 if (FreeRegInactiveCount == MaxInactiveCount)
1448 break; // We found the one with the max inactive count.
1452 // Remember what register we picked so we can skip it next time.
1453 recordRecentlyUsed(FreeReg);
1458 /// getFreePhysReg - return a free physical register for this virtual register
1459 /// interval if we have one, otherwise return 0.
1460 unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
1461 SmallVector<unsigned, 256> inactiveCounts;
1462 unsigned MaxInactiveCount = 0;
1464 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
1465 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
1467 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
1469 unsigned reg = i->first->reg;
1470 assert(TargetRegisterInfo::isVirtualRegister(reg) &&
1471 "Can only allocate virtual registers!");
1473 // If this is not in a related reg class to the register we're allocating,
1475 const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
1476 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
1477 reg = vrm_->getPhys(reg);
1478 if (inactiveCounts.size() <= reg)
1479 inactiveCounts.resize(reg+1);
1480 ++inactiveCounts[reg];
1481 MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
1485 // If copy coalescer has assigned a "preferred" register, check if it's
1487 unsigned Preference = vrm_->getRegAllocPref(cur->reg);
1489 DEBUG(dbgs() << "(preferred: " << tri_->getName(Preference) << ") ");
1490 if (isRegAvail(Preference) &&
1491 RC->contains(Preference))
1495 if (!DowngradedRegs.empty()) {
1496 unsigned FreeReg = getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts,
1501 return getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts, false);
1504 FunctionPass* llvm::createLinearScanRegisterAllocator() {
1505 return new RALinScan();