1 //===-- RegAllocLocal.cpp - A BasicBlock generic register allocator -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This register allocator allocates registers to a basic block at a time,
11 // attempting to keep values in registers and reusing registers as appropriate.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "llvm/BasicBlock.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/RegAllocRegistry.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/IndexedMap.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/ADT/Statistic.h"
32 #include "llvm/ADT/STLExtras.h"
36 STATISTIC(NumStores, "Number of stores added");
37 STATISTIC(NumLoads , "Number of loads added");
39 static RegisterRegAlloc
40 localRegAlloc("local", "local register allocator",
41 createLocalRegisterAllocator);
44 class VISIBILITY_HIDDEN RALocal : public MachineFunctionPass {
47 RALocal() : MachineFunctionPass(&ID), StackSlotForVirtReg(-1) {}
49 const TargetMachine *TM;
51 const TargetRegisterInfo *TRI;
52 const TargetInstrInfo *TII;
54 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
55 // values are spilled.
56 IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
58 // Virt2PhysRegMap - This map contains entries for each virtual register
59 // that is currently available in a physical register.
60 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysRegMap;
62 unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) {
63 return Virt2PhysRegMap[VirtReg];
66 // PhysRegsUsed - This array is effectively a map, containing entries for
67 // each physical register that currently has a value (ie, it is in
68 // Virt2PhysRegMap). The value mapped to is the virtual register
69 // corresponding to the physical register (the inverse of the
70 // Virt2PhysRegMap), or 0. The value is set to 0 if this register is pinned
71 // because it is used by a future instruction, and to -2 if it is not
72 // allocatable. If the entry for a physical register is -1, then the
73 // physical register is "not in the map".
75 std::vector<int> PhysRegsUsed;
77 // PhysRegsUseOrder - This contains a list of the physical registers that
78 // currently have a virtual register value in them. This list provides an
79 // ordering of registers, imposing a reallocation order. This list is only
80 // used if all registers are allocated and we have to spill one, in which
81 // case we spill the least recently used register. Entries at the front of
82 // the list are the least recently used registers, entries at the back are
83 // the most recently used.
85 std::vector<unsigned> PhysRegsUseOrder;
87 // Virt2LastUseMap - This maps each virtual register to its last use
88 // (MachineInstr*, operand index pair).
89 IndexedMap<std::pair<MachineInstr*, unsigned>, VirtReg2IndexFunctor>
92 std::pair<MachineInstr*,unsigned>& getVirtRegLastUse(unsigned Reg) {
93 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
94 return Virt2LastUseMap[Reg];
97 // VirtRegModified - This bitset contains information about which virtual
98 // registers need to be spilled back to memory when their registers are
99 // scavenged. If a virtual register has simply been rematerialized, there
100 // is no reason to spill it to memory when we need the register back.
102 BitVector VirtRegModified;
104 // UsedInMultipleBlocks - Tracks whether a particular register is used in
105 // more than one block.
106 BitVector UsedInMultipleBlocks;
108 void markVirtRegModified(unsigned Reg, bool Val = true) {
109 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
110 Reg -= TargetRegisterInfo::FirstVirtualRegister;
112 VirtRegModified.set(Reg);
114 VirtRegModified.reset(Reg);
117 bool isVirtRegModified(unsigned Reg) const {
118 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
119 assert(Reg - TargetRegisterInfo::FirstVirtualRegister < VirtRegModified.size()
120 && "Illegal virtual register!");
121 return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister];
124 void AddToPhysRegsUseOrder(unsigned Reg) {
125 std::vector<unsigned>::iterator It =
126 std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), Reg);
127 if (It != PhysRegsUseOrder.end())
128 PhysRegsUseOrder.erase(It);
129 PhysRegsUseOrder.push_back(Reg);
132 void MarkPhysRegRecentlyUsed(unsigned Reg) {
133 if (PhysRegsUseOrder.empty() ||
134 PhysRegsUseOrder.back() == Reg) return; // Already most recently used
136 for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i)
137 if (areRegsEqual(Reg, PhysRegsUseOrder[i-1])) {
138 unsigned RegMatch = PhysRegsUseOrder[i-1]; // remove from middle
139 PhysRegsUseOrder.erase(PhysRegsUseOrder.begin()+i-1);
140 // Add it to the end of the list
141 PhysRegsUseOrder.push_back(RegMatch);
143 return; // Found an exact match, exit early
148 virtual const char *getPassName() const {
149 return "Local Register Allocator";
152 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
153 AU.addRequiredID(PHIEliminationID);
154 AU.addRequiredID(TwoAddressInstructionPassID);
155 MachineFunctionPass::getAnalysisUsage(AU);
159 /// runOnMachineFunction - Register allocate the whole function
160 bool runOnMachineFunction(MachineFunction &Fn);
162 /// AllocateBasicBlock - Register allocate the specified basic block.
163 void AllocateBasicBlock(MachineBasicBlock &MBB);
166 /// areRegsEqual - This method returns true if the specified registers are
167 /// related to each other. To do this, it checks to see if they are equal
168 /// or if the first register is in the alias set of the second register.
170 bool areRegsEqual(unsigned R1, unsigned R2) const {
171 if (R1 == R2) return true;
172 for (const unsigned *AliasSet = TRI->getAliasSet(R2);
173 *AliasSet; ++AliasSet) {
174 if (*AliasSet == R1) return true;
179 /// getStackSpaceFor - This returns the frame index of the specified virtual
180 /// register on the stack, allocating space if necessary.
181 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
183 /// removePhysReg - This method marks the specified physical register as no
184 /// longer being in use.
186 void removePhysReg(unsigned PhysReg);
188 /// spillVirtReg - This method spills the value specified by PhysReg into
189 /// the virtual register slot specified by VirtReg. It then updates the RA
190 /// data structures to indicate the fact that PhysReg is now available.
192 void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
193 unsigned VirtReg, unsigned PhysReg);
195 /// spillPhysReg - This method spills the specified physical register into
196 /// the virtual register slot associated with it. If OnlyVirtRegs is set to
197 /// true, then the request is ignored if the physical register does not
198 /// contain a virtual register.
200 void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
201 unsigned PhysReg, bool OnlyVirtRegs = false);
203 /// assignVirtToPhysReg - This method updates local state so that we know
204 /// that PhysReg is the proper container for VirtReg now. The physical
205 /// register must not be used for anything else when this is called.
207 void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg);
209 /// isPhysRegAvailable - Return true if the specified physical register is
210 /// free and available for use. This also includes checking to see if
211 /// aliased registers are all free...
213 bool isPhysRegAvailable(unsigned PhysReg) const;
215 /// getFreeReg - Look to see if there is a free register available in the
216 /// specified register class. If not, return 0.
218 unsigned getFreeReg(const TargetRegisterClass *RC);
220 /// getReg - Find a physical register to hold the specified virtual
221 /// register. If all compatible physical registers are used, this method
222 /// spills the last used virtual register to the stack, and uses that
225 unsigned getReg(MachineBasicBlock &MBB, MachineInstr *MI,
228 /// reloadVirtReg - This method transforms the specified specified virtual
229 /// register use to refer to a physical register. This method may do this
230 /// in one of several ways: if the register is available in a physical
231 /// register already, it uses that physical register. If the value is not
232 /// in a physical register, and if there are physical registers available,
233 /// it loads it into a register. If register pressure is high, and it is
234 /// possible, it tries to fold the load of the virtual register into the
235 /// instruction itself. It avoids doing this if register pressure is low to
236 /// improve the chance that subsequent instructions can use the reloaded
237 /// value. This method returns the modified instruction.
239 MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
242 /// ComputeLocalLiveness - Computes liveness of registers within a basic
243 /// block, setting the killed/dead flags as appropriate.
244 void ComputeLocalLiveness(MachineBasicBlock& MBB);
246 void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
249 char RALocal::ID = 0;
252 /// getStackSpaceFor - This allocates space for the specified virtual register
253 /// to be held on the stack.
254 int RALocal::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
255 // Find the location Reg would belong...
256 int SS = StackSlotForVirtReg[VirtReg];
258 return SS; // Already has space allocated?
260 // Allocate a new stack object for this spill location...
261 int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
264 // Assign the slot...
265 StackSlotForVirtReg[VirtReg] = FrameIdx;
270 /// removePhysReg - This method marks the specified physical register as no
271 /// longer being in use.
273 void RALocal::removePhysReg(unsigned PhysReg) {
274 PhysRegsUsed[PhysReg] = -1; // PhyReg no longer used
276 std::vector<unsigned>::iterator It =
277 std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), PhysReg);
278 if (It != PhysRegsUseOrder.end())
279 PhysRegsUseOrder.erase(It);
283 /// spillVirtReg - This method spills the value specified by PhysReg into the
284 /// virtual register slot specified by VirtReg. It then updates the RA data
285 /// structures to indicate the fact that PhysReg is now available.
287 void RALocal::spillVirtReg(MachineBasicBlock &MBB,
288 MachineBasicBlock::iterator I,
289 unsigned VirtReg, unsigned PhysReg) {
290 assert(VirtReg && "Spilling a physical register is illegal!"
291 " Must not have appropriate kill for the register or use exists beyond"
292 " the intended one.");
293 DOUT << " Spilling register " << TRI->getName(PhysReg)
294 << " containing %reg" << VirtReg;
296 if (!isVirtRegModified(VirtReg)) {
297 DOUT << " which has not been modified, so no store necessary!";
298 std::pair<MachineInstr*, unsigned> &LastUse = getVirtRegLastUse(VirtReg);
300 LastUse.first->getOperand(LastUse.second).setIsKill();
302 // Otherwise, there is a virtual register corresponding to this physical
303 // register. We only need to spill it into its stack slot if it has been
305 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
306 int FrameIndex = getStackSpaceFor(VirtReg, RC);
307 DOUT << " to stack slot #" << FrameIndex;
308 // If the instruction reads the register that's spilled, (e.g. this can
309 // happen if it is a move to a physical register), then the spill
310 // instruction is not a kill.
311 bool isKill = !(I != MBB.end() && I->readsRegister(PhysReg));
312 TII->storeRegToStackSlot(MBB, I, PhysReg, isKill, FrameIndex, RC);
313 ++NumStores; // Update statistics
316 getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available
319 removePhysReg(PhysReg);
323 /// spillPhysReg - This method spills the specified physical register into the
324 /// virtual register slot associated with it. If OnlyVirtRegs is set to true,
325 /// then the request is ignored if the physical register does not contain a
326 /// virtual register.
328 void RALocal::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
329 unsigned PhysReg, bool OnlyVirtRegs) {
330 if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used!
331 assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!");
332 if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs)
333 spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg);
335 // If the selected register aliases any other registers, we must make
336 // sure that one of the aliases isn't alive.
337 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
338 *AliasSet; ++AliasSet)
339 if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register.
340 PhysRegsUsed[*AliasSet] != -2) // If allocatable.
341 if (PhysRegsUsed[*AliasSet])
342 spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
347 /// assignVirtToPhysReg - This method updates local state so that we know
348 /// that PhysReg is the proper container for VirtReg now. The physical
349 /// register must not be used for anything else when this is called.
351 void RALocal::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
352 assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!");
353 // Update information to note the fact that this register was just used, and
355 PhysRegsUsed[PhysReg] = VirtReg;
356 getVirt2PhysRegMapSlot(VirtReg) = PhysReg;
357 AddToPhysRegsUseOrder(PhysReg); // New use of PhysReg
361 /// isPhysRegAvailable - Return true if the specified physical register is free
362 /// and available for use. This also includes checking to see if aliased
363 /// registers are all free...
365 bool RALocal::isPhysRegAvailable(unsigned PhysReg) const {
366 if (PhysRegsUsed[PhysReg] != -1) return false;
368 // If the selected register aliases any other allocated registers, it is
370 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
371 *AliasSet; ++AliasSet)
372 if (PhysRegsUsed[*AliasSet] >= 0) // Aliased register in use?
373 return false; // Can't use this reg then.
378 /// getFreeReg - Look to see if there is a free register available in the
379 /// specified register class. If not, return 0.
381 unsigned RALocal::getFreeReg(const TargetRegisterClass *RC) {
382 // Get iterators defining the range of registers that are valid to allocate in
383 // this class, which also specifies the preferred allocation order.
384 TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
385 TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
387 for (; RI != RE; ++RI)
388 if (isPhysRegAvailable(*RI)) { // Is reg unused?
389 assert(*RI != 0 && "Cannot use register!");
390 return *RI; // Found an unused register!
396 /// getReg - Find a physical register to hold the specified virtual
397 /// register. If all compatible physical registers are used, this method spills
398 /// the last used virtual register to the stack, and uses that register.
400 unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I,
402 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
404 // First check to see if we have a free register of the requested type...
405 unsigned PhysReg = getFreeReg(RC);
407 // If we didn't find an unused register, scavenge one now!
409 assert(!PhysRegsUseOrder.empty() && "No allocated registers??");
411 // Loop over all of the preallocated registers from the least recently used
412 // to the most recently used. When we find one that is capable of holding
413 // our register, use it.
414 for (unsigned i = 0; PhysReg == 0; ++i) {
415 assert(i != PhysRegsUseOrder.size() &&
416 "Couldn't find a register of the appropriate class!");
418 unsigned R = PhysRegsUseOrder[i];
420 // We can only use this register if it holds a virtual register (ie, it
421 // can be spilled). Do not use it if it is an explicitly allocated
422 // physical register!
423 assert(PhysRegsUsed[R] != -1 &&
424 "PhysReg in PhysRegsUseOrder, but is not allocated?");
425 if (PhysRegsUsed[R] && PhysRegsUsed[R] != -2) {
426 // If the current register is compatible, use it.
427 if (RC->contains(R)) {
431 // If one of the registers aliased to the current register is
432 // compatible, use it.
433 for (const unsigned *AliasIt = TRI->getAliasSet(R);
434 *AliasIt; ++AliasIt) {
435 if (RC->contains(*AliasIt) &&
436 // If this is pinned down for some reason, don't use it. For
437 // example, if CL is pinned, and we run across CH, don't use
438 // CH as justification for using scavenging ECX (which will
440 PhysRegsUsed[*AliasIt] != 0 &&
442 // Make sure the register is allocatable. Don't allocate SIL on
444 PhysRegsUsed[*AliasIt] != -2) {
445 PhysReg = *AliasIt; // Take an aliased register
453 assert(PhysReg && "Physical register not assigned!?!?");
455 // At this point PhysRegsUseOrder[i] is the least recently used register of
456 // compatible register class. Spill it to memory and reap its remains.
457 spillPhysReg(MBB, I, PhysReg);
460 // Now that we know which register we need to assign this to, do it now!
461 assignVirtToPhysReg(VirtReg, PhysReg);
466 /// reloadVirtReg - This method transforms the specified specified virtual
467 /// register use to refer to a physical register. This method may do this in
468 /// one of several ways: if the register is available in a physical register
469 /// already, it uses that physical register. If the value is not in a physical
470 /// register, and if there are physical registers available, it loads it into a
471 /// register. If register pressure is high, and it is possible, it tries to
472 /// fold the load of the virtual register into the instruction itself. It
473 /// avoids doing this if register pressure is low to improve the chance that
474 /// subsequent instructions can use the reloaded value. This method returns the
475 /// modified instruction.
477 MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
479 unsigned VirtReg = MI->getOperand(OpNum).getReg();
481 // If the virtual register is already available, just update the instruction
483 if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
484 MarkPhysRegRecentlyUsed(PR); // Already have this value available!
485 MI->getOperand(OpNum).setReg(PR); // Assign the input register
486 getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
490 // Otherwise, we need to fold it into the current instruction, or reload it.
491 // If we have registers available to hold the value, use them.
492 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
493 unsigned PhysReg = getFreeReg(RC);
494 int FrameIndex = getStackSpaceFor(VirtReg, RC);
496 if (PhysReg) { // Register is available, allocate it!
497 assignVirtToPhysReg(VirtReg, PhysReg);
498 } else { // No registers available.
499 // Force some poor hapless value out of the register file to
500 // make room for the new register, and reload it.
501 PhysReg = getReg(MBB, MI, VirtReg);
504 markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded
506 DOUT << " Reloading %reg" << VirtReg << " into "
507 << TRI->getName(PhysReg) << "\n";
509 // Add move instruction(s)
510 TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
511 ++NumLoads; // Update statistics
513 MF->getRegInfo().setPhysRegUsed(PhysReg);
514 MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
515 getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
519 /// isReadModWriteImplicitKill - True if this is an implicit kill for a
520 /// read/mod/write register, i.e. update partial register.
521 static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
522 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
523 MachineOperand& MO = MI->getOperand(i);
524 if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
525 MO.isDef() && !MO.isDead())
531 /// isReadModWriteImplicitDef - True if this is an implicit def for a
532 /// read/mod/write register, i.e. update partial register.
533 static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
534 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
535 MachineOperand& MO = MI->getOperand(i);
536 if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
537 !MO.isDef() && MO.isKill())
543 // precedes - Helper function to determine with MachineInstr A
544 // precedes MachineInstr B within the same MBB.
545 static bool precedes(MachineBasicBlock::iterator A,
546 MachineBasicBlock::iterator B) {
550 MachineBasicBlock::iterator I = A->getParent()->begin();
551 while (I != A->getParent()->end()) {
563 /// ComputeLocalLiveness - Computes liveness of registers within a basic
564 /// block, setting the killed/dead flags as appropriate.
565 void RALocal::ComputeLocalLiveness(MachineBasicBlock& MBB) {
566 MachineRegisterInfo& MRI = MBB.getParent()->getRegInfo();
567 // Keep track of the most recently seen previous use or def of each reg,
568 // so that we can update them with dead/kill markers.
569 DenseMap<unsigned, std::pair<MachineInstr*, unsigned> > LastUseDef;
570 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
572 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
573 MachineOperand& MO = I->getOperand(i);
574 // Uses don't trigger any flags, but we need to save
575 // them for later. Also, we have to process these
576 // _before_ processing the defs, since an instr
577 // uses regs before it defs them.
578 if (MO.isReg() && MO.getReg() && MO.isUse()) {
579 LastUseDef[MO.getReg()] = std::make_pair(I, i);
582 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) continue;
584 const unsigned* subregs = TRI->getAliasSet(MO.getReg());
587 DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
588 alias = LastUseDef.find(*subregs);
590 if (alias != LastUseDef.end() &&
591 alias->second.first != I)
592 LastUseDef[*subregs] = std::make_pair(I, i);
600 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
601 MachineOperand& MO = I->getOperand(i);
602 // Defs others than 2-addr redefs _do_ trigger flag changes:
603 // - A def followed by a def is dead
604 // - A use followed by a def is a kill
605 if (MO.isReg() && MO.getReg() && MO.isDef()) {
606 DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
607 last = LastUseDef.find(MO.getReg());
608 if (last != LastUseDef.end()) {
609 // Check if this is a two address instruction. If so, then
610 // the def does not kill the use.
611 if (last->second.first == I &&
612 I->isRegReDefinedByTwoAddr(i))
615 MachineOperand& lastUD =
616 last->second.first->getOperand(last->second.second);
618 lastUD.setIsDead(true);
620 lastUD.setIsKill(true);
623 LastUseDef[MO.getReg()] = std::make_pair(I, i);
628 // Live-out (of the function) registers contain return values of the function,
629 // so we need to make sure they are alive at return time.
630 if (!MBB.empty() && MBB.back().getDesc().isReturn()) {
631 MachineInstr* Ret = &MBB.back();
632 for (MachineRegisterInfo::liveout_iterator
633 I = MF->getRegInfo().liveout_begin(),
634 E = MF->getRegInfo().liveout_end(); I != E; ++I)
635 if (!Ret->readsRegister(*I)) {
636 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
637 LastUseDef[*I] = std::make_pair(Ret, Ret->getNumOperands()-1);
641 // Finally, loop over the final use/def of each reg
642 // in the block and determine if it is dead.
643 for (DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
644 I = LastUseDef.begin(), E = LastUseDef.end(); I != E; ++I) {
645 MachineInstr* MI = I->second.first;
646 unsigned idx = I->second.second;
647 MachineOperand& MO = MI->getOperand(idx);
649 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(MO.getReg());
651 // A crude approximation of "live-out" calculation
652 bool usedOutsideBlock = isPhysReg ? false :
653 UsedInMultipleBlocks.test(MO.getReg() -
654 TargetRegisterInfo::FirstVirtualRegister);
655 if (!isPhysReg && !usedOutsideBlock)
656 for (MachineRegisterInfo::reg_iterator UI = MRI.reg_begin(MO.getReg()),
657 UE = MRI.reg_end(); UI != UE; ++UI)
659 // - used in another block
660 // - used in the same block before it is defined (loop)
661 if (UI->getParent() != &MBB ||
662 (MO.isDef() && UI.getOperand().isUse() && precedes(&*UI, MI))) {
663 UsedInMultipleBlocks.set(MO.getReg() -
664 TargetRegisterInfo::FirstVirtualRegister);
665 usedOutsideBlock = true;
669 // Physical registers and those that are not live-out of the block
670 // are killed/dead at their last use/def within this block.
671 if (isPhysReg || !usedOutsideBlock) {
673 // Don't mark uses that are tied to defs as kills.
674 if (MI->getDesc().getOperandConstraint(idx, TOI::TIED_TO) == -1)
682 void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
683 // loop over each instruction
684 MachineBasicBlock::iterator MII = MBB.begin();
686 DEBUG(const BasicBlock *LBB = MBB.getBasicBlock();
687 if (LBB) DOUT << "\nStarting RegAlloc of BB: " << LBB->getName());
689 // If this is the first basic block in the machine function, add live-in
690 // registers as active.
691 if (&MBB == &*MF->begin() || MBB.isLandingPad()) {
692 for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(),
693 E = MBB.livein_end(); I != E; ++I) {
695 MF->getRegInfo().setPhysRegUsed(Reg);
696 PhysRegsUsed[Reg] = 0; // It is free and reserved now
697 AddToPhysRegsUseOrder(Reg);
698 for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
699 *AliasSet; ++AliasSet) {
700 if (PhysRegsUsed[*AliasSet] != -2) {
701 AddToPhysRegsUseOrder(*AliasSet);
702 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
703 MF->getRegInfo().setPhysRegUsed(*AliasSet);
709 ComputeLocalLiveness(MBB);
711 // Otherwise, sequentially allocate each instruction in the MBB.
712 while (MII != MBB.end()) {
713 MachineInstr *MI = MII++;
714 const TargetInstrDesc &TID = MI->getDesc();
715 DEBUG(DOUT << "\nStarting RegAlloc of: " << *MI;
716 DOUT << " Regs have values: ";
717 for (unsigned i = 0; i != TRI->getNumRegs(); ++i)
718 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
719 DOUT << "[" << TRI->getName(i)
720 << ",%reg" << PhysRegsUsed[i] << "] ";
723 // Loop over the implicit uses, making sure that they are at the head of the
724 // use order list, so they don't get reallocated.
725 if (TID.ImplicitUses) {
726 for (const unsigned *ImplicitUses = TID.ImplicitUses;
727 *ImplicitUses; ++ImplicitUses)
728 MarkPhysRegRecentlyUsed(*ImplicitUses);
731 SmallVector<unsigned, 8> Kills;
732 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
733 MachineOperand& MO = MI->getOperand(i);
734 if (MO.isReg() && MO.isKill()) {
735 if (!MO.isImplicit())
736 Kills.push_back(MO.getReg());
737 else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
738 // These are extra physical register kills when a sub-register
739 // is defined (def of a sub-register is a read/mod/write of the
740 // larger registers). Ignore.
741 Kills.push_back(MO.getReg());
745 // If any physical regs are earlyclobber, spill any value they might
746 // have in them, then mark them unallocatable.
747 // If any virtual regs are earlyclobber, allocate them now (before
748 // freeing inputs that are killed).
749 if (MI->getOpcode()==TargetInstrInfo::INLINEASM) {
750 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
751 MachineOperand& MO = MI->getOperand(i);
752 if (MO.isReg() && MO.isDef() && MO.isEarlyClobber() &&
754 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
755 unsigned DestVirtReg = MO.getReg();
756 unsigned DestPhysReg;
758 // If DestVirtReg already has a value, use it.
759 if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
760 DestPhysReg = getReg(MBB, MI, DestVirtReg);
761 MF->getRegInfo().setPhysRegUsed(DestPhysReg);
762 markVirtRegModified(DestVirtReg);
763 getVirtRegLastUse(DestVirtReg) =
764 std::make_pair((MachineInstr*)0, 0);
765 DOUT << " Assigning " << TRI->getName(DestPhysReg)
766 << " to %reg" << DestVirtReg << "\n";
767 MO.setReg(DestPhysReg); // Assign the earlyclobber register
769 unsigned Reg = MO.getReg();
770 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
771 // These are extra physical register defs when a sub-register
772 // is defined (def of a sub-register is a read/mod/write of the
773 // larger registers). Ignore.
774 if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
776 MF->getRegInfo().setPhysRegUsed(Reg);
777 spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
778 PhysRegsUsed[Reg] = 0; // It is free and reserved now
779 AddToPhysRegsUseOrder(Reg);
781 for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
782 *AliasSet; ++AliasSet) {
783 if (PhysRegsUsed[*AliasSet] != -2) {
784 MF->getRegInfo().setPhysRegUsed(*AliasSet);
785 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
786 AddToPhysRegsUseOrder(*AliasSet);
794 // Get the used operands into registers. This has the potential to spill
795 // incoming values if we are out of registers. Note that we completely
796 // ignore physical register uses here. We assume that if an explicit
797 // physical register is referenced by the instruction, that it is guaranteed
798 // to be live-in, or the input is badly hosed.
800 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
801 MachineOperand& MO = MI->getOperand(i);
802 // here we are looking for only used operands (never def&use)
803 if (MO.isReg() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
804 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
805 MI = reloadVirtReg(MBB, MI, i);
808 // If this instruction is the last user of this register, kill the
809 // value, freeing the register being used, so it doesn't need to be
810 // spilled to memory.
812 for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
813 unsigned VirtReg = Kills[i];
814 unsigned PhysReg = VirtReg;
815 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
816 // If the virtual register was never materialized into a register, it
817 // might not be in the map, but it won't hurt to zero it out anyway.
818 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
819 PhysReg = PhysRegSlot;
821 } else if (PhysRegsUsed[PhysReg] == -2) {
822 // Unallocatable register dead, ignore.
825 assert((!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1) &&
826 "Silently clearing a virtual register?");
830 DOUT << " Last use of " << TRI->getName(PhysReg)
831 << "[%reg" << VirtReg <<"], removing it from live set\n";
832 removePhysReg(PhysReg);
833 for (const unsigned *AliasSet = TRI->getSubRegisters(PhysReg);
834 *AliasSet; ++AliasSet) {
835 if (PhysRegsUsed[*AliasSet] != -2) {
836 DOUT << " Last use of "
837 << TRI->getName(*AliasSet)
838 << "[%reg" << VirtReg <<"], removing it from live set\n";
839 removePhysReg(*AliasSet);
845 // Loop over all of the operands of the instruction, spilling registers that
846 // are defined, and marking explicit destinations in the PhysRegsUsed map.
847 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
848 MachineOperand& MO = MI->getOperand(i);
849 if (MO.isReg() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
850 !MO.isEarlyClobber() &&
851 TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
852 unsigned Reg = MO.getReg();
853 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
854 // These are extra physical register defs when a sub-register
855 // is defined (def of a sub-register is a read/mod/write of the
856 // larger registers). Ignore.
857 if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
859 MF->getRegInfo().setPhysRegUsed(Reg);
860 spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
861 PhysRegsUsed[Reg] = 0; // It is free and reserved now
862 AddToPhysRegsUseOrder(Reg);
864 for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
865 *AliasSet; ++AliasSet) {
866 if (PhysRegsUsed[*AliasSet] != -2) {
867 MF->getRegInfo().setPhysRegUsed(*AliasSet);
868 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
869 AddToPhysRegsUseOrder(*AliasSet);
875 // Loop over the implicit defs, spilling them as well.
876 if (TID.ImplicitDefs) {
877 for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
878 *ImplicitDefs; ++ImplicitDefs) {
879 unsigned Reg = *ImplicitDefs;
880 if (PhysRegsUsed[Reg] != -2) {
881 spillPhysReg(MBB, MI, Reg, true);
882 AddToPhysRegsUseOrder(Reg);
883 PhysRegsUsed[Reg] = 0; // It is free and reserved now
885 MF->getRegInfo().setPhysRegUsed(Reg);
886 for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
887 *AliasSet; ++AliasSet) {
888 if (PhysRegsUsed[*AliasSet] != -2) {
889 AddToPhysRegsUseOrder(*AliasSet);
890 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
891 MF->getRegInfo().setPhysRegUsed(*AliasSet);
897 SmallVector<unsigned, 8> DeadDefs;
898 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
899 MachineOperand& MO = MI->getOperand(i);
900 if (MO.isReg() && MO.isDead())
901 DeadDefs.push_back(MO.getReg());
904 // Okay, we have allocated all of the source operands and spilled any values
905 // that would be destroyed by defs of this instruction. Loop over the
906 // explicit defs and assign them to a register, spilling incoming values if
907 // we need to scavenge a register.
909 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
910 MachineOperand& MO = MI->getOperand(i);
911 if (MO.isReg() && MO.isDef() && MO.getReg() &&
912 !MO.isEarlyClobber() &&
913 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
914 unsigned DestVirtReg = MO.getReg();
915 unsigned DestPhysReg;
917 // If DestVirtReg already has a value, use it.
918 if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
919 DestPhysReg = getReg(MBB, MI, DestVirtReg);
920 MF->getRegInfo().setPhysRegUsed(DestPhysReg);
921 markVirtRegModified(DestVirtReg);
922 getVirtRegLastUse(DestVirtReg) = std::make_pair((MachineInstr*)0, 0);
923 DOUT << " Assigning " << TRI->getName(DestPhysReg)
924 << " to %reg" << DestVirtReg << "\n";
925 MO.setReg(DestPhysReg); // Assign the output register
929 // If this instruction defines any registers that are immediately dead,
932 for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) {
933 unsigned VirtReg = DeadDefs[i];
934 unsigned PhysReg = VirtReg;
935 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
936 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
937 PhysReg = PhysRegSlot;
938 assert(PhysReg != 0);
940 } else if (PhysRegsUsed[PhysReg] == -2) {
941 // Unallocatable register dead, ignore.
946 DOUT << " Register " << TRI->getName(PhysReg)
947 << " [%reg" << VirtReg
948 << "] is never used, removing it from live set\n";
949 removePhysReg(PhysReg);
950 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
951 *AliasSet; ++AliasSet) {
952 if (PhysRegsUsed[*AliasSet] != -2) {
953 DOUT << " Register " << TRI->getName(*AliasSet)
954 << " [%reg" << *AliasSet
955 << "] is never used, removing it from live set\n";
956 removePhysReg(*AliasSet);
962 // Finally, if this is a noop copy instruction, zap it.
963 unsigned SrcReg, DstReg;
964 if (TII->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg)
968 MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
970 // Spill all physical registers holding virtual registers now.
971 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
972 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) {
973 if (unsigned VirtReg = PhysRegsUsed[i])
974 spillVirtReg(MBB, MI, VirtReg, i);
980 // This checking code is very expensive.
982 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
983 e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
984 if (unsigned PR = Virt2PhysRegMap[i]) {
985 cerr << "Register still mapped: " << i << " -> " << PR << "\n";
988 assert(AllOk && "Virtual registers still in phys regs?");
991 // Clear any physical register which appear live at the end of the basic
992 // block, but which do not hold any virtual registers. e.g., the stack
994 PhysRegsUseOrder.clear();
997 /// runOnMachineFunction - Register allocate the whole function
999 bool RALocal::runOnMachineFunction(MachineFunction &Fn) {
1000 DOUT << "Machine Function " << "\n";
1002 TM = &Fn.getTarget();
1003 TRI = TM->getRegisterInfo();
1004 TII = TM->getInstrInfo();
1006 PhysRegsUsed.assign(TRI->getNumRegs(), -1);
1008 // At various places we want to efficiently check to see whether a register
1009 // is allocatable. To handle this, we mark all unallocatable registers as
1010 // being pinned down, permanently.
1012 BitVector Allocable = TRI->getAllocatableSet(Fn);
1013 for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
1015 PhysRegsUsed[i] = -2; // Mark the reg unallocable.
1018 // initialize the virtual->physical register map to have a 'null'
1019 // mapping for all virtual registers
1020 unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg();
1021 StackSlotForVirtReg.grow(LastVirtReg);
1022 Virt2PhysRegMap.grow(LastVirtReg);
1023 Virt2LastUseMap.grow(LastVirtReg);
1024 VirtRegModified.resize(LastVirtReg+1-TargetRegisterInfo::FirstVirtualRegister);
1025 UsedInMultipleBlocks.resize(LastVirtReg+1-TargetRegisterInfo::FirstVirtualRegister);
1027 // Loop over all of the basic blocks, eliminating virtual register references
1028 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
1030 AllocateBasicBlock(*MBB);
1032 StackSlotForVirtReg.clear();
1033 PhysRegsUsed.clear();
1034 VirtRegModified.clear();
1035 UsedInMultipleBlocks.clear();
1036 Virt2PhysRegMap.clear();
1037 Virt2LastUseMap.clear();
1041 FunctionPass *llvm::createLocalRegisterAllocator() {
1042 return new RALocal();