1 //===-- RegAllocLocal.cpp - A BasicBlock generic register allocator -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This register allocator allocates registers to a basic block at a time,
11 // attempting to keep values in registers and reusing registers as appropriate.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "llvm/BasicBlock.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/RegAllocRegistry.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/ADT/IndexedMap.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/Statistic.h"
31 #include "llvm/ADT/STLExtras.h"
36 STATISTIC(NumStores, "Number of stores added");
37 STATISTIC(NumLoads , "Number of loads added");
39 static RegisterRegAlloc
40 localRegAlloc("local", " local register allocator",
41 createLocalRegisterAllocator);
44 class VISIBILITY_HIDDEN RALocal : public MachineFunctionPass {
47 RALocal() : MachineFunctionPass((intptr_t)&ID) {}
49 const TargetMachine *TM;
51 const TargetRegisterInfo *TRI;
52 const TargetInstrInfo *TII;
54 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
55 // values are spilled.
56 std::map<unsigned, int> StackSlotForVirtReg;
58 // Virt2PhysRegMap - This map contains entries for each virtual register
59 // that is currently available in a physical register.
60 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysRegMap;
62 unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) {
63 return Virt2PhysRegMap[VirtReg];
66 // PhysRegsUsed - This array is effectively a map, containing entries for
67 // each physical register that currently has a value (ie, it is in
68 // Virt2PhysRegMap). The value mapped to is the virtual register
69 // corresponding to the physical register (the inverse of the
70 // Virt2PhysRegMap), or 0. The value is set to 0 if this register is pinned
71 // because it is used by a future instruction, and to -2 if it is not
72 // allocatable. If the entry for a physical register is -1, then the
73 // physical register is "not in the map".
75 std::vector<int> PhysRegsUsed;
77 // PhysRegsUseOrder - This contains a list of the physical registers that
78 // currently have a virtual register value in them. This list provides an
79 // ordering of registers, imposing a reallocation order. This list is only
80 // used if all registers are allocated and we have to spill one, in which
81 // case we spill the least recently used register. Entries at the front of
82 // the list are the least recently used registers, entries at the back are
83 // the most recently used.
85 std::vector<unsigned> PhysRegsUseOrder;
87 // Virt2LastUseMap - This maps each virtual register to its last use
88 // (MachineInstr*, operand index pair).
89 IndexedMap<std::pair<MachineInstr*, unsigned>, VirtReg2IndexFunctor>
92 std::pair<MachineInstr*,unsigned>& getVirtRegLastUse(unsigned Reg) {
93 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
94 return Virt2LastUseMap[Reg];
97 // VirtRegModified - This bitset contains information about which virtual
98 // registers need to be spilled back to memory when their registers are
99 // scavenged. If a virtual register has simply been rematerialized, there
100 // is no reason to spill it to memory when we need the register back.
102 BitVector VirtRegModified;
104 // UsedInMultipleBlocks - Tracks whether a particular register is used in
105 // more than one block.
106 BitVector UsedInMultipleBlocks;
108 void markVirtRegModified(unsigned Reg, bool Val = true) {
109 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
110 Reg -= TargetRegisterInfo::FirstVirtualRegister;
112 VirtRegModified.set(Reg);
114 VirtRegModified.reset(Reg);
117 bool isVirtRegModified(unsigned Reg) const {
118 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
119 assert(Reg - TargetRegisterInfo::FirstVirtualRegister < VirtRegModified.size()
120 && "Illegal virtual register!");
121 return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister];
124 void AddToPhysRegsUseOrder(unsigned Reg) {
125 std::vector<unsigned>::iterator It =
126 std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), Reg);
127 if (It != PhysRegsUseOrder.end())
128 PhysRegsUseOrder.erase(It);
129 PhysRegsUseOrder.push_back(Reg);
132 void MarkPhysRegRecentlyUsed(unsigned Reg) {
133 if (PhysRegsUseOrder.empty() ||
134 PhysRegsUseOrder.back() == Reg) return; // Already most recently used
136 for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i)
137 if (areRegsEqual(Reg, PhysRegsUseOrder[i-1])) {
138 unsigned RegMatch = PhysRegsUseOrder[i-1]; // remove from middle
139 PhysRegsUseOrder.erase(PhysRegsUseOrder.begin()+i-1);
140 // Add it to the end of the list
141 PhysRegsUseOrder.push_back(RegMatch);
143 return; // Found an exact match, exit early
148 virtual const char *getPassName() const {
149 return "Local Register Allocator";
152 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
153 AU.addRequiredID(PHIEliminationID);
154 AU.addRequiredID(TwoAddressInstructionPassID);
155 MachineFunctionPass::getAnalysisUsage(AU);
159 /// runOnMachineFunction - Register allocate the whole function
160 bool runOnMachineFunction(MachineFunction &Fn);
162 /// AllocateBasicBlock - Register allocate the specified basic block.
163 void AllocateBasicBlock(MachineBasicBlock &MBB);
166 /// areRegsEqual - This method returns true if the specified registers are
167 /// related to each other. To do this, it checks to see if they are equal
168 /// or if the first register is in the alias set of the second register.
170 bool areRegsEqual(unsigned R1, unsigned R2) const {
171 if (R1 == R2) return true;
172 for (const unsigned *AliasSet = TRI->getAliasSet(R2);
173 *AliasSet; ++AliasSet) {
174 if (*AliasSet == R1) return true;
179 /// getStackSpaceFor - This returns the frame index of the specified virtual
180 /// register on the stack, allocating space if necessary.
181 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
183 /// removePhysReg - This method marks the specified physical register as no
184 /// longer being in use.
186 void removePhysReg(unsigned PhysReg);
188 /// spillVirtReg - This method spills the value specified by PhysReg into
189 /// the virtual register slot specified by VirtReg. It then updates the RA
190 /// data structures to indicate the fact that PhysReg is now available.
192 void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
193 unsigned VirtReg, unsigned PhysReg);
195 /// spillPhysReg - This method spills the specified physical register into
196 /// the virtual register slot associated with it. If OnlyVirtRegs is set to
197 /// true, then the request is ignored if the physical register does not
198 /// contain a virtual register.
200 void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
201 unsigned PhysReg, bool OnlyVirtRegs = false);
203 /// assignVirtToPhysReg - This method updates local state so that we know
204 /// that PhysReg is the proper container for VirtReg now. The physical
205 /// register must not be used for anything else when this is called.
207 void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg);
209 /// isPhysRegAvailable - Return true if the specified physical register is
210 /// free and available for use. This also includes checking to see if
211 /// aliased registers are all free...
213 bool isPhysRegAvailable(unsigned PhysReg) const;
215 /// getFreeReg - Look to see if there is a free register available in the
216 /// specified register class. If not, return 0.
218 unsigned getFreeReg(const TargetRegisterClass *RC);
220 /// getReg - Find a physical register to hold the specified virtual
221 /// register. If all compatible physical registers are used, this method
222 /// spills the last used virtual register to the stack, and uses that
225 unsigned getReg(MachineBasicBlock &MBB, MachineInstr *MI,
228 /// reloadVirtReg - This method transforms the specified specified virtual
229 /// register use to refer to a physical register. This method may do this
230 /// in one of several ways: if the register is available in a physical
231 /// register already, it uses that physical register. If the value is not
232 /// in a physical register, and if there are physical registers available,
233 /// it loads it into a register. If register pressure is high, and it is
234 /// possible, it tries to fold the load of the virtual register into the
235 /// instruction itself. It avoids doing this if register pressure is low to
236 /// improve the chance that subsequent instructions can use the reloaded
237 /// value. This method returns the modified instruction.
239 MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
243 void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
246 char RALocal::ID = 0;
249 /// getStackSpaceFor - This allocates space for the specified virtual register
250 /// to be held on the stack.
251 int RALocal::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
252 // Find the location Reg would belong...
253 std::map<unsigned, int>::iterator I =StackSlotForVirtReg.lower_bound(VirtReg);
255 if (I != StackSlotForVirtReg.end() && I->first == VirtReg)
256 return I->second; // Already has space allocated?
258 // Allocate a new stack object for this spill location...
259 int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
262 // Assign the slot...
263 StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx));
268 /// removePhysReg - This method marks the specified physical register as no
269 /// longer being in use.
271 void RALocal::removePhysReg(unsigned PhysReg) {
272 PhysRegsUsed[PhysReg] = -1; // PhyReg no longer used
274 std::vector<unsigned>::iterator It =
275 std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), PhysReg);
276 if (It != PhysRegsUseOrder.end())
277 PhysRegsUseOrder.erase(It);
281 /// spillVirtReg - This method spills the value specified by PhysReg into the
282 /// virtual register slot specified by VirtReg. It then updates the RA data
283 /// structures to indicate the fact that PhysReg is now available.
285 void RALocal::spillVirtReg(MachineBasicBlock &MBB,
286 MachineBasicBlock::iterator I,
287 unsigned VirtReg, unsigned PhysReg) {
288 assert(VirtReg && "Spilling a physical register is illegal!"
289 " Must not have appropriate kill for the register or use exists beyond"
290 " the intended one.");
291 DOUT << " Spilling register " << TRI->getName(PhysReg)
292 << " containing %reg" << VirtReg;
294 const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
296 if (!isVirtRegModified(VirtReg)) {
297 DOUT << " which has not been modified, so no store necessary!";
298 std::pair<MachineInstr*, unsigned> &LastUse = getVirtRegLastUse(VirtReg);
300 LastUse.first->getOperand(LastUse.second).setIsKill();
302 // Otherwise, there is a virtual register corresponding to this physical
303 // register. We only need to spill it into its stack slot if it has been
305 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
306 int FrameIndex = getStackSpaceFor(VirtReg, RC);
307 DOUT << " to stack slot #" << FrameIndex;
308 // If the instruction reads the register that's spilled, (e.g. this can
309 // happen if it is a move to a physical register), then the spill
310 // instruction is not a kill.
311 bool isKill = !(I != MBB.end() && I->readsRegister(PhysReg));
312 TII->storeRegToStackSlot(MBB, I, PhysReg, isKill, FrameIndex, RC);
313 ++NumStores; // Update statistics
316 getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available
319 removePhysReg(PhysReg);
323 /// spillPhysReg - This method spills the specified physical register into the
324 /// virtual register slot associated with it. If OnlyVirtRegs is set to true,
325 /// then the request is ignored if the physical register does not contain a
326 /// virtual register.
328 void RALocal::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
329 unsigned PhysReg, bool OnlyVirtRegs) {
330 if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used!
331 assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!");
332 if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs)
333 spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg);
335 // If the selected register aliases any other registers, we must make
336 // sure that one of the aliases isn't alive.
337 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
338 *AliasSet; ++AliasSet)
339 if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register.
340 PhysRegsUsed[*AliasSet] != -2) // If allocatable.
341 if (PhysRegsUsed[*AliasSet])
342 spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
347 /// assignVirtToPhysReg - This method updates local state so that we know
348 /// that PhysReg is the proper container for VirtReg now. The physical
349 /// register must not be used for anything else when this is called.
351 void RALocal::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
352 assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!");
353 // Update information to note the fact that this register was just used, and
355 PhysRegsUsed[PhysReg] = VirtReg;
356 getVirt2PhysRegMapSlot(VirtReg) = PhysReg;
357 AddToPhysRegsUseOrder(PhysReg); // New use of PhysReg
361 /// isPhysRegAvailable - Return true if the specified physical register is free
362 /// and available for use. This also includes checking to see if aliased
363 /// registers are all free...
365 bool RALocal::isPhysRegAvailable(unsigned PhysReg) const {
366 if (PhysRegsUsed[PhysReg] != -1) return false;
368 // If the selected register aliases any other allocated registers, it is
370 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
371 *AliasSet; ++AliasSet)
372 if (PhysRegsUsed[*AliasSet] >= 0) // Aliased register in use?
373 return false; // Can't use this reg then.
378 /// getFreeReg - Look to see if there is a free register available in the
379 /// specified register class. If not, return 0.
381 unsigned RALocal::getFreeReg(const TargetRegisterClass *RC) {
382 // Get iterators defining the range of registers that are valid to allocate in
383 // this class, which also specifies the preferred allocation order.
384 TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
385 TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
387 for (; RI != RE; ++RI)
388 if (isPhysRegAvailable(*RI)) { // Is reg unused?
389 assert(*RI != 0 && "Cannot use register!");
390 return *RI; // Found an unused register!
396 /// getReg - Find a physical register to hold the specified virtual
397 /// register. If all compatible physical registers are used, this method spills
398 /// the last used virtual register to the stack, and uses that register.
400 unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I,
402 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
404 // First check to see if we have a free register of the requested type...
405 unsigned PhysReg = getFreeReg(RC);
407 // If we didn't find an unused register, scavenge one now!
409 assert(!PhysRegsUseOrder.empty() && "No allocated registers??");
411 // Loop over all of the preallocated registers from the least recently used
412 // to the most recently used. When we find one that is capable of holding
413 // our register, use it.
414 for (unsigned i = 0; PhysReg == 0; ++i) {
415 assert(i != PhysRegsUseOrder.size() &&
416 "Couldn't find a register of the appropriate class!");
418 unsigned R = PhysRegsUseOrder[i];
420 // We can only use this register if it holds a virtual register (ie, it
421 // can be spilled). Do not use it if it is an explicitly allocated
422 // physical register!
423 assert(PhysRegsUsed[R] != -1 &&
424 "PhysReg in PhysRegsUseOrder, but is not allocated?");
425 if (PhysRegsUsed[R] && PhysRegsUsed[R] != -2) {
426 // If the current register is compatible, use it.
427 if (RC->contains(R)) {
431 // If one of the registers aliased to the current register is
432 // compatible, use it.
433 for (const unsigned *AliasIt = TRI->getAliasSet(R);
434 *AliasIt; ++AliasIt) {
435 if (RC->contains(*AliasIt) &&
436 // If this is pinned down for some reason, don't use it. For
437 // example, if CL is pinned, and we run across CH, don't use
438 // CH as justification for using scavenging ECX (which will
440 PhysRegsUsed[*AliasIt] != 0 &&
442 // Make sure the register is allocatable. Don't allocate SIL on
444 PhysRegsUsed[*AliasIt] != -2) {
445 PhysReg = *AliasIt; // Take an aliased register
453 assert(PhysReg && "Physical register not assigned!?!?");
455 // At this point PhysRegsUseOrder[i] is the least recently used register of
456 // compatible register class. Spill it to memory and reap its remains.
457 spillPhysReg(MBB, I, PhysReg);
460 // Now that we know which register we need to assign this to, do it now!
461 assignVirtToPhysReg(VirtReg, PhysReg);
466 /// reloadVirtReg - This method transforms the specified specified virtual
467 /// register use to refer to a physical register. This method may do this in
468 /// one of several ways: if the register is available in a physical register
469 /// already, it uses that physical register. If the value is not in a physical
470 /// register, and if there are physical registers available, it loads it into a
471 /// register. If register pressure is high, and it is possible, it tries to
472 /// fold the load of the virtual register into the instruction itself. It
473 /// avoids doing this if register pressure is low to improve the chance that
474 /// subsequent instructions can use the reloaded value. This method returns the
475 /// modified instruction.
477 MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
479 unsigned VirtReg = MI->getOperand(OpNum).getReg();
481 // If the virtual register is already available, just update the instruction
483 if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
484 MarkPhysRegRecentlyUsed(PR); // Already have this value available!
485 MI->getOperand(OpNum).setReg(PR); // Assign the input register
486 getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
490 // Otherwise, we need to fold it into the current instruction, or reload it.
491 // If we have registers available to hold the value, use them.
492 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
493 unsigned PhysReg = getFreeReg(RC);
494 int FrameIndex = getStackSpaceFor(VirtReg, RC);
496 if (PhysReg) { // Register is available, allocate it!
497 assignVirtToPhysReg(VirtReg, PhysReg);
498 } else { // No registers available.
499 // Force some poor hapless value out of the register file to
500 // make room for the new register, and reload it.
501 PhysReg = getReg(MBB, MI, VirtReg);
504 markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded
506 DOUT << " Reloading %reg" << VirtReg << " into "
507 << TRI->getName(PhysReg) << "\n";
509 // Add move instruction(s)
510 const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
511 TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
512 ++NumLoads; // Update statistics
514 MF->getRegInfo().setPhysRegUsed(PhysReg);
515 MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
516 getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
520 /// isReadModWriteImplicitKill - True if this is an implicit kill for a
521 /// read/mod/write register, i.e. update partial register.
522 static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
523 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
524 MachineOperand& MO = MI->getOperand(i);
525 if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() &&
526 MO.isDef() && !MO.isDead())
532 /// isReadModWriteImplicitDef - True if this is an implicit def for a
533 /// read/mod/write register, i.e. update partial register.
534 static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
535 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
536 MachineOperand& MO = MI->getOperand(i);
537 if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() &&
538 !MO.isDef() && MO.isKill())
544 // precedes - Helper function to determine with MachineInstr A
545 // precedes MachineInstr B within the same MBB.
546 static bool precedes(MachineBasicBlock::iterator A,
547 MachineBasicBlock::iterator B) {
551 MachineBasicBlock::iterator I = A->getParent()->begin();
552 while (I != A->getParent()->end()) {
564 void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
565 // loop over each instruction
566 MachineBasicBlock::iterator MII = MBB.begin();
567 const TargetInstrInfo &TII = *TM->getInstrInfo();
569 DEBUG(const BasicBlock *LBB = MBB.getBasicBlock();
570 if (LBB) DOUT << "\nStarting RegAlloc of BB: " << LBB->getName());
572 // If this is the first basic block in the machine function, add live-in
573 // registers as active.
574 if (&MBB == &*MF->begin() || MBB.isLandingPad()) {
575 for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(),
576 E = MBB.livein_end(); I != E; ++I) {
578 MF->getRegInfo().setPhysRegUsed(Reg);
579 PhysRegsUsed[Reg] = 0; // It is free and reserved now
580 AddToPhysRegsUseOrder(Reg);
581 for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
582 *AliasSet; ++AliasSet) {
583 if (PhysRegsUsed[*AliasSet] != -2) {
584 AddToPhysRegsUseOrder(*AliasSet);
585 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
586 MF->getRegInfo().setPhysRegUsed(*AliasSet);
593 MachineRegisterInfo& MRI = MBB.getParent()->getRegInfo();
594 // Keep track of the most recently seen previous use or def of each reg,
595 // so that we can update them with dead/kill markers.
596 std::map<unsigned, std::pair<MachineInstr*, unsigned> > LastUseDef;
597 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
599 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
600 MachineOperand& MO = I->getOperand(i);
601 // Uses don't trigger any flags, but we need to save
602 // them for later. Also, we have to process these
603 // _before_ processing the defs, since an instr
604 // uses regs before it defs them.
605 if (MO.isReg() && MO.getReg() && MO.isUse())
606 LastUseDef[MO.getReg()] = std::make_pair(I, i);
609 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
610 MachineOperand& MO = I->getOperand(i);
611 // Defs others than 2-addr redefs _do_ trigger flag changes:
612 // - A def followed by a def is dead
613 // - A use followed by a def is a kill
614 if (MO.isReg() && MO.getReg() && MO.isDef() &&
615 !I->isRegReDefinedByTwoAddr(MO.getReg())) {
616 std::map<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
617 last = LastUseDef.find(MO.getReg());
618 if (last != LastUseDef.end()) {
619 MachineOperand& lastUD =
620 last->second.first->getOperand(last->second.second);
622 lastUD.setIsDead(true);
623 else if (lastUD.isUse())
624 lastUD.setIsKill(true);
627 LastUseDef[MO.getReg()] = std::make_pair(I, i);
632 // Live-out (of the function) registers contain return values of the function,
633 // so we need to make sure they are alive at return time.
634 if (!MBB.empty() && MBB.back().getDesc().isReturn()) {
635 MachineInstr* Ret = &MBB.back();
636 for (MachineRegisterInfo::liveout_iterator
637 I = MF->getRegInfo().liveout_begin(),
638 E = MF->getRegInfo().liveout_end(); I != E; ++I)
639 if (!Ret->readsRegister(*I)) {
640 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
641 LastUseDef[*I] = std::make_pair(Ret, Ret->getNumOperands()-1);
645 // Finally, loop over the final use/def of each reg
646 // in the block and determine if it is dead.
647 for (std::map<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
648 I = LastUseDef.begin(), E = LastUseDef.end(); I != E; ++I) {
649 MachineInstr* MI = I->second.first;
650 unsigned idx = I->second.second;
651 MachineOperand& MO = MI->getOperand(idx);
653 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(MO.getReg());
655 // A crude approximation of "live-out" calculation
656 bool usedOutsideBlock = isPhysReg ? false :
657 UsedInMultipleBlocks.test(MO.getReg() -
658 TargetRegisterInfo::FirstVirtualRegister);
659 if (!isPhysReg && !usedOutsideBlock)
660 for (MachineRegisterInfo::reg_iterator UI = MRI.reg_begin(MO.getReg()),
661 UE = MRI.reg_end(); UI != UE; ++UI)
663 // - used in another block
664 // - used in the same block before it is defined (loop)
665 if (UI->getParent() != &MBB ||
666 (MO.isDef() && UI.getOperand().isUse() && precedes(&*UI, MI))) {
667 UsedInMultipleBlocks.set(MO.getReg() -
668 TargetRegisterInfo::FirstVirtualRegister);
669 usedOutsideBlock = true;
673 // Physical registers and those that are not live-out of the block
674 // are killed/dead at their last use/def within this block.
675 if (isPhysReg || !usedOutsideBlock) {
678 else if (MI->getOperand(idx).isDef())
683 // Otherwise, sequentially allocate each instruction in the MBB.
684 while (MII != MBB.end()) {
685 MachineInstr *MI = MII++;
686 const TargetInstrDesc &TID = MI->getDesc();
687 DEBUG(DOUT << "\nStarting RegAlloc of: " << *MI;
688 DOUT << " Regs have values: ";
689 for (unsigned i = 0; i != TRI->getNumRegs(); ++i)
690 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
691 DOUT << "[" << TRI->getName(i)
692 << ",%reg" << PhysRegsUsed[i] << "] ";
695 // Loop over the implicit uses, making sure that they are at the head of the
696 // use order list, so they don't get reallocated.
697 if (TID.ImplicitUses) {
698 for (const unsigned *ImplicitUses = TID.ImplicitUses;
699 *ImplicitUses; ++ImplicitUses)
700 MarkPhysRegRecentlyUsed(*ImplicitUses);
703 SmallVector<unsigned, 8> Kills;
704 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
705 MachineOperand& MO = MI->getOperand(i);
706 if (MO.isRegister() && MO.isKill()) {
707 if (!MO.isImplicit())
708 Kills.push_back(MO.getReg());
709 else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
710 // These are extra physical register kills when a sub-register
711 // is defined (def of a sub-register is a read/mod/write of the
712 // larger registers). Ignore.
713 Kills.push_back(MO.getReg());
717 // Get the used operands into registers. This has the potential to spill
718 // incoming values if we are out of registers. Note that we completely
719 // ignore physical register uses here. We assume that if an explicit
720 // physical register is referenced by the instruction, that it is guaranteed
721 // to be live-in, or the input is badly hosed.
723 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
724 MachineOperand& MO = MI->getOperand(i);
725 // here we are looking for only used operands (never def&use)
726 if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
727 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
728 MI = reloadVirtReg(MBB, MI, i);
731 // If this instruction is the last user of this register, kill the
732 // value, freeing the register being used, so it doesn't need to be
733 // spilled to memory.
735 for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
736 unsigned VirtReg = Kills[i];
737 unsigned PhysReg = VirtReg;
738 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
739 // If the virtual register was never materialized into a register, it
740 // might not be in the map, but it won't hurt to zero it out anyway.
741 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
742 PhysReg = PhysRegSlot;
744 } else if (PhysRegsUsed[PhysReg] == -2) {
745 // Unallocatable register dead, ignore.
748 assert((!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1) &&
749 "Silently clearing a virtual register?");
753 DOUT << " Last use of " << TRI->getName(PhysReg)
754 << "[%reg" << VirtReg <<"], removing it from live set\n";
755 removePhysReg(PhysReg);
756 for (const unsigned *AliasSet = TRI->getSubRegisters(PhysReg);
757 *AliasSet; ++AliasSet) {
758 if (PhysRegsUsed[*AliasSet] != -2) {
759 DOUT << " Last use of "
760 << TRI->getName(*AliasSet)
761 << "[%reg" << VirtReg <<"], removing it from live set\n";
762 removePhysReg(*AliasSet);
768 // Loop over all of the operands of the instruction, spilling registers that
769 // are defined, and marking explicit destinations in the PhysRegsUsed map.
770 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
771 MachineOperand& MO = MI->getOperand(i);
772 if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
773 TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
774 unsigned Reg = MO.getReg();
775 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
776 // These are extra physical register defs when a sub-register
777 // is defined (def of a sub-register is a read/mod/write of the
778 // larger registers). Ignore.
779 if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
781 MF->getRegInfo().setPhysRegUsed(Reg);
782 spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
783 PhysRegsUsed[Reg] = 0; // It is free and reserved now
784 AddToPhysRegsUseOrder(Reg);
786 for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
787 *AliasSet; ++AliasSet) {
788 if (PhysRegsUsed[*AliasSet] != -2) {
789 MF->getRegInfo().setPhysRegUsed(*AliasSet);
790 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
791 AddToPhysRegsUseOrder(*AliasSet);
797 // Loop over the implicit defs, spilling them as well.
798 if (TID.ImplicitDefs) {
799 for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
800 *ImplicitDefs; ++ImplicitDefs) {
801 unsigned Reg = *ImplicitDefs;
802 if (PhysRegsUsed[Reg] != -2) {
803 spillPhysReg(MBB, MI, Reg, true);
804 AddToPhysRegsUseOrder(Reg);
805 PhysRegsUsed[Reg] = 0; // It is free and reserved now
807 MF->getRegInfo().setPhysRegUsed(Reg);
808 for (const unsigned *AliasSet = TRI->getSubRegisters(Reg);
809 *AliasSet; ++AliasSet) {
810 if (PhysRegsUsed[*AliasSet] != -2) {
811 AddToPhysRegsUseOrder(*AliasSet);
812 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
813 MF->getRegInfo().setPhysRegUsed(*AliasSet);
819 SmallVector<unsigned, 8> DeadDefs;
820 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
821 MachineOperand& MO = MI->getOperand(i);
822 if (MO.isRegister() && MO.isDead())
823 DeadDefs.push_back(MO.getReg());
826 // Okay, we have allocated all of the source operands and spilled any values
827 // that would be destroyed by defs of this instruction. Loop over the
828 // explicit defs and assign them to a register, spilling incoming values if
829 // we need to scavenge a register.
831 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
832 MachineOperand& MO = MI->getOperand(i);
833 if (MO.isRegister() && MO.isDef() && MO.getReg() &&
834 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
835 unsigned DestVirtReg = MO.getReg();
836 unsigned DestPhysReg;
838 // If DestVirtReg already has a value, use it.
839 if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
840 DestPhysReg = getReg(MBB, MI, DestVirtReg);
841 MF->getRegInfo().setPhysRegUsed(DestPhysReg);
842 markVirtRegModified(DestVirtReg);
843 getVirtRegLastUse(DestVirtReg) = std::make_pair((MachineInstr*)0, 0);
844 DOUT << " Assigning " << TRI->getName(DestPhysReg)
845 << " to %reg" << DestVirtReg << "\n";
846 MI->getOperand(i).setReg(DestPhysReg); // Assign the output register
850 // If this instruction defines any registers that are immediately dead,
853 for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) {
854 unsigned VirtReg = DeadDefs[i];
855 unsigned PhysReg = VirtReg;
856 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
857 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
858 PhysReg = PhysRegSlot;
859 assert(PhysReg != 0);
861 } else if (PhysRegsUsed[PhysReg] == -2) {
862 // Unallocatable register dead, ignore.
867 DOUT << " Register " << TRI->getName(PhysReg)
868 << " [%reg" << VirtReg
869 << "] is never used, removing it frame live list\n";
870 removePhysReg(PhysReg);
871 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
872 *AliasSet; ++AliasSet) {
873 if (PhysRegsUsed[*AliasSet] != -2) {
874 DOUT << " Register " << TRI->getName(*AliasSet)
875 << " [%reg" << *AliasSet
876 << "] is never used, removing it frame live list\n";
877 removePhysReg(*AliasSet);
883 // Finally, if this is a noop copy instruction, zap it.
884 unsigned SrcReg, DstReg;
885 if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg)
889 MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
891 // Spill all physical registers holding virtual registers now.
892 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
893 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) {
894 if (unsigned VirtReg = PhysRegsUsed[i])
895 spillVirtReg(MBB, MI, VirtReg, i);
901 // This checking code is very expensive.
903 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
904 e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
905 if (unsigned PR = Virt2PhysRegMap[i]) {
906 cerr << "Register still mapped: " << i << " -> " << PR << "\n";
909 assert(AllOk && "Virtual registers still in phys regs?");
912 // Clear any physical register which appear live at the end of the basic
913 // block, but which do not hold any virtual registers. e.g., the stack
915 PhysRegsUseOrder.clear();
918 /// runOnMachineFunction - Register allocate the whole function
920 bool RALocal::runOnMachineFunction(MachineFunction &Fn) {
921 DOUT << "Machine Function " << "\n";
923 TM = &Fn.getTarget();
924 TRI = TM->getRegisterInfo();
925 TII = TM->getInstrInfo();
927 PhysRegsUsed.assign(TRI->getNumRegs(), -1);
929 // At various places we want to efficiently check to see whether a register
930 // is allocatable. To handle this, we mark all unallocatable registers as
931 // being pinned down, permanently.
933 BitVector Allocable = TRI->getAllocatableSet(Fn);
934 for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
936 PhysRegsUsed[i] = -2; // Mark the reg unallocable.
939 // initialize the virtual->physical register map to have a 'null'
940 // mapping for all virtual registers
941 unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg();
942 Virt2PhysRegMap.grow(LastVirtReg);
943 Virt2LastUseMap.grow(LastVirtReg);
944 VirtRegModified.resize(LastVirtReg+1-TargetRegisterInfo::FirstVirtualRegister);
945 UsedInMultipleBlocks.resize(LastVirtReg+1-TargetRegisterInfo::FirstVirtualRegister);
947 // Loop over all of the basic blocks, eliminating virtual register references
948 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
950 AllocateBasicBlock(*MBB);
952 StackSlotForVirtReg.clear();
953 PhysRegsUsed.clear();
954 VirtRegModified.clear();
955 UsedInMultipleBlocks.clear();
956 Virt2PhysRegMap.clear();
957 Virt2LastUseMap.clear();
961 FunctionPass *llvm::createLocalRegisterAllocator() {
962 return new RALocal();