1 //===-- RegAllocLocal.cpp - A BasicBlock generic register allocator -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This register allocator allocates registers to a basic block at a time,
11 // attempting to keep values in registers and reusing registers as appropriate.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "llvm/BasicBlock.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/RegAllocRegistry.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/IndexedMap.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
38 STATISTIC(NumStores, "Number of stores added");
39 STATISTIC(NumLoads , "Number of loads added");
41 static RegisterRegAlloc
42 localRegAlloc("local", "local register allocator",
43 createLocalRegisterAllocator);
46 class RALocal : public MachineFunctionPass {
49 RALocal() : MachineFunctionPass(&ID), StackSlotForVirtReg(-1) {}
51 const TargetMachine *TM;
53 MachineRegisterInfo *MRI;
54 const TargetRegisterInfo *TRI;
55 const TargetInstrInfo *TII;
57 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
58 // values are spilled.
59 IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
61 // Virt2PhysRegMap - This map contains entries for each virtual register
62 // that is currently available in a physical register.
63 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysRegMap;
65 unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) {
66 return Virt2PhysRegMap[VirtReg];
69 // PhysRegsUsed - This array is effectively a map, containing entries for
70 // each physical register that currently has a value (ie, it is in
71 // Virt2PhysRegMap). The value mapped to is the virtual register
72 // corresponding to the physical register (the inverse of the
73 // Virt2PhysRegMap), or 0. The value is set to 0 if this register is pinned
74 // because it is used by a future instruction, and to -2 if it is not
75 // allocatable. If the entry for a physical register is -1, then the
76 // physical register is "not in the map".
78 std::vector<int> PhysRegsUsed;
80 // PhysRegsUseOrder - This contains a list of the physical registers that
81 // currently have a virtual register value in them. This list provides an
82 // ordering of registers, imposing a reallocation order. This list is only
83 // used if all registers are allocated and we have to spill one, in which
84 // case we spill the least recently used register. Entries at the front of
85 // the list are the least recently used registers, entries at the back are
86 // the most recently used.
88 std::vector<unsigned> PhysRegsUseOrder;
90 // Virt2LastUseMap - This maps each virtual register to its last use
91 // (MachineInstr*, operand index pair).
92 IndexedMap<std::pair<MachineInstr*, unsigned>, VirtReg2IndexFunctor>
95 std::pair<MachineInstr*,unsigned>& getVirtRegLastUse(unsigned Reg) {
96 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
97 return Virt2LastUseMap[Reg];
100 // VirtRegModified - This bitset contains information about which virtual
101 // registers need to be spilled back to memory when their registers are
102 // scavenged. If a virtual register has simply been rematerialized, there
103 // is no reason to spill it to memory when we need the register back.
105 BitVector VirtRegModified;
107 // UsedInMultipleBlocks - Tracks whether a particular register is used in
108 // more than one block.
109 BitVector UsedInMultipleBlocks;
111 void markVirtRegModified(unsigned Reg, bool Val = true) {
112 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
113 Reg -= TargetRegisterInfo::FirstVirtualRegister;
115 VirtRegModified.set(Reg);
117 VirtRegModified.reset(Reg);
120 bool isVirtRegModified(unsigned Reg) const {
121 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
122 assert(Reg - TargetRegisterInfo::FirstVirtualRegister <
123 VirtRegModified.size() && "Illegal virtual register!");
124 return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister];
127 void AddToPhysRegsUseOrder(unsigned Reg) {
128 std::vector<unsigned>::iterator It =
129 std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), Reg);
130 if (It != PhysRegsUseOrder.end())
131 PhysRegsUseOrder.erase(It);
132 PhysRegsUseOrder.push_back(Reg);
135 void MarkPhysRegRecentlyUsed(unsigned Reg) {
136 if (PhysRegsUseOrder.empty() ||
137 PhysRegsUseOrder.back() == Reg) return; // Already most recently used
139 for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i) {
140 unsigned RegMatch = PhysRegsUseOrder[i-1]; // remove from middle
141 if (!areRegsEqual(Reg, RegMatch)) continue;
143 PhysRegsUseOrder.erase(PhysRegsUseOrder.begin()+i-1);
144 // Add it to the end of the list
145 PhysRegsUseOrder.push_back(RegMatch);
147 return; // Found an exact match, exit early
152 virtual const char *getPassName() const {
153 return "Local Register Allocator";
156 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
157 AU.setPreservesCFG();
158 AU.addRequiredID(PHIEliminationID);
159 AU.addRequiredID(TwoAddressInstructionPassID);
160 MachineFunctionPass::getAnalysisUsage(AU);
164 /// runOnMachineFunction - Register allocate the whole function
165 bool runOnMachineFunction(MachineFunction &Fn);
167 /// AllocateBasicBlock - Register allocate the specified basic block.
168 void AllocateBasicBlock(MachineBasicBlock &MBB);
171 /// areRegsEqual - This method returns true if the specified registers are
172 /// related to each other. To do this, it checks to see if they are equal
173 /// or if the first register is in the alias set of the second register.
175 bool areRegsEqual(unsigned R1, unsigned R2) const {
176 if (R1 == R2) return true;
177 for (const unsigned *AliasSet = TRI->getAliasSet(R2);
178 *AliasSet; ++AliasSet) {
179 if (*AliasSet == R1) return true;
184 /// getStackSpaceFor - This returns the frame index of the specified virtual
185 /// register on the stack, allocating space if necessary.
186 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
188 /// removePhysReg - This method marks the specified physical register as no
189 /// longer being in use.
191 void removePhysReg(unsigned PhysReg);
193 void storeVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
194 unsigned VirtReg, unsigned PhysReg, bool isKill);
196 /// spillVirtReg - This method spills the value specified by PhysReg into
197 /// the virtual register slot specified by VirtReg. It then updates the RA
198 /// data structures to indicate the fact that PhysReg is now available.
200 void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
201 unsigned VirtReg, unsigned PhysReg);
203 /// spillPhysReg - This method spills the specified physical register into
204 /// the virtual register slot associated with it. If OnlyVirtRegs is set to
205 /// true, then the request is ignored if the physical register does not
206 /// contain a virtual register.
208 void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
209 unsigned PhysReg, bool OnlyVirtRegs = false);
211 /// assignVirtToPhysReg - This method updates local state so that we know
212 /// that PhysReg is the proper container for VirtReg now. The physical
213 /// register must not be used for anything else when this is called.
215 void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg);
217 /// isPhysRegAvailable - Return true if the specified physical register is
218 /// free and available for use. This also includes checking to see if
219 /// aliased registers are all free...
221 bool isPhysRegAvailable(unsigned PhysReg) const;
223 /// getFreeReg - Look to see if there is a free register available in the
224 /// specified register class. If not, return 0.
226 unsigned getFreeReg(const TargetRegisterClass *RC);
228 /// getReg - Find a physical register to hold the specified virtual
229 /// register. If all compatible physical registers are used, this method
230 /// spills the last used virtual register to the stack, and uses that
231 /// register. If NoFree is true, that means the caller knows there isn't
232 /// a free register, do not call getFreeReg().
233 unsigned getReg(MachineBasicBlock &MBB, MachineInstr *MI,
234 unsigned VirtReg, bool NoFree = false);
236 /// reloadVirtReg - This method transforms the specified virtual
237 /// register use to refer to a physical register. This method may do this
238 /// in one of several ways: if the register is available in a physical
239 /// register already, it uses that physical register. If the value is not
240 /// in a physical register, and if there are physical registers available,
241 /// it loads it into a register: PhysReg if that is an available physical
242 /// register, otherwise any physical register of the right class.
243 /// If register pressure is high, and it is possible, it tries to fold the
244 /// load of the virtual register into the instruction itself. It avoids
245 /// doing this if register pressure is low to improve the chance that
246 /// subsequent instructions can use the reloaded value. This method
247 /// returns the modified instruction.
249 MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
250 unsigned OpNum, SmallSet<unsigned, 4> &RRegs,
253 /// ComputeLocalLiveness - Computes liveness of registers within a basic
254 /// block, setting the killed/dead flags as appropriate.
255 void ComputeLocalLiveness(MachineBasicBlock& MBB);
257 void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
260 char RALocal::ID = 0;
263 /// getStackSpaceFor - This allocates space for the specified virtual register
264 /// to be held on the stack.
265 int RALocal::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
266 // Find the location Reg would belong...
267 int SS = StackSlotForVirtReg[VirtReg];
269 return SS; // Already has space allocated?
271 // Allocate a new stack object for this spill location...
272 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
276 StackSlotForVirtReg[VirtReg] = FrameIdx;
281 /// removePhysReg - This method marks the specified physical register as no
282 /// longer being in use.
284 void RALocal::removePhysReg(unsigned PhysReg) {
285 PhysRegsUsed[PhysReg] = -1; // PhyReg no longer used
287 std::vector<unsigned>::iterator It =
288 std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), PhysReg);
289 if (It != PhysRegsUseOrder.end())
290 PhysRegsUseOrder.erase(It);
293 /// storeVirtReg - Store a virtual register to its assigned stack slot.
294 void RALocal::storeVirtReg(MachineBasicBlock &MBB,
295 MachineBasicBlock::iterator I,
296 unsigned VirtReg, unsigned PhysReg,
298 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
299 int FrameIndex = getStackSpaceFor(VirtReg, RC);
300 DEBUG(dbgs() << " to stack slot #" << FrameIndex);
301 TII->storeRegToStackSlot(MBB, I, PhysReg, isKill, FrameIndex, RC, TRI);
302 ++NumStores; // Update statistics
305 /// spillVirtReg - This method spills the value specified by PhysReg into the
306 /// virtual register slot specified by VirtReg. It then updates the RA data
307 /// structures to indicate the fact that PhysReg is now available.
309 void RALocal::spillVirtReg(MachineBasicBlock &MBB,
310 MachineBasicBlock::iterator I,
311 unsigned VirtReg, unsigned PhysReg) {
312 assert(VirtReg && "Spilling a physical register is illegal!"
313 " Must not have appropriate kill for the register or use exists beyond"
314 " the intended one.");
315 DEBUG(dbgs() << " Spilling register " << TRI->getName(PhysReg)
316 << " containing %reg" << VirtReg);
318 if (!isVirtRegModified(VirtReg)) {
319 DEBUG(dbgs() << " which has not been modified, so no store necessary!");
320 std::pair<MachineInstr*, unsigned> &LastUse = getVirtRegLastUse(VirtReg);
322 LastUse.first->getOperand(LastUse.second).setIsKill();
324 // Otherwise, there is a virtual register corresponding to this physical
325 // register. We only need to spill it into its stack slot if it has been
327 // If the instruction reads the register that's spilled, (e.g. this can
328 // happen if it is a move to a physical register), then the spill
329 // instruction is not a kill.
330 bool isKill = !(I != MBB.end() && I->readsRegister(PhysReg));
331 storeVirtReg(MBB, I, VirtReg, PhysReg, isKill);
334 getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available
336 DEBUG(dbgs() << '\n');
337 removePhysReg(PhysReg);
341 /// spillPhysReg - This method spills the specified physical register into the
342 /// virtual register slot associated with it. If OnlyVirtRegs is set to true,
343 /// then the request is ignored if the physical register does not contain a
344 /// virtual register.
346 void RALocal::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
347 unsigned PhysReg, bool OnlyVirtRegs) {
348 if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used!
349 assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!");
350 if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs)
351 spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg);
355 // If the selected register aliases any other registers, we must make
356 // sure that one of the aliases isn't alive.
357 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
358 *AliasSet; ++AliasSet) {
359 if (PhysRegsUsed[*AliasSet] == -1 || // Spill aliased register.
360 PhysRegsUsed[*AliasSet] == -2) // If allocatable.
363 if (PhysRegsUsed[*AliasSet])
364 spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
369 /// assignVirtToPhysReg - This method updates local state so that we know
370 /// that PhysReg is the proper container for VirtReg now. The physical
371 /// register must not be used for anything else when this is called.
373 void RALocal::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
374 assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!");
375 // Update information to note the fact that this register was just used, and
377 PhysRegsUsed[PhysReg] = VirtReg;
378 getVirt2PhysRegMapSlot(VirtReg) = PhysReg;
379 AddToPhysRegsUseOrder(PhysReg); // New use of PhysReg
383 /// isPhysRegAvailable - Return true if the specified physical register is free
384 /// and available for use. This also includes checking to see if aliased
385 /// registers are all free...
387 bool RALocal::isPhysRegAvailable(unsigned PhysReg) const {
388 if (PhysRegsUsed[PhysReg] != -1) return false;
390 // If the selected register aliases any other allocated registers, it is
392 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
393 *AliasSet; ++AliasSet)
394 if (PhysRegsUsed[*AliasSet] >= 0) // Aliased register in use?
395 return false; // Can't use this reg then.
400 /// getFreeReg - Look to see if there is a free register available in the
401 /// specified register class. If not, return 0.
403 unsigned RALocal::getFreeReg(const TargetRegisterClass *RC) {
404 // Get iterators defining the range of registers that are valid to allocate in
405 // this class, which also specifies the preferred allocation order.
406 TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
407 TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
409 for (; RI != RE; ++RI)
410 if (isPhysRegAvailable(*RI)) { // Is reg unused?
411 assert(*RI != 0 && "Cannot use register!");
412 return *RI; // Found an unused register!
418 /// getReg - Find a physical register to hold the specified virtual
419 /// register. If all compatible physical registers are used, this method spills
420 /// the last used virtual register to the stack, and uses that register.
422 unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I,
423 unsigned VirtReg, bool NoFree) {
424 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
426 // First check to see if we have a free register of the requested type...
427 unsigned PhysReg = NoFree ? 0 : getFreeReg(RC);
430 // Assign the register.
431 assignVirtToPhysReg(VirtReg, PhysReg);
435 // If we didn't find an unused register, scavenge one now!
436 assert(!PhysRegsUseOrder.empty() && "No allocated registers??");
438 // Loop over all of the preallocated registers from the least recently used
439 // to the most recently used. When we find one that is capable of holding
440 // our register, use it.
441 for (unsigned i = 0; PhysReg == 0; ++i) {
442 assert(i != PhysRegsUseOrder.size() &&
443 "Couldn't find a register of the appropriate class!");
445 unsigned R = PhysRegsUseOrder[i];
447 // We can only use this register if it holds a virtual register (ie, it
448 // can be spilled). Do not use it if it is an explicitly allocated
449 // physical register!
450 assert(PhysRegsUsed[R] != -1 &&
451 "PhysReg in PhysRegsUseOrder, but is not allocated?");
452 if (PhysRegsUsed[R] && PhysRegsUsed[R] != -2) {
453 // If the current register is compatible, use it.
454 if (RC->contains(R)) {
459 // If one of the registers aliased to the current register is
460 // compatible, use it.
461 for (const unsigned *AliasIt = TRI->getAliasSet(R);
462 *AliasIt; ++AliasIt) {
463 if (!RC->contains(*AliasIt)) continue;
465 // If this is pinned down for some reason, don't use it. For
466 // example, if CL is pinned, and we run across CH, don't use
467 // CH as justification for using scavenging ECX (which will
469 if (PhysRegsUsed[*AliasIt] == 0) continue;
471 // Make sure the register is allocatable. Don't allocate SIL on
473 if (PhysRegsUsed[*AliasIt] == -2) continue;
475 PhysReg = *AliasIt; // Take an aliased register
481 assert(PhysReg && "Physical register not assigned!?!?");
483 // At this point PhysRegsUseOrder[i] is the least recently used register of
484 // compatible register class. Spill it to memory and reap its remains.
485 spillPhysReg(MBB, I, PhysReg);
487 // Now that we know which register we need to assign this to, do it now!
488 assignVirtToPhysReg(VirtReg, PhysReg);
493 /// reloadVirtReg - This method transforms the specified virtual
494 /// register use to refer to a physical register. This method may do this in
495 /// one of several ways: if the register is available in a physical register
496 /// already, it uses that physical register. If the value is not in a physical
497 /// register, and if there are physical registers available, it loads it into a
498 /// register: PhysReg if that is an available physical register, otherwise any
499 /// register. If register pressure is high, and it is possible, it tries to
500 /// fold the load of the virtual register into the instruction itself. It
501 /// avoids doing this if register pressure is low to improve the chance that
502 /// subsequent instructions can use the reloaded value. This method returns
503 /// the modified instruction.
505 MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
507 SmallSet<unsigned, 4> &ReloadedRegs,
509 unsigned VirtReg = MI->getOperand(OpNum).getReg();
510 unsigned SubIdx = MI->getOperand(OpNum).getSubReg();
512 // If the virtual register is already available, just update the instruction
514 if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
516 PR = TRI->getSubReg(PR, SubIdx);
517 MI->getOperand(OpNum).setSubReg(0);
519 MI->getOperand(OpNum).setReg(PR); // Assign the input register
520 if (!MI->isDebugValue()) {
521 // Do not do these for DBG_VALUE as they can affect codegen.
522 MarkPhysRegRecentlyUsed(PR); // Already have this value available!
523 getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
528 // Otherwise, we need to fold it into the current instruction, or reload it.
529 // If we have registers available to hold the value, use them.
530 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
531 // If we already have a PhysReg (this happens when the instruction is a
532 // reg-to-reg copy with a PhysReg destination) use that.
533 if (!PhysReg || !TargetRegisterInfo::isPhysicalRegister(PhysReg) ||
534 !isPhysRegAvailable(PhysReg))
535 PhysReg = getFreeReg(RC);
536 int FrameIndex = getStackSpaceFor(VirtReg, RC);
538 if (PhysReg) { // Register is available, allocate it!
539 assignVirtToPhysReg(VirtReg, PhysReg);
540 } else { // No registers available.
541 // Force some poor hapless value out of the register file to
542 // make room for the new register, and reload it.
543 PhysReg = getReg(MBB, MI, VirtReg, true);
546 markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded
548 DEBUG(dbgs() << " Reloading %reg" << VirtReg << " into "
549 << TRI->getName(PhysReg) << "\n");
551 // Add move instruction(s)
552 TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC, TRI);
553 ++NumLoads; // Update statistics
555 MF->getRegInfo().setPhysRegUsed(PhysReg);
556 // Assign the input register.
558 MI->getOperand(OpNum).setSubReg(0);
559 MI->getOperand(OpNum).setReg(TRI->getSubReg(PhysReg, SubIdx));
561 MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
562 getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
564 if (!ReloadedRegs.insert(PhysReg)) {
566 raw_string_ostream Msg(msg);
567 Msg << "Ran out of registers during register allocation!";
568 if (MI->isInlineAsm()) {
569 Msg << "\nPlease check your inline asm statement for invalid "
573 report_fatal_error(Msg.str());
575 for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
576 *SubRegs; ++SubRegs) {
577 if (ReloadedRegs.insert(*SubRegs)) continue;
580 raw_string_ostream Msg(msg);
581 Msg << "Ran out of registers during register allocation!";
582 if (MI->isInlineAsm()) {
583 Msg << "\nPlease check your inline asm statement for invalid "
587 report_fatal_error(Msg.str());
593 /// isReadModWriteImplicitKill - True if this is an implicit kill for a
594 /// read/mod/write register, i.e. update partial register.
595 static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
596 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
597 MachineOperand &MO = MI->getOperand(i);
598 if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
599 MO.isDef() && !MO.isDead())
605 /// isReadModWriteImplicitDef - True if this is an implicit def for a
606 /// read/mod/write register, i.e. update partial register.
607 static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
608 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
609 MachineOperand &MO = MI->getOperand(i);
610 if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
611 !MO.isDef() && MO.isKill())
617 // precedes - Helper function to determine with MachineInstr A
618 // precedes MachineInstr B within the same MBB.
619 static bool precedes(MachineBasicBlock::iterator A,
620 MachineBasicBlock::iterator B) {
624 MachineBasicBlock::iterator I = A->getParent()->begin();
625 while (I != A->getParent()->end()) {
637 /// ComputeLocalLiveness - Computes liveness of registers within a basic
638 /// block, setting the killed/dead flags as appropriate.
639 void RALocal::ComputeLocalLiveness(MachineBasicBlock& MBB) {
640 // Keep track of the most recently seen previous use or def of each reg,
641 // so that we can update them with dead/kill markers.
642 DenseMap<unsigned, std::pair<MachineInstr*, unsigned> > LastUseDef;
643 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
645 if (I->isDebugValue())
648 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
649 MachineOperand &MO = I->getOperand(i);
650 // Uses don't trigger any flags, but we need to save
651 // them for later. Also, we have to process these
652 // _before_ processing the defs, since an instr
653 // uses regs before it defs them.
654 if (!MO.isReg() || !MO.getReg() || !MO.isUse())
657 // Ignore helpful kill flags from earlier passes.
660 LastUseDef[MO.getReg()] = std::make_pair(I, i);
662 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) continue;
664 const unsigned *Aliases = TRI->getAliasSet(MO.getReg());
669 DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
670 alias = LastUseDef.find(*Aliases);
672 if (alias != LastUseDef.end() && alias->second.first != I)
673 LastUseDef[*Aliases] = std::make_pair(I, i);
679 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
680 MachineOperand &MO = I->getOperand(i);
681 // Defs others than 2-addr redefs _do_ trigger flag changes:
682 // - A def followed by a def is dead
683 // - A use followed by a def is a kill
684 if (!MO.isReg() || !MO.getReg() || !MO.isDef()) continue;
686 unsigned SubIdx = MO.getSubReg();
687 DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
688 last = LastUseDef.find(MO.getReg());
689 if (last != LastUseDef.end()) {
690 // Check if this is a two address instruction. If so, then
691 // the def does not kill the use.
692 if (last->second.first == I && I->isRegTiedToUseOperand(i))
695 MachineOperand &lastUD =
696 last->second.first->getOperand(last->second.second);
697 if (SubIdx && lastUD.getSubReg() != SubIdx)
698 // Partial re-def, the last def is not dead.
702 // %reg1024:5<def> = op %reg1024, 5
706 lastUD.setIsDead(true);
708 lastUD.setIsKill(true);
711 LastUseDef[MO.getReg()] = std::make_pair(I, i);
715 // Live-out (of the function) registers contain return values of the function,
716 // so we need to make sure they are alive at return time.
717 MachineBasicBlock::iterator Ret = MBB.getFirstTerminator();
718 bool BBEndsInReturn = (Ret != MBB.end() && Ret->getDesc().isReturn());
721 for (MachineRegisterInfo::liveout_iterator
722 I = MF->getRegInfo().liveout_begin(),
723 E = MF->getRegInfo().liveout_end(); I != E; ++I)
724 if (!Ret->readsRegister(*I)) {
725 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
726 LastUseDef[*I] = std::make_pair(Ret, Ret->getNumOperands()-1);
729 // Finally, loop over the final use/def of each reg
730 // in the block and determine if it is dead.
731 for (DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
732 I = LastUseDef.begin(), E = LastUseDef.end(); I != E; ++I) {
733 MachineInstr *MI = I->second.first;
734 unsigned idx = I->second.second;
735 MachineOperand &MO = MI->getOperand(idx);
737 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(MO.getReg());
739 // A crude approximation of "live-out" calculation
740 bool usedOutsideBlock = isPhysReg ? false :
741 UsedInMultipleBlocks.test(MO.getReg() -
742 TargetRegisterInfo::FirstVirtualRegister);
744 // If the machine BB ends in a return instruction, then the value isn't used
745 // outside of the BB.
746 if (!isPhysReg && (!usedOutsideBlock || BBEndsInReturn)) {
747 // DBG_VALUE complicates this: if the only refs of a register outside
748 // this block are DBG_VALUE, we can't keep the reg live just for that,
749 // as it will cause the reg to be spilled at the end of this block when
750 // it wouldn't have been otherwise. Nullify the DBG_VALUEs when that
752 bool UsedByDebugValueOnly = false;
753 for (MachineRegisterInfo::reg_iterator UI = MRI->reg_begin(MO.getReg()),
754 UE = MRI->reg_end(); UI != UE; ++UI) {
756 // - used in another block
757 // - used in the same block before it is defined (loop)
758 if (UI->getParent() == &MBB &&
759 !(MO.isDef() && UI.getOperand().isUse() && precedes(&*UI, MI)))
762 if (UI->isDebugValue()) {
763 UsedByDebugValueOnly = true;
767 // A non-DBG_VALUE use means we can leave DBG_VALUE uses alone.
768 UsedInMultipleBlocks.set(MO.getReg() -
769 TargetRegisterInfo::FirstVirtualRegister);
770 usedOutsideBlock = true;
771 UsedByDebugValueOnly = false;
775 if (UsedByDebugValueOnly)
776 for (MachineRegisterInfo::reg_iterator UI = MRI->reg_begin(MO.getReg()),
777 UE = MRI->reg_end(); UI != UE; ++UI)
778 if (UI->isDebugValue() &&
779 (UI->getParent() != &MBB ||
780 (MO.isDef() && precedes(&*UI, MI))))
781 UI.getOperand().setReg(0U);
784 // Physical registers and those that are not live-out of the block are
785 // killed/dead at their last use/def within this block.
786 if (isPhysReg || !usedOutsideBlock || BBEndsInReturn) {
788 // Don't mark uses that are tied to defs as kills.
789 if (!MI->isRegTiedToDefOperand(idx))
798 void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
799 // loop over each instruction
800 MachineBasicBlock::iterator MII = MBB.begin();
803 const BasicBlock *LBB = MBB.getBasicBlock();
805 dbgs() << "\nStarting RegAlloc of BB: " << LBB->getName();
808 // Add live-in registers as active.
809 for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(),
810 E = MBB.livein_end(); I != E; ++I) {
812 MF->getRegInfo().setPhysRegUsed(Reg);
813 PhysRegsUsed[Reg] = 0; // It is free and reserved now
814 AddToPhysRegsUseOrder(Reg);
815 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
816 *SubRegs; ++SubRegs) {
817 if (PhysRegsUsed[*SubRegs] == -2) continue;
819 AddToPhysRegsUseOrder(*SubRegs);
820 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
821 MF->getRegInfo().setPhysRegUsed(*SubRegs);
825 ComputeLocalLiveness(MBB);
827 // Otherwise, sequentially allocate each instruction in the MBB.
828 while (MII != MBB.end()) {
829 MachineInstr *MI = MII++;
830 const TargetInstrDesc &TID = MI->getDesc();
832 dbgs() << "\nStarting RegAlloc of: " << *MI;
833 dbgs() << " Regs have values: ";
834 for (unsigned i = 0; i != TRI->getNumRegs(); ++i)
835 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) {
836 if (PhysRegsUsed[i] && isVirtRegModified(PhysRegsUsed[i]))
838 dbgs() << "[" << TRI->getName(i)
839 << ",%reg" << PhysRegsUsed[i] << "] ";
844 // Determine whether this is a copy instruction. The cases where the
845 // source or destination are phys regs are handled specially.
846 unsigned SrcCopyReg, DstCopyReg, SrcCopySubReg, DstCopySubReg;
847 unsigned SrcCopyPhysReg = 0U;
848 bool isCopy = TII->isMoveInstr(*MI, SrcCopyReg, DstCopyReg,
849 SrcCopySubReg, DstCopySubReg);
850 if (isCopy && TargetRegisterInfo::isVirtualRegister(SrcCopyReg))
851 SrcCopyPhysReg = getVirt2PhysRegMapSlot(SrcCopyReg);
853 // Loop over the implicit uses, making sure that they are at the head of the
854 // use order list, so they don't get reallocated.
855 if (TID.ImplicitUses) {
856 for (const unsigned *ImplicitUses = TID.ImplicitUses;
857 *ImplicitUses; ++ImplicitUses)
858 MarkPhysRegRecentlyUsed(*ImplicitUses);
861 SmallVector<unsigned, 8> Kills;
862 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
863 MachineOperand &MO = MI->getOperand(i);
864 if (!MO.isReg() || !MO.isKill()) continue;
866 if (!MO.isImplicit())
867 Kills.push_back(MO.getReg());
868 else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
869 // These are extra physical register kills when a sub-register
870 // is defined (def of a sub-register is a read/mod/write of the
871 // larger registers). Ignore.
872 Kills.push_back(MO.getReg());
875 // If any physical regs are earlyclobber, spill any value they might
876 // have in them, then mark them unallocatable.
877 // If any virtual regs are earlyclobber, allocate them now (before
878 // freeing inputs that are killed).
879 if (MI->isInlineAsm()) {
880 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
881 MachineOperand &MO = MI->getOperand(i);
882 if (!MO.isReg() || !MO.isDef() || !MO.isEarlyClobber() ||
886 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
887 unsigned DestVirtReg = MO.getReg();
888 unsigned DestPhysReg;
890 // If DestVirtReg already has a value, use it.
891 if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
892 DestPhysReg = getReg(MBB, MI, DestVirtReg);
893 MF->getRegInfo().setPhysRegUsed(DestPhysReg);
894 markVirtRegModified(DestVirtReg);
895 getVirtRegLastUse(DestVirtReg) =
896 std::make_pair((MachineInstr*)0, 0);
897 DEBUG(dbgs() << " Assigning " << TRI->getName(DestPhysReg)
898 << " to %reg" << DestVirtReg << "\n");
899 if (unsigned DestSubIdx = MO.getSubReg()) {
901 DestPhysReg = TRI->getSubReg(DestPhysReg, DestSubIdx);
903 MO.setReg(DestPhysReg); // Assign the earlyclobber register
905 unsigned Reg = MO.getReg();
906 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
907 // These are extra physical register defs when a sub-register
908 // is defined (def of a sub-register is a read/mod/write of the
909 // larger registers). Ignore.
910 if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
912 MF->getRegInfo().setPhysRegUsed(Reg);
913 spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
914 PhysRegsUsed[Reg] = 0; // It is free and reserved now
915 AddToPhysRegsUseOrder(Reg);
917 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
918 *SubRegs; ++SubRegs) {
919 if (PhysRegsUsed[*SubRegs] == -2) continue;
920 MF->getRegInfo().setPhysRegUsed(*SubRegs);
921 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
922 AddToPhysRegsUseOrder(*SubRegs);
928 // If a DBG_VALUE says something is located in a spilled register,
929 // change the DBG_VALUE to be undef, which prevents the register
930 // from being reloaded here. Doing that would change the generated
931 // code, unless another use immediately follows this instruction.
932 if (MI->isDebugValue() &&
933 MI->getNumOperands()==3 && MI->getOperand(0).isReg()) {
934 unsigned VirtReg = MI->getOperand(0).getReg();
935 if (VirtReg && TargetRegisterInfo::isVirtualRegister(VirtReg) &&
936 !getVirt2PhysRegMapSlot(VirtReg))
937 MI->getOperand(0).setReg(0U);
940 // Get the used operands into registers. This has the potential to spill
941 // incoming values if we are out of registers. Note that we completely
942 // ignore physical register uses here. We assume that if an explicit
943 // physical register is referenced by the instruction, that it is guaranteed
944 // to be live-in, or the input is badly hosed.
946 SmallSet<unsigned, 4> ReloadedRegs;
947 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
948 MachineOperand &MO = MI->getOperand(i);
949 // here we are looking for only used operands (never def&use)
950 if (MO.isReg() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
951 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
952 MI = reloadVirtReg(MBB, MI, i, ReloadedRegs,
953 isCopy ? DstCopyReg : 0);
956 // If this instruction is the last user of this register, kill the
957 // value, freeing the register being used, so it doesn't need to be
958 // spilled to memory.
960 for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
961 unsigned VirtReg = Kills[i];
962 unsigned PhysReg = VirtReg;
963 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
964 // If the virtual register was never materialized into a register, it
965 // might not be in the map, but it won't hurt to zero it out anyway.
966 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
967 PhysReg = PhysRegSlot;
969 } else if (PhysRegsUsed[PhysReg] == -2) {
970 // Unallocatable register dead, ignore.
973 assert((!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1) &&
974 "Silently clearing a virtual register?");
977 if (!PhysReg) continue;
979 DEBUG(dbgs() << " Last use of " << TRI->getName(PhysReg)
980 << "[%reg" << VirtReg <<"], removing it from live set\n");
981 removePhysReg(PhysReg);
982 for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
983 *SubRegs; ++SubRegs) {
984 if (PhysRegsUsed[*SubRegs] != -2) {
985 DEBUG(dbgs() << " Last use of "
986 << TRI->getName(*SubRegs) << "[%reg" << VirtReg
987 <<"], removing it from live set\n");
988 removePhysReg(*SubRegs);
993 // Loop over all of the operands of the instruction, spilling registers that
994 // are defined, and marking explicit destinations in the PhysRegsUsed map.
995 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
996 MachineOperand &MO = MI->getOperand(i);
997 if (!MO.isReg() || !MO.isDef() || MO.isImplicit() || !MO.getReg() ||
998 MO.isEarlyClobber() ||
999 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1002 unsigned Reg = MO.getReg();
1003 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
1004 // These are extra physical register defs when a sub-register
1005 // is defined (def of a sub-register is a read/mod/write of the
1006 // larger registers). Ignore.
1007 if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
1009 MF->getRegInfo().setPhysRegUsed(Reg);
1010 spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
1011 PhysRegsUsed[Reg] = 0; // It is free and reserved now
1012 AddToPhysRegsUseOrder(Reg);
1014 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
1015 *SubRegs; ++SubRegs) {
1016 if (PhysRegsUsed[*SubRegs] == -2) continue;
1018 MF->getRegInfo().setPhysRegUsed(*SubRegs);
1019 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
1020 AddToPhysRegsUseOrder(*SubRegs);
1024 // Loop over the implicit defs, spilling them as well.
1025 if (TID.ImplicitDefs) {
1026 for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
1027 *ImplicitDefs; ++ImplicitDefs) {
1028 unsigned Reg = *ImplicitDefs;
1029 if (PhysRegsUsed[Reg] != -2) {
1030 spillPhysReg(MBB, MI, Reg, true);
1031 AddToPhysRegsUseOrder(Reg);
1032 PhysRegsUsed[Reg] = 0; // It is free and reserved now
1034 MF->getRegInfo().setPhysRegUsed(Reg);
1035 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
1036 *SubRegs; ++SubRegs) {
1037 if (PhysRegsUsed[*SubRegs] == -2) continue;
1039 AddToPhysRegsUseOrder(*SubRegs);
1040 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
1041 MF->getRegInfo().setPhysRegUsed(*SubRegs);
1046 SmallVector<unsigned, 8> DeadDefs;
1047 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1048 MachineOperand &MO = MI->getOperand(i);
1049 if (MO.isReg() && MO.isDead())
1050 DeadDefs.push_back(MO.getReg());
1053 // Okay, we have allocated all of the source operands and spilled any values
1054 // that would be destroyed by defs of this instruction. Loop over the
1055 // explicit defs and assign them to a register, spilling incoming values if
1056 // we need to scavenge a register.
1058 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1059 MachineOperand &MO = MI->getOperand(i);
1060 if (!MO.isReg() || !MO.isDef() || !MO.getReg() ||
1061 MO.isEarlyClobber() ||
1062 !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1065 unsigned DestVirtReg = MO.getReg();
1066 unsigned DestPhysReg;
1068 // If DestVirtReg already has a value, use it.
1069 if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg))) {
1070 // If this is a copy try to reuse the input as the output;
1071 // that will make the copy go away.
1072 // If this is a copy, the source reg is a phys reg, and
1073 // that reg is available, use that phys reg for DestPhysReg.
1074 // If this is a copy, the source reg is a virtual reg, and
1075 // the phys reg that was assigned to that virtual reg is now
1076 // available, use that phys reg for DestPhysReg. (If it's now
1077 // available that means this was the last use of the source.)
1079 TargetRegisterInfo::isPhysicalRegister(SrcCopyReg) &&
1080 isPhysRegAvailable(SrcCopyReg)) {
1081 DestPhysReg = SrcCopyReg;
1082 assignVirtToPhysReg(DestVirtReg, DestPhysReg);
1083 } else if (isCopy &&
1084 TargetRegisterInfo::isVirtualRegister(SrcCopyReg) &&
1085 SrcCopyPhysReg && isPhysRegAvailable(SrcCopyPhysReg) &&
1086 MF->getRegInfo().getRegClass(DestVirtReg)->
1087 contains(SrcCopyPhysReg)) {
1088 DestPhysReg = SrcCopyPhysReg;
1089 assignVirtToPhysReg(DestVirtReg, DestPhysReg);
1091 DestPhysReg = getReg(MBB, MI, DestVirtReg);
1093 MF->getRegInfo().setPhysRegUsed(DestPhysReg);
1094 markVirtRegModified(DestVirtReg);
1095 getVirtRegLastUse(DestVirtReg) = std::make_pair((MachineInstr*)0, 0);
1096 DEBUG(dbgs() << " Assigning " << TRI->getName(DestPhysReg)
1097 << " to %reg" << DestVirtReg << "\n");
1099 if (unsigned DestSubIdx = MO.getSubReg()) {
1101 DestPhysReg = TRI->getSubReg(DestPhysReg, DestSubIdx);
1103 MO.setReg(DestPhysReg); // Assign the output register
1106 // If this instruction defines any registers that are immediately dead,
1109 for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) {
1110 unsigned VirtReg = DeadDefs[i];
1111 unsigned PhysReg = VirtReg;
1112 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
1113 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
1114 PhysReg = PhysRegSlot;
1115 assert(PhysReg != 0);
1117 } else if (PhysRegsUsed[PhysReg] == -2) {
1118 // Unallocatable register dead, ignore.
1120 } else if (!PhysReg)
1123 DEBUG(dbgs() << " Register " << TRI->getName(PhysReg)
1124 << " [%reg" << VirtReg
1125 << "] is never used, removing it from live set\n");
1126 removePhysReg(PhysReg);
1127 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
1128 *AliasSet; ++AliasSet) {
1129 if (PhysRegsUsed[*AliasSet] != -2) {
1130 DEBUG(dbgs() << " Register " << TRI->getName(*AliasSet)
1131 << " [%reg" << *AliasSet
1132 << "] is never used, removing it from live set\n");
1133 removePhysReg(*AliasSet);
1138 // If this instruction is a call, make sure there are no dirty registers. The
1139 // call might throw an exception, and the landing pad expects to find all
1140 // registers in stack slots.
1142 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
1143 if (PhysRegsUsed[i] <= 0) continue;
1144 unsigned VirtReg = PhysRegsUsed[i];
1145 if (!isVirtRegModified(VirtReg)) continue;
1146 DEBUG(dbgs() << " Storing dirty %reg" << VirtReg);
1147 storeVirtReg(MBB, MI, VirtReg, i, false);
1148 markVirtRegModified(VirtReg, false);
1149 DEBUG(dbgs() << " because the call might throw\n");
1152 // Finally, if this is a noop copy instruction, zap it. (Except that if
1153 // the copy is dead, it must be kept to avoid messing up liveness info for
1154 // the register scavenger. See pr4100.)
1155 if (TII->isMoveInstr(*MI, SrcCopyReg, DstCopyReg,
1156 SrcCopySubReg, DstCopySubReg) &&
1157 SrcCopyReg == DstCopyReg && DeadDefs.empty())
1161 MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
1163 // Spill all physical registers holding virtual registers now.
1164 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
1165 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) {
1166 if (unsigned VirtReg = PhysRegsUsed[i])
1167 spillVirtReg(MBB, MI, VirtReg, i);
1173 // This checking code is very expensive.
1175 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
1176 e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
1177 if (unsigned PR = Virt2PhysRegMap[i]) {
1178 cerr << "Register still mapped: " << i << " -> " << PR << "\n";
1181 assert(AllOk && "Virtual registers still in phys regs?");
1184 // Clear any physical register which appear live at the end of the basic
1185 // block, but which do not hold any virtual registers. e.g., the stack
1187 PhysRegsUseOrder.clear();
1190 /// runOnMachineFunction - Register allocate the whole function
1192 bool RALocal::runOnMachineFunction(MachineFunction &Fn) {
1193 DEBUG(dbgs() << "Machine Function\n");
1195 MRI = &Fn.getRegInfo();
1196 TM = &Fn.getTarget();
1197 TRI = TM->getRegisterInfo();
1198 TII = TM->getInstrInfo();
1200 PhysRegsUsed.assign(TRI->getNumRegs(), -1);
1202 // At various places we want to efficiently check to see whether a register
1203 // is allocatable. To handle this, we mark all unallocatable registers as
1204 // being pinned down, permanently.
1206 BitVector Allocable = TRI->getAllocatableSet(Fn);
1207 for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
1209 PhysRegsUsed[i] = -2; // Mark the reg unallocable.
1212 // initialize the virtual->physical register map to have a 'null'
1213 // mapping for all virtual registers
1214 unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg();
1215 StackSlotForVirtReg.grow(LastVirtReg);
1216 Virt2PhysRegMap.grow(LastVirtReg);
1217 Virt2LastUseMap.grow(LastVirtReg);
1218 VirtRegModified.resize(LastVirtReg+1 -
1219 TargetRegisterInfo::FirstVirtualRegister);
1220 UsedInMultipleBlocks.resize(LastVirtReg+1 -
1221 TargetRegisterInfo::FirstVirtualRegister);
1223 // Loop over all of the basic blocks, eliminating virtual register references
1224 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
1226 AllocateBasicBlock(*MBB);
1228 StackSlotForVirtReg.clear();
1229 PhysRegsUsed.clear();
1230 VirtRegModified.clear();
1231 UsedInMultipleBlocks.clear();
1232 Virt2PhysRegMap.clear();
1233 Virt2LastUseMap.clear();
1237 FunctionPass *llvm::createLocalRegisterAllocator() {
1238 return new RALocal();