1 //===-- RegAllocLocal.cpp - A BasicBlock generic register allocator -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This register allocator allocates registers to a basic block at a time,
11 // attempting to keep values in registers and reusing registers as appropriate.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "llvm/BasicBlock.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/RegAllocRegistry.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/IndexedMap.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
38 STATISTIC(NumStores, "Number of stores added");
39 STATISTIC(NumLoads , "Number of loads added");
41 static RegisterRegAlloc
42 localRegAlloc("local", "local register allocator",
43 createLocalRegisterAllocator);
46 class RALocal : public MachineFunctionPass {
49 RALocal() : MachineFunctionPass(&ID), StackSlotForVirtReg(-1) {}
51 const TargetMachine *TM;
53 const TargetRegisterInfo *TRI;
54 const TargetInstrInfo *TII;
56 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
57 // values are spilled.
58 IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
60 // Virt2PhysRegMap - This map contains entries for each virtual register
61 // that is currently available in a physical register.
62 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysRegMap;
64 unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) {
65 return Virt2PhysRegMap[VirtReg];
68 // PhysRegsUsed - This array is effectively a map, containing entries for
69 // each physical register that currently has a value (ie, it is in
70 // Virt2PhysRegMap). The value mapped to is the virtual register
71 // corresponding to the physical register (the inverse of the
72 // Virt2PhysRegMap), or 0. The value is set to 0 if this register is pinned
73 // because it is used by a future instruction, and to -2 if it is not
74 // allocatable. If the entry for a physical register is -1, then the
75 // physical register is "not in the map".
77 std::vector<int> PhysRegsUsed;
79 // PhysRegsUseOrder - This contains a list of the physical registers that
80 // currently have a virtual register value in them. This list provides an
81 // ordering of registers, imposing a reallocation order. This list is only
82 // used if all registers are allocated and we have to spill one, in which
83 // case we spill the least recently used register. Entries at the front of
84 // the list are the least recently used registers, entries at the back are
85 // the most recently used.
87 std::vector<unsigned> PhysRegsUseOrder;
89 // Virt2LastUseMap - This maps each virtual register to its last use
90 // (MachineInstr*, operand index pair).
91 IndexedMap<std::pair<MachineInstr*, unsigned>, VirtReg2IndexFunctor>
94 std::pair<MachineInstr*,unsigned>& getVirtRegLastUse(unsigned Reg) {
95 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
96 return Virt2LastUseMap[Reg];
99 // VirtRegModified - This bitset contains information about which virtual
100 // registers need to be spilled back to memory when their registers are
101 // scavenged. If a virtual register has simply been rematerialized, there
102 // is no reason to spill it to memory when we need the register back.
104 BitVector VirtRegModified;
106 // UsedInMultipleBlocks - Tracks whether a particular register is used in
107 // more than one block.
108 BitVector UsedInMultipleBlocks;
110 void markVirtRegModified(unsigned Reg, bool Val = true) {
111 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
112 Reg -= TargetRegisterInfo::FirstVirtualRegister;
114 VirtRegModified.set(Reg);
116 VirtRegModified.reset(Reg);
119 bool isVirtRegModified(unsigned Reg) const {
120 assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
121 assert(Reg - TargetRegisterInfo::FirstVirtualRegister < VirtRegModified.size()
122 && "Illegal virtual register!");
123 return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister];
126 void AddToPhysRegsUseOrder(unsigned Reg) {
127 std::vector<unsigned>::iterator It =
128 std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), Reg);
129 if (It != PhysRegsUseOrder.end())
130 PhysRegsUseOrder.erase(It);
131 PhysRegsUseOrder.push_back(Reg);
134 void MarkPhysRegRecentlyUsed(unsigned Reg) {
135 if (PhysRegsUseOrder.empty() ||
136 PhysRegsUseOrder.back() == Reg) return; // Already most recently used
138 for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i)
139 if (areRegsEqual(Reg, PhysRegsUseOrder[i-1])) {
140 unsigned RegMatch = PhysRegsUseOrder[i-1]; // remove from middle
141 PhysRegsUseOrder.erase(PhysRegsUseOrder.begin()+i-1);
142 // Add it to the end of the list
143 PhysRegsUseOrder.push_back(RegMatch);
145 return; // Found an exact match, exit early
150 virtual const char *getPassName() const {
151 return "Local Register Allocator";
154 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
155 AU.setPreservesCFG();
156 AU.addRequiredID(PHIEliminationID);
157 AU.addRequiredID(TwoAddressInstructionPassID);
158 MachineFunctionPass::getAnalysisUsage(AU);
162 /// runOnMachineFunction - Register allocate the whole function
163 bool runOnMachineFunction(MachineFunction &Fn);
165 /// AllocateBasicBlock - Register allocate the specified basic block.
166 void AllocateBasicBlock(MachineBasicBlock &MBB);
169 /// areRegsEqual - This method returns true if the specified registers are
170 /// related to each other. To do this, it checks to see if they are equal
171 /// or if the first register is in the alias set of the second register.
173 bool areRegsEqual(unsigned R1, unsigned R2) const {
174 if (R1 == R2) return true;
175 for (const unsigned *AliasSet = TRI->getAliasSet(R2);
176 *AliasSet; ++AliasSet) {
177 if (*AliasSet == R1) return true;
182 /// getStackSpaceFor - This returns the frame index of the specified virtual
183 /// register on the stack, allocating space if necessary.
184 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
186 /// removePhysReg - This method marks the specified physical register as no
187 /// longer being in use.
189 void removePhysReg(unsigned PhysReg);
191 /// spillVirtReg - This method spills the value specified by PhysReg into
192 /// the virtual register slot specified by VirtReg. It then updates the RA
193 /// data structures to indicate the fact that PhysReg is now available.
195 void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
196 unsigned VirtReg, unsigned PhysReg);
198 /// spillPhysReg - This method spills the specified physical register into
199 /// the virtual register slot associated with it. If OnlyVirtRegs is set to
200 /// true, then the request is ignored if the physical register does not
201 /// contain a virtual register.
203 void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
204 unsigned PhysReg, bool OnlyVirtRegs = false);
206 /// assignVirtToPhysReg - This method updates local state so that we know
207 /// that PhysReg is the proper container for VirtReg now. The physical
208 /// register must not be used for anything else when this is called.
210 void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg);
212 /// isPhysRegAvailable - Return true if the specified physical register is
213 /// free and available for use. This also includes checking to see if
214 /// aliased registers are all free...
216 bool isPhysRegAvailable(unsigned PhysReg) const;
218 /// getFreeReg - Look to see if there is a free register available in the
219 /// specified register class. If not, return 0.
221 unsigned getFreeReg(const TargetRegisterClass *RC);
223 /// getReg - Find a physical register to hold the specified virtual
224 /// register. If all compatible physical registers are used, this method
225 /// spills the last used virtual register to the stack, and uses that
226 /// register. If NoFree is true, that means the caller knows there isn't
227 /// a free register, do not call getFreeReg().
228 unsigned getReg(MachineBasicBlock &MBB, MachineInstr *MI,
229 unsigned VirtReg, bool NoFree = false);
231 /// reloadVirtReg - This method transforms the specified virtual
232 /// register use to refer to a physical register. This method may do this
233 /// in one of several ways: if the register is available in a physical
234 /// register already, it uses that physical register. If the value is not
235 /// in a physical register, and if there are physical registers available,
236 /// it loads it into a register: PhysReg if that is an available physical
237 /// register, otherwise any physical register of the right class.
238 /// If register pressure is high, and it is possible, it tries to fold the
239 /// load of the virtual register into the instruction itself. It avoids
240 /// doing this if register pressure is low to improve the chance that
241 /// subsequent instructions can use the reloaded value. This method
242 /// returns the modified instruction.
244 MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
245 unsigned OpNum, SmallSet<unsigned, 4> &RRegs,
248 /// ComputeLocalLiveness - Computes liveness of registers within a basic
249 /// block, setting the killed/dead flags as appropriate.
250 void ComputeLocalLiveness(MachineBasicBlock& MBB);
252 void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
255 char RALocal::ID = 0;
258 /// getStackSpaceFor - This allocates space for the specified virtual register
259 /// to be held on the stack.
260 int RALocal::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
261 // Find the location Reg would belong...
262 int SS = StackSlotForVirtReg[VirtReg];
264 return SS; // Already has space allocated?
266 // Allocate a new stack object for this spill location...
267 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
270 // Assign the slot...
271 StackSlotForVirtReg[VirtReg] = FrameIdx;
276 /// removePhysReg - This method marks the specified physical register as no
277 /// longer being in use.
279 void RALocal::removePhysReg(unsigned PhysReg) {
280 PhysRegsUsed[PhysReg] = -1; // PhyReg no longer used
282 std::vector<unsigned>::iterator It =
283 std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), PhysReg);
284 if (It != PhysRegsUseOrder.end())
285 PhysRegsUseOrder.erase(It);
289 /// spillVirtReg - This method spills the value specified by PhysReg into the
290 /// virtual register slot specified by VirtReg. It then updates the RA data
291 /// structures to indicate the fact that PhysReg is now available.
293 void RALocal::spillVirtReg(MachineBasicBlock &MBB,
294 MachineBasicBlock::iterator I,
295 unsigned VirtReg, unsigned PhysReg) {
296 assert(VirtReg && "Spilling a physical register is illegal!"
297 " Must not have appropriate kill for the register or use exists beyond"
298 " the intended one.");
299 DEBUG(dbgs() << " Spilling register " << TRI->getName(PhysReg)
300 << " containing %reg" << VirtReg);
302 if (!isVirtRegModified(VirtReg)) {
303 DEBUG(dbgs() << " which has not been modified, so no store necessary!");
304 std::pair<MachineInstr*, unsigned> &LastUse = getVirtRegLastUse(VirtReg);
306 LastUse.first->getOperand(LastUse.second).setIsKill();
308 // Otherwise, there is a virtual register corresponding to this physical
309 // register. We only need to spill it into its stack slot if it has been
311 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
312 int FrameIndex = getStackSpaceFor(VirtReg, RC);
313 DEBUG(dbgs() << " to stack slot #" << FrameIndex);
314 // If the instruction reads the register that's spilled, (e.g. this can
315 // happen if it is a move to a physical register), then the spill
316 // instruction is not a kill.
317 bool isKill = !(I != MBB.end() && I->readsRegister(PhysReg));
318 TII->storeRegToStackSlot(MBB, I, PhysReg, isKill, FrameIndex, RC);
319 ++NumStores; // Update statistics
322 getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available
324 DEBUG(dbgs() << '\n');
325 removePhysReg(PhysReg);
329 /// spillPhysReg - This method spills the specified physical register into the
330 /// virtual register slot associated with it. If OnlyVirtRegs is set to true,
331 /// then the request is ignored if the physical register does not contain a
332 /// virtual register.
334 void RALocal::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
335 unsigned PhysReg, bool OnlyVirtRegs) {
336 if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used!
337 assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!");
338 if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs)
339 spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg);
341 // If the selected register aliases any other registers, we must make
342 // sure that one of the aliases isn't alive.
343 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
344 *AliasSet; ++AliasSet)
345 if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register.
346 PhysRegsUsed[*AliasSet] != -2) // If allocatable.
347 if (PhysRegsUsed[*AliasSet])
348 spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet);
353 /// assignVirtToPhysReg - This method updates local state so that we know
354 /// that PhysReg is the proper container for VirtReg now. The physical
355 /// register must not be used for anything else when this is called.
357 void RALocal::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
358 assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!");
359 // Update information to note the fact that this register was just used, and
361 PhysRegsUsed[PhysReg] = VirtReg;
362 getVirt2PhysRegMapSlot(VirtReg) = PhysReg;
363 AddToPhysRegsUseOrder(PhysReg); // New use of PhysReg
367 /// isPhysRegAvailable - Return true if the specified physical register is free
368 /// and available for use. This also includes checking to see if aliased
369 /// registers are all free...
371 bool RALocal::isPhysRegAvailable(unsigned PhysReg) const {
372 if (PhysRegsUsed[PhysReg] != -1) return false;
374 // If the selected register aliases any other allocated registers, it is
376 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
377 *AliasSet; ++AliasSet)
378 if (PhysRegsUsed[*AliasSet] >= 0) // Aliased register in use?
379 return false; // Can't use this reg then.
384 /// getFreeReg - Look to see if there is a free register available in the
385 /// specified register class. If not, return 0.
387 unsigned RALocal::getFreeReg(const TargetRegisterClass *RC) {
388 // Get iterators defining the range of registers that are valid to allocate in
389 // this class, which also specifies the preferred allocation order.
390 TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
391 TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
393 for (; RI != RE; ++RI)
394 if (isPhysRegAvailable(*RI)) { // Is reg unused?
395 assert(*RI != 0 && "Cannot use register!");
396 return *RI; // Found an unused register!
402 /// getReg - Find a physical register to hold the specified virtual
403 /// register. If all compatible physical registers are used, this method spills
404 /// the last used virtual register to the stack, and uses that register.
406 unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I,
407 unsigned VirtReg, bool NoFree) {
408 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
410 // First check to see if we have a free register of the requested type...
411 unsigned PhysReg = NoFree ? 0 : getFreeReg(RC);
413 // If we didn't find an unused register, scavenge one now!
415 assert(!PhysRegsUseOrder.empty() && "No allocated registers??");
417 // Loop over all of the preallocated registers from the least recently used
418 // to the most recently used. When we find one that is capable of holding
419 // our register, use it.
420 for (unsigned i = 0; PhysReg == 0; ++i) {
421 assert(i != PhysRegsUseOrder.size() &&
422 "Couldn't find a register of the appropriate class!");
424 unsigned R = PhysRegsUseOrder[i];
426 // We can only use this register if it holds a virtual register (ie, it
427 // can be spilled). Do not use it if it is an explicitly allocated
428 // physical register!
429 assert(PhysRegsUsed[R] != -1 &&
430 "PhysReg in PhysRegsUseOrder, but is not allocated?");
431 if (PhysRegsUsed[R] && PhysRegsUsed[R] != -2) {
432 // If the current register is compatible, use it.
433 if (RC->contains(R)) {
437 // If one of the registers aliased to the current register is
438 // compatible, use it.
439 for (const unsigned *AliasIt = TRI->getAliasSet(R);
440 *AliasIt; ++AliasIt) {
441 if (RC->contains(*AliasIt) &&
442 // If this is pinned down for some reason, don't use it. For
443 // example, if CL is pinned, and we run across CH, don't use
444 // CH as justification for using scavenging ECX (which will
446 PhysRegsUsed[*AliasIt] != 0 &&
448 // Make sure the register is allocatable. Don't allocate SIL on
450 PhysRegsUsed[*AliasIt] != -2) {
451 PhysReg = *AliasIt; // Take an aliased register
459 assert(PhysReg && "Physical register not assigned!?!?");
461 // At this point PhysRegsUseOrder[i] is the least recently used register of
462 // compatible register class. Spill it to memory and reap its remains.
463 spillPhysReg(MBB, I, PhysReg);
466 // Now that we know which register we need to assign this to, do it now!
467 assignVirtToPhysReg(VirtReg, PhysReg);
472 /// reloadVirtReg - This method transforms the specified virtual
473 /// register use to refer to a physical register. This method may do this in
474 /// one of several ways: if the register is available in a physical register
475 /// already, it uses that physical register. If the value is not in a physical
476 /// register, and if there are physical registers available, it loads it into a
477 /// register: PhysReg if that is an available physical register, otherwise any
478 /// register. If register pressure is high, and it is possible, it tries to
479 /// fold the load of the virtual register into the instruction itself. It
480 /// avoids doing this if register pressure is low to improve the chance that
481 /// subsequent instructions can use the reloaded value. This method returns
482 /// the modified instruction.
484 MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
486 SmallSet<unsigned, 4> &ReloadedRegs,
488 unsigned VirtReg = MI->getOperand(OpNum).getReg();
490 // If the virtual register is already available, just update the instruction
492 if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
493 MI->getOperand(OpNum).setReg(PR); // Assign the input register
494 if (!MI->isDebugValue()) {
495 // Do not do these for DBG_VALUE as they can affect codegen.
496 MarkPhysRegRecentlyUsed(PR); // Already have this value available!
497 getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
502 // Otherwise, we need to fold it into the current instruction, or reload it.
503 // If we have registers available to hold the value, use them.
504 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
505 // If we already have a PhysReg (this happens when the instruction is a
506 // reg-to-reg copy with a PhysReg destination) use that.
507 if (!PhysReg || !TargetRegisterInfo::isPhysicalRegister(PhysReg) ||
508 !isPhysRegAvailable(PhysReg))
509 PhysReg = getFreeReg(RC);
510 int FrameIndex = getStackSpaceFor(VirtReg, RC);
512 if (PhysReg) { // Register is available, allocate it!
513 assignVirtToPhysReg(VirtReg, PhysReg);
514 } else { // No registers available.
515 // Force some poor hapless value out of the register file to
516 // make room for the new register, and reload it.
517 PhysReg = getReg(MBB, MI, VirtReg, true);
520 markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded
522 DEBUG(dbgs() << " Reloading %reg" << VirtReg << " into "
523 << TRI->getName(PhysReg) << "\n");
525 // Add move instruction(s)
526 TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
527 ++NumLoads; // Update statistics
529 MF->getRegInfo().setPhysRegUsed(PhysReg);
530 MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
531 getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum);
533 if (!ReloadedRegs.insert(PhysReg)) {
535 raw_string_ostream Msg(msg);
536 Msg << "Ran out of registers during register allocation!";
537 if (MI->isInlineAsm()) {
538 Msg << "\nPlease check your inline asm statement for invalid "
542 llvm_report_error(Msg.str());
544 for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
545 *SubRegs; ++SubRegs) {
546 if (!ReloadedRegs.insert(*SubRegs)) {
548 raw_string_ostream Msg(msg);
549 Msg << "Ran out of registers during register allocation!";
550 if (MI->isInlineAsm()) {
551 Msg << "\nPlease check your inline asm statement for invalid "
555 llvm_report_error(Msg.str());
562 /// isReadModWriteImplicitKill - True if this is an implicit kill for a
563 /// read/mod/write register, i.e. update partial register.
564 static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) {
565 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
566 MachineOperand& MO = MI->getOperand(i);
567 if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
568 MO.isDef() && !MO.isDead())
574 /// isReadModWriteImplicitDef - True if this is an implicit def for a
575 /// read/mod/write register, i.e. update partial register.
576 static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
577 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
578 MachineOperand& MO = MI->getOperand(i);
579 if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() &&
580 !MO.isDef() && MO.isKill())
586 // precedes - Helper function to determine with MachineInstr A
587 // precedes MachineInstr B within the same MBB.
588 static bool precedes(MachineBasicBlock::iterator A,
589 MachineBasicBlock::iterator B) {
593 MachineBasicBlock::iterator I = A->getParent()->begin();
594 while (I != A->getParent()->end()) {
606 /// ComputeLocalLiveness - Computes liveness of registers within a basic
607 /// block, setting the killed/dead flags as appropriate.
608 void RALocal::ComputeLocalLiveness(MachineBasicBlock& MBB) {
609 MachineRegisterInfo& MRI = MBB.getParent()->getRegInfo();
610 // Keep track of the most recently seen previous use or def of each reg,
611 // so that we can update them with dead/kill markers.
612 DenseMap<unsigned, std::pair<MachineInstr*, unsigned> > LastUseDef;
613 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
615 if (I->isDebugValue())
617 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
618 MachineOperand& MO = I->getOperand(i);
619 // Uses don't trigger any flags, but we need to save
620 // them for later. Also, we have to process these
621 // _before_ processing the defs, since an instr
622 // uses regs before it defs them.
623 if (MO.isReg() && MO.getReg() && MO.isUse()) {
624 LastUseDef[MO.getReg()] = std::make_pair(I, i);
627 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) continue;
629 const unsigned* Aliases = TRI->getAliasSet(MO.getReg());
632 DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
633 alias = LastUseDef.find(*Aliases);
635 if (alias != LastUseDef.end() && alias->second.first != I)
636 LastUseDef[*Aliases] = std::make_pair(I, i);
644 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
645 MachineOperand& MO = I->getOperand(i);
646 // Defs others than 2-addr redefs _do_ trigger flag changes:
647 // - A def followed by a def is dead
648 // - A use followed by a def is a kill
649 if (MO.isReg() && MO.getReg() && MO.isDef()) {
650 DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
651 last = LastUseDef.find(MO.getReg());
652 if (last != LastUseDef.end()) {
653 // Check if this is a two address instruction. If so, then
654 // the def does not kill the use.
655 if (last->second.first == I &&
656 I->isRegTiedToUseOperand(i))
659 MachineOperand& lastUD =
660 last->second.first->getOperand(last->second.second);
662 lastUD.setIsDead(true);
664 lastUD.setIsKill(true);
667 LastUseDef[MO.getReg()] = std::make_pair(I, i);
672 // Live-out (of the function) registers contain return values of the function,
673 // so we need to make sure they are alive at return time.
674 MachineBasicBlock::iterator Ret = MBB.getFirstTerminator();
675 bool BBEndsInReturn = (Ret != MBB.end() && Ret->getDesc().isReturn());
678 for (MachineRegisterInfo::liveout_iterator
679 I = MF->getRegInfo().liveout_begin(),
680 E = MF->getRegInfo().liveout_end(); I != E; ++I)
681 if (!Ret->readsRegister(*I)) {
682 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
683 LastUseDef[*I] = std::make_pair(Ret, Ret->getNumOperands()-1);
686 // Finally, loop over the final use/def of each reg
687 // in the block and determine if it is dead.
688 for (DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
689 I = LastUseDef.begin(), E = LastUseDef.end(); I != E; ++I) {
690 MachineInstr* MI = I->second.first;
691 unsigned idx = I->second.second;
692 MachineOperand& MO = MI->getOperand(idx);
694 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(MO.getReg());
696 // A crude approximation of "live-out" calculation
697 bool usedOutsideBlock = isPhysReg ? false :
698 UsedInMultipleBlocks.test(MO.getReg() -
699 TargetRegisterInfo::FirstVirtualRegister);
701 // If the machine BB ends in a return instruction, then the value isn't used
702 // outside of the BB.
703 if (!isPhysReg && (!usedOutsideBlock || BBEndsInReturn)) {
704 // DBG_VALUE complicates this: if the only refs of a register outside
705 // this block are DBG_VALUE, we can't keep the reg live just for that,
706 // as it will cause the reg to be spilled at the end of this block when
707 // it wouldn't have been otherwise. Nullify the DBG_VALUEs when that
709 bool UsedByDebugValueOnly = false;
710 for (MachineRegisterInfo::reg_iterator UI = MRI.reg_begin(MO.getReg()),
711 UE = MRI.reg_end(); UI != UE; ++UI) {
713 // - used in another block
714 // - used in the same block before it is defined (loop)
715 if (UI->getParent() != &MBB ||
716 (MO.isDef() && UI.getOperand().isUse() && precedes(&*UI, MI))) {
717 if (UI->isDebugValue()) {
718 UsedByDebugValueOnly = true;
722 // A non-DBG_VALUE use means we can leave DBG_VALUE uses alone.
723 UsedInMultipleBlocks.set(MO.getReg() -
724 TargetRegisterInfo::FirstVirtualRegister);
725 usedOutsideBlock = true;
726 UsedByDebugValueOnly = false;
731 if (UsedByDebugValueOnly)
732 for (MachineRegisterInfo::reg_iterator UI = MRI.reg_begin(MO.getReg()),
733 UE = MRI.reg_end(); UI != UE; ++UI)
734 if (UI->isDebugValue() &&
735 (UI->getParent() != &MBB ||
736 (MO.isDef() && precedes(&*UI, MI))))
737 UI.getOperand().setReg(0U);
740 // Physical registers and those that are not live-out of the block are
741 // killed/dead at their last use/def within this block.
742 if (isPhysReg || !usedOutsideBlock || BBEndsInReturn)
744 // Don't mark uses that are tied to defs as kills.
745 if (!MI->isRegTiedToDefOperand(idx))
753 void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
754 // loop over each instruction
755 MachineBasicBlock::iterator MII = MBB.begin();
758 const BasicBlock *LBB = MBB.getBasicBlock();
760 dbgs() << "\nStarting RegAlloc of BB: " << LBB->getName();
763 // Add live-in registers as active.
764 for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(),
765 E = MBB.livein_end(); I != E; ++I) {
767 MF->getRegInfo().setPhysRegUsed(Reg);
768 PhysRegsUsed[Reg] = 0; // It is free and reserved now
769 AddToPhysRegsUseOrder(Reg);
770 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
771 *SubRegs; ++SubRegs) {
772 if (PhysRegsUsed[*SubRegs] != -2) {
773 AddToPhysRegsUseOrder(*SubRegs);
774 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
775 MF->getRegInfo().setPhysRegUsed(*SubRegs);
780 ComputeLocalLiveness(MBB);
782 // Otherwise, sequentially allocate each instruction in the MBB.
783 while (MII != MBB.end()) {
784 MachineInstr *MI = MII++;
785 const TargetInstrDesc &TID = MI->getDesc();
787 dbgs() << "\nStarting RegAlloc of: " << *MI;
788 dbgs() << " Regs have values: ";
789 for (unsigned i = 0; i != TRI->getNumRegs(); ++i)
790 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
791 dbgs() << "[" << TRI->getName(i)
792 << ",%reg" << PhysRegsUsed[i] << "] ";
796 // Determine whether this is a copy instruction. The cases where the
797 // source or destination are phys regs are handled specially.
798 unsigned SrcCopyReg, DstCopyReg, SrcCopySubReg, DstCopySubReg;
799 unsigned SrcCopyPhysReg = 0U;
800 bool isCopy = TII->isMoveInstr(*MI, SrcCopyReg, DstCopyReg,
801 SrcCopySubReg, DstCopySubReg);
802 if (isCopy && TargetRegisterInfo::isVirtualRegister(SrcCopyReg))
803 SrcCopyPhysReg = getVirt2PhysRegMapSlot(SrcCopyReg);
805 // Loop over the implicit uses, making sure that they are at the head of the
806 // use order list, so they don't get reallocated.
807 if (TID.ImplicitUses) {
808 for (const unsigned *ImplicitUses = TID.ImplicitUses;
809 *ImplicitUses; ++ImplicitUses)
810 MarkPhysRegRecentlyUsed(*ImplicitUses);
813 SmallVector<unsigned, 8> Kills;
814 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
815 MachineOperand& MO = MI->getOperand(i);
816 if (MO.isReg() && MO.isKill()) {
817 if (!MO.isImplicit())
818 Kills.push_back(MO.getReg());
819 else if (!isReadModWriteImplicitKill(MI, MO.getReg()))
820 // These are extra physical register kills when a sub-register
821 // is defined (def of a sub-register is a read/mod/write of the
822 // larger registers). Ignore.
823 Kills.push_back(MO.getReg());
827 // If any physical regs are earlyclobber, spill any value they might
828 // have in them, then mark them unallocatable.
829 // If any virtual regs are earlyclobber, allocate them now (before
830 // freeing inputs that are killed).
831 if (MI->isInlineAsm()) {
832 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
833 MachineOperand& MO = MI->getOperand(i);
834 if (MO.isReg() && MO.isDef() && MO.isEarlyClobber() &&
836 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
837 unsigned DestVirtReg = MO.getReg();
838 unsigned DestPhysReg;
840 // If DestVirtReg already has a value, use it.
841 if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
842 DestPhysReg = getReg(MBB, MI, DestVirtReg);
843 MF->getRegInfo().setPhysRegUsed(DestPhysReg);
844 markVirtRegModified(DestVirtReg);
845 getVirtRegLastUse(DestVirtReg) =
846 std::make_pair((MachineInstr*)0, 0);
847 DEBUG(dbgs() << " Assigning " << TRI->getName(DestPhysReg)
848 << " to %reg" << DestVirtReg << "\n");
849 MO.setReg(DestPhysReg); // Assign the earlyclobber register
851 unsigned Reg = MO.getReg();
852 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
853 // These are extra physical register defs when a sub-register
854 // is defined (def of a sub-register is a read/mod/write of the
855 // larger registers). Ignore.
856 if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
858 MF->getRegInfo().setPhysRegUsed(Reg);
859 spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
860 PhysRegsUsed[Reg] = 0; // It is free and reserved now
861 AddToPhysRegsUseOrder(Reg);
863 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
864 *SubRegs; ++SubRegs) {
865 if (PhysRegsUsed[*SubRegs] != -2) {
866 MF->getRegInfo().setPhysRegUsed(*SubRegs);
867 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
868 AddToPhysRegsUseOrder(*SubRegs);
876 // If a DBG_VALUE says something is located in a spilled register,
877 // change the DBG_VALUE to be undef, which prevents the register
878 // from being reloaded here. Doing that would change the generated
879 // code, unless another use immediately follows this instruction.
880 if (MI->isDebugValue() &&
881 MI->getNumOperands()==3 && MI->getOperand(0).isReg()) {
882 unsigned VirtReg = MI->getOperand(0).getReg();
883 if (VirtReg && TargetRegisterInfo::isVirtualRegister(VirtReg) &&
884 !getVirt2PhysRegMapSlot(VirtReg))
885 MI->getOperand(0).setReg(0U);
888 // Get the used operands into registers. This has the potential to spill
889 // incoming values if we are out of registers. Note that we completely
890 // ignore physical register uses here. We assume that if an explicit
891 // physical register is referenced by the instruction, that it is guaranteed
892 // to be live-in, or the input is badly hosed.
894 SmallSet<unsigned, 4> ReloadedRegs;
895 for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
896 MachineOperand& MO = MI->getOperand(i);
897 // here we are looking for only used operands (never def&use)
898 if (MO.isReg() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
899 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
900 MI = reloadVirtReg(MBB, MI, i, ReloadedRegs,
901 isCopy ? DstCopyReg : 0);
904 // If this instruction is the last user of this register, kill the
905 // value, freeing the register being used, so it doesn't need to be
906 // spilled to memory.
908 for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
909 unsigned VirtReg = Kills[i];
910 unsigned PhysReg = VirtReg;
911 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
912 // If the virtual register was never materialized into a register, it
913 // might not be in the map, but it won't hurt to zero it out anyway.
914 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
915 PhysReg = PhysRegSlot;
917 } else if (PhysRegsUsed[PhysReg] == -2) {
918 // Unallocatable register dead, ignore.
921 assert((!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1) &&
922 "Silently clearing a virtual register?");
926 DEBUG(dbgs() << " Last use of " << TRI->getName(PhysReg)
927 << "[%reg" << VirtReg <<"], removing it from live set\n");
928 removePhysReg(PhysReg);
929 for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg);
930 *SubRegs; ++SubRegs) {
931 if (PhysRegsUsed[*SubRegs] != -2) {
932 DEBUG(dbgs() << " Last use of "
933 << TRI->getName(*SubRegs) << "[%reg" << VirtReg
934 <<"], removing it from live set\n");
935 removePhysReg(*SubRegs);
941 // Loop over all of the operands of the instruction, spilling registers that
942 // are defined, and marking explicit destinations in the PhysRegsUsed map.
943 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
944 MachineOperand& MO = MI->getOperand(i);
945 if (MO.isReg() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
946 !MO.isEarlyClobber() &&
947 TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
948 unsigned Reg = MO.getReg();
949 if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
950 // These are extra physical register defs when a sub-register
951 // is defined (def of a sub-register is a read/mod/write of the
952 // larger registers). Ignore.
953 if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
955 MF->getRegInfo().setPhysRegUsed(Reg);
956 spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
957 PhysRegsUsed[Reg] = 0; // It is free and reserved now
958 AddToPhysRegsUseOrder(Reg);
960 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
961 *SubRegs; ++SubRegs) {
962 if (PhysRegsUsed[*SubRegs] != -2) {
963 MF->getRegInfo().setPhysRegUsed(*SubRegs);
964 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
965 AddToPhysRegsUseOrder(*SubRegs);
971 // Loop over the implicit defs, spilling them as well.
972 if (TID.ImplicitDefs) {
973 for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
974 *ImplicitDefs; ++ImplicitDefs) {
975 unsigned Reg = *ImplicitDefs;
976 if (PhysRegsUsed[Reg] != -2) {
977 spillPhysReg(MBB, MI, Reg, true);
978 AddToPhysRegsUseOrder(Reg);
979 PhysRegsUsed[Reg] = 0; // It is free and reserved now
981 MF->getRegInfo().setPhysRegUsed(Reg);
982 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
983 *SubRegs; ++SubRegs) {
984 if (PhysRegsUsed[*SubRegs] != -2) {
985 AddToPhysRegsUseOrder(*SubRegs);
986 PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now
987 MF->getRegInfo().setPhysRegUsed(*SubRegs);
993 SmallVector<unsigned, 8> DeadDefs;
994 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
995 MachineOperand& MO = MI->getOperand(i);
996 if (MO.isReg() && MO.isDead())
997 DeadDefs.push_back(MO.getReg());
1000 // Okay, we have allocated all of the source operands and spilled any values
1001 // that would be destroyed by defs of this instruction. Loop over the
1002 // explicit defs and assign them to a register, spilling incoming values if
1003 // we need to scavenge a register.
1005 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1006 MachineOperand& MO = MI->getOperand(i);
1007 if (MO.isReg() && MO.isDef() && MO.getReg() &&
1008 !MO.isEarlyClobber() &&
1009 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
1010 unsigned DestVirtReg = MO.getReg();
1011 unsigned DestPhysReg;
1013 // If DestVirtReg already has a value, use it.
1014 if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg))) {
1015 // If this is a copy try to reuse the input as the output;
1016 // that will make the copy go away.
1017 // If this is a copy, the source reg is a phys reg, and
1018 // that reg is available, use that phys reg for DestPhysReg.
1019 // If this is a copy, the source reg is a virtual reg, and
1020 // the phys reg that was assigned to that virtual reg is now
1021 // available, use that phys reg for DestPhysReg. (If it's now
1022 // available that means this was the last use of the source.)
1024 TargetRegisterInfo::isPhysicalRegister(SrcCopyReg) &&
1025 isPhysRegAvailable(SrcCopyReg)) {
1026 DestPhysReg = SrcCopyReg;
1027 assignVirtToPhysReg(DestVirtReg, DestPhysReg);
1028 } else if (isCopy &&
1029 TargetRegisterInfo::isVirtualRegister(SrcCopyReg) &&
1030 SrcCopyPhysReg && isPhysRegAvailable(SrcCopyPhysReg) &&
1031 MF->getRegInfo().getRegClass(DestVirtReg)->
1032 contains(SrcCopyPhysReg)) {
1033 DestPhysReg = SrcCopyPhysReg;
1034 assignVirtToPhysReg(DestVirtReg, DestPhysReg);
1036 DestPhysReg = getReg(MBB, MI, DestVirtReg);
1038 MF->getRegInfo().setPhysRegUsed(DestPhysReg);
1039 markVirtRegModified(DestVirtReg);
1040 getVirtRegLastUse(DestVirtReg) = std::make_pair((MachineInstr*)0, 0);
1041 DEBUG(dbgs() << " Assigning " << TRI->getName(DestPhysReg)
1042 << " to %reg" << DestVirtReg << "\n");
1043 MO.setReg(DestPhysReg); // Assign the output register
1047 // If this instruction defines any registers that are immediately dead,
1050 for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) {
1051 unsigned VirtReg = DeadDefs[i];
1052 unsigned PhysReg = VirtReg;
1053 if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
1054 unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
1055 PhysReg = PhysRegSlot;
1056 assert(PhysReg != 0);
1058 } else if (PhysRegsUsed[PhysReg] == -2) {
1059 // Unallocatable register dead, ignore.
1064 DEBUG(dbgs() << " Register " << TRI->getName(PhysReg)
1065 << " [%reg" << VirtReg
1066 << "] is never used, removing it from live set\n");
1067 removePhysReg(PhysReg);
1068 for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
1069 *AliasSet; ++AliasSet) {
1070 if (PhysRegsUsed[*AliasSet] != -2) {
1071 DEBUG(dbgs() << " Register " << TRI->getName(*AliasSet)
1072 << " [%reg" << *AliasSet
1073 << "] is never used, removing it from live set\n");
1074 removePhysReg(*AliasSet);
1080 // Finally, if this is a noop copy instruction, zap it. (Except that if
1081 // the copy is dead, it must be kept to avoid messing up liveness info for
1082 // the register scavenger. See pr4100.)
1083 if (TII->isMoveInstr(*MI, SrcCopyReg, DstCopyReg,
1084 SrcCopySubReg, DstCopySubReg) &&
1085 SrcCopyReg == DstCopyReg && DeadDefs.empty())
1089 MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
1091 // Spill all physical registers holding virtual registers now.
1092 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
1093 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) {
1094 if (unsigned VirtReg = PhysRegsUsed[i])
1095 spillVirtReg(MBB, MI, VirtReg, i);
1101 // This checking code is very expensive.
1103 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
1104 e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
1105 if (unsigned PR = Virt2PhysRegMap[i]) {
1106 cerr << "Register still mapped: " << i << " -> " << PR << "\n";
1109 assert(AllOk && "Virtual registers still in phys regs?");
1112 // Clear any physical register which appear live at the end of the basic
1113 // block, but which do not hold any virtual registers. e.g., the stack
1115 PhysRegsUseOrder.clear();
1118 /// runOnMachineFunction - Register allocate the whole function
1120 bool RALocal::runOnMachineFunction(MachineFunction &Fn) {
1121 DEBUG(dbgs() << "Machine Function\n");
1123 TM = &Fn.getTarget();
1124 TRI = TM->getRegisterInfo();
1125 TII = TM->getInstrInfo();
1127 PhysRegsUsed.assign(TRI->getNumRegs(), -1);
1129 // At various places we want to efficiently check to see whether a register
1130 // is allocatable. To handle this, we mark all unallocatable registers as
1131 // being pinned down, permanently.
1133 BitVector Allocable = TRI->getAllocatableSet(Fn);
1134 for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
1136 PhysRegsUsed[i] = -2; // Mark the reg unallocable.
1139 // initialize the virtual->physical register map to have a 'null'
1140 // mapping for all virtual registers
1141 unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg();
1142 StackSlotForVirtReg.grow(LastVirtReg);
1143 Virt2PhysRegMap.grow(LastVirtReg);
1144 Virt2LastUseMap.grow(LastVirtReg);
1145 VirtRegModified.resize(LastVirtReg+1-TargetRegisterInfo::FirstVirtualRegister);
1146 UsedInMultipleBlocks.resize(LastVirtReg+1-TargetRegisterInfo::FirstVirtualRegister);
1148 // Loop over all of the basic blocks, eliminating virtual register references
1149 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
1151 AllocateBasicBlock(*MBB);
1153 StackSlotForVirtReg.clear();
1154 PhysRegsUsed.clear();
1155 VirtRegModified.clear();
1156 UsedInMultipleBlocks.clear();
1157 Virt2PhysRegMap.clear();
1158 Virt2LastUseMap.clear();
1162 FunctionPass *llvm::createLocalRegisterAllocator() {
1163 return new RALocal();