1 //===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
11 // register allocator for LLVM. This allocator works by constructing a PBQP
12 // problem representing the register allocation problem under consideration,
13 // solving this using a PBQP solver, and mapping the solution back to a
14 // register assignment. If any variables are selected for spilling then spill
15 // code is inserted and the process repeated.
17 // The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
18 // for register allocation. For more information on PBQP for register
19 // allocation, see the following papers:
21 // (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
22 // PBQP. In Proceedings of the 7th Joint Modular Languages Conference
23 // (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
25 // (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
26 // architectures. In Proceedings of the Joint Conference on Languages,
27 // Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
30 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "regalloc"
34 #include "RenderMachineFunction.h"
36 #include "VirtRegMap.h"
37 #include "RegisterCoalescer.h"
38 #include "llvm/Module.h"
39 #include "llvm/Analysis/AliasAnalysis.h"
40 #include "llvm/CodeGen/CalcSpillWeights.h"
41 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
42 #include "llvm/CodeGen/LiveRangeEdit.h"
43 #include "llvm/CodeGen/LiveStackAnalysis.h"
44 #include "llvm/CodeGen/RegAllocPBQP.h"
45 #include "llvm/CodeGen/MachineDominators.h"
46 #include "llvm/CodeGen/MachineFunctionPass.h"
47 #include "llvm/CodeGen/MachineLoopInfo.h"
48 #include "llvm/CodeGen/MachineRegisterInfo.h"
49 #include "llvm/CodeGen/PBQP/HeuristicSolver.h"
50 #include "llvm/CodeGen/PBQP/Graph.h"
51 #include "llvm/CodeGen/PBQP/Heuristics/Briggs.h"
52 #include "llvm/CodeGen/RegAllocRegistry.h"
53 #include "llvm/Support/Debug.h"
54 #include "llvm/Support/raw_ostream.h"
55 #include "llvm/Target/TargetInstrInfo.h"
56 #include "llvm/Target/TargetMachine.h"
65 static RegisterRegAlloc
66 registerPBQPRepAlloc("pbqp", "PBQP register allocator",
67 createDefaultPBQPRegisterAllocator);
70 pbqpCoalescing("pbqp-coalescing",
71 cl::desc("Attempt coalescing during PBQP register allocation."),
72 cl::init(false), cl::Hidden);
76 pbqpDumpGraphs("pbqp-dump-graphs",
77 cl::desc("Dump graphs for each function/round in the compilation unit."),
78 cl::init(false), cl::Hidden);
84 /// PBQP based allocators solve the register allocation problem by mapping
85 /// register allocation problems to Partitioned Boolean Quadratic
86 /// Programming problems.
87 class RegAllocPBQP : public MachineFunctionPass {
92 /// Construct a PBQP register allocator.
93 RegAllocPBQP(std::auto_ptr<PBQPBuilder> b, char *cPassID=0)
94 : MachineFunctionPass(ID), builder(b), customPassID(cPassID) {
95 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
96 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
97 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
98 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
99 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
100 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
101 initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry());
104 /// Return the pass name.
105 virtual const char* getPassName() const {
106 return "PBQP Register Allocator";
109 /// PBQP analysis usage.
110 virtual void getAnalysisUsage(AnalysisUsage &au) const;
112 /// Perform register allocation
113 virtual bool runOnMachineFunction(MachineFunction &MF);
117 typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
118 typedef std::vector<const LiveInterval*> Node2LIMap;
119 typedef std::vector<unsigned> AllowedSet;
120 typedef std::vector<AllowedSet> AllowedSetMap;
121 typedef std::pair<unsigned, unsigned> RegPair;
122 typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;
123 typedef std::vector<PBQP::Graph::NodeItr> NodeVector;
124 typedef std::set<unsigned> RegSet;
127 std::auto_ptr<PBQPBuilder> builder;
132 const TargetMachine *tm;
133 const TargetRegisterInfo *tri;
134 const TargetInstrInfo *tii;
135 const MachineLoopInfo *loopInfo;
136 MachineRegisterInfo *mri;
137 RenderMachineFunction *rmf;
139 std::auto_ptr<Spiller> spiller;
144 RegSet vregsToAlloc, emptyIntervalVRegs;
146 /// \brief Finds the initial set of vreg intervals to allocate.
147 void findVRegIntervalsToAlloc();
149 /// \brief Given a solved PBQP problem maps this solution back to a register
151 bool mapPBQPToRegAlloc(const PBQPRAProblem &problem,
152 const PBQP::Solution &solution);
154 /// \brief Postprocessing before final spilling. Sets basic block "live in"
156 void finalizeAlloc() const;
160 char RegAllocPBQP::ID = 0;
162 } // End anonymous namespace.
164 unsigned PBQPRAProblem::getVRegForNode(PBQP::Graph::ConstNodeItr node) const {
165 Node2VReg::const_iterator vregItr = node2VReg.find(node);
166 assert(vregItr != node2VReg.end() && "No vreg for node.");
167 return vregItr->second;
170 PBQP::Graph::NodeItr PBQPRAProblem::getNodeForVReg(unsigned vreg) const {
171 VReg2Node::const_iterator nodeItr = vreg2Node.find(vreg);
172 assert(nodeItr != vreg2Node.end() && "No node for vreg.");
173 return nodeItr->second;
177 const PBQPRAProblem::AllowedSet&
178 PBQPRAProblem::getAllowedSet(unsigned vreg) const {
179 AllowedSetMap::const_iterator allowedSetItr = allowedSets.find(vreg);
180 assert(allowedSetItr != allowedSets.end() && "No pregs for vreg.");
181 const AllowedSet &allowedSet = allowedSetItr->second;
185 unsigned PBQPRAProblem::getPRegForOption(unsigned vreg, unsigned option) const {
186 assert(isPRegOption(vreg, option) && "Not a preg option.");
188 const AllowedSet& allowedSet = getAllowedSet(vreg);
189 assert(option <= allowedSet.size() && "Option outside allowed set.");
190 return allowedSet[option - 1];
193 std::auto_ptr<PBQPRAProblem> PBQPBuilder::build(MachineFunction *mf,
194 const LiveIntervals *lis,
195 const MachineLoopInfo *loopInfo,
196 const RegSet &vregs) {
198 typedef std::vector<const LiveInterval*> LIVector;
199 ArrayRef<SlotIndex> regMaskSlots = lis->getRegMaskSlots();
200 MachineRegisterInfo *mri = &mf->getRegInfo();
201 const TargetRegisterInfo *tri = mf->getTarget().getRegisterInfo();
203 std::auto_ptr<PBQPRAProblem> p(new PBQPRAProblem());
204 PBQP::Graph &g = p->getGraph();
207 // Collect the set of preg intervals, record that they're used in the MF.
208 for (LiveIntervals::const_iterator itr = lis->begin(), end = lis->end();
210 if (TargetRegisterInfo::isPhysicalRegister(itr->first)) {
211 pregs.insert(itr->first);
212 mri->setPhysRegUsed(itr->first);
216 BitVector reservedRegs = tri->getReservedRegs(*mf);
218 // Iterate over vregs.
219 for (RegSet::const_iterator vregItr = vregs.begin(), vregEnd = vregs.end();
220 vregItr != vregEnd; ++vregItr) {
221 unsigned vreg = *vregItr;
222 const TargetRegisterClass *trc = mri->getRegClass(vreg);
223 const LiveInterval *vregLI = &lis->getInterval(vreg);
225 // Compute an initial allowed set for the current vreg.
226 typedef std::vector<unsigned> VRAllowed;
228 ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(*mf);
229 for (unsigned i = 0; i != rawOrder.size(); ++i) {
230 unsigned preg = rawOrder[i];
231 if (!reservedRegs.test(preg)) {
232 vrAllowed.push_back(preg);
236 RegSet overlappingPRegs;
238 // Record physical registers whose ranges overlap.
239 for (RegSet::const_iterator pregItr = pregs.begin(),
240 pregEnd = pregs.end();
241 pregItr != pregEnd; ++pregItr) {
242 unsigned preg = *pregItr;
243 const LiveInterval *pregLI = &lis->getInterval(preg);
245 if (pregLI->empty()) {
249 if (vregLI->overlaps(*pregLI))
250 overlappingPRegs.insert(preg);
253 // Record any overlaps with regmask operands.
254 BitVector regMaskOverlaps(tri->getNumRegs());
255 for (ArrayRef<SlotIndex>::iterator rmItr = regMaskSlots.begin(),
256 rmEnd = regMaskSlots.end();
257 rmItr != rmEnd; ++rmItr) {
258 SlotIndex rmIdx = *rmItr;
259 if (vregLI->liveAt(rmIdx)) {
260 MachineInstr *rmMI = lis->getInstructionFromIndex(rmIdx);
261 const uint32_t* regMask = 0;
262 for (MachineInstr::mop_iterator mopItr = rmMI->operands_begin(),
263 mopEnd = rmMI->operands_end();
264 mopItr != mopEnd; ++mopItr) {
265 if (mopItr->isRegMask()) {
266 regMask = mopItr->getRegMask();
270 assert(regMask != 0 && "Couldn't find register mask.");
271 regMaskOverlaps.setBitsNotInMask(regMask);
275 for (unsigned preg = 0; preg < tri->getNumRegs(); ++preg) {
276 if (regMaskOverlaps.test(preg))
277 overlappingPRegs.insert(preg);
280 for (RegSet::const_iterator pregItr = overlappingPRegs.begin(),
281 pregEnd = overlappingPRegs.end();
282 pregItr != pregEnd; ++pregItr) {
283 unsigned preg = *pregItr;
285 // Remove the register from the allowed set.
286 VRAllowed::iterator eraseItr =
287 std::find(vrAllowed.begin(), vrAllowed.end(), preg);
289 if (eraseItr != vrAllowed.end()) {
290 vrAllowed.erase(eraseItr);
293 // Also remove any aliases.
294 for (MCRegAliasIterator AI(preg, tri, false); AI.isValid(); ++AI) {
295 VRAllowed::iterator eraseItr =
296 std::find(vrAllowed.begin(), vrAllowed.end(), *AI);
297 if (eraseItr != vrAllowed.end()) {
298 vrAllowed.erase(eraseItr);
303 // Construct the node.
304 PBQP::Graph::NodeItr node =
305 g.addNode(PBQP::Vector(vrAllowed.size() + 1, 0));
307 // Record the mapping and allowed set in the problem.
308 p->recordVReg(vreg, node, vrAllowed.begin(), vrAllowed.end());
310 PBQP::PBQPNum spillCost = (vregLI->weight != 0.0) ?
311 vregLI->weight : std::numeric_limits<PBQP::PBQPNum>::min();
313 addSpillCosts(g.getNodeCosts(node), spillCost);
316 for (RegSet::const_iterator vr1Itr = vregs.begin(), vrEnd = vregs.end();
317 vr1Itr != vrEnd; ++vr1Itr) {
318 unsigned vr1 = *vr1Itr;
319 const LiveInterval &l1 = lis->getInterval(vr1);
320 const PBQPRAProblem::AllowedSet &vr1Allowed = p->getAllowedSet(vr1);
322 for (RegSet::const_iterator vr2Itr = llvm::next(vr1Itr);
323 vr2Itr != vrEnd; ++vr2Itr) {
324 unsigned vr2 = *vr2Itr;
325 const LiveInterval &l2 = lis->getInterval(vr2);
326 const PBQPRAProblem::AllowedSet &vr2Allowed = p->getAllowedSet(vr2);
328 assert(!l2.empty() && "Empty interval in vreg set?");
329 if (l1.overlaps(l2)) {
330 PBQP::Graph::EdgeItr edge =
331 g.addEdge(p->getNodeForVReg(vr1), p->getNodeForVReg(vr2),
332 PBQP::Matrix(vr1Allowed.size()+1, vr2Allowed.size()+1, 0));
334 addInterferenceCosts(g.getEdgeCosts(edge), vr1Allowed, vr2Allowed, tri);
342 void PBQPBuilder::addSpillCosts(PBQP::Vector &costVec,
343 PBQP::PBQPNum spillCost) {
344 costVec[0] = spillCost;
347 void PBQPBuilder::addInterferenceCosts(
348 PBQP::Matrix &costMat,
349 const PBQPRAProblem::AllowedSet &vr1Allowed,
350 const PBQPRAProblem::AllowedSet &vr2Allowed,
351 const TargetRegisterInfo *tri) {
352 assert(costMat.getRows() == vr1Allowed.size() + 1 && "Matrix height mismatch.");
353 assert(costMat.getCols() == vr2Allowed.size() + 1 && "Matrix width mismatch.");
355 for (unsigned i = 0; i != vr1Allowed.size(); ++i) {
356 unsigned preg1 = vr1Allowed[i];
358 for (unsigned j = 0; j != vr2Allowed.size(); ++j) {
359 unsigned preg2 = vr2Allowed[j];
361 if (tri->regsOverlap(preg1, preg2)) {
362 costMat[i + 1][j + 1] = std::numeric_limits<PBQP::PBQPNum>::infinity();
368 std::auto_ptr<PBQPRAProblem> PBQPBuilderWithCoalescing::build(
370 const LiveIntervals *lis,
371 const MachineLoopInfo *loopInfo,
372 const RegSet &vregs) {
374 std::auto_ptr<PBQPRAProblem> p = PBQPBuilder::build(mf, lis, loopInfo, vregs);
375 PBQP::Graph &g = p->getGraph();
377 const TargetMachine &tm = mf->getTarget();
378 CoalescerPair cp(*tm.getRegisterInfo());
380 // Scan the machine function and add a coalescing cost whenever CoalescerPair
382 for (MachineFunction::const_iterator mbbItr = mf->begin(),
384 mbbItr != mbbEnd; ++mbbItr) {
385 const MachineBasicBlock *mbb = &*mbbItr;
387 for (MachineBasicBlock::const_iterator miItr = mbb->begin(),
389 miItr != miEnd; ++miItr) {
390 const MachineInstr *mi = &*miItr;
392 if (!cp.setRegisters(mi)) {
393 continue; // Not coalescable.
396 if (cp.getSrcReg() == cp.getDstReg()) {
397 continue; // Already coalesced.
400 unsigned dst = cp.getDstReg(),
401 src = cp.getSrcReg();
403 const float copyFactor = 0.5; // Cost of copy relative to load. Current
404 // value plucked randomly out of the air.
406 PBQP::PBQPNum cBenefit =
407 copyFactor * LiveIntervals::getSpillWeight(false, true,
408 loopInfo->getLoopDepth(mbb));
411 if (!lis->isAllocatable(dst)) {
415 const PBQPRAProblem::AllowedSet &allowed = p->getAllowedSet(src);
416 unsigned pregOpt = 0;
417 while (pregOpt < allowed.size() && allowed[pregOpt] != dst) {
420 if (pregOpt < allowed.size()) {
421 ++pregOpt; // +1 to account for spill option.
422 PBQP::Graph::NodeItr node = p->getNodeForVReg(src);
423 addPhysRegCoalesce(g.getNodeCosts(node), pregOpt, cBenefit);
426 const PBQPRAProblem::AllowedSet *allowed1 = &p->getAllowedSet(dst);
427 const PBQPRAProblem::AllowedSet *allowed2 = &p->getAllowedSet(src);
428 PBQP::Graph::NodeItr node1 = p->getNodeForVReg(dst);
429 PBQP::Graph::NodeItr node2 = p->getNodeForVReg(src);
430 PBQP::Graph::EdgeItr edge = g.findEdge(node1, node2);
431 if (edge == g.edgesEnd()) {
432 edge = g.addEdge(node1, node2, PBQP::Matrix(allowed1->size() + 1,
433 allowed2->size() + 1,
436 if (g.getEdgeNode1(edge) == node2) {
437 std::swap(node1, node2);
438 std::swap(allowed1, allowed2);
442 addVirtRegCoalesce(g.getEdgeCosts(edge), *allowed1, *allowed2,
451 void PBQPBuilderWithCoalescing::addPhysRegCoalesce(PBQP::Vector &costVec,
453 PBQP::PBQPNum benefit) {
454 costVec[pregOption] += -benefit;
457 void PBQPBuilderWithCoalescing::addVirtRegCoalesce(
458 PBQP::Matrix &costMat,
459 const PBQPRAProblem::AllowedSet &vr1Allowed,
460 const PBQPRAProblem::AllowedSet &vr2Allowed,
461 PBQP::PBQPNum benefit) {
463 assert(costMat.getRows() == vr1Allowed.size() + 1 && "Size mismatch.");
464 assert(costMat.getCols() == vr2Allowed.size() + 1 && "Size mismatch.");
466 for (unsigned i = 0; i != vr1Allowed.size(); ++i) {
467 unsigned preg1 = vr1Allowed[i];
468 for (unsigned j = 0; j != vr2Allowed.size(); ++j) {
469 unsigned preg2 = vr2Allowed[j];
471 if (preg1 == preg2) {
472 costMat[i + 1][j + 1] += -benefit;
479 void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
480 au.setPreservesCFG();
481 au.addRequired<AliasAnalysis>();
482 au.addPreserved<AliasAnalysis>();
483 au.addRequired<SlotIndexes>();
484 au.addPreserved<SlotIndexes>();
485 au.addRequired<LiveIntervals>();
486 //au.addRequiredID(SplitCriticalEdgesID);
488 au.addRequiredID(*customPassID);
489 au.addRequired<CalculateSpillWeights>();
490 au.addRequired<LiveStacks>();
491 au.addPreserved<LiveStacks>();
492 au.addRequired<MachineDominatorTree>();
493 au.addPreserved<MachineDominatorTree>();
494 au.addRequired<MachineLoopInfo>();
495 au.addPreserved<MachineLoopInfo>();
496 au.addRequired<VirtRegMap>();
497 au.addRequired<RenderMachineFunction>();
498 MachineFunctionPass::getAnalysisUsage(au);
501 void RegAllocPBQP::findVRegIntervalsToAlloc() {
503 // Iterate over all live ranges.
504 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end();
507 // Ignore physical ones.
508 if (TargetRegisterInfo::isPhysicalRegister(itr->first))
511 LiveInterval *li = itr->second;
513 // If this live interval is non-empty we will use pbqp to allocate it.
514 // Empty intervals we allocate in a simple post-processing stage in
517 vregsToAlloc.insert(li->reg);
519 emptyIntervalVRegs.insert(li->reg);
524 bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAProblem &problem,
525 const PBQP::Solution &solution) {
526 // Set to true if we have any spills
527 bool anotherRoundNeeded = false;
529 // Clear the existing allocation.
532 const PBQP::Graph &g = problem.getGraph();
533 // Iterate over the nodes mapping the PBQP solution to a register
535 for (PBQP::Graph::ConstNodeItr node = g.nodesBegin(),
536 nodeEnd = g.nodesEnd();
537 node != nodeEnd; ++node) {
538 unsigned vreg = problem.getVRegForNode(node);
539 unsigned alloc = solution.getSelection(node);
541 if (problem.isPRegOption(vreg, alloc)) {
542 unsigned preg = problem.getPRegForOption(vreg, alloc);
543 DEBUG(dbgs() << "VREG " << PrintReg(vreg, tri) << " -> "
544 << tri->getName(preg) << "\n");
545 assert(preg != 0 && "Invalid preg selected.");
546 vrm->assignVirt2Phys(vreg, preg);
547 } else if (problem.isSpillOption(vreg, alloc)) {
548 vregsToAlloc.erase(vreg);
549 SmallVector<LiveInterval*, 8> newSpills;
550 LiveRangeEdit LRE(&lis->getInterval(vreg), newSpills, *mf, *lis, vrm);
553 DEBUG(dbgs() << "VREG " << PrintReg(vreg, tri) << " -> SPILLED (Cost: "
554 << LRE.getParent().weight << ", New vregs: ");
556 // Copy any newly inserted live intervals into the list of regs to
558 for (LiveRangeEdit::iterator itr = LRE.begin(), end = LRE.end();
560 assert(!(*itr)->empty() && "Empty spill range.");
561 DEBUG(dbgs() << PrintReg((*itr)->reg, tri) << " ");
562 vregsToAlloc.insert((*itr)->reg);
565 DEBUG(dbgs() << ")\n");
567 // We need another round if spill intervals were added.
568 anotherRoundNeeded |= !LRE.empty();
570 llvm_unreachable("Unknown allocation option.");
574 return !anotherRoundNeeded;
578 void RegAllocPBQP::finalizeAlloc() const {
579 typedef LiveIntervals::iterator LIIterator;
580 typedef LiveInterval::Ranges::const_iterator LRIterator;
582 // First allocate registers for the empty intervals.
583 for (RegSet::const_iterator
584 itr = emptyIntervalVRegs.begin(), end = emptyIntervalVRegs.end();
586 LiveInterval *li = &lis->getInterval(*itr);
588 unsigned physReg = vrm->getRegAllocPref(li->reg);
591 const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
592 physReg = liRC->getRawAllocationOrder(*mf).front();
595 vrm->assignVirt2Phys(li->reg, physReg);
598 // Finally iterate over the basic blocks to compute and set the live-in sets.
599 SmallVector<MachineBasicBlock*, 8> liveInMBBs;
600 MachineBasicBlock *entryMBB = &*mf->begin();
602 for (LIIterator liItr = lis->begin(), liEnd = lis->end();
603 liItr != liEnd; ++liItr) {
605 const LiveInterval *li = liItr->second;
608 // Get the physical register for this interval
609 if (TargetRegisterInfo::isPhysicalRegister(li->reg)) {
611 } else if (vrm->isAssignedReg(li->reg)) {
612 reg = vrm->getPhys(li->reg);
614 // Ranges which are assigned a stack slot only are ignored.
619 // Filter out zero regs - they're for intervals that were spilled.
623 // Iterate over the ranges of the current interval...
624 for (LRIterator lrItr = li->begin(), lrEnd = li->end();
625 lrItr != lrEnd; ++lrItr) {
627 // Find the set of basic blocks which this range is live into...
628 if (lis->findLiveInMBBs(lrItr->start, lrItr->end, liveInMBBs)) {
629 // And add the physreg for this interval to their live-in sets.
630 for (unsigned i = 0; i != liveInMBBs.size(); ++i) {
631 if (liveInMBBs[i] != entryMBB) {
632 if (!liveInMBBs[i]->isLiveIn(reg)) {
633 liveInMBBs[i]->addLiveIn(reg);
644 bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
647 tm = &mf->getTarget();
648 tri = tm->getRegisterInfo();
649 tii = tm->getInstrInfo();
650 mri = &mf->getRegInfo();
652 lis = &getAnalysis<LiveIntervals>();
653 lss = &getAnalysis<LiveStacks>();
654 loopInfo = &getAnalysis<MachineLoopInfo>();
655 rmf = &getAnalysis<RenderMachineFunction>();
657 vrm = &getAnalysis<VirtRegMap>();
658 spiller.reset(createInlineSpiller(*this, MF, *vrm));
660 mri->freezeReservedRegs(MF);
662 DEBUG(dbgs() << "PBQP Register Allocating for " << mf->getFunction()->getName() << "\n");
664 // Allocator main loop:
666 // * Map current regalloc problem to a PBQP problem
667 // * Solve the PBQP problem
668 // * Map the solution back to a register allocation
669 // * Spill if necessary
671 // This process is continued till no more spills are generated.
673 // Find the vreg intervals in need of allocation.
674 findVRegIntervalsToAlloc();
676 const Function* func = mf->getFunction();
678 func->getParent()->getModuleIdentifier() + "." +
679 func->getName().str();
682 // If there are non-empty intervals allocate them using pbqp.
683 if (!vregsToAlloc.empty()) {
685 bool pbqpAllocComplete = false;
688 while (!pbqpAllocComplete) {
689 DEBUG(dbgs() << " PBQP Regalloc round " << round << ":\n");
691 std::auto_ptr<PBQPRAProblem> problem =
692 builder->build(mf, lis, loopInfo, vregsToAlloc);
695 if (pbqpDumpGraphs) {
696 std::ostringstream rs;
698 std::string graphFileName(fqn + "." + rs.str() + ".pbqpgraph");
700 raw_fd_ostream os(graphFileName.c_str(), tmp);
701 DEBUG(dbgs() << "Dumping graph for round " << round << " to \""
702 << graphFileName << "\"\n");
703 problem->getGraph().dump(os);
707 PBQP::Solution solution =
708 PBQP::HeuristicSolver<PBQP::Heuristics::Briggs>::solve(
709 problem->getGraph());
711 pbqpAllocComplete = mapPBQPToRegAlloc(*problem, solution);
717 // Finalise allocation, allocate empty ranges.
720 rmf->renderMachineFunction("After PBQP register allocation.", vrm);
722 vregsToAlloc.clear();
723 emptyIntervalVRegs.clear();
725 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *vrm << "\n");
728 vrm->rewrite(lis->getSlotIndexes());
730 // All machine operands and other references to virtual registers have been
731 // replaced. Remove the virtual registers.
733 mri->clearVirtRegs();
738 FunctionPass* llvm::createPBQPRegisterAllocator(
739 std::auto_ptr<PBQPBuilder> builder,
740 char *customPassID) {
741 return new RegAllocPBQP(builder, customPassID);
744 FunctionPass* llvm::createDefaultPBQPRegisterAllocator() {
745 if (pbqpCoalescing) {
746 return createPBQPRegisterAllocator(
747 std::auto_ptr<PBQPBuilder>(new PBQPBuilderWithCoalescing()));
749 return createPBQPRegisterAllocator(
750 std::auto_ptr<PBQPBuilder>(new PBQPBuilder()));