1 //===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
11 // register allocator for LLVM. This allocator works by constructing a PBQP
12 // problem representing the register allocation problem under consideration,
13 // solving this using a PBQP solver, and mapping the solution back to a
14 // register assignment. If any variables are selected for spilling then spill
15 // code is inserted and the process repeated.
17 // The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
18 // for register allocation. For more information on PBQP for register
19 // allocation, see the following papers:
21 // (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
22 // PBQP. In Proceedings of the 7th Joint Modular Languages Conference
23 // (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
25 // (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
26 // architectures. In Proceedings of the Joint Conference on Languages,
27 // Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
30 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "regalloc"
34 #include "RenderMachineFunction.h"
36 #include "VirtRegMap.h"
37 #include "VirtRegRewriter.h"
38 #include "llvm/CodeGen/CalcSpillWeights.h"
39 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
40 #include "llvm/CodeGen/LiveStackAnalysis.h"
41 #include "llvm/CodeGen/RegAllocPBQP.h"
42 #include "llvm/CodeGen/MachineFunctionPass.h"
43 #include "llvm/CodeGen/MachineLoopInfo.h"
44 #include "llvm/CodeGen/MachineRegisterInfo.h"
45 #include "llvm/CodeGen/PBQP/HeuristicSolver.h"
46 #include "llvm/CodeGen/PBQP/Graph.h"
47 #include "llvm/CodeGen/PBQP/Heuristics/Briggs.h"
48 #include "llvm/CodeGen/RegAllocRegistry.h"
49 #include "llvm/CodeGen/RegisterCoalescer.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/Target/TargetInstrInfo.h"
53 #include "llvm/Target/TargetMachine.h"
61 static RegisterRegAlloc
62 registerPBQPRepAlloc("pbqp", "PBQP register allocator",
63 llvm::createPBQPRegisterAllocator);
66 pbqpCoalescing("pbqp-coalescing",
67 cl::desc("Attempt coalescing during PBQP register allocation."),
68 cl::init(false), cl::Hidden);
71 pbqpBuilder("pbqp-builder",
72 cl::desc("Use new builder system."),
73 cl::init(false), cl::Hidden);
77 pbqpPreSplitting("pbqp-pre-splitting",
78 cl::desc("Pre-splite before PBQP register allocation."),
79 cl::init(false), cl::Hidden);
81 char RegAllocPBQP::ID = 0;
83 unsigned PBQPRAProblem::getVRegForNode(PBQP::Graph::ConstNodeItr node) const {
84 Node2VReg::const_iterator vregItr = node2VReg.find(node);
85 assert(vregItr != node2VReg.end() && "No vreg for node.");
86 return vregItr->second;
89 PBQP::Graph::NodeItr PBQPRAProblem::getNodeForVReg(unsigned vreg) const {
90 VReg2Node::const_iterator nodeItr = vreg2Node.find(vreg);
91 assert(nodeItr != vreg2Node.end() && "No node for vreg.");
92 return nodeItr->second;
96 const PBQPRAProblem::AllowedSet&
97 PBQPRAProblem::getAllowedSet(unsigned vreg) const {
98 AllowedSetMap::const_iterator allowedSetItr = allowedSets.find(vreg);
99 assert(allowedSetItr != allowedSets.end() && "No pregs for vreg.");
100 const AllowedSet &allowedSet = allowedSetItr->second;
104 unsigned PBQPRAProblem::getPRegForOption(unsigned vreg, unsigned option) const {
105 assert(isPRegOption(vreg, option) && "Not a preg option.");
107 const AllowedSet& allowedSet = getAllowedSet(vreg);
108 assert(option <= allowedSet.size() && "Option outside allowed set.");
109 return allowedSet[option - 1];
112 std::auto_ptr<PBQPRAProblem> PBQPBuilder::build(MachineFunction *mf,
113 const LiveIntervals *lis,
114 const MachineLoopInfo *loopInfo,
115 const RegSet &vregs) {
117 typedef std::vector<const LiveInterval*> LIVector;
119 MachineRegisterInfo *mri = &mf->getRegInfo();
120 const TargetRegisterInfo *tri = mf->getTarget().getRegisterInfo();
122 std::auto_ptr<PBQPRAProblem> p(new PBQPRAProblem());
123 PBQP::Graph &g = p->getGraph();
126 // Collect the set of preg intervals, record that they're used in the MF.
127 for (LiveIntervals::const_iterator itr = lis->begin(), end = lis->end();
129 if (TargetRegisterInfo::isPhysicalRegister(itr->first)) {
130 pregs.insert(itr->first);
131 mri->setPhysRegUsed(itr->first);
135 BitVector reservedRegs = tri->getReservedRegs(*mf);
137 // Iterate over vregs.
138 for (RegSet::const_iterator vregItr = vregs.begin(), vregEnd = vregs.end();
139 vregItr != vregEnd; ++vregItr) {
140 unsigned vreg = *vregItr;
141 const TargetRegisterClass *trc = mri->getRegClass(vreg);
142 const LiveInterval *vregLI = &lis->getInterval(vreg);
144 // Compute an initial allowed set for the current vreg.
145 typedef std::vector<unsigned> VRAllowed;
147 for (TargetRegisterClass::iterator aoItr = trc->allocation_order_begin(*mf),
148 aoEnd = trc->allocation_order_end(*mf);
149 aoItr != aoEnd; ++aoItr) {
150 unsigned preg = *aoItr;
151 if (!reservedRegs.test(preg)) {
152 vrAllowed.push_back(preg);
156 // Remove any physical registers which overlap.
157 for (RegSet::const_iterator pregItr = pregs.begin(),
158 pregEnd = pregs.end();
159 pregItr != pregEnd; ++pregItr) {
160 unsigned preg = *pregItr;
161 const LiveInterval *pregLI = &lis->getInterval(preg);
166 if (!vregLI->overlaps(*pregLI))
169 // Remove the register from the allowed set.
170 VRAllowed::iterator eraseItr =
171 std::find(vrAllowed.begin(), vrAllowed.end(), preg);
173 if (eraseItr != vrAllowed.end()) {
174 vrAllowed.erase(eraseItr);
177 // Also remove any aliases.
178 const unsigned *aliasItr = tri->getAliasSet(preg);
180 for (; *aliasItr != 0; ++aliasItr) {
181 VRAllowed::iterator eraseItr =
182 std::find(vrAllowed.begin(), vrAllowed.end(), *aliasItr);
184 if (eraseItr != vrAllowed.end()) {
185 vrAllowed.erase(eraseItr);
191 // Construct the node.
192 PBQP::Graph::NodeItr node =
193 g.addNode(PBQP::Vector(vrAllowed.size() + 1, 0));
195 // Record the mapping and allowed set in the problem.
196 p->recordVReg(vreg, node, vrAllowed.begin(), vrAllowed.end());
198 PBQP::PBQPNum spillCost = (vregLI->weight != 0.0) ?
199 vregLI->weight : std::numeric_limits<PBQP::PBQPNum>::min();
201 addSpillCosts(g.getNodeCosts(node), spillCost);
204 for (RegSet::const_iterator vr1Itr = vregs.begin(), vrEnd = vregs.end();
205 vr1Itr != vrEnd; ++vr1Itr) {
206 unsigned vr1 = *vr1Itr;
207 const LiveInterval &l1 = lis->getInterval(vr1);
208 const PBQPRAProblem::AllowedSet &vr1Allowed = p->getAllowedSet(vr1);
210 for (RegSet::const_iterator vr2Itr = llvm::next(vr1Itr);
211 vr2Itr != vrEnd; ++vr2Itr) {
212 unsigned vr2 = *vr2Itr;
213 const LiveInterval &l2 = lis->getInterval(vr2);
214 const PBQPRAProblem::AllowedSet &vr2Allowed = p->getAllowedSet(vr2);
216 assert(!l2.empty() && "Empty interval in vreg set?");
217 if (l1.overlaps(l2)) {
218 PBQP::Graph::EdgeItr edge =
219 g.addEdge(p->getNodeForVReg(vr1), p->getNodeForVReg(vr2),
220 PBQP::Matrix(vr1Allowed.size()+1, vr2Allowed.size()+1, 0));
222 addInterferenceCosts(g.getEdgeCosts(edge), vr1Allowed, vr2Allowed, tri);
230 void PBQPBuilder::addSpillCosts(PBQP::Vector &costVec,
231 PBQP::PBQPNum spillCost) {
232 costVec[0] = spillCost;
235 void PBQPBuilder::addInterferenceCosts(
236 PBQP::Matrix &costMat,
237 const PBQPRAProblem::AllowedSet &vr1Allowed,
238 const PBQPRAProblem::AllowedSet &vr2Allowed,
239 const TargetRegisterInfo *tri) {
240 assert(costMat.getRows() == vr1Allowed.size() + 1 && "Matrix height mismatch.");
241 assert(costMat.getCols() == vr2Allowed.size() + 1 && "Matrix width mismatch.");
243 for (unsigned i = 0; i < vr1Allowed.size(); ++i) {
244 unsigned preg1 = vr1Allowed[i];
246 for (unsigned j = 0; j < vr2Allowed.size(); ++j) {
247 unsigned preg2 = vr2Allowed[j];
249 if (tri->regsOverlap(preg1, preg2)) {
250 costMat[i + 1][j + 1] = std::numeric_limits<PBQP::PBQPNum>::infinity();
256 std::auto_ptr<PBQPRAProblem> PBQPBuilderWithCoalescing::build(
258 const LiveIntervals *lis,
259 const MachineLoopInfo *loopInfo,
260 const RegSet &vregs) {
262 std::auto_ptr<PBQPRAProblem> p = PBQPBuilder::build(mf, lis, loopInfo, vregs);
263 PBQP::Graph &g = p->getGraph();
265 const TargetMachine &tm = mf->getTarget();
266 CoalescerPair cp(*tm.getInstrInfo(), *tm.getRegisterInfo());
268 // Scan the machine function and add a coalescing cost whenever CoalescerPair
270 for (MachineFunction::const_iterator mbbItr = mf->begin(),
272 mbbItr != mbbEnd; ++mbbItr) {
273 const MachineBasicBlock *mbb = &*mbbItr;
275 for (MachineBasicBlock::const_iterator miItr = mbb->begin(),
277 miItr != miEnd; ++miItr) {
278 const MachineInstr *mi = &*miItr;
280 if (!mi->isCopy() && !mi->isSubregToReg())
281 continue; // Not coalescable.
283 if (!cp.setRegisters(mi))
284 continue; // Not coalescable.
286 if (cp.getSrcReg() == cp.getDstReg())
287 continue; // Already coalesced.
289 if (cp.isCoalescable(mi)) {
291 unsigned dst = cp.getDstReg(),
292 src = cp.getSrcReg();
296 PBQP::PBQPNum cBenefit =
297 std::pow(10.0f, (float)loopInfo->getLoopDepth(mbb));
300 if (!lis->isAllocatable(dst))
303 const PBQPRAProblem::AllowedSet &allowed = p->getAllowedSet(src);
304 unsigned pregOpt = 0;
305 while (pregOpt < allowed.size() && allowed[pregOpt] != dst)
307 if (pregOpt < allowed.size()) {
308 ++pregOpt; // +1 to account for spill option.
309 PBQP::Graph::NodeItr node = p->getNodeForVReg(src);
310 addPhysRegCoalesce(g.getNodeCosts(node), pregOpt, cBenefit);
313 const PBQPRAProblem::AllowedSet *allowed1 = &p->getAllowedSet(dst);
314 const PBQPRAProblem::AllowedSet *allowed2 = &p->getAllowedSet(src);
315 PBQP::Graph::NodeItr node1 = p->getNodeForVReg(dst);
316 PBQP::Graph::NodeItr node2 = p->getNodeForVReg(src);
317 PBQP::Graph::EdgeItr edge = g.findEdge(node1, node2);
318 if (edge == g.edgesEnd()) {
319 edge = g.addEdge(node1, node2, PBQP::Matrix(allowed1->size() + 1,
320 allowed2->size() + 1,
323 if (g.getEdgeNode1(edge) == node2) {
324 std::swap(node1, node2);
325 std::swap(allowed1, allowed2);
329 addVirtRegCoalesce(g.getEdgeCosts(edge), *allowed1, *allowed2,
340 void PBQPBuilderWithCoalescing::addPhysRegCoalesce(PBQP::Vector &costVec,
342 PBQP::PBQPNum benefit) {
343 costVec[pregOption] += -benefit;
346 void PBQPBuilderWithCoalescing::addVirtRegCoalesce(
347 PBQP::Matrix &costMat,
348 const PBQPRAProblem::AllowedSet &vr1Allowed,
349 const PBQPRAProblem::AllowedSet &vr2Allowed,
350 PBQP::PBQPNum benefit) {
352 assert(costMat.getRows() == vr1Allowed.size() + 1 && "Size mismatch.");
353 assert(costMat.getCols() == vr2Allowed.size() + 1 && "Size mismatch.");
355 for (unsigned i = 0; i < vr1Allowed.size(); ++i) {
356 unsigned preg1 = vr1Allowed[i];
357 for (unsigned j = 0; j < vr2Allowed.size(); ++j) {
358 unsigned preg2 = vr2Allowed[j];
360 if (preg1 == preg2) {
361 costMat[i + 1][j + 1] += -benefit;
368 void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
369 au.addRequired<SlotIndexes>();
370 au.addPreserved<SlotIndexes>();
371 au.addRequired<LiveIntervals>();
372 //au.addRequiredID(SplitCriticalEdgesID);
373 au.addRequired<RegisterCoalescer>();
374 au.addRequired<CalculateSpillWeights>();
375 au.addRequired<LiveStacks>();
376 au.addPreserved<LiveStacks>();
377 au.addRequired<MachineLoopInfo>();
378 au.addPreserved<MachineLoopInfo>();
379 if (pbqpPreSplitting)
380 au.addRequired<LoopSplitter>();
381 au.addRequired<VirtRegMap>();
382 au.addRequired<RenderMachineFunction>();
383 MachineFunctionPass::getAnalysisUsage(au);
386 template <typename RegContainer>
387 PBQP::Vector RegAllocPBQP::buildCostVector(unsigned vReg,
388 const RegContainer &allowed,
389 const CoalesceMap &coalesces,
390 PBQP::PBQPNum spillCost) const {
392 typedef typename RegContainer::const_iterator AllowedItr;
394 // Allocate vector. Additional element (0th) used for spill option
395 PBQP::Vector v(allowed.size() + 1, 0);
399 // Iterate over the allowed registers inserting coalesce benefits if there
402 for (AllowedItr itr = allowed.begin(), end = allowed.end();
403 itr != end; ++itr, ++ai) {
405 unsigned pReg = *itr;
407 CoalesceMap::const_iterator cmItr =
408 coalesces.find(RegPair(vReg, pReg));
410 // No coalesce - on to the next preg.
411 if (cmItr == coalesces.end())
414 // We have a coalesce - insert the benefit.
415 v[ai + 1] = -cmItr->second;
421 template <typename RegContainer>
422 PBQP::Matrix* RegAllocPBQP::buildInterferenceMatrix(
423 const RegContainer &allowed1, const RegContainer &allowed2) const {
425 typedef typename RegContainer::const_iterator RegContainerIterator;
427 // Construct a PBQP matrix representing the cost of allocation options. The
428 // rows and columns correspond to the allocation options for the two live
429 // intervals. Elements will be infinite where corresponding registers alias,
430 // since we cannot allocate aliasing registers to interfering live intervals.
431 // All other elements (non-aliasing combinations) will have zero cost. Note
432 // that the spill option (element 0,0) has zero cost, since we can allocate
433 // both intervals to memory safely (the cost for each individual allocation
434 // to memory is accounted for by the cost vectors for each live interval).
436 new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0);
438 // Assume this is a zero matrix until proven otherwise. Zero matrices occur
439 // between interfering live ranges with non-overlapping register sets (e.g.
440 // non-overlapping reg classes, or disjoint sets of allowed regs within the
441 // same class). The term "overlapping" is used advisedly: sets which do not
442 // intersect, but contain registers which alias, will have non-zero matrices.
443 // We optimize zero matrices away to improve solver speed.
444 bool isZeroMatrix = true;
447 // Row index. Starts at 1, since the 0th row is for the spill option, which
451 // Iterate over allowed sets, insert infinities where required.
452 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end();
453 a1Itr != a1End; ++a1Itr) {
455 // Column index, starts at 1 as for row index.
457 unsigned reg1 = *a1Itr;
459 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end();
460 a2Itr != a2End; ++a2Itr) {
462 unsigned reg2 = *a2Itr;
464 // If the row/column regs are identical or alias insert an infinity.
465 if (tri->regsOverlap(reg1, reg2)) {
466 (*m)[ri][ci] = std::numeric_limits<PBQP::PBQPNum>::infinity();
467 isZeroMatrix = false;
476 // If this turns out to be a zero matrix...
478 // free it and return null.
483 // ...otherwise return the cost matrix.
487 template <typename RegContainer>
488 PBQP::Matrix* RegAllocPBQP::buildCoalescingMatrix(
489 const RegContainer &allowed1, const RegContainer &allowed2,
490 PBQP::PBQPNum cBenefit) const {
492 typedef typename RegContainer::const_iterator RegContainerIterator;
494 // Construct a PBQP Matrix representing the benefits of coalescing. As with
495 // interference matrices the rows and columns represent allowed registers
496 // for the LiveIntervals which are (potentially) to be coalesced. The amount
497 // -cBenefit will be placed in any element representing the same register
498 // for both intervals.
500 new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0);
502 // Reset costs to zero.
505 // Assume the matrix is zero till proven otherwise. Zero matrices will be
506 // optimized away as in the interference case.
507 bool isZeroMatrix = true;
509 // Row index. Starts at 1, since the 0th row is for the spill option, which
513 // Iterate over the allowed sets, insert coalescing benefits where
515 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end();
516 a1Itr != a1End; ++a1Itr) {
518 // Column index, starts at 1 as for row index.
520 unsigned reg1 = *a1Itr;
522 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end();
523 a2Itr != a2End; ++a2Itr) {
525 // If the row and column represent the same register insert a beneficial
526 // cost to preference this allocation - it would allow us to eliminate a
528 if (reg1 == *a2Itr) {
529 (*m)[ri][ci] = -cBenefit;
530 isZeroMatrix = false;
539 // If this turns out to be a zero matrix...
541 // ...free it and return null.
549 RegAllocPBQP::CoalesceMap RegAllocPBQP::findCoalesces() {
551 typedef MachineFunction::const_iterator MFIterator;
552 typedef MachineBasicBlock::const_iterator MBBIterator;
553 typedef LiveInterval::const_vni_iterator VNIIterator;
555 CoalesceMap coalescesFound;
557 // To find coalesces we need to iterate over the function looking for
558 // copy instructions.
559 for (MFIterator bbItr = mf->begin(), bbEnd = mf->end();
560 bbItr != bbEnd; ++bbItr) {
562 const MachineBasicBlock *mbb = &*bbItr;
564 for (MBBIterator iItr = mbb->begin(), iEnd = mbb->end();
565 iItr != iEnd; ++iItr) {
567 const MachineInstr *instr = &*iItr;
569 // If this isn't a copy then continue to the next instruction.
570 if (!instr->isCopy())
573 unsigned srcReg = instr->getOperand(1).getReg();
574 unsigned dstReg = instr->getOperand(0).getReg();
576 // If the registers are already the same our job is nice and easy.
577 if (dstReg == srcReg)
580 bool srcRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(srcReg),
581 dstRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(dstReg);
583 // If both registers are physical then we can't coalesce.
584 if (srcRegIsPhysical && dstRegIsPhysical)
587 // If it's a copy that includes two virtual register but the source and
588 // destination classes differ then we can't coalesce.
589 if (!srcRegIsPhysical && !dstRegIsPhysical &&
590 mri->getRegClass(srcReg) != mri->getRegClass(dstReg))
593 // If one is physical and one is virtual, check that the physical is
594 // allocatable in the class of the virtual.
595 if (srcRegIsPhysical && !dstRegIsPhysical) {
596 const TargetRegisterClass *dstRegClass = mri->getRegClass(dstReg);
597 if (std::find(dstRegClass->allocation_order_begin(*mf),
598 dstRegClass->allocation_order_end(*mf), srcReg) ==
599 dstRegClass->allocation_order_end(*mf))
602 if (!srcRegIsPhysical && dstRegIsPhysical) {
603 const TargetRegisterClass *srcRegClass = mri->getRegClass(srcReg);
604 if (std::find(srcRegClass->allocation_order_begin(*mf),
605 srcRegClass->allocation_order_end(*mf), dstReg) ==
606 srcRegClass->allocation_order_end(*mf))
610 // If we've made it here we have a copy with compatible register classes.
611 // We can probably coalesce, but we need to consider overlap.
612 const LiveInterval *srcLI = &lis->getInterval(srcReg),
613 *dstLI = &lis->getInterval(dstReg);
615 if (srcLI->overlaps(*dstLI)) {
616 // Even in the case of an overlap we might still be able to coalesce,
617 // but we need to make sure that no definition of either range occurs
618 // while the other range is live.
620 // Otherwise start by assuming we're ok.
623 // Test all defs of the source range.
625 vniItr = srcLI->vni_begin(), vniEnd = srcLI->vni_end();
626 vniItr != vniEnd; ++vniItr) {
628 // If we find a poorly defined def we err on the side of caution.
629 if (!(*vniItr)->def.isValid()) {
634 // If we find a def that kills the coalescing opportunity then
635 // record it and break from the loop.
636 if (dstLI->liveAt((*vniItr)->def)) {
642 // If we have a bad def give up, continue to the next instruction.
646 // Otherwise test definitions of the destination range.
648 vniItr = dstLI->vni_begin(), vniEnd = dstLI->vni_end();
649 vniItr != vniEnd; ++vniItr) {
651 // We want to make sure we skip the copy instruction itself.
652 if ((*vniItr)->getCopy() == instr)
655 if (!(*vniItr)->def.isValid()) {
660 if (srcLI->liveAt((*vniItr)->def)) {
666 // As before a bad def we give up and continue to the next instr.
671 // If we make it to here then either the ranges didn't overlap, or they
672 // did, but none of their definitions would prevent us from coalescing.
673 // We're good to go with the coalesce.
675 float cBenefit = std::pow(10.0f, (float)loopInfo->getLoopDepth(mbb)) / 5.0;
677 coalescesFound[RegPair(srcReg, dstReg)] = cBenefit;
678 coalescesFound[RegPair(dstReg, srcReg)] = cBenefit;
683 return coalescesFound;
686 void RegAllocPBQP::findVRegIntervalsToAlloc() {
688 // Iterate over all live ranges.
689 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end();
692 // Ignore physical ones.
693 if (TargetRegisterInfo::isPhysicalRegister(itr->first))
696 LiveInterval *li = itr->second;
698 // If this live interval is non-empty we will use pbqp to allocate it.
699 // Empty intervals we allocate in a simple post-processing stage in
702 vregsToAlloc.insert(li->reg);
705 emptyIntervalVRegs.insert(li->reg);
710 PBQP::Graph RegAllocPBQP::constructPBQPProblem() {
712 typedef std::vector<const LiveInterval*> LIVector;
713 typedef std::vector<unsigned> RegVector;
715 // This will store the physical intervals for easy reference.
716 LIVector physIntervals;
718 // Start by clearing the old node <-> live interval mappings & allowed sets
723 // Populate physIntervals, update preg use:
724 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end();
727 if (TargetRegisterInfo::isPhysicalRegister(itr->first)) {
728 physIntervals.push_back(itr->second);
729 mri->setPhysRegUsed(itr->second->reg);
733 // Iterate over vreg intervals, construct live interval <-> node number
735 for (RegSet::const_iterator itr = vregsToAlloc.begin(),
736 end = vregsToAlloc.end();
738 const LiveInterval *li = &lis->getInterval(*itr);
740 li2Node[li] = node2LI.size();
741 node2LI.push_back(li);
744 // Get the set of potential coalesces.
745 CoalesceMap coalesces;
747 if (pbqpCoalescing) {
748 coalesces = findCoalesces();
751 // Construct a PBQP solver for this problem
753 problemNodes.resize(vregsToAlloc.size());
755 // Resize allowedSets container appropriately.
756 allowedSets.resize(vregsToAlloc.size());
758 BitVector ReservedRegs = tri->getReservedRegs(*mf);
760 // Iterate over virtual register intervals to compute allowed sets...
761 for (unsigned node = 0; node < node2LI.size(); ++node) {
763 // Grab pointers to the interval and its register class.
764 const LiveInterval *li = node2LI[node];
765 const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
767 // Start by assuming all allocable registers in the class are allowed...
769 TargetRegisterClass::iterator aob = liRC->allocation_order_begin(*mf);
770 TargetRegisterClass::iterator aoe = liRC->allocation_order_end(*mf);
771 for (TargetRegisterClass::iterator it = aob; it != aoe; ++it)
772 if (!ReservedRegs.test(*it))
773 liAllowed.push_back(*it);
775 // Eliminate the physical registers which overlap with this range, along
776 // with all their aliases.
777 for (LIVector::iterator pItr = physIntervals.begin(),
778 pEnd = physIntervals.end(); pItr != pEnd; ++pItr) {
780 if (!li->overlaps(**pItr))
783 unsigned pReg = (*pItr)->reg;
785 // If we get here then the live intervals overlap, but we're still ok
786 // if they're coalescable.
787 if (coalesces.find(RegPair(li->reg, pReg)) != coalesces.end()) {
788 DEBUG(dbgs() << "CoalescingOverride: (" << li->reg << ", " << pReg << ")\n");
792 // If we get here then we have a genuine exclusion.
794 // Remove the overlapping reg...
795 RegVector::iterator eraseItr =
796 std::find(liAllowed.begin(), liAllowed.end(), pReg);
798 if (eraseItr != liAllowed.end())
799 liAllowed.erase(eraseItr);
801 const unsigned *aliasItr = tri->getAliasSet(pReg);
804 // ...and its aliases.
805 for (; *aliasItr != 0; ++aliasItr) {
806 RegVector::iterator eraseItr =
807 std::find(liAllowed.begin(), liAllowed.end(), *aliasItr);
809 if (eraseItr != liAllowed.end()) {
810 liAllowed.erase(eraseItr);
816 // Copy the allowed set into a member vector for use when constructing cost
817 // vectors & matrices, and mapping PBQP solutions back to assignments.
818 allowedSets[node] = AllowedSet(liAllowed.begin(), liAllowed.end());
820 // Set the spill cost to the interval weight, or epsilon if the
821 // interval weight is zero
822 PBQP::PBQPNum spillCost = (li->weight != 0.0) ?
823 li->weight : std::numeric_limits<PBQP::PBQPNum>::min();
825 // Build a cost vector for this interval.
828 buildCostVector(li->reg, allowedSets[node], coalesces, spillCost));
833 // Now add the cost matrices...
834 for (unsigned node1 = 0; node1 < node2LI.size(); ++node1) {
835 const LiveInterval *li = node2LI[node1];
837 // Test for live range overlaps and insert interference matrices.
838 for (unsigned node2 = node1 + 1; node2 < node2LI.size(); ++node2) {
839 const LiveInterval *li2 = node2LI[node2];
841 CoalesceMap::const_iterator cmItr =
842 coalesces.find(RegPair(li->reg, li2->reg));
846 if (cmItr != coalesces.end()) {
847 m = buildCoalescingMatrix(allowedSets[node1], allowedSets[node2],
850 else if (li->overlaps(*li2)) {
851 m = buildInterferenceMatrix(allowedSets[node1], allowedSets[node2]);
855 problem.addEdge(problemNodes[node1],
864 assert(problem.getNumNodes() == allowedSets.size());
866 std::cerr << "Allocating for " << problem.getNumNodes() << " nodes, "
867 << problem.getNumEdges() << " edges.\n";
869 problem.printDot(std::cerr);
871 // We're done, PBQP problem constructed - return it.
875 void RegAllocPBQP::addStackInterval(const LiveInterval *spilled,
876 MachineRegisterInfo* mri) {
877 int stackSlot = vrm->getStackSlot(spilled->reg);
879 if (stackSlot == VirtRegMap::NO_STACK_SLOT)
882 const TargetRegisterClass *RC = mri->getRegClass(spilled->reg);
883 LiveInterval &stackInterval = lss->getOrCreateInterval(stackSlot, RC);
886 if (stackInterval.getNumValNums() != 0)
887 vni = stackInterval.getValNumInfo(0);
889 vni = stackInterval.getNextValue(
890 SlotIndex(), 0, false, lss->getVNInfoAllocator());
892 LiveInterval &rhsInterval = lis->getInterval(spilled->reg);
893 stackInterval.MergeRangesInAsValue(rhsInterval, vni);
896 bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQP::Solution &solution) {
898 // Set to true if we have any spills
899 bool anotherRoundNeeded = false;
901 // Clear the existing allocation.
904 // Iterate over the nodes mapping the PBQP solution to a register assignment.
905 for (unsigned node = 0; node < node2LI.size(); ++node) {
906 unsigned virtReg = node2LI[node]->reg,
907 allocSelection = solution.getSelection(problemNodes[node]);
910 // If the PBQP solution is non-zero it's a physical register...
911 if (allocSelection != 0) {
912 // Get the physical reg, subtracting 1 to account for the spill option.
913 unsigned physReg = allowedSets[node][allocSelection - 1];
915 DEBUG(dbgs() << "VREG " << virtReg << " -> "
916 << tri->getName(physReg) << " (Option: " << allocSelection << ")\n");
918 assert(physReg != 0);
920 // Add to the virt reg map and update the used phys regs.
921 vrm->assignVirt2Phys(virtReg, physReg);
923 // ...Otherwise it's a spill.
926 // Make sure we ignore this virtual reg on the next round
928 vregsToAlloc.erase(virtReg);
930 // Insert spill ranges for this live range
931 const LiveInterval *spillInterval = node2LI[node];
932 double oldSpillWeight = spillInterval->weight;
933 SmallVector<LiveInterval*, 8> spillIs;
934 rmf->rememberUseDefs(spillInterval);
935 std::vector<LiveInterval*> newSpills =
936 lis->addIntervalsForSpills(*spillInterval, spillIs, loopInfo, *vrm);
937 addStackInterval(spillInterval, mri);
938 rmf->rememberSpills(spillInterval, newSpills);
940 (void) oldSpillWeight;
941 DEBUG(dbgs() << "VREG " << virtReg << " -> SPILLED (Option: 0, Cost: "
942 << oldSpillWeight << ", New vregs: ");
944 // Copy any newly inserted live intervals into the list of regs to
946 for (std::vector<LiveInterval*>::const_iterator
947 itr = newSpills.begin(), end = newSpills.end();
950 assert(!(*itr)->empty() && "Empty spill range.");
952 DEBUG(dbgs() << (*itr)->reg << " ");
954 vregsToAlloc.insert((*itr)->reg);
957 DEBUG(dbgs() << ")\n");
959 // We need another round if spill intervals were added.
960 anotherRoundNeeded |= !newSpills.empty();
964 return !anotherRoundNeeded;
967 bool RegAllocPBQP::mapPBQPToRegAlloc2(const PBQPRAProblem &problem,
968 const PBQP::Solution &solution) {
969 // Set to true if we have any spills
970 bool anotherRoundNeeded = false;
972 // Clear the existing allocation.
975 const PBQP::Graph &g = problem.getGraph();
976 // Iterate over the nodes mapping the PBQP solution to a register
978 for (PBQP::Graph::ConstNodeItr node = g.nodesBegin(),
979 nodeEnd = g.nodesEnd();
980 node != nodeEnd; ++node) {
981 unsigned vreg = problem.getVRegForNode(node);
982 unsigned alloc = solution.getSelection(node);
984 if (problem.isPRegOption(vreg, alloc)) {
985 unsigned preg = problem.getPRegForOption(vreg, alloc);
986 DEBUG(dbgs() << "VREG " << vreg << " -> " << tri->getName(preg) << "\n");
987 assert(preg != 0 && "Invalid preg selected.");
988 vrm->assignVirt2Phys(vreg, preg);
989 } else if (problem.isSpillOption(vreg, alloc)) {
990 vregsToAlloc.erase(vreg);
991 const LiveInterval* spillInterval = &lis->getInterval(vreg);
992 double oldWeight = spillInterval->weight;
993 SmallVector<LiveInterval*, 8> spillIs;
994 rmf->rememberUseDefs(spillInterval);
995 std::vector<LiveInterval*> newSpills =
996 lis->addIntervalsForSpills(*spillInterval, spillIs, loopInfo, *vrm);
997 addStackInterval(spillInterval, mri);
998 rmf->rememberSpills(spillInterval, newSpills);
1001 DEBUG(dbgs() << "VREG " << vreg << " -> SPILLED (Cost: "
1002 << oldWeight << ", New vregs: ");
1004 // Copy any newly inserted live intervals into the list of regs to
1006 for (std::vector<LiveInterval*>::const_iterator
1007 itr = newSpills.begin(), end = newSpills.end();
1008 itr != end; ++itr) {
1009 assert(!(*itr)->empty() && "Empty spill range.");
1010 DEBUG(dbgs() << (*itr)->reg << " ");
1011 vregsToAlloc.insert((*itr)->reg);
1014 DEBUG(dbgs() << ")\n");
1016 // We need another round if spill intervals were added.
1017 anotherRoundNeeded |= !newSpills.empty();
1019 assert(false && "Unknown allocation option.");
1023 return !anotherRoundNeeded;
1027 void RegAllocPBQP::finalizeAlloc() const {
1028 typedef LiveIntervals::iterator LIIterator;
1029 typedef LiveInterval::Ranges::const_iterator LRIterator;
1031 // First allocate registers for the empty intervals.
1032 for (RegSet::const_iterator
1033 itr = emptyIntervalVRegs.begin(), end = emptyIntervalVRegs.end();
1034 itr != end; ++itr) {
1035 LiveInterval *li = &lis->getInterval(*itr);
1037 unsigned physReg = vrm->getRegAllocPref(li->reg);
1040 const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
1041 physReg = *liRC->allocation_order_begin(*mf);
1044 vrm->assignVirt2Phys(li->reg, physReg);
1047 // Finally iterate over the basic blocks to compute and set the live-in sets.
1048 SmallVector<MachineBasicBlock*, 8> liveInMBBs;
1049 MachineBasicBlock *entryMBB = &*mf->begin();
1051 for (LIIterator liItr = lis->begin(), liEnd = lis->end();
1052 liItr != liEnd; ++liItr) {
1054 const LiveInterval *li = liItr->second;
1057 // Get the physical register for this interval
1058 if (TargetRegisterInfo::isPhysicalRegister(li->reg)) {
1061 else if (vrm->isAssignedReg(li->reg)) {
1062 reg = vrm->getPhys(li->reg);
1065 // Ranges which are assigned a stack slot only are ignored.
1070 // Filter out zero regs - they're for intervals that were spilled.
1074 // Iterate over the ranges of the current interval...
1075 for (LRIterator lrItr = li->begin(), lrEnd = li->end();
1076 lrItr != lrEnd; ++lrItr) {
1078 // Find the set of basic blocks which this range is live into...
1079 if (lis->findLiveInMBBs(lrItr->start, lrItr->end, liveInMBBs)) {
1080 // And add the physreg for this interval to their live-in sets.
1081 for (unsigned i = 0; i < liveInMBBs.size(); ++i) {
1082 if (liveInMBBs[i] != entryMBB) {
1083 if (!liveInMBBs[i]->isLiveIn(reg)) {
1084 liveInMBBs[i]->addLiveIn(reg);
1095 bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
1098 tm = &mf->getTarget();
1099 tri = tm->getRegisterInfo();
1100 tii = tm->getInstrInfo();
1101 mri = &mf->getRegInfo();
1103 lis = &getAnalysis<LiveIntervals>();
1104 lss = &getAnalysis<LiveStacks>();
1105 loopInfo = &getAnalysis<MachineLoopInfo>();
1106 rmf = &getAnalysis<RenderMachineFunction>();
1108 vrm = &getAnalysis<VirtRegMap>();
1111 DEBUG(dbgs() << "PBQP Register Allocating for " << mf->getFunction()->getName() << "\n");
1113 // Allocator main loop:
1115 // * Map current regalloc problem to a PBQP problem
1116 // * Solve the PBQP problem
1117 // * Map the solution back to a register allocation
1118 // * Spill if necessary
1120 // This process is continued till no more spills are generated.
1122 // Find the vreg intervals in need of allocation.
1123 findVRegIntervalsToAlloc();
1125 // If there are non-empty intervals allocate them using pbqp.
1126 if (!vregsToAlloc.empty()) {
1128 bool pbqpAllocComplete = false;
1132 while (!pbqpAllocComplete) {
1133 DEBUG(dbgs() << " PBQP Regalloc round " << round << ":\n");
1135 PBQP::Graph problem = constructPBQPProblem();
1136 PBQP::Solution solution =
1137 PBQP::HeuristicSolver<PBQP::Heuristics::Briggs>::solve(problem);
1139 pbqpAllocComplete = mapPBQPToRegAlloc(solution);
1144 while (!pbqpAllocComplete) {
1145 DEBUG(dbgs() << " PBQP Regalloc round " << round << ":\n");
1147 std::auto_ptr<PBQPRAProblem> problem =
1148 builder->build(mf, lis, loopInfo, vregsToAlloc);
1149 PBQP::Solution solution =
1150 PBQP::HeuristicSolver<PBQP::Heuristics::Briggs>::solve(
1151 problem->getGraph());
1153 pbqpAllocComplete = mapPBQPToRegAlloc2(*problem, solution);
1160 // Finalise allocation, allocate empty ranges.
1163 rmf->renderMachineFunction("After PBQP register allocation.", vrm);
1165 vregsToAlloc.clear();
1166 emptyIntervalVRegs.clear();
1169 allowedSets.clear();
1170 problemNodes.clear();
1172 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *vrm << "\n");
1175 std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
1177 rewriter->runOnMachineFunction(*mf, *vrm, lis);
1182 FunctionPass* createPBQPRegisterAllocator() {
1183 if (pbqpCoalescing) {
1184 return new RegAllocPBQP(
1185 std::auto_ptr<PBQPBuilder>(new PBQPBuilderWithCoalescing()));
1187 return new RegAllocPBQP(
1188 std::auto_ptr<PBQPBuilder>(new PBQPBuilder()));