1 //===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
11 // register allocator for LLVM. This allocator works by constructing a PBQP
12 // problem representing the register allocation problem under consideration,
13 // solving this using a PBQP solver, and mapping the solution back to a
14 // register assignment. If any variables are selected for spilling then spill
15 // code is inserted and the process repeated.
17 // The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
18 // for register allocation. For more information on PBQP for register
19 // allocation, see the following papers:
21 // (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
22 // PBQP. In Proceedings of the 7th Joint Modular Languages Conference
23 // (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
25 // (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
26 // architectures. In Proceedings of the Joint Conference on Languages,
27 // Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
30 //===----------------------------------------------------------------------===//
32 #include "llvm/CodeGen/RegAllocPBQP.h"
33 #include "RegisterCoalescer.h"
35 #include "llvm/Analysis/AliasAnalysis.h"
36 #include "llvm/CodeGen/CalcSpillWeights.h"
37 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
38 #include "llvm/CodeGen/LiveRangeEdit.h"
39 #include "llvm/CodeGen/LiveStackAnalysis.h"
40 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
41 #include "llvm/CodeGen/MachineDominators.h"
42 #include "llvm/CodeGen/MachineFunctionPass.h"
43 #include "llvm/CodeGen/MachineLoopInfo.h"
44 #include "llvm/CodeGen/MachineRegisterInfo.h"
45 #include "llvm/CodeGen/RegAllocRegistry.h"
46 #include "llvm/CodeGen/VirtRegMap.h"
47 #include "llvm/IR/Module.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/FileSystem.h"
50 #include "llvm/Support/raw_ostream.h"
51 #include "llvm/Target/TargetInstrInfo.h"
52 #include "llvm/Target/TargetSubtargetInfo.h"
62 #define DEBUG_TYPE "regalloc"
64 static RegisterRegAlloc
65 RegisterPBQPRepAlloc("pbqp", "PBQP register allocator",
66 createDefaultPBQPRegisterAllocator);
69 PBQPCoalescing("pbqp-coalescing",
70 cl::desc("Attempt coalescing during PBQP register allocation."),
71 cl::init(false), cl::Hidden);
75 PBQPDumpGraphs("pbqp-dump-graphs",
76 cl::desc("Dump graphs for each function/round in the compilation unit."),
77 cl::init(false), cl::Hidden);
83 /// PBQP based allocators solve the register allocation problem by mapping
84 /// register allocation problems to Partitioned Boolean Quadratic
85 /// Programming problems.
86 class RegAllocPBQP : public MachineFunctionPass {
91 /// Construct a PBQP register allocator.
92 RegAllocPBQP(char *cPassID = nullptr)
93 : MachineFunctionPass(ID), customPassID(cPassID) {
94 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
95 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
96 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
97 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
100 /// Return the pass name.
101 const char* getPassName() const override {
102 return "PBQP Register Allocator";
105 /// PBQP analysis usage.
106 void getAnalysisUsage(AnalysisUsage &au) const override;
108 /// Perform register allocation
109 bool runOnMachineFunction(MachineFunction &MF) override;
113 typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
114 typedef std::vector<const LiveInterval*> Node2LIMap;
115 typedef std::vector<unsigned> AllowedSet;
116 typedef std::vector<AllowedSet> AllowedSetMap;
117 typedef std::pair<unsigned, unsigned> RegPair;
118 typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;
119 typedef std::set<unsigned> RegSet;
123 RegSet VRegsToAlloc, EmptyIntervalVRegs;
125 /// \brief Finds the initial set of vreg intervals to allocate.
126 void findVRegIntervalsToAlloc(const MachineFunction &MF, LiveIntervals &LIS);
128 /// \brief Constructs an initial graph.
129 void initializeGraph(PBQPRAGraph &G);
131 /// \brief Given a solved PBQP problem maps this solution back to a register
133 bool mapPBQPToRegAlloc(const PBQPRAGraph &G,
134 const PBQP::Solution &Solution,
136 Spiller &VRegSpiller);
138 /// \brief Postprocessing before final spilling. Sets basic block "live in"
140 void finalizeAlloc(MachineFunction &MF, LiveIntervals &LIS,
141 VirtRegMap &VRM) const;
145 char RegAllocPBQP::ID = 0;
147 /// @brief Set spill costs for each node in the PBQP reg-alloc graph.
148 class SpillCosts : public PBQPRAConstraint {
150 void apply(PBQPRAGraph &G) override {
151 LiveIntervals &LIS = G.getMetadata().LIS;
153 for (auto NId : G.nodeIds()) {
154 PBQP::PBQPNum SpillCost =
155 LIS.getInterval(G.getNodeMetadata(NId).getVReg()).weight;
156 if (SpillCost == 0.0)
157 SpillCost = std::numeric_limits<PBQP::PBQPNum>::min();
158 PBQPRAGraph::RawVector NodeCosts(G.getNodeCosts(NId));
159 NodeCosts[PBQP::RegAlloc::getSpillOptionIdx()] = SpillCost;
160 G.setNodeCosts(NId, std::move(NodeCosts));
165 /// @brief Add interference edges between overlapping vregs.
166 class Interference : public PBQPRAConstraint {
171 typedef const PBQP::RegAlloc::AllowedRegVector* AllowedRegVecPtr;
172 typedef std::pair<AllowedRegVecPtr, AllowedRegVecPtr> IMatrixKey;
173 typedef DenseMap<IMatrixKey, PBQPRAGraph::MatrixPtr> IMatrixCache;
175 // Holds (Interval, CurrentSegmentID, and NodeId). The first two are required
176 // for the fast interference graph construction algorithm. The last is there
177 // to save us from looking up node ids via the VRegToNode map in the graph
179 typedef std::tuple<LiveInterval*, size_t, PBQP::GraphBase::NodeId>
182 static SlotIndex getStartPoint(const IntervalInfo &I) {
183 return std::get<0>(I)->segments[std::get<1>(I)].start;
186 static SlotIndex getEndPoint(const IntervalInfo &I) {
187 return std::get<0>(I)->segments[std::get<1>(I)].end;
190 static PBQP::GraphBase::NodeId getNodeId(const IntervalInfo &I) {
191 return std::get<2>(I);
194 static bool lowestStartPoint(const IntervalInfo &I1,
195 const IntervalInfo &I2) {
196 // Condition reversed because priority queue has the *highest* element at
197 // the front, rather than the lowest.
198 return getStartPoint(I1) > getStartPoint(I2);
201 static bool lowestEndPoint(const IntervalInfo &I1,
202 const IntervalInfo &I2) {
203 SlotIndex E1 = getEndPoint(I1);
204 SlotIndex E2 = getEndPoint(I2);
212 // If two intervals end at the same point, we need a way to break the tie or
213 // the set will assume they're actually equal and refuse to insert a
214 // "duplicate". Just compare the vregs - fast and guaranteed unique.
215 return std::get<0>(I1)->reg < std::get<0>(I2)->reg;
218 static bool isAtLastSegment(const IntervalInfo &I) {
219 return std::get<1>(I) == std::get<0>(I)->size() - 1;
222 static IntervalInfo nextSegment(const IntervalInfo &I) {
223 return std::make_tuple(std::get<0>(I), std::get<1>(I) + 1, std::get<2>(I));
228 void apply(PBQPRAGraph &G) override {
229 // The following is loosely based on the linear scan algorithm introduced in
230 // "Linear Scan Register Allocation" by Poletto and Sarkar. This version
231 // isn't linear, because the size of the active set isn't bound by the
232 // number of registers, but rather the size of the largest clique in the
233 // graph. Still, we expect this to be better than N^2.
234 LiveIntervals &LIS = G.getMetadata().LIS;
236 // Interferenc matrices are incredibly regular - they're only a function of
237 // the allowed sets, so we cache them to avoid the overhead of constructing
238 // and uniquing them.
241 typedef std::set<IntervalInfo, decltype(&lowestEndPoint)> IntervalSet;
242 typedef std::priority_queue<IntervalInfo, std::vector<IntervalInfo>,
243 decltype(&lowestStartPoint)> IntervalQueue;
244 IntervalSet Active(lowestEndPoint);
245 IntervalQueue Inactive(lowestStartPoint);
247 // Start by building the inactive set.
248 for (auto NId : G.nodeIds()) {
249 unsigned VReg = G.getNodeMetadata(NId).getVReg();
250 LiveInterval &LI = LIS.getInterval(VReg);
251 assert(!LI.empty() && "PBQP graph contains node for empty interval");
252 Inactive.push(std::make_tuple(&LI, 0, NId));
255 while (!Inactive.empty()) {
256 // Tentatively grab the "next" interval - this choice may be overriden
258 IntervalInfo Cur = Inactive.top();
260 // Retire any active intervals that end before Cur starts.
261 IntervalSet::iterator RetireItr = Active.begin();
262 while (RetireItr != Active.end() &&
263 (getEndPoint(*RetireItr) <= getStartPoint(Cur))) {
264 // If this interval has subsequent segments, add the next one to the
266 if (!isAtLastSegment(*RetireItr))
267 Inactive.push(nextSegment(*RetireItr));
271 Active.erase(Active.begin(), RetireItr);
273 // One of the newly retired segments may actually start before the
274 // Cur segment, so re-grab the front of the inactive list.
275 Cur = Inactive.top();
278 // At this point we know that Cur overlaps all active intervals. Add the
279 // interference edges.
280 PBQP::GraphBase::NodeId NId = getNodeId(Cur);
281 for (const auto &A : Active) {
282 PBQP::GraphBase::NodeId MId = getNodeId(A);
284 // Check that we haven't already added this edge
285 // FIXME: findEdge is expensive in the worst case (O(max_clique(G))).
286 // It might be better to replace this with a local bit-matrix.
287 if (G.findEdge(NId, MId) != PBQPRAGraph::invalidEdgeId())
290 // This is a new edge - add it to the graph.
291 createInterferenceEdge(G, NId, MId, C);
294 // Finally, add Cur to the Active set.
301 void createInterferenceEdge(PBQPRAGraph &G, PBQPRAGraph::NodeId NId,
302 PBQPRAGraph::NodeId MId, IMatrixCache &C) {
304 const TargetRegisterInfo &TRI =
305 *G.getMetadata().MF.getTarget().getSubtargetImpl()->getRegisterInfo();
307 const auto &NRegs = G.getNodeMetadata(NId).getAllowedRegs();
308 const auto &MRegs = G.getNodeMetadata(MId).getAllowedRegs();
310 // Try looking the edge costs up in the IMatrixCache first.
311 IMatrixKey K(&NRegs, &MRegs);
312 IMatrixCache::iterator I = C.find(K);
314 G.addEdgeBypassingCostAllocator(NId, MId, I->second);
318 PBQPRAGraph::RawMatrix M(NRegs.size() + 1, MRegs.size() + 1, 0);
319 for (unsigned I = 0; I != NRegs.size(); ++I) {
320 unsigned PRegN = NRegs[I];
321 for (unsigned J = 0; J != MRegs.size(); ++J) {
322 unsigned PRegM = MRegs[J];
323 if (TRI.regsOverlap(PRegN, PRegM))
324 M[I + 1][J + 1] = std::numeric_limits<PBQP::PBQPNum>::infinity();
328 PBQPRAGraph::EdgeId EId = G.addEdge(NId, MId, std::move(M));
329 C[K] = G.getEdgeCostsPtr(EId);
334 class Coalescing : public PBQPRAConstraint {
336 void apply(PBQPRAGraph &G) override {
337 MachineFunction &MF = G.getMetadata().MF;
338 MachineBlockFrequencyInfo &MBFI = G.getMetadata().MBFI;
339 CoalescerPair CP(*MF.getTarget().getSubtargetImpl()->getRegisterInfo());
341 // Scan the machine function and add a coalescing cost whenever CoalescerPair
343 for (const auto &MBB : MF) {
344 for (const auto &MI : MBB) {
346 // Skip not-coalescable or already coalesced copies.
347 if (!CP.setRegisters(&MI) || CP.getSrcReg() == CP.getDstReg())
350 unsigned DstReg = CP.getDstReg();
351 unsigned SrcReg = CP.getSrcReg();
353 const float CopyFactor = 0.5; // Cost of copy relative to load. Current
354 // value plucked randomly out of the air.
356 PBQP::PBQPNum CBenefit =
357 CopyFactor * LiveIntervals::getSpillWeight(false, true, &MBFI, &MI);
360 if (!MF.getRegInfo().isAllocatable(DstReg))
363 PBQPRAGraph::NodeId NId = G.getMetadata().getNodeIdForVReg(SrcReg);
365 const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed =
366 G.getNodeMetadata(NId).getAllowedRegs();
368 unsigned PRegOpt = 0;
369 while (PRegOpt < Allowed.size() && Allowed[PRegOpt] != DstReg)
372 if (PRegOpt < Allowed.size()) {
373 PBQPRAGraph::RawVector NewCosts(G.getNodeCosts(NId));
374 NewCosts[PRegOpt + 1] -= CBenefit;
375 G.setNodeCosts(NId, std::move(NewCosts));
378 PBQPRAGraph::NodeId N1Id = G.getMetadata().getNodeIdForVReg(DstReg);
379 PBQPRAGraph::NodeId N2Id = G.getMetadata().getNodeIdForVReg(SrcReg);
380 const PBQPRAGraph::NodeMetadata::AllowedRegVector *Allowed1 =
381 &G.getNodeMetadata(N1Id).getAllowedRegs();
382 const PBQPRAGraph::NodeMetadata::AllowedRegVector *Allowed2 =
383 &G.getNodeMetadata(N2Id).getAllowedRegs();
385 PBQPRAGraph::EdgeId EId = G.findEdge(N1Id, N2Id);
386 if (EId == G.invalidEdgeId()) {
387 PBQPRAGraph::RawMatrix Costs(Allowed1->size() + 1,
388 Allowed2->size() + 1, 0);
389 addVirtRegCoalesce(Costs, *Allowed1, *Allowed2, CBenefit);
390 G.addEdge(N1Id, N2Id, std::move(Costs));
392 if (G.getEdgeNode1Id(EId) == N2Id) {
393 std::swap(N1Id, N2Id);
394 std::swap(Allowed1, Allowed2);
396 PBQPRAGraph::RawMatrix Costs(G.getEdgeCosts(EId));
397 addVirtRegCoalesce(Costs, *Allowed1, *Allowed2, CBenefit);
398 G.setEdgeCosts(EId, std::move(Costs));
407 void addVirtRegCoalesce(
408 PBQPRAGraph::RawMatrix &CostMat,
409 const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed1,
410 const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed2,
411 PBQP::PBQPNum Benefit) {
412 assert(CostMat.getRows() == Allowed1.size() + 1 && "Size mismatch.");
413 assert(CostMat.getCols() == Allowed2.size() + 1 && "Size mismatch.");
414 for (unsigned I = 0; I != Allowed1.size(); ++I) {
415 unsigned PReg1 = Allowed1[I];
416 for (unsigned J = 0; J != Allowed2.size(); ++J) {
417 unsigned PReg2 = Allowed2[J];
419 CostMat[I + 1][J + 1] -= Benefit;
426 } // End anonymous namespace.
428 // Out-of-line destructor/anchor for PBQPRAConstraint.
429 PBQPRAConstraint::~PBQPRAConstraint() {}
430 void PBQPRAConstraint::anchor() {}
431 void PBQPRAConstraintList::anchor() {}
433 void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
434 au.setPreservesCFG();
435 au.addRequired<AliasAnalysis>();
436 au.addPreserved<AliasAnalysis>();
437 au.addRequired<SlotIndexes>();
438 au.addPreserved<SlotIndexes>();
439 au.addRequired<LiveIntervals>();
440 au.addPreserved<LiveIntervals>();
441 //au.addRequiredID(SplitCriticalEdgesID);
443 au.addRequiredID(*customPassID);
444 au.addRequired<LiveStacks>();
445 au.addPreserved<LiveStacks>();
446 au.addRequired<MachineBlockFrequencyInfo>();
447 au.addPreserved<MachineBlockFrequencyInfo>();
448 au.addRequired<MachineLoopInfo>();
449 au.addPreserved<MachineLoopInfo>();
450 au.addRequired<MachineDominatorTree>();
451 au.addPreserved<MachineDominatorTree>();
452 au.addRequired<VirtRegMap>();
453 au.addPreserved<VirtRegMap>();
454 MachineFunctionPass::getAnalysisUsage(au);
457 void RegAllocPBQP::findVRegIntervalsToAlloc(const MachineFunction &MF,
458 LiveIntervals &LIS) {
459 const MachineRegisterInfo &MRI = MF.getRegInfo();
461 // Iterate over all live ranges.
462 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
463 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
464 if (MRI.reg_nodbg_empty(Reg))
466 LiveInterval &LI = LIS.getInterval(Reg);
468 // If this live interval is non-empty we will use pbqp to allocate it.
469 // Empty intervals we allocate in a simple post-processing stage in
472 VRegsToAlloc.insert(LI.reg);
474 EmptyIntervalVRegs.insert(LI.reg);
479 void RegAllocPBQP::initializeGraph(PBQPRAGraph &G) {
480 MachineFunction &MF = G.getMetadata().MF;
482 LiveIntervals &LIS = G.getMetadata().LIS;
483 const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
484 const TargetRegisterInfo &TRI =
485 *G.getMetadata().MF.getTarget().getSubtargetImpl()->getRegisterInfo();
487 for (auto VReg : VRegsToAlloc) {
488 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
489 LiveInterval &VRegLI = LIS.getInterval(VReg);
491 // Record any overlaps with regmask operands.
492 BitVector RegMaskOverlaps;
493 LIS.checkRegMaskInterference(VRegLI, RegMaskOverlaps);
495 // Compute an initial allowed set for the current vreg.
496 std::vector<unsigned> VRegAllowed;
497 ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF);
498 for (unsigned I = 0; I != RawPRegOrder.size(); ++I) {
499 unsigned PReg = RawPRegOrder[I];
500 if (MRI.isReserved(PReg))
503 // vregLI crosses a regmask operand that clobbers preg.
504 if (!RegMaskOverlaps.empty() && !RegMaskOverlaps.test(PReg))
507 // vregLI overlaps fixed regunit interference.
508 bool Interference = false;
509 for (MCRegUnitIterator Units(PReg, &TRI); Units.isValid(); ++Units) {
510 if (VRegLI.overlaps(LIS.getRegUnit(*Units))) {
518 // preg is usable for this virtual register.
519 VRegAllowed.push_back(PReg);
522 PBQPRAGraph::RawVector NodeCosts(VRegAllowed.size() + 1, 0);
523 PBQPRAGraph::NodeId NId = G.addNode(std::move(NodeCosts));
524 G.getNodeMetadata(NId).setVReg(VReg);
525 G.getNodeMetadata(NId).setAllowedRegs(
526 G.getMetadata().getAllowedRegs(std::move(VRegAllowed)));
527 G.getMetadata().setNodeIdForVReg(VReg, NId);
531 bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAGraph &G,
532 const PBQP::Solution &Solution,
534 Spiller &VRegSpiller) {
535 MachineFunction &MF = G.getMetadata().MF;
536 LiveIntervals &LIS = G.getMetadata().LIS;
537 const TargetRegisterInfo &TRI =
538 *MF.getTarget().getSubtargetImpl()->getRegisterInfo();
541 // Set to true if we have any spills
542 bool AnotherRoundNeeded = false;
544 // Clear the existing allocation.
547 // Iterate over the nodes mapping the PBQP solution to a register
549 for (auto NId : G.nodeIds()) {
550 unsigned VReg = G.getNodeMetadata(NId).getVReg();
551 unsigned AllocOption = Solution.getSelection(NId);
553 if (AllocOption != PBQP::RegAlloc::getSpillOptionIdx()) {
554 unsigned PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOption - 1];
555 DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> "
556 << TRI.getName(PReg) << "\n");
557 assert(PReg != 0 && "Invalid preg selected.");
558 VRM.assignVirt2Phys(VReg, PReg);
560 VRegsToAlloc.erase(VReg);
561 SmallVector<unsigned, 8> NewSpills;
562 LiveRangeEdit LRE(&LIS.getInterval(VReg), NewSpills, MF, LIS, &VRM);
563 VRegSpiller.spill(LRE);
565 DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> SPILLED (Cost: "
566 << LRE.getParent().weight << ", New vregs: ");
568 // Copy any newly inserted live intervals into the list of regs to
570 for (LiveRangeEdit::iterator I = LRE.begin(), E = LRE.end();
572 LiveInterval &LI = LIS.getInterval(*I);
573 assert(!LI.empty() && "Empty spill range.");
574 DEBUG(dbgs() << PrintReg(LI.reg, &TRI) << " ");
575 VRegsToAlloc.insert(LI.reg);
578 DEBUG(dbgs() << ")\n");
580 // We need another round if spill intervals were added.
581 AnotherRoundNeeded |= !LRE.empty();
585 return !AnotherRoundNeeded;
588 void RegAllocPBQP::finalizeAlloc(MachineFunction &MF,
590 VirtRegMap &VRM) const {
591 MachineRegisterInfo &MRI = MF.getRegInfo();
593 // First allocate registers for the empty intervals.
594 for (RegSet::const_iterator
595 I = EmptyIntervalVRegs.begin(), E = EmptyIntervalVRegs.end();
597 LiveInterval &LI = LIS.getInterval(*I);
599 unsigned PReg = MRI.getSimpleHint(LI.reg);
602 const TargetRegisterClass &RC = *MRI.getRegClass(LI.reg);
603 PReg = RC.getRawAllocationOrder(MF).front();
606 VRM.assignVirt2Phys(LI.reg, PReg);
610 bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
611 LiveIntervals &LIS = getAnalysis<LiveIntervals>();
612 MachineBlockFrequencyInfo &MBFI =
613 getAnalysis<MachineBlockFrequencyInfo>();
615 calculateSpillWeightsAndHints(LIS, MF, getAnalysis<MachineLoopInfo>(), MBFI);
617 VirtRegMap &VRM = getAnalysis<VirtRegMap>();
619 std::unique_ptr<Spiller> VRegSpiller(createInlineSpiller(*this, MF, VRM));
621 MF.getRegInfo().freezeReservedRegs(MF);
623 DEBUG(dbgs() << "PBQP Register Allocating for " << MF.getName() << "\n");
625 // Allocator main loop:
627 // * Map current regalloc problem to a PBQP problem
628 // * Solve the PBQP problem
629 // * Map the solution back to a register allocation
630 // * Spill if necessary
632 // This process is continued till no more spills are generated.
634 // Find the vreg intervals in need of allocation.
635 findVRegIntervalsToAlloc(MF, LIS);
638 const Function &F = *MF.getFunction();
639 std::string FullyQualifiedName =
640 F.getParent()->getModuleIdentifier() + "." + F.getName().str();
643 // If there are non-empty intervals allocate them using pbqp.
644 if (!VRegsToAlloc.empty()) {
646 const TargetSubtargetInfo &Subtarget = *MF.getTarget().getSubtargetImpl();
647 std::unique_ptr<PBQPRAConstraintList> ConstraintsRoot =
648 llvm::make_unique<PBQPRAConstraintList>();
649 ConstraintsRoot->addConstraint(llvm::make_unique<SpillCosts>());
650 ConstraintsRoot->addConstraint(llvm::make_unique<Interference>());
652 ConstraintsRoot->addConstraint(llvm::make_unique<Coalescing>());
653 ConstraintsRoot->addConstraint(Subtarget.getCustomPBQPConstraints());
655 bool PBQPAllocComplete = false;
658 while (!PBQPAllocComplete) {
659 DEBUG(dbgs() << " PBQP Regalloc round " << Round << ":\n");
661 PBQPRAGraph G(PBQPRAGraph::GraphMetadata(MF, LIS, MBFI));
663 ConstraintsRoot->apply(G);
666 if (PBQPDumpGraphs) {
667 std::ostringstream RS;
669 std::string GraphFileName = FullyQualifiedName + "." + RS.str() +
672 raw_fd_ostream OS(GraphFileName, EC, sys::fs::F_Text);
673 DEBUG(dbgs() << "Dumping graph for round " << Round << " to \""
674 << GraphFileName << "\"\n");
679 PBQP::Solution Solution = PBQP::RegAlloc::solve(G);
680 PBQPAllocComplete = mapPBQPToRegAlloc(G, Solution, VRM, *VRegSpiller);
685 // Finalise allocation, allocate empty ranges.
686 finalizeAlloc(MF, LIS, VRM);
687 VRegsToAlloc.clear();
688 EmptyIntervalVRegs.clear();
690 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << VRM << "\n");
695 FunctionPass *llvm::createPBQPRegisterAllocator(char *customPassID) {
696 return new RegAllocPBQP(customPassID);
699 FunctionPass* llvm::createDefaultPBQPRegisterAllocator() {
700 return createPBQPRegisterAllocator();