1 //===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
11 // register allocator for LLVM. This allocator works by constructing a PBQP
12 // problem representing the register allocation problem under consideration,
13 // solving this using a PBQP solver, and mapping the solution back to a
14 // register assignment. If any variables are selected for spilling then spill
15 // code is inserted and the process repeated.
17 // The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
18 // for register allocation. For more information on PBQP for register
19 // allocation, see the following papers:
21 // (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
22 // PBQP. In Proceedings of the 7th Joint Modular Languages Conference
23 // (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
25 // (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
26 // architectures. In Proceedings of the Joint Conference on Languages,
27 // Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
30 //===----------------------------------------------------------------------===//
32 #include "llvm/CodeGen/RegAllocPBQP.h"
33 #include "RegisterCoalescer.h"
35 #include "llvm/Analysis/AliasAnalysis.h"
36 #include "llvm/CodeGen/CalcSpillWeights.h"
37 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
38 #include "llvm/CodeGen/LiveRangeEdit.h"
39 #include "llvm/CodeGen/LiveStackAnalysis.h"
40 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
41 #include "llvm/CodeGen/MachineDominators.h"
42 #include "llvm/CodeGen/MachineFunctionPass.h"
43 #include "llvm/CodeGen/MachineLoopInfo.h"
44 #include "llvm/CodeGen/MachineRegisterInfo.h"
45 #include "llvm/CodeGen/RegAllocRegistry.h"
46 #include "llvm/CodeGen/VirtRegMap.h"
47 #include "llvm/IR/Module.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/FileSystem.h"
50 #include "llvm/Support/raw_ostream.h"
51 #include "llvm/Target/TargetInstrInfo.h"
52 #include "llvm/Target/TargetSubtargetInfo.h"
62 #define DEBUG_TYPE "regalloc"
64 static RegisterRegAlloc
65 RegisterPBQPRepAlloc("pbqp", "PBQP register allocator",
66 createDefaultPBQPRegisterAllocator);
69 PBQPCoalescing("pbqp-coalescing",
70 cl::desc("Attempt coalescing during PBQP register allocation."),
71 cl::init(false), cl::Hidden);
75 PBQPDumpGraphs("pbqp-dump-graphs",
76 cl::desc("Dump graphs for each function/round in the compilation unit."),
77 cl::init(false), cl::Hidden);
83 /// PBQP based allocators solve the register allocation problem by mapping
84 /// register allocation problems to Partitioned Boolean Quadratic
85 /// Programming problems.
86 class RegAllocPBQP : public MachineFunctionPass {
91 /// Construct a PBQP register allocator.
92 RegAllocPBQP(char *cPassID = nullptr)
93 : MachineFunctionPass(ID), customPassID(cPassID) {
94 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
95 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
96 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
97 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
100 /// Return the pass name.
101 const char* getPassName() const override {
102 return "PBQP Register Allocator";
105 /// PBQP analysis usage.
106 void getAnalysisUsage(AnalysisUsage &au) const override;
108 /// Perform register allocation
109 bool runOnMachineFunction(MachineFunction &MF) override;
113 typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
114 typedef std::vector<const LiveInterval*> Node2LIMap;
115 typedef std::vector<unsigned> AllowedSet;
116 typedef std::vector<AllowedSet> AllowedSetMap;
117 typedef std::pair<unsigned, unsigned> RegPair;
118 typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;
119 typedef std::set<unsigned> RegSet;
123 RegSet VRegsToAlloc, EmptyIntervalVRegs;
125 /// \brief Finds the initial set of vreg intervals to allocate.
126 void findVRegIntervalsToAlloc(const MachineFunction &MF, LiveIntervals &LIS);
128 /// \brief Constructs an initial graph.
129 void initializeGraph(PBQPRAGraph &G, VirtRegMap &VRM, Spiller &VRegSpiller);
131 /// \brief Spill the given VReg.
132 void spillVReg(unsigned VReg, SmallVectorImpl<unsigned> &NewIntervals,
133 MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM,
134 Spiller &VRegSpiller);
136 /// \brief Given a solved PBQP problem maps this solution back to a register
138 bool mapPBQPToRegAlloc(const PBQPRAGraph &G,
139 const PBQP::Solution &Solution,
141 Spiller &VRegSpiller);
143 /// \brief Postprocessing before final spilling. Sets basic block "live in"
145 void finalizeAlloc(MachineFunction &MF, LiveIntervals &LIS,
146 VirtRegMap &VRM) const;
150 char RegAllocPBQP::ID = 0;
152 /// @brief Set spill costs for each node in the PBQP reg-alloc graph.
153 class SpillCosts : public PBQPRAConstraint {
155 void apply(PBQPRAGraph &G) override {
156 LiveIntervals &LIS = G.getMetadata().LIS;
158 // A minimum spill costs, so that register constraints can can be set
159 // without normalization in the [0.0:MinSpillCost( interval.
160 const PBQP::PBQPNum MinSpillCost = 10.0;
162 for (auto NId : G.nodeIds()) {
163 PBQP::PBQPNum SpillCost =
164 LIS.getInterval(G.getNodeMetadata(NId).getVReg()).weight;
165 if (SpillCost == 0.0)
166 SpillCost = std::numeric_limits<PBQP::PBQPNum>::min();
168 SpillCost += MinSpillCost;
169 PBQPRAGraph::RawVector NodeCosts(G.getNodeCosts(NId));
170 NodeCosts[PBQP::RegAlloc::getSpillOptionIdx()] = SpillCost;
171 G.setNodeCosts(NId, std::move(NodeCosts));
176 /// @brief Add interference edges between overlapping vregs.
177 class Interference : public PBQPRAConstraint {
180 typedef const PBQP::RegAlloc::AllowedRegVector* AllowedRegVecPtr;
181 typedef std::pair<AllowedRegVecPtr, AllowedRegVecPtr> IMatrixKey;
182 typedef DenseMap<IMatrixKey, PBQPRAGraph::MatrixPtr> IMatrixCache;
184 // Holds (Interval, CurrentSegmentID, and NodeId). The first two are required
185 // for the fast interference graph construction algorithm. The last is there
186 // to save us from looking up node ids via the VRegToNode map in the graph
188 typedef std::tuple<LiveInterval*, size_t, PBQP::GraphBase::NodeId>
191 static SlotIndex getStartPoint(const IntervalInfo &I) {
192 return std::get<0>(I)->segments[std::get<1>(I)].start;
195 static SlotIndex getEndPoint(const IntervalInfo &I) {
196 return std::get<0>(I)->segments[std::get<1>(I)].end;
199 static PBQP::GraphBase::NodeId getNodeId(const IntervalInfo &I) {
200 return std::get<2>(I);
203 static bool lowestStartPoint(const IntervalInfo &I1,
204 const IntervalInfo &I2) {
205 // Condition reversed because priority queue has the *highest* element at
206 // the front, rather than the lowest.
207 return getStartPoint(I1) > getStartPoint(I2);
210 static bool lowestEndPoint(const IntervalInfo &I1,
211 const IntervalInfo &I2) {
212 SlotIndex E1 = getEndPoint(I1);
213 SlotIndex E2 = getEndPoint(I2);
221 // If two intervals end at the same point, we need a way to break the tie or
222 // the set will assume they're actually equal and refuse to insert a
223 // "duplicate". Just compare the vregs - fast and guaranteed unique.
224 return std::get<0>(I1)->reg < std::get<0>(I2)->reg;
227 static bool isAtLastSegment(const IntervalInfo &I) {
228 return std::get<1>(I) == std::get<0>(I)->size() - 1;
231 static IntervalInfo nextSegment(const IntervalInfo &I) {
232 return std::make_tuple(std::get<0>(I), std::get<1>(I) + 1, std::get<2>(I));
237 void apply(PBQPRAGraph &G) override {
238 // The following is loosely based on the linear scan algorithm introduced in
239 // "Linear Scan Register Allocation" by Poletto and Sarkar. This version
240 // isn't linear, because the size of the active set isn't bound by the
241 // number of registers, but rather the size of the largest clique in the
242 // graph. Still, we expect this to be better than N^2.
243 LiveIntervals &LIS = G.getMetadata().LIS;
245 // Interferenc matrices are incredibly regular - they're only a function of
246 // the allowed sets, so we cache them to avoid the overhead of constructing
247 // and uniquing them.
250 typedef std::set<IntervalInfo, decltype(&lowestEndPoint)> IntervalSet;
251 typedef std::priority_queue<IntervalInfo, std::vector<IntervalInfo>,
252 decltype(&lowestStartPoint)> IntervalQueue;
253 IntervalSet Active(lowestEndPoint);
254 IntervalQueue Inactive(lowestStartPoint);
256 // Start by building the inactive set.
257 for (auto NId : G.nodeIds()) {
258 unsigned VReg = G.getNodeMetadata(NId).getVReg();
259 LiveInterval &LI = LIS.getInterval(VReg);
260 assert(!LI.empty() && "PBQP graph contains node for empty interval");
261 Inactive.push(std::make_tuple(&LI, 0, NId));
264 while (!Inactive.empty()) {
265 // Tentatively grab the "next" interval - this choice may be overriden
267 IntervalInfo Cur = Inactive.top();
269 // Retire any active intervals that end before Cur starts.
270 IntervalSet::iterator RetireItr = Active.begin();
271 while (RetireItr != Active.end() &&
272 (getEndPoint(*RetireItr) <= getStartPoint(Cur))) {
273 // If this interval has subsequent segments, add the next one to the
275 if (!isAtLastSegment(*RetireItr))
276 Inactive.push(nextSegment(*RetireItr));
280 Active.erase(Active.begin(), RetireItr);
282 // One of the newly retired segments may actually start before the
283 // Cur segment, so re-grab the front of the inactive list.
284 Cur = Inactive.top();
287 // At this point we know that Cur overlaps all active intervals. Add the
288 // interference edges.
289 PBQP::GraphBase::NodeId NId = getNodeId(Cur);
290 for (const auto &A : Active) {
291 PBQP::GraphBase::NodeId MId = getNodeId(A);
293 // Check that we haven't already added this edge
294 // FIXME: findEdge is expensive in the worst case (O(max_clique(G))).
295 // It might be better to replace this with a local bit-matrix.
296 if (G.findEdge(NId, MId) != PBQPRAGraph::invalidEdgeId())
299 // This is a new edge - add it to the graph.
300 createInterferenceEdge(G, NId, MId, C);
303 // Finally, add Cur to the Active set.
310 void createInterferenceEdge(PBQPRAGraph &G, PBQPRAGraph::NodeId NId,
311 PBQPRAGraph::NodeId MId, IMatrixCache &C) {
313 const TargetRegisterInfo &TRI =
314 *G.getMetadata().MF.getSubtarget().getRegisterInfo();
316 const auto &NRegs = G.getNodeMetadata(NId).getAllowedRegs();
317 const auto &MRegs = G.getNodeMetadata(MId).getAllowedRegs();
319 // Try looking the edge costs up in the IMatrixCache first.
320 IMatrixKey K(&NRegs, &MRegs);
321 IMatrixCache::iterator I = C.find(K);
323 G.addEdgeBypassingCostAllocator(NId, MId, I->second);
327 PBQPRAGraph::RawMatrix M(NRegs.size() + 1, MRegs.size() + 1, 0);
328 for (unsigned I = 0; I != NRegs.size(); ++I) {
329 unsigned PRegN = NRegs[I];
330 for (unsigned J = 0; J != MRegs.size(); ++J) {
331 unsigned PRegM = MRegs[J];
332 if (TRI.regsOverlap(PRegN, PRegM))
333 M[I + 1][J + 1] = std::numeric_limits<PBQP::PBQPNum>::infinity();
337 PBQPRAGraph::EdgeId EId = G.addEdge(NId, MId, std::move(M));
338 C[K] = G.getEdgeCostsPtr(EId);
343 class Coalescing : public PBQPRAConstraint {
345 void apply(PBQPRAGraph &G) override {
346 MachineFunction &MF = G.getMetadata().MF;
347 MachineBlockFrequencyInfo &MBFI = G.getMetadata().MBFI;
348 CoalescerPair CP(*MF.getSubtarget().getRegisterInfo());
350 // Scan the machine function and add a coalescing cost whenever CoalescerPair
352 for (const auto &MBB : MF) {
353 for (const auto &MI : MBB) {
355 // Skip not-coalescable or already coalesced copies.
356 if (!CP.setRegisters(&MI) || CP.getSrcReg() == CP.getDstReg())
359 unsigned DstReg = CP.getDstReg();
360 unsigned SrcReg = CP.getSrcReg();
362 const float Scale = 1.0f / MBFI.getEntryFreq();
363 PBQP::PBQPNum CBenefit = MBFI.getBlockFreq(&MBB).getFrequency() * Scale;
366 if (!MF.getRegInfo().isAllocatable(DstReg))
369 PBQPRAGraph::NodeId NId = G.getMetadata().getNodeIdForVReg(SrcReg);
371 const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed =
372 G.getNodeMetadata(NId).getAllowedRegs();
374 unsigned PRegOpt = 0;
375 while (PRegOpt < Allowed.size() && Allowed[PRegOpt] != DstReg)
378 if (PRegOpt < Allowed.size()) {
379 PBQPRAGraph::RawVector NewCosts(G.getNodeCosts(NId));
380 NewCosts[PRegOpt + 1] -= CBenefit;
381 G.setNodeCosts(NId, std::move(NewCosts));
384 PBQPRAGraph::NodeId N1Id = G.getMetadata().getNodeIdForVReg(DstReg);
385 PBQPRAGraph::NodeId N2Id = G.getMetadata().getNodeIdForVReg(SrcReg);
386 const PBQPRAGraph::NodeMetadata::AllowedRegVector *Allowed1 =
387 &G.getNodeMetadata(N1Id).getAllowedRegs();
388 const PBQPRAGraph::NodeMetadata::AllowedRegVector *Allowed2 =
389 &G.getNodeMetadata(N2Id).getAllowedRegs();
391 PBQPRAGraph::EdgeId EId = G.findEdge(N1Id, N2Id);
392 if (EId == G.invalidEdgeId()) {
393 PBQPRAGraph::RawMatrix Costs(Allowed1->size() + 1,
394 Allowed2->size() + 1, 0);
395 addVirtRegCoalesce(Costs, *Allowed1, *Allowed2, CBenefit);
396 G.addEdge(N1Id, N2Id, std::move(Costs));
398 if (G.getEdgeNode1Id(EId) == N2Id) {
399 std::swap(N1Id, N2Id);
400 std::swap(Allowed1, Allowed2);
402 PBQPRAGraph::RawMatrix Costs(G.getEdgeCosts(EId));
403 addVirtRegCoalesce(Costs, *Allowed1, *Allowed2, CBenefit);
404 G.setEdgeCosts(EId, std::move(Costs));
413 void addVirtRegCoalesce(
414 PBQPRAGraph::RawMatrix &CostMat,
415 const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed1,
416 const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed2,
417 PBQP::PBQPNum Benefit) {
418 assert(CostMat.getRows() == Allowed1.size() + 1 && "Size mismatch.");
419 assert(CostMat.getCols() == Allowed2.size() + 1 && "Size mismatch.");
420 for (unsigned I = 0; I != Allowed1.size(); ++I) {
421 unsigned PReg1 = Allowed1[I];
422 for (unsigned J = 0; J != Allowed2.size(); ++J) {
423 unsigned PReg2 = Allowed2[J];
425 CostMat[I + 1][J + 1] -= Benefit;
432 } // End anonymous namespace.
434 // Out-of-line destructor/anchor for PBQPRAConstraint.
435 PBQPRAConstraint::~PBQPRAConstraint() {}
436 void PBQPRAConstraint::anchor() {}
437 void PBQPRAConstraintList::anchor() {}
439 void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
440 au.setPreservesCFG();
441 au.addRequired<AliasAnalysis>();
442 au.addPreserved<AliasAnalysis>();
443 au.addRequired<SlotIndexes>();
444 au.addPreserved<SlotIndexes>();
445 au.addRequired<LiveIntervals>();
446 au.addPreserved<LiveIntervals>();
447 //au.addRequiredID(SplitCriticalEdgesID);
449 au.addRequiredID(*customPassID);
450 au.addRequired<LiveStacks>();
451 au.addPreserved<LiveStacks>();
452 au.addRequired<MachineBlockFrequencyInfo>();
453 au.addPreserved<MachineBlockFrequencyInfo>();
454 au.addRequired<MachineLoopInfo>();
455 au.addPreserved<MachineLoopInfo>();
456 au.addRequired<MachineDominatorTree>();
457 au.addPreserved<MachineDominatorTree>();
458 au.addRequired<VirtRegMap>();
459 au.addPreserved<VirtRegMap>();
460 MachineFunctionPass::getAnalysisUsage(au);
463 void RegAllocPBQP::findVRegIntervalsToAlloc(const MachineFunction &MF,
464 LiveIntervals &LIS) {
465 const MachineRegisterInfo &MRI = MF.getRegInfo();
467 // Iterate over all live ranges.
468 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
469 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
470 if (MRI.reg_nodbg_empty(Reg))
472 LiveInterval &LI = LIS.getInterval(Reg);
474 // If this live interval is non-empty we will use pbqp to allocate it.
475 // Empty intervals we allocate in a simple post-processing stage in
478 VRegsToAlloc.insert(LI.reg);
480 EmptyIntervalVRegs.insert(LI.reg);
485 static bool isACalleeSavedRegister(unsigned reg, const TargetRegisterInfo &TRI,
486 const MachineFunction &MF) {
487 const MCPhysReg *CSR = TRI.getCalleeSavedRegs(&MF);
488 for (unsigned i = 0; CSR[i] != 0; ++i)
489 if (TRI.regsOverlap(reg, CSR[i]))
494 void RegAllocPBQP::initializeGraph(PBQPRAGraph &G, VirtRegMap &VRM,
495 Spiller &VRegSpiller) {
496 MachineFunction &MF = G.getMetadata().MF;
498 LiveIntervals &LIS = G.getMetadata().LIS;
499 const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
500 const TargetRegisterInfo &TRI =
501 *G.getMetadata().MF.getSubtarget().getRegisterInfo();
503 std::vector<unsigned> Worklist(VRegsToAlloc.begin(), VRegsToAlloc.end());
505 while (!Worklist.empty()) {
506 unsigned VReg = Worklist.back();
509 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
510 LiveInterval &VRegLI = LIS.getInterval(VReg);
512 // Record any overlaps with regmask operands.
513 BitVector RegMaskOverlaps;
514 LIS.checkRegMaskInterference(VRegLI, RegMaskOverlaps);
516 // Compute an initial allowed set for the current vreg.
517 std::vector<unsigned> VRegAllowed;
518 ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF);
519 for (unsigned I = 0; I != RawPRegOrder.size(); ++I) {
520 unsigned PReg = RawPRegOrder[I];
521 if (MRI.isReserved(PReg))
524 // vregLI crosses a regmask operand that clobbers preg.
525 if (!RegMaskOverlaps.empty() && !RegMaskOverlaps.test(PReg))
528 // vregLI overlaps fixed regunit interference.
529 bool Interference = false;
530 for (MCRegUnitIterator Units(PReg, &TRI); Units.isValid(); ++Units) {
531 if (VRegLI.overlaps(LIS.getRegUnit(*Units))) {
539 // preg is usable for this virtual register.
540 VRegAllowed.push_back(PReg);
543 // Check for vregs that have no allowed registers. These should be
544 // pre-spilled and the new vregs added to the worklist.
545 if (VRegAllowed.empty()) {
546 SmallVector<unsigned, 8> NewVRegs;
547 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller);
548 for (auto NewVReg : NewVRegs)
549 Worklist.push_back(NewVReg);
553 PBQPRAGraph::RawVector NodeCosts(VRegAllowed.size() + 1, 0);
555 // Tweak cost of callee saved registers, as using then force spilling and
556 // restoring them. This would only happen in the prologue / epilogue though.
557 for (unsigned i = 0; i != VRegAllowed.size(); ++i)
558 if (isACalleeSavedRegister(VRegAllowed[i], TRI, MF))
559 NodeCosts[1 + i] += 1.0;
561 PBQPRAGraph::NodeId NId = G.addNode(std::move(NodeCosts));
562 G.getNodeMetadata(NId).setVReg(VReg);
563 G.getNodeMetadata(NId).setAllowedRegs(
564 G.getMetadata().getAllowedRegs(std::move(VRegAllowed)));
565 G.getMetadata().setNodeIdForVReg(VReg, NId);
569 void RegAllocPBQP::spillVReg(unsigned VReg,
570 SmallVectorImpl<unsigned> &NewIntervals,
571 MachineFunction &MF, LiveIntervals &LIS,
572 VirtRegMap &VRM, Spiller &VRegSpiller) {
574 VRegsToAlloc.erase(VReg);
575 LiveRangeEdit LRE(&LIS.getInterval(VReg), NewIntervals, MF, LIS, &VRM);
576 VRegSpiller.spill(LRE);
578 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
580 DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> SPILLED (Cost: "
581 << LRE.getParent().weight << ", New vregs: ");
583 // Copy any newly inserted live intervals into the list of regs to
585 for (LiveRangeEdit::iterator I = LRE.begin(), E = LRE.end();
587 const LiveInterval &LI = LIS.getInterval(*I);
588 assert(!LI.empty() && "Empty spill range.");
589 DEBUG(dbgs() << PrintReg(LI.reg, &TRI) << " ");
590 VRegsToAlloc.insert(LI.reg);
593 DEBUG(dbgs() << ")\n");
596 bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAGraph &G,
597 const PBQP::Solution &Solution,
599 Spiller &VRegSpiller) {
600 MachineFunction &MF = G.getMetadata().MF;
601 LiveIntervals &LIS = G.getMetadata().LIS;
602 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
605 // Set to true if we have any spills
606 bool AnotherRoundNeeded = false;
608 // Clear the existing allocation.
611 // Iterate over the nodes mapping the PBQP solution to a register
613 for (auto NId : G.nodeIds()) {
614 unsigned VReg = G.getNodeMetadata(NId).getVReg();
615 unsigned AllocOption = Solution.getSelection(NId);
617 if (AllocOption != PBQP::RegAlloc::getSpillOptionIdx()) {
618 unsigned PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOption - 1];
619 DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> "
620 << TRI.getName(PReg) << "\n");
621 assert(PReg != 0 && "Invalid preg selected.");
622 VRM.assignVirt2Phys(VReg, PReg);
624 // Spill VReg. If this introduces new intervals we'll need another round
626 SmallVector<unsigned, 8> NewVRegs;
627 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller);
628 AnotherRoundNeeded |= !NewVRegs.empty();
632 return !AnotherRoundNeeded;
635 void RegAllocPBQP::finalizeAlloc(MachineFunction &MF,
637 VirtRegMap &VRM) const {
638 MachineRegisterInfo &MRI = MF.getRegInfo();
640 // First allocate registers for the empty intervals.
641 for (RegSet::const_iterator
642 I = EmptyIntervalVRegs.begin(), E = EmptyIntervalVRegs.end();
644 LiveInterval &LI = LIS.getInterval(*I);
646 unsigned PReg = MRI.getSimpleHint(LI.reg);
649 const TargetRegisterClass &RC = *MRI.getRegClass(LI.reg);
650 PReg = RC.getRawAllocationOrder(MF).front();
653 VRM.assignVirt2Phys(LI.reg, PReg);
657 static inline float normalizePBQPSpillWeight(float UseDefFreq, unsigned Size,
659 // All intervals have a spill weight that is mostly proportional to the number
660 // of uses, with uses in loops having a bigger weight.
661 return NumInstr * normalizeSpillWeight(UseDefFreq, Size, 1);
664 bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
665 LiveIntervals &LIS = getAnalysis<LiveIntervals>();
666 MachineBlockFrequencyInfo &MBFI =
667 getAnalysis<MachineBlockFrequencyInfo>();
669 calculateSpillWeightsAndHints(LIS, MF, getAnalysis<MachineLoopInfo>(), MBFI,
670 normalizePBQPSpillWeight);
672 VirtRegMap &VRM = getAnalysis<VirtRegMap>();
674 std::unique_ptr<Spiller> VRegSpiller(createInlineSpiller(*this, MF, VRM));
676 MF.getRegInfo().freezeReservedRegs(MF);
678 DEBUG(dbgs() << "PBQP Register Allocating for " << MF.getName() << "\n");
680 // Allocator main loop:
682 // * Map current regalloc problem to a PBQP problem
683 // * Solve the PBQP problem
684 // * Map the solution back to a register allocation
685 // * Spill if necessary
687 // This process is continued till no more spills are generated.
689 // Find the vreg intervals in need of allocation.
690 findVRegIntervalsToAlloc(MF, LIS);
693 const Function &F = *MF.getFunction();
694 std::string FullyQualifiedName =
695 F.getParent()->getModuleIdentifier() + "." + F.getName().str();
698 // If there are non-empty intervals allocate them using pbqp.
699 if (!VRegsToAlloc.empty()) {
701 const TargetSubtargetInfo &Subtarget = MF.getSubtarget();
702 std::unique_ptr<PBQPRAConstraintList> ConstraintsRoot =
703 llvm::make_unique<PBQPRAConstraintList>();
704 ConstraintsRoot->addConstraint(llvm::make_unique<SpillCosts>());
705 ConstraintsRoot->addConstraint(llvm::make_unique<Interference>());
707 ConstraintsRoot->addConstraint(llvm::make_unique<Coalescing>());
708 ConstraintsRoot->addConstraint(Subtarget.getCustomPBQPConstraints());
710 bool PBQPAllocComplete = false;
713 while (!PBQPAllocComplete) {
714 DEBUG(dbgs() << " PBQP Regalloc round " << Round << ":\n");
716 PBQPRAGraph G(PBQPRAGraph::GraphMetadata(MF, LIS, MBFI));
717 initializeGraph(G, VRM, *VRegSpiller);
718 ConstraintsRoot->apply(G);
721 if (PBQPDumpGraphs) {
722 std::ostringstream RS;
724 std::string GraphFileName = FullyQualifiedName + "." + RS.str() +
727 raw_fd_ostream OS(GraphFileName, EC, sys::fs::F_Text);
728 DEBUG(dbgs() << "Dumping graph for round " << Round << " to \""
729 << GraphFileName << "\"\n");
734 PBQP::Solution Solution = PBQP::RegAlloc::solve(G);
735 PBQPAllocComplete = mapPBQPToRegAlloc(G, Solution, VRM, *VRegSpiller);
740 // Finalise allocation, allocate empty ranges.
741 finalizeAlloc(MF, LIS, VRM);
742 VRegsToAlloc.clear();
743 EmptyIntervalVRegs.clear();
745 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << VRM << "\n");
751 // A Helper class for print node and register info in a consistent way
752 class PrintNodeInfo {
754 typedef PBQP::RegAlloc::PBQPRAGraph Graph;
755 typedef PBQP::RegAlloc::PBQPRAGraph::NodeId NodeId;
757 PrintNodeInfo(NodeId NId, const Graph &G) : G(G), NId(NId) {}
759 void print(raw_ostream &OS) const {
760 const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
761 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
762 unsigned VReg = G.getNodeMetadata(NId).getVReg();
763 const char *RegClassName = TRI->getRegClassName(MRI.getRegClass(VReg));
764 OS << NId << " (" << RegClassName << ':' << PrintReg(VReg, TRI) << ')';
772 inline raw_ostream &operator<<(raw_ostream &OS, const PrintNodeInfo &PR) {
776 } // anonymous namespace
778 void PBQP::RegAlloc::PBQPRAGraph::dump(raw_ostream &OS) const {
779 for (auto NId : nodeIds()) {
780 const Vector &Costs = getNodeCosts(NId);
781 assert(Costs.getLength() != 0 && "Empty vector in graph.");
782 OS << PrintNodeInfo(NId, *this) << ": " << Costs << '\n';
786 for (auto EId : edgeIds()) {
787 NodeId N1Id = getEdgeNode1Id(EId);
788 NodeId N2Id = getEdgeNode2Id(EId);
789 assert(N1Id != N2Id && "PBQP graphs should not have self-edges.");
790 const Matrix &M = getEdgeCosts(EId);
791 assert(M.getRows() != 0 && "No rows in matrix.");
792 assert(M.getCols() != 0 && "No cols in matrix.");
793 OS << PrintNodeInfo(N1Id, *this) << ' ' << M.getRows() << " rows / ";
794 OS << PrintNodeInfo(N2Id, *this) << ' ' << M.getCols() << " cols:\n";
799 void PBQP::RegAlloc::PBQPRAGraph::dump() const { dump(dbgs()); }
801 void PBQP::RegAlloc::PBQPRAGraph::printDot(raw_ostream &OS) const {
803 for (auto NId : nodeIds()) {
804 OS << " node" << NId << " [ label=\""
805 << PrintNodeInfo(NId, *this) << "\\n"
806 << getNodeCosts(NId) << "\" ]\n";
809 OS << " edge [ len=" << nodeIds().size() << " ]\n";
810 for (auto EId : edgeIds()) {
811 OS << " node" << getEdgeNode1Id(EId)
812 << " -- node" << getEdgeNode2Id(EId)
814 const Matrix &EdgeCosts = getEdgeCosts(EId);
815 for (unsigned i = 0; i < EdgeCosts.getRows(); ++i) {
816 OS << EdgeCosts.getRowAsVector(i) << "\\n";
823 FunctionPass *llvm::createPBQPRegisterAllocator(char *customPassID) {
824 return new RegAllocPBQP(customPassID);
827 FunctionPass* llvm::createDefaultPBQPRegisterAllocator() {
828 return createPBQPRegisterAllocator();