1 //===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
11 // register allocator for LLVM. This allocator works by constructing a PBQP
12 // problem representing the register allocation problem under consideration,
13 // solving this using a PBQP solver, and mapping the solution back to a
14 // register assignment. If any variables are selected for spilling then spill
15 // code is inserted and the process repeated.
17 // The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
18 // for register allocation. For more information on PBQP for register
19 // allocation, see the following papers:
21 // (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
22 // PBQP. In Proceedings of the 7th Joint Modular Languages Conference
23 // (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
25 // (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
26 // architectures. In Proceedings of the Joint Conference on Languages,
27 // Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
30 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "regalloc"
34 #include "LiveRangeEdit.h"
35 #include "RenderMachineFunction.h"
37 #include "VirtRegMap.h"
38 #include "RegisterCoalescer.h"
39 #include "llvm/Analysis/AliasAnalysis.h"
40 #include "llvm/CodeGen/CalcSpillWeights.h"
41 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
42 #include "llvm/CodeGen/LiveStackAnalysis.h"
43 #include "llvm/CodeGen/RegAllocPBQP.h"
44 #include "llvm/CodeGen/MachineDominators.h"
45 #include "llvm/CodeGen/MachineFunctionPass.h"
46 #include "llvm/CodeGen/MachineLoopInfo.h"
47 #include "llvm/CodeGen/MachineRegisterInfo.h"
48 #include "llvm/CodeGen/PBQP/HeuristicSolver.h"
49 #include "llvm/CodeGen/PBQP/Graph.h"
50 #include "llvm/CodeGen/PBQP/Heuristics/Briggs.h"
51 #include "llvm/CodeGen/RegAllocRegistry.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetInstrInfo.h"
55 #include "llvm/Target/TargetMachine.h"
63 static RegisterRegAlloc
64 registerPBQPRepAlloc("pbqp", "PBQP register allocator",
65 createDefaultPBQPRegisterAllocator);
68 pbqpCoalescing("pbqp-coalescing",
69 cl::desc("Attempt coalescing during PBQP register allocation."),
70 cl::init(false), cl::Hidden);
75 /// PBQP based allocators solve the register allocation problem by mapping
76 /// register allocation problems to Partitioned Boolean Quadratic
77 /// Programming problems.
78 class RegAllocPBQP : public MachineFunctionPass {
83 /// Construct a PBQP register allocator.
84 RegAllocPBQP(std::auto_ptr<PBQPBuilder> b, char *cPassID=0)
85 : MachineFunctionPass(ID), builder(b), customPassID(cPassID) {
86 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
87 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
88 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
89 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
90 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
91 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
92 initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry());
95 /// Return the pass name.
96 virtual const char* getPassName() const {
97 return "PBQP Register Allocator";
100 /// PBQP analysis usage.
101 virtual void getAnalysisUsage(AnalysisUsage &au) const;
103 /// Perform register allocation
104 virtual bool runOnMachineFunction(MachineFunction &MF);
108 typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
109 typedef std::vector<const LiveInterval*> Node2LIMap;
110 typedef std::vector<unsigned> AllowedSet;
111 typedef std::vector<AllowedSet> AllowedSetMap;
112 typedef std::pair<unsigned, unsigned> RegPair;
113 typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;
114 typedef std::vector<PBQP::Graph::NodeItr> NodeVector;
115 typedef std::set<unsigned> RegSet;
118 std::auto_ptr<PBQPBuilder> builder;
123 const TargetMachine *tm;
124 const TargetRegisterInfo *tri;
125 const TargetInstrInfo *tii;
126 const MachineLoopInfo *loopInfo;
127 MachineRegisterInfo *mri;
128 RenderMachineFunction *rmf;
130 std::auto_ptr<Spiller> spiller;
135 RegSet vregsToAlloc, emptyIntervalVRegs;
137 /// \brief Finds the initial set of vreg intervals to allocate.
138 void findVRegIntervalsToAlloc();
140 /// \brief Given a solved PBQP problem maps this solution back to a register
142 bool mapPBQPToRegAlloc(const PBQPRAProblem &problem,
143 const PBQP::Solution &solution);
145 /// \brief Postprocessing before final spilling. Sets basic block "live in"
147 void finalizeAlloc() const;
151 char RegAllocPBQP::ID = 0;
153 } // End anonymous namespace.
155 unsigned PBQPRAProblem::getVRegForNode(PBQP::Graph::ConstNodeItr node) const {
156 Node2VReg::const_iterator vregItr = node2VReg.find(node);
157 assert(vregItr != node2VReg.end() && "No vreg for node.");
158 return vregItr->second;
161 PBQP::Graph::NodeItr PBQPRAProblem::getNodeForVReg(unsigned vreg) const {
162 VReg2Node::const_iterator nodeItr = vreg2Node.find(vreg);
163 assert(nodeItr != vreg2Node.end() && "No node for vreg.");
164 return nodeItr->second;
168 const PBQPRAProblem::AllowedSet&
169 PBQPRAProblem::getAllowedSet(unsigned vreg) const {
170 AllowedSetMap::const_iterator allowedSetItr = allowedSets.find(vreg);
171 assert(allowedSetItr != allowedSets.end() && "No pregs for vreg.");
172 const AllowedSet &allowedSet = allowedSetItr->second;
176 unsigned PBQPRAProblem::getPRegForOption(unsigned vreg, unsigned option) const {
177 assert(isPRegOption(vreg, option) && "Not a preg option.");
179 const AllowedSet& allowedSet = getAllowedSet(vreg);
180 assert(option <= allowedSet.size() && "Option outside allowed set.");
181 return allowedSet[option - 1];
184 std::auto_ptr<PBQPRAProblem> PBQPBuilder::build(MachineFunction *mf,
185 const LiveIntervals *lis,
186 const MachineLoopInfo *loopInfo,
187 const RegSet &vregs) {
189 typedef std::vector<const LiveInterval*> LIVector;
191 MachineRegisterInfo *mri = &mf->getRegInfo();
192 const TargetRegisterInfo *tri = mf->getTarget().getRegisterInfo();
194 std::auto_ptr<PBQPRAProblem> p(new PBQPRAProblem());
195 PBQP::Graph &g = p->getGraph();
198 // Collect the set of preg intervals, record that they're used in the MF.
199 for (LiveIntervals::const_iterator itr = lis->begin(), end = lis->end();
201 if (TargetRegisterInfo::isPhysicalRegister(itr->first)) {
202 pregs.insert(itr->first);
203 mri->setPhysRegUsed(itr->first);
207 BitVector reservedRegs = tri->getReservedRegs(*mf);
209 // Iterate over vregs.
210 for (RegSet::const_iterator vregItr = vregs.begin(), vregEnd = vregs.end();
211 vregItr != vregEnd; ++vregItr) {
212 unsigned vreg = *vregItr;
213 const TargetRegisterClass *trc = mri->getRegClass(vreg);
214 const LiveInterval *vregLI = &lis->getInterval(vreg);
216 // Compute an initial allowed set for the current vreg.
217 typedef std::vector<unsigned> VRAllowed;
219 ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(*mf);
220 for (unsigned i = 0; i != rawOrder.size(); ++i) {
221 unsigned preg = rawOrder[i];
222 if (!reservedRegs.test(preg)) {
223 vrAllowed.push_back(preg);
227 // Remove any physical registers which overlap.
228 for (RegSet::const_iterator pregItr = pregs.begin(),
229 pregEnd = pregs.end();
230 pregItr != pregEnd; ++pregItr) {
231 unsigned preg = *pregItr;
232 const LiveInterval *pregLI = &lis->getInterval(preg);
234 if (pregLI->empty()) {
238 if (!vregLI->overlaps(*pregLI)) {
242 // Remove the register from the allowed set.
243 VRAllowed::iterator eraseItr =
244 std::find(vrAllowed.begin(), vrAllowed.end(), preg);
246 if (eraseItr != vrAllowed.end()) {
247 vrAllowed.erase(eraseItr);
250 // Also remove any aliases.
251 const uint16_t *aliasItr = tri->getAliasSet(preg);
253 for (; *aliasItr != 0; ++aliasItr) {
254 VRAllowed::iterator eraseItr =
255 std::find(vrAllowed.begin(), vrAllowed.end(), *aliasItr);
257 if (eraseItr != vrAllowed.end()) {
258 vrAllowed.erase(eraseItr);
264 // Construct the node.
265 PBQP::Graph::NodeItr node =
266 g.addNode(PBQP::Vector(vrAllowed.size() + 1, 0));
268 // Record the mapping and allowed set in the problem.
269 p->recordVReg(vreg, node, vrAllowed.begin(), vrAllowed.end());
271 PBQP::PBQPNum spillCost = (vregLI->weight != 0.0) ?
272 vregLI->weight : std::numeric_limits<PBQP::PBQPNum>::min();
274 addSpillCosts(g.getNodeCosts(node), spillCost);
277 for (RegSet::const_iterator vr1Itr = vregs.begin(), vrEnd = vregs.end();
278 vr1Itr != vrEnd; ++vr1Itr) {
279 unsigned vr1 = *vr1Itr;
280 const LiveInterval &l1 = lis->getInterval(vr1);
281 const PBQPRAProblem::AllowedSet &vr1Allowed = p->getAllowedSet(vr1);
283 for (RegSet::const_iterator vr2Itr = llvm::next(vr1Itr);
284 vr2Itr != vrEnd; ++vr2Itr) {
285 unsigned vr2 = *vr2Itr;
286 const LiveInterval &l2 = lis->getInterval(vr2);
287 const PBQPRAProblem::AllowedSet &vr2Allowed = p->getAllowedSet(vr2);
289 assert(!l2.empty() && "Empty interval in vreg set?");
290 if (l1.overlaps(l2)) {
291 PBQP::Graph::EdgeItr edge =
292 g.addEdge(p->getNodeForVReg(vr1), p->getNodeForVReg(vr2),
293 PBQP::Matrix(vr1Allowed.size()+1, vr2Allowed.size()+1, 0));
295 addInterferenceCosts(g.getEdgeCosts(edge), vr1Allowed, vr2Allowed, tri);
303 void PBQPBuilder::addSpillCosts(PBQP::Vector &costVec,
304 PBQP::PBQPNum spillCost) {
305 costVec[0] = spillCost;
308 void PBQPBuilder::addInterferenceCosts(
309 PBQP::Matrix &costMat,
310 const PBQPRAProblem::AllowedSet &vr1Allowed,
311 const PBQPRAProblem::AllowedSet &vr2Allowed,
312 const TargetRegisterInfo *tri) {
313 assert(costMat.getRows() == vr1Allowed.size() + 1 && "Matrix height mismatch.");
314 assert(costMat.getCols() == vr2Allowed.size() + 1 && "Matrix width mismatch.");
316 for (unsigned i = 0; i != vr1Allowed.size(); ++i) {
317 unsigned preg1 = vr1Allowed[i];
319 for (unsigned j = 0; j != vr2Allowed.size(); ++j) {
320 unsigned preg2 = vr2Allowed[j];
322 if (tri->regsOverlap(preg1, preg2)) {
323 costMat[i + 1][j + 1] = std::numeric_limits<PBQP::PBQPNum>::infinity();
329 std::auto_ptr<PBQPRAProblem> PBQPBuilderWithCoalescing::build(
331 const LiveIntervals *lis,
332 const MachineLoopInfo *loopInfo,
333 const RegSet &vregs) {
335 std::auto_ptr<PBQPRAProblem> p = PBQPBuilder::build(mf, lis, loopInfo, vregs);
336 PBQP::Graph &g = p->getGraph();
338 const TargetMachine &tm = mf->getTarget();
339 CoalescerPair cp(*tm.getInstrInfo(), *tm.getRegisterInfo());
341 // Scan the machine function and add a coalescing cost whenever CoalescerPair
343 for (MachineFunction::const_iterator mbbItr = mf->begin(),
345 mbbItr != mbbEnd; ++mbbItr) {
346 const MachineBasicBlock *mbb = &*mbbItr;
348 for (MachineBasicBlock::const_iterator miItr = mbb->begin(),
350 miItr != miEnd; ++miItr) {
351 const MachineInstr *mi = &*miItr;
353 if (!cp.setRegisters(mi)) {
354 continue; // Not coalescable.
357 if (cp.getSrcReg() == cp.getDstReg()) {
358 continue; // Already coalesced.
361 unsigned dst = cp.getDstReg(),
362 src = cp.getSrcReg();
364 const float copyFactor = 0.5; // Cost of copy relative to load. Current
365 // value plucked randomly out of the air.
367 PBQP::PBQPNum cBenefit =
368 copyFactor * LiveIntervals::getSpillWeight(false, true,
369 loopInfo->getLoopDepth(mbb));
372 if (!lis->isAllocatable(dst)) {
376 const PBQPRAProblem::AllowedSet &allowed = p->getAllowedSet(src);
377 unsigned pregOpt = 0;
378 while (pregOpt < allowed.size() && allowed[pregOpt] != dst) {
381 if (pregOpt < allowed.size()) {
382 ++pregOpt; // +1 to account for spill option.
383 PBQP::Graph::NodeItr node = p->getNodeForVReg(src);
384 addPhysRegCoalesce(g.getNodeCosts(node), pregOpt, cBenefit);
387 const PBQPRAProblem::AllowedSet *allowed1 = &p->getAllowedSet(dst);
388 const PBQPRAProblem::AllowedSet *allowed2 = &p->getAllowedSet(src);
389 PBQP::Graph::NodeItr node1 = p->getNodeForVReg(dst);
390 PBQP::Graph::NodeItr node2 = p->getNodeForVReg(src);
391 PBQP::Graph::EdgeItr edge = g.findEdge(node1, node2);
392 if (edge == g.edgesEnd()) {
393 edge = g.addEdge(node1, node2, PBQP::Matrix(allowed1->size() + 1,
394 allowed2->size() + 1,
397 if (g.getEdgeNode1(edge) == node2) {
398 std::swap(node1, node2);
399 std::swap(allowed1, allowed2);
403 addVirtRegCoalesce(g.getEdgeCosts(edge), *allowed1, *allowed2,
412 void PBQPBuilderWithCoalescing::addPhysRegCoalesce(PBQP::Vector &costVec,
414 PBQP::PBQPNum benefit) {
415 costVec[pregOption] += -benefit;
418 void PBQPBuilderWithCoalescing::addVirtRegCoalesce(
419 PBQP::Matrix &costMat,
420 const PBQPRAProblem::AllowedSet &vr1Allowed,
421 const PBQPRAProblem::AllowedSet &vr2Allowed,
422 PBQP::PBQPNum benefit) {
424 assert(costMat.getRows() == vr1Allowed.size() + 1 && "Size mismatch.");
425 assert(costMat.getCols() == vr2Allowed.size() + 1 && "Size mismatch.");
427 for (unsigned i = 0; i != vr1Allowed.size(); ++i) {
428 unsigned preg1 = vr1Allowed[i];
429 for (unsigned j = 0; j != vr2Allowed.size(); ++j) {
430 unsigned preg2 = vr2Allowed[j];
432 if (preg1 == preg2) {
433 costMat[i + 1][j + 1] += -benefit;
440 void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
441 au.setPreservesCFG();
442 au.addRequired<AliasAnalysis>();
443 au.addPreserved<AliasAnalysis>();
444 au.addRequired<SlotIndexes>();
445 au.addPreserved<SlotIndexes>();
446 au.addRequired<LiveIntervals>();
447 //au.addRequiredID(SplitCriticalEdgesID);
449 au.addRequiredID(*customPassID);
450 au.addRequired<CalculateSpillWeights>();
451 au.addRequired<LiveStacks>();
452 au.addPreserved<LiveStacks>();
453 au.addRequired<MachineDominatorTree>();
454 au.addPreserved<MachineDominatorTree>();
455 au.addRequired<MachineLoopInfo>();
456 au.addPreserved<MachineLoopInfo>();
457 au.addRequired<VirtRegMap>();
458 au.addRequired<RenderMachineFunction>();
459 MachineFunctionPass::getAnalysisUsage(au);
462 void RegAllocPBQP::findVRegIntervalsToAlloc() {
464 // Iterate over all live ranges.
465 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end();
468 // Ignore physical ones.
469 if (TargetRegisterInfo::isPhysicalRegister(itr->first))
472 LiveInterval *li = itr->second;
474 // If this live interval is non-empty we will use pbqp to allocate it.
475 // Empty intervals we allocate in a simple post-processing stage in
478 vregsToAlloc.insert(li->reg);
480 emptyIntervalVRegs.insert(li->reg);
485 bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAProblem &problem,
486 const PBQP::Solution &solution) {
487 // Set to true if we have any spills
488 bool anotherRoundNeeded = false;
490 // Clear the existing allocation.
493 const PBQP::Graph &g = problem.getGraph();
494 // Iterate over the nodes mapping the PBQP solution to a register
496 for (PBQP::Graph::ConstNodeItr node = g.nodesBegin(),
497 nodeEnd = g.nodesEnd();
498 node != nodeEnd; ++node) {
499 unsigned vreg = problem.getVRegForNode(node);
500 unsigned alloc = solution.getSelection(node);
502 if (problem.isPRegOption(vreg, alloc)) {
503 unsigned preg = problem.getPRegForOption(vreg, alloc);
504 DEBUG(dbgs() << "VREG " << vreg << " -> " << tri->getName(preg) << "\n");
505 assert(preg != 0 && "Invalid preg selected.");
506 vrm->assignVirt2Phys(vreg, preg);
507 } else if (problem.isSpillOption(vreg, alloc)) {
508 vregsToAlloc.erase(vreg);
509 SmallVector<LiveInterval*, 8> newSpills;
510 LiveRangeEdit LRE(lis->getInterval(vreg), newSpills);
513 DEBUG(dbgs() << "VREG " << vreg << " -> SPILLED (Cost: "
514 << LRE.getParent().weight << ", New vregs: ");
516 // Copy any newly inserted live intervals into the list of regs to
518 for (LiveRangeEdit::iterator itr = LRE.begin(), end = LRE.end();
520 assert(!(*itr)->empty() && "Empty spill range.");
521 DEBUG(dbgs() << (*itr)->reg << " ");
522 vregsToAlloc.insert((*itr)->reg);
525 DEBUG(dbgs() << ")\n");
527 // We need another round if spill intervals were added.
528 anotherRoundNeeded |= !LRE.empty();
530 llvm_unreachable("Unknown allocation option.");
534 return !anotherRoundNeeded;
538 void RegAllocPBQP::finalizeAlloc() const {
539 typedef LiveIntervals::iterator LIIterator;
540 typedef LiveInterval::Ranges::const_iterator LRIterator;
542 // First allocate registers for the empty intervals.
543 for (RegSet::const_iterator
544 itr = emptyIntervalVRegs.begin(), end = emptyIntervalVRegs.end();
546 LiveInterval *li = &lis->getInterval(*itr);
548 unsigned physReg = vrm->getRegAllocPref(li->reg);
551 const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
552 physReg = liRC->getRawAllocationOrder(*mf).front();
555 vrm->assignVirt2Phys(li->reg, physReg);
558 // Finally iterate over the basic blocks to compute and set the live-in sets.
559 SmallVector<MachineBasicBlock*, 8> liveInMBBs;
560 MachineBasicBlock *entryMBB = &*mf->begin();
562 for (LIIterator liItr = lis->begin(), liEnd = lis->end();
563 liItr != liEnd; ++liItr) {
565 const LiveInterval *li = liItr->second;
568 // Get the physical register for this interval
569 if (TargetRegisterInfo::isPhysicalRegister(li->reg)) {
571 } else if (vrm->isAssignedReg(li->reg)) {
572 reg = vrm->getPhys(li->reg);
574 // Ranges which are assigned a stack slot only are ignored.
579 // Filter out zero regs - they're for intervals that were spilled.
583 // Iterate over the ranges of the current interval...
584 for (LRIterator lrItr = li->begin(), lrEnd = li->end();
585 lrItr != lrEnd; ++lrItr) {
587 // Find the set of basic blocks which this range is live into...
588 if (lis->findLiveInMBBs(lrItr->start, lrItr->end, liveInMBBs)) {
589 // And add the physreg for this interval to their live-in sets.
590 for (unsigned i = 0; i != liveInMBBs.size(); ++i) {
591 if (liveInMBBs[i] != entryMBB) {
592 if (!liveInMBBs[i]->isLiveIn(reg)) {
593 liveInMBBs[i]->addLiveIn(reg);
604 bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
607 tm = &mf->getTarget();
608 tri = tm->getRegisterInfo();
609 tii = tm->getInstrInfo();
610 mri = &mf->getRegInfo();
612 lis = &getAnalysis<LiveIntervals>();
613 lss = &getAnalysis<LiveStacks>();
614 loopInfo = &getAnalysis<MachineLoopInfo>();
615 rmf = &getAnalysis<RenderMachineFunction>();
617 vrm = &getAnalysis<VirtRegMap>();
618 spiller.reset(createInlineSpiller(*this, MF, *vrm));
620 mri->freezeReservedRegs(MF);
622 DEBUG(dbgs() << "PBQP Register Allocating for " << mf->getFunction()->getName() << "\n");
624 // Allocator main loop:
626 // * Map current regalloc problem to a PBQP problem
627 // * Solve the PBQP problem
628 // * Map the solution back to a register allocation
629 // * Spill if necessary
631 // This process is continued till no more spills are generated.
633 // Find the vreg intervals in need of allocation.
634 findVRegIntervalsToAlloc();
636 // If there are non-empty intervals allocate them using pbqp.
637 if (!vregsToAlloc.empty()) {
639 bool pbqpAllocComplete = false;
642 while (!pbqpAllocComplete) {
643 DEBUG(dbgs() << " PBQP Regalloc round " << round << ":\n");
645 std::auto_ptr<PBQPRAProblem> problem =
646 builder->build(mf, lis, loopInfo, vregsToAlloc);
647 PBQP::Solution solution =
648 PBQP::HeuristicSolver<PBQP::Heuristics::Briggs>::solve(
649 problem->getGraph());
651 pbqpAllocComplete = mapPBQPToRegAlloc(*problem, solution);
657 // Finalise allocation, allocate empty ranges.
660 rmf->renderMachineFunction("After PBQP register allocation.", vrm);
662 vregsToAlloc.clear();
663 emptyIntervalVRegs.clear();
665 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *vrm << "\n");
668 vrm->rewrite(lis->getSlotIndexes());
670 // All machine operands and other references to virtual registers have been
671 // replaced. Remove the virtual registers.
673 mri->clearVirtRegs();
678 FunctionPass* llvm::createPBQPRegisterAllocator(
679 std::auto_ptr<PBQPBuilder> builder,
680 char *customPassID) {
681 return new RegAllocPBQP(builder, customPassID);
684 FunctionPass* llvm::createDefaultPBQPRegisterAllocator() {
685 if (pbqpCoalescing) {
686 return createPBQPRegisterAllocator(
687 std::auto_ptr<PBQPBuilder>(new PBQPBuilderWithCoalescing()));
689 return createPBQPRegisterAllocator(
690 std::auto_ptr<PBQPBuilder>(new PBQPBuilder()));