1 //===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
11 // register allocator for LLVM. This allocator works by constructing a PBQP
12 // problem representing the register allocation problem under consideration,
13 // solving this using a PBQP solver, and mapping the solution back to a
14 // register assignment. If any variables are selected for spilling then spill
15 // code is inserted and the process repeated.
17 // The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
18 // for register allocation. For more information on PBQP for register
19 // allocation, see the following papers:
21 // (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
22 // PBQP. In Proceedings of the 7th Joint Modular Languages Conference
23 // (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
25 // (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
26 // architectures. In Proceedings of the Joint Conference on Languages,
27 // Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
30 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "regalloc"
34 #include "PBQP/HeuristicSolver.h"
35 #include "PBQP/Graph.h"
36 #include "PBQP/Heuristics/Briggs.h"
37 #include "VirtRegMap.h"
38 #include "VirtRegRewriter.h"
39 #include "llvm/CodeGen/CalcSpillWeights.h"
40 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
41 #include "llvm/CodeGen/LiveStackAnalysis.h"
42 #include "llvm/CodeGen/MachineFunctionPass.h"
43 #include "llvm/CodeGen/MachineLoopInfo.h"
44 #include "llvm/CodeGen/MachineRegisterInfo.h"
45 #include "llvm/CodeGen/RegAllocRegistry.h"
46 #include "llvm/CodeGen/RegisterCoalescer.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetMachine.h"
59 static RegisterRegAlloc
60 registerPBQPRepAlloc("pbqp", "PBQP register allocator",
61 llvm::createPBQPRegisterAllocator);
64 pbqpCoalescing("pbqp-coalescing",
65 cl::desc("Attempt coalescing during PBQP register allocation."),
66 cl::init(false), cl::Hidden);
71 /// PBQP based allocators solve the register allocation problem by mapping
72 /// register allocation problems to Partitioned Boolean Quadratic
73 /// Programming problems.
74 class PBQPRegAlloc : public MachineFunctionPass {
79 /// Construct a PBQP register allocator.
80 PBQPRegAlloc() : MachineFunctionPass(&ID) {}
82 /// Return the pass name.
83 virtual const char* getPassName() const {
84 return "PBQP Register Allocator";
87 /// PBQP analysis usage.
88 virtual void getAnalysisUsage(AnalysisUsage &au) const {
89 au.addRequired<SlotIndexes>();
90 au.addPreserved<SlotIndexes>();
91 au.addRequired<LiveIntervals>();
92 //au.addRequiredID(SplitCriticalEdgesID);
93 au.addRequired<RegisterCoalescer>();
94 au.addRequired<CalculateSpillWeights>();
95 au.addRequired<LiveStacks>();
96 au.addPreserved<LiveStacks>();
97 au.addRequired<MachineLoopInfo>();
98 au.addPreserved<MachineLoopInfo>();
99 au.addRequired<VirtRegMap>();
100 MachineFunctionPass::getAnalysisUsage(au);
103 /// Perform register allocation
104 virtual bool runOnMachineFunction(MachineFunction &MF);
110 bool operator()(const LiveInterval *li1, const LiveInterval *li2) const {
111 return li1->reg < li2->reg;
115 typedef std::map<const LiveInterval*, unsigned, LIOrdering> LI2NodeMap;
116 typedef std::vector<const LiveInterval*> Node2LIMap;
117 typedef std::vector<unsigned> AllowedSet;
118 typedef std::vector<AllowedSet> AllowedSetMap;
119 typedef std::set<unsigned> RegSet;
120 typedef std::pair<unsigned, unsigned> RegPair;
121 typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;
123 typedef std::set<LiveInterval*, LIOrdering> LiveIntervalSet;
125 typedef std::vector<PBQP::Graph::NodeItr> NodeVector;
128 const TargetMachine *tm;
129 const TargetRegisterInfo *tri;
130 const TargetInstrInfo *tii;
131 const MachineLoopInfo *loopInfo;
132 MachineRegisterInfo *mri;
140 AllowedSetMap allowedSets;
141 LiveIntervalSet vregIntervalsToAlloc,
143 NodeVector problemNodes;
146 /// Builds a PBQP cost vector.
147 template <typename RegContainer>
148 PBQP::Vector buildCostVector(unsigned vReg,
149 const RegContainer &allowed,
150 const CoalesceMap &cealesces,
151 PBQP::PBQPNum spillCost) const;
153 /// \brief Builds a PBQP interference matrix.
155 /// @return Either a pointer to a non-zero PBQP matrix representing the
156 /// allocation option costs, or a null pointer for a zero matrix.
158 /// Expects allowed sets for two interfering LiveIntervals. These allowed
159 /// sets should contain only allocable registers from the LiveInterval's
160 /// register class, with any interfering pre-colored registers removed.
161 template <typename RegContainer>
162 PBQP::Matrix* buildInterferenceMatrix(const RegContainer &allowed1,
163 const RegContainer &allowed2) const;
166 /// Expects allowed sets for two potentially coalescable LiveIntervals,
167 /// and an estimated benefit due to coalescing. The allowed sets should
168 /// contain only allocable registers from the LiveInterval's register
169 /// classes, with any interfering pre-colored registers removed.
170 template <typename RegContainer>
171 PBQP::Matrix* buildCoalescingMatrix(const RegContainer &allowed1,
172 const RegContainer &allowed2,
173 PBQP::PBQPNum cBenefit) const;
175 /// \brief Finds coalescing opportunities and returns them as a map.
177 /// Any entries in the map are guaranteed coalescable, even if their
178 /// corresponding live intervals overlap.
179 CoalesceMap findCoalesces();
181 /// \brief Finds the initial set of vreg intervals to allocate.
182 void findVRegIntervalsToAlloc();
184 /// \brief Constructs a PBQP problem representation of the register
185 /// allocation problem for this function.
187 /// @return a PBQP solver object for the register allocation problem.
188 PBQP::Graph constructPBQPProblem();
190 /// \brief Adds a stack interval if the given live interval has been
191 /// spilled. Used to support stack slot coloring.
192 void addStackInterval(const LiveInterval *spilled,MachineRegisterInfo* mri);
194 /// \brief Given a solved PBQP problem maps this solution back to a register
196 bool mapPBQPToRegAlloc(const PBQP::Solution &solution);
198 /// \brief Postprocessing before final spilling. Sets basic block "live in"
200 void finalizeAlloc() const;
204 char PBQPRegAlloc::ID = 0;
208 template <typename RegContainer>
209 PBQP::Vector PBQPRegAlloc::buildCostVector(unsigned vReg,
210 const RegContainer &allowed,
211 const CoalesceMap &coalesces,
212 PBQP::PBQPNum spillCost) const {
214 typedef typename RegContainer::const_iterator AllowedItr;
216 // Allocate vector. Additional element (0th) used for spill option
217 PBQP::Vector v(allowed.size() + 1, 0);
221 // Iterate over the allowed registers inserting coalesce benefits if there
224 for (AllowedItr itr = allowed.begin(), end = allowed.end();
225 itr != end; ++itr, ++ai) {
227 unsigned pReg = *itr;
229 CoalesceMap::const_iterator cmItr =
230 coalesces.find(RegPair(vReg, pReg));
232 // No coalesce - on to the next preg.
233 if (cmItr == coalesces.end())
236 // We have a coalesce - insert the benefit.
237 v[ai + 1] = -cmItr->second;
243 template <typename RegContainer>
244 PBQP::Matrix* PBQPRegAlloc::buildInterferenceMatrix(
245 const RegContainer &allowed1, const RegContainer &allowed2) const {
247 typedef typename RegContainer::const_iterator RegContainerIterator;
249 // Construct a PBQP matrix representing the cost of allocation options. The
250 // rows and columns correspond to the allocation options for the two live
251 // intervals. Elements will be infinite where corresponding registers alias,
252 // since we cannot allocate aliasing registers to interfering live intervals.
253 // All other elements (non-aliasing combinations) will have zero cost. Note
254 // that the spill option (element 0,0) has zero cost, since we can allocate
255 // both intervals to memory safely (the cost for each individual allocation
256 // to memory is accounted for by the cost vectors for each live interval).
258 new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0);
260 // Assume this is a zero matrix until proven otherwise. Zero matrices occur
261 // between interfering live ranges with non-overlapping register sets (e.g.
262 // non-overlapping reg classes, or disjoint sets of allowed regs within the
263 // same class). The term "overlapping" is used advisedly: sets which do not
264 // intersect, but contain registers which alias, will have non-zero matrices.
265 // We optimize zero matrices away to improve solver speed.
266 bool isZeroMatrix = true;
269 // Row index. Starts at 1, since the 0th row is for the spill option, which
273 // Iterate over allowed sets, insert infinities where required.
274 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end();
275 a1Itr != a1End; ++a1Itr) {
277 // Column index, starts at 1 as for row index.
279 unsigned reg1 = *a1Itr;
281 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end();
282 a2Itr != a2End; ++a2Itr) {
284 unsigned reg2 = *a2Itr;
286 // If the row/column regs are identical or alias insert an infinity.
287 if (tri->regsOverlap(reg1, reg2)) {
288 (*m)[ri][ci] = std::numeric_limits<PBQP::PBQPNum>::infinity();
289 isZeroMatrix = false;
298 // If this turns out to be a zero matrix...
300 // free it and return null.
305 // ...otherwise return the cost matrix.
309 template <typename RegContainer>
310 PBQP::Matrix* PBQPRegAlloc::buildCoalescingMatrix(
311 const RegContainer &allowed1, const RegContainer &allowed2,
312 PBQP::PBQPNum cBenefit) const {
314 typedef typename RegContainer::const_iterator RegContainerIterator;
316 // Construct a PBQP Matrix representing the benefits of coalescing. As with
317 // interference matrices the rows and columns represent allowed registers
318 // for the LiveIntervals which are (potentially) to be coalesced. The amount
319 // -cBenefit will be placed in any element representing the same register
320 // for both intervals.
322 new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0);
324 // Reset costs to zero.
327 // Assume the matrix is zero till proven otherwise. Zero matrices will be
328 // optimized away as in the interference case.
329 bool isZeroMatrix = true;
331 // Row index. Starts at 1, since the 0th row is for the spill option, which
335 // Iterate over the allowed sets, insert coalescing benefits where
337 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end();
338 a1Itr != a1End; ++a1Itr) {
340 // Column index, starts at 1 as for row index.
342 unsigned reg1 = *a1Itr;
344 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end();
345 a2Itr != a2End; ++a2Itr) {
347 // If the row and column represent the same register insert a beneficial
348 // cost to preference this allocation - it would allow us to eliminate a
350 if (reg1 == *a2Itr) {
351 (*m)[ri][ci] = -cBenefit;
352 isZeroMatrix = false;
361 // If this turns out to be a zero matrix...
363 // ...free it and return null.
371 PBQPRegAlloc::CoalesceMap PBQPRegAlloc::findCoalesces() {
373 typedef MachineFunction::const_iterator MFIterator;
374 typedef MachineBasicBlock::const_iterator MBBIterator;
375 typedef LiveInterval::const_vni_iterator VNIIterator;
377 CoalesceMap coalescesFound;
379 // To find coalesces we need to iterate over the function looking for
380 // copy instructions.
381 for (MFIterator bbItr = mf->begin(), bbEnd = mf->end();
382 bbItr != bbEnd; ++bbItr) {
384 const MachineBasicBlock *mbb = &*bbItr;
386 for (MBBIterator iItr = mbb->begin(), iEnd = mbb->end();
387 iItr != iEnd; ++iItr) {
389 const MachineInstr *instr = &*iItr;
391 // If this isn't a copy then continue to the next instruction.
392 if (!instr->isCopy())
395 unsigned srcReg = instr->getOperand(1).getReg();
396 unsigned dstReg = instr->getOperand(0).getReg();
398 // If the registers are already the same our job is nice and easy.
399 if (dstReg == srcReg)
402 bool srcRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(srcReg),
403 dstRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(dstReg);
405 // If both registers are physical then we can't coalesce.
406 if (srcRegIsPhysical && dstRegIsPhysical)
409 // If it's a copy that includes two virtual register but the source and
410 // destination classes differ then we can't coalesce.
411 if (!srcRegIsPhysical && !dstRegIsPhysical &&
412 mri->getRegClass(srcReg) != mri->getRegClass(dstReg))
415 // If one is physical and one is virtual, check that the physical is
416 // allocatable in the class of the virtual.
417 if (srcRegIsPhysical && !dstRegIsPhysical) {
418 const TargetRegisterClass *dstRegClass = mri->getRegClass(dstReg);
419 if (std::find(dstRegClass->allocation_order_begin(*mf),
420 dstRegClass->allocation_order_end(*mf), srcReg) ==
421 dstRegClass->allocation_order_end(*mf))
424 if (!srcRegIsPhysical && dstRegIsPhysical) {
425 const TargetRegisterClass *srcRegClass = mri->getRegClass(srcReg);
426 if (std::find(srcRegClass->allocation_order_begin(*mf),
427 srcRegClass->allocation_order_end(*mf), dstReg) ==
428 srcRegClass->allocation_order_end(*mf))
432 // If we've made it here we have a copy with compatible register classes.
433 // We can probably coalesce, but we need to consider overlap.
434 const LiveInterval *srcLI = &lis->getInterval(srcReg),
435 *dstLI = &lis->getInterval(dstReg);
437 if (srcLI->overlaps(*dstLI)) {
438 // Even in the case of an overlap we might still be able to coalesce,
439 // but we need to make sure that no definition of either range occurs
440 // while the other range is live.
442 // Otherwise start by assuming we're ok.
445 // Test all defs of the source range.
447 vniItr = srcLI->vni_begin(), vniEnd = srcLI->vni_end();
448 vniItr != vniEnd; ++vniItr) {
450 // If we find a poorly defined def we err on the side of caution.
451 if (!(*vniItr)->def.isValid()) {
456 // If we find a def that kills the coalescing opportunity then
457 // record it and break from the loop.
458 if (dstLI->liveAt((*vniItr)->def)) {
464 // If we have a bad def give up, continue to the next instruction.
468 // Otherwise test definitions of the destination range.
470 vniItr = dstLI->vni_begin(), vniEnd = dstLI->vni_end();
471 vniItr != vniEnd; ++vniItr) {
473 // We want to make sure we skip the copy instruction itself.
474 if ((*vniItr)->getCopy() == instr)
477 if (!(*vniItr)->def.isValid()) {
482 if (srcLI->liveAt((*vniItr)->def)) {
488 // As before a bad def we give up and continue to the next instr.
493 // If we make it to here then either the ranges didn't overlap, or they
494 // did, but none of their definitions would prevent us from coalescing.
495 // We're good to go with the coalesce.
497 float cBenefit = std::pow(10.0f, (float)loopInfo->getLoopDepth(mbb)) / 5.0;
499 coalescesFound[RegPair(srcReg, dstReg)] = cBenefit;
500 coalescesFound[RegPair(dstReg, srcReg)] = cBenefit;
505 return coalescesFound;
508 void PBQPRegAlloc::findVRegIntervalsToAlloc() {
510 // Iterate over all live ranges.
511 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end();
514 // Ignore physical ones.
515 if (TargetRegisterInfo::isPhysicalRegister(itr->first))
518 LiveInterval *li = itr->second;
520 // If this live interval is non-empty we will use pbqp to allocate it.
521 // Empty intervals we allocate in a simple post-processing stage in
524 vregIntervalsToAlloc.insert(li);
527 emptyVRegIntervals.insert(li);
532 PBQP::Graph PBQPRegAlloc::constructPBQPProblem() {
534 typedef std::vector<const LiveInterval*> LIVector;
535 typedef std::vector<unsigned> RegVector;
537 // This will store the physical intervals for easy reference.
538 LIVector physIntervals;
540 // Start by clearing the old node <-> live interval mappings & allowed sets
545 // Populate physIntervals, update preg use:
546 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end();
549 if (TargetRegisterInfo::isPhysicalRegister(itr->first)) {
550 physIntervals.push_back(itr->second);
551 mri->setPhysRegUsed(itr->second->reg);
555 // Iterate over vreg intervals, construct live interval <-> node number
557 for (LiveIntervalSet::const_iterator
558 itr = vregIntervalsToAlloc.begin(), end = vregIntervalsToAlloc.end();
560 const LiveInterval *li = *itr;
562 li2Node[li] = node2LI.size();
563 node2LI.push_back(li);
566 // Get the set of potential coalesces.
567 CoalesceMap coalesces;
569 if (pbqpCoalescing) {
570 coalesces = findCoalesces();
573 // Construct a PBQP solver for this problem
575 problemNodes.resize(vregIntervalsToAlloc.size());
577 // Resize allowedSets container appropriately.
578 allowedSets.resize(vregIntervalsToAlloc.size());
580 // Iterate over virtual register intervals to compute allowed sets...
581 for (unsigned node = 0; node < node2LI.size(); ++node) {
583 // Grab pointers to the interval and its register class.
584 const LiveInterval *li = node2LI[node];
585 const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
587 // Start by assuming all allocable registers in the class are allowed...
588 RegVector liAllowed(liRC->allocation_order_begin(*mf),
589 liRC->allocation_order_end(*mf));
591 // Eliminate the physical registers which overlap with this range, along
592 // with all their aliases.
593 for (LIVector::iterator pItr = physIntervals.begin(),
594 pEnd = physIntervals.end(); pItr != pEnd; ++pItr) {
596 if (!li->overlaps(**pItr))
599 unsigned pReg = (*pItr)->reg;
601 // If we get here then the live intervals overlap, but we're still ok
602 // if they're coalescable.
603 if (coalesces.find(RegPair(li->reg, pReg)) != coalesces.end())
606 // If we get here then we have a genuine exclusion.
608 // Remove the overlapping reg...
609 RegVector::iterator eraseItr =
610 std::find(liAllowed.begin(), liAllowed.end(), pReg);
612 if (eraseItr != liAllowed.end())
613 liAllowed.erase(eraseItr);
615 const unsigned *aliasItr = tri->getAliasSet(pReg);
618 // ...and its aliases.
619 for (; *aliasItr != 0; ++aliasItr) {
620 RegVector::iterator eraseItr =
621 std::find(liAllowed.begin(), liAllowed.end(), *aliasItr);
623 if (eraseItr != liAllowed.end()) {
624 liAllowed.erase(eraseItr);
630 // Copy the allowed set into a member vector for use when constructing cost
631 // vectors & matrices, and mapping PBQP solutions back to assignments.
632 allowedSets[node] = AllowedSet(liAllowed.begin(), liAllowed.end());
634 // Set the spill cost to the interval weight, or epsilon if the
635 // interval weight is zero
636 PBQP::PBQPNum spillCost = (li->weight != 0.0) ?
637 li->weight : std::numeric_limits<PBQP::PBQPNum>::min();
639 // Build a cost vector for this interval.
642 buildCostVector(li->reg, allowedSets[node], coalesces, spillCost));
647 // Now add the cost matrices...
648 for (unsigned node1 = 0; node1 < node2LI.size(); ++node1) {
649 const LiveInterval *li = node2LI[node1];
651 // Test for live range overlaps and insert interference matrices.
652 for (unsigned node2 = node1 + 1; node2 < node2LI.size(); ++node2) {
653 const LiveInterval *li2 = node2LI[node2];
655 CoalesceMap::const_iterator cmItr =
656 coalesces.find(RegPair(li->reg, li2->reg));
660 if (cmItr != coalesces.end()) {
661 m = buildCoalescingMatrix(allowedSets[node1], allowedSets[node2],
664 else if (li->overlaps(*li2)) {
665 m = buildInterferenceMatrix(allowedSets[node1], allowedSets[node2]);
669 problem.addEdge(problemNodes[node1],
678 assert(problem.getNumNodes() == allowedSets.size());
680 std::cerr << "Allocating for " << problem.getNumNodes() << " nodes, "
681 << problem.getNumEdges() << " edges.\n";
683 problem.printDot(std::cerr);
685 // We're done, PBQP problem constructed - return it.
689 void PBQPRegAlloc::addStackInterval(const LiveInterval *spilled,
690 MachineRegisterInfo* mri) {
691 int stackSlot = vrm->getStackSlot(spilled->reg);
693 if (stackSlot == VirtRegMap::NO_STACK_SLOT)
696 const TargetRegisterClass *RC = mri->getRegClass(spilled->reg);
697 LiveInterval &stackInterval = lss->getOrCreateInterval(stackSlot, RC);
700 if (stackInterval.getNumValNums() != 0)
701 vni = stackInterval.getValNumInfo(0);
703 vni = stackInterval.getNextValue(
704 SlotIndex(), 0, false, lss->getVNInfoAllocator());
706 LiveInterval &rhsInterval = lis->getInterval(spilled->reg);
707 stackInterval.MergeRangesInAsValue(rhsInterval, vni);
710 bool PBQPRegAlloc::mapPBQPToRegAlloc(const PBQP::Solution &solution) {
712 // Set to true if we have any spills
713 bool anotherRoundNeeded = false;
715 // Clear the existing allocation.
718 // Iterate over the nodes mapping the PBQP solution to a register assignment.
719 for (unsigned node = 0; node < node2LI.size(); ++node) {
720 unsigned virtReg = node2LI[node]->reg,
721 allocSelection = solution.getSelection(problemNodes[node]);
724 // If the PBQP solution is non-zero it's a physical register...
725 if (allocSelection != 0) {
726 // Get the physical reg, subtracting 1 to account for the spill option.
727 unsigned physReg = allowedSets[node][allocSelection - 1];
729 DEBUG(dbgs() << "VREG " << virtReg << " -> "
730 << tri->getName(physReg) << "\n");
732 assert(physReg != 0);
734 // Add to the virt reg map and update the used phys regs.
735 vrm->assignVirt2Phys(virtReg, physReg);
737 // ...Otherwise it's a spill.
740 // Make sure we ignore this virtual reg on the next round
742 vregIntervalsToAlloc.erase(&lis->getInterval(virtReg));
744 // Insert spill ranges for this live range
745 const LiveInterval *spillInterval = node2LI[node];
746 double oldSpillWeight = spillInterval->weight;
747 SmallVector<LiveInterval*, 8> spillIs;
748 std::vector<LiveInterval*> newSpills =
749 lis->addIntervalsForSpills(*spillInterval, spillIs, loopInfo, *vrm);
750 addStackInterval(spillInterval, mri);
752 (void) oldSpillWeight;
753 DEBUG(dbgs() << "VREG " << virtReg << " -> SPILLED (Cost: "
754 << oldSpillWeight << ", New vregs: ");
756 // Copy any newly inserted live intervals into the list of regs to
758 for (std::vector<LiveInterval*>::const_iterator
759 itr = newSpills.begin(), end = newSpills.end();
762 assert(!(*itr)->empty() && "Empty spill range.");
764 DEBUG(dbgs() << (*itr)->reg << " ");
766 vregIntervalsToAlloc.insert(*itr);
769 DEBUG(dbgs() << ")\n");
771 // We need another round if spill intervals were added.
772 anotherRoundNeeded |= !newSpills.empty();
776 return !anotherRoundNeeded;
779 void PBQPRegAlloc::finalizeAlloc() const {
780 typedef LiveIntervals::iterator LIIterator;
781 typedef LiveInterval::Ranges::const_iterator LRIterator;
783 // First allocate registers for the empty intervals.
784 for (LiveIntervalSet::const_iterator
785 itr = emptyVRegIntervals.begin(), end = emptyVRegIntervals.end();
787 LiveInterval *li = *itr;
789 unsigned physReg = vrm->getRegAllocPref(li->reg);
792 const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
793 physReg = *liRC->allocation_order_begin(*mf);
796 vrm->assignVirt2Phys(li->reg, physReg);
799 // Finally iterate over the basic blocks to compute and set the live-in sets.
800 SmallVector<MachineBasicBlock*, 8> liveInMBBs;
801 MachineBasicBlock *entryMBB = &*mf->begin();
803 for (LIIterator liItr = lis->begin(), liEnd = lis->end();
804 liItr != liEnd; ++liItr) {
806 const LiveInterval *li = liItr->second;
809 // Get the physical register for this interval
810 if (TargetRegisterInfo::isPhysicalRegister(li->reg)) {
813 else if (vrm->isAssignedReg(li->reg)) {
814 reg = vrm->getPhys(li->reg);
817 // Ranges which are assigned a stack slot only are ignored.
822 // Filter out zero regs - they're for intervals that were spilled.
826 // Iterate over the ranges of the current interval...
827 for (LRIterator lrItr = li->begin(), lrEnd = li->end();
828 lrItr != lrEnd; ++lrItr) {
830 // Find the set of basic blocks which this range is live into...
831 if (lis->findLiveInMBBs(lrItr->start, lrItr->end, liveInMBBs)) {
832 // And add the physreg for this interval to their live-in sets.
833 for (unsigned i = 0; i < liveInMBBs.size(); ++i) {
834 if (liveInMBBs[i] != entryMBB) {
835 if (!liveInMBBs[i]->isLiveIn(reg)) {
836 liveInMBBs[i]->addLiveIn(reg);
847 bool PBQPRegAlloc::runOnMachineFunction(MachineFunction &MF) {
850 tm = &mf->getTarget();
851 tri = tm->getRegisterInfo();
852 tii = tm->getInstrInfo();
853 mri = &mf->getRegInfo();
855 lis = &getAnalysis<LiveIntervals>();
856 lss = &getAnalysis<LiveStacks>();
857 loopInfo = &getAnalysis<MachineLoopInfo>();
859 vrm = &getAnalysis<VirtRegMap>();
861 DEBUG(dbgs() << "PBQP Register Allocating for " << mf->getFunction()->getName() << "\n");
863 // Allocator main loop:
865 // * Map current regalloc problem to a PBQP problem
866 // * Solve the PBQP problem
867 // * Map the solution back to a register allocation
868 // * Spill if necessary
870 // This process is continued till no more spills are generated.
872 // Find the vreg intervals in need of allocation.
873 findVRegIntervalsToAlloc();
875 // If there are non-empty intervals allocate them using pbqp.
876 if (!vregIntervalsToAlloc.empty()) {
878 bool pbqpAllocComplete = false;
881 while (!pbqpAllocComplete) {
882 DEBUG(dbgs() << " PBQP Regalloc round " << round << ":\n");
884 PBQP::Graph problem = constructPBQPProblem();
885 PBQP::Solution solution =
886 PBQP::HeuristicSolver<PBQP::Heuristics::Briggs>::solve(problem);
888 pbqpAllocComplete = mapPBQPToRegAlloc(solution);
894 // Finalise allocation, allocate empty ranges.
897 vregIntervalsToAlloc.clear();
898 emptyVRegIntervals.clear();
902 problemNodes.clear();
904 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *vrm << "\n");
907 std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
909 rewriter->runOnMachineFunction(*mf, *vrm, lis);
914 FunctionPass* llvm::createPBQPRegisterAllocator() {
915 return new PBQPRegAlloc();