1 //===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
11 // register allocator for LLVM. This allocator works by constructing a PBQP
12 // problem representing the register allocation problem under consideration,
13 // solving this using a PBQP solver, and mapping the solution back to a
14 // register assignment. If any variables are selected for spilling then spill
15 // code is inserted and the process repeated.
17 // The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
18 // for register allocation. For more information on PBQP for register
19 // allocation, see the following papers:
21 // (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
22 // PBQP. In Proceedings of the 7th Joint Modular Languages Conference
23 // (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
25 // (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
26 // architectures. In Proceedings of the Joint Conference on Languages,
27 // Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
30 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "regalloc"
35 #include "VirtRegMap.h"
36 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
37 #include "llvm/CodeGen/LiveStackAnalysis.h"
38 #include "llvm/CodeGen/MachineFunctionPass.h"
39 #include "llvm/CodeGen/MachineLoopInfo.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/RegAllocRegistry.h"
42 #include "llvm/CodeGen/RegisterCoalescer.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetMachine.h"
54 static RegisterRegAlloc
55 registerPBQPRepAlloc("pbqp", "PBQP register allocator",
56 createPBQPRegisterAllocator);
61 //! PBQP based allocators solve the register allocation problem by mapping
62 //! register allocation problems to Partitioned Boolean Quadratic
63 //! Programming problems.
64 class VISIBILITY_HIDDEN PBQPRegAlloc : public MachineFunctionPass {
69 //! Construct a PBQP register allocator.
70 PBQPRegAlloc() : MachineFunctionPass((intptr_t)&ID) {}
72 //! Return the pass name.
73 virtual const char* getPassName() const throw() {
74 return "PBQP Register Allocator";
77 //! PBQP analysis usage.
78 virtual void getAnalysisUsage(AnalysisUsage &au) const {
79 au.addRequired<LiveIntervals>();
80 au.addRequiredTransitive<RegisterCoalescer>();
81 au.addRequired<LiveStacks>();
82 au.addPreserved<LiveStacks>();
83 au.addRequired<MachineLoopInfo>();
84 au.addPreserved<MachineLoopInfo>();
85 MachineFunctionPass::getAnalysisUsage(au);
88 //! Perform register allocation
89 virtual bool runOnMachineFunction(MachineFunction &MF);
92 typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
93 typedef std::vector<const LiveInterval*> Node2LIMap;
94 typedef std::vector<unsigned> AllowedSet;
95 typedef std::vector<AllowedSet> AllowedSetMap;
96 typedef std::set<unsigned> RegSet;
97 typedef std::pair<unsigned, unsigned> RegPair;
98 typedef std::map<RegPair, PBQPNum> CoalesceMap;
100 typedef std::set<LiveInterval*> LiveIntervalSet;
103 const TargetMachine *tm;
104 const TargetRegisterInfo *tri;
105 const TargetInstrInfo *tii;
106 const MachineLoopInfo *loopInfo;
107 MachineRegisterInfo *mri;
115 AllowedSetMap allowedSets;
116 LiveIntervalSet vregIntervalsToAlloc,
120 //! Builds a PBQP cost vector.
121 template <typename RegContainer>
122 PBQPVector* buildCostVector(unsigned vReg,
123 const RegContainer &allowed,
124 const CoalesceMap &cealesces,
125 PBQPNum spillCost) const;
127 //! \brief Builds a PBQP interference matrix.
129 //! @return Either a pointer to a non-zero PBQP matrix representing the
130 //! allocation option costs, or a null pointer for a zero matrix.
132 //! Expects allowed sets for two interfering LiveIntervals. These allowed
133 //! sets should contain only allocable registers from the LiveInterval's
134 //! register class, with any interfering pre-colored registers removed.
135 template <typename RegContainer>
136 PBQPMatrix* buildInterferenceMatrix(const RegContainer &allowed1,
137 const RegContainer &allowed2) const;
140 //! Expects allowed sets for two potentially coalescable LiveIntervals,
141 //! and an estimated benefit due to coalescing. The allowed sets should
142 //! contain only allocable registers from the LiveInterval's register
143 //! classes, with any interfering pre-colored registers removed.
144 template <typename RegContainer>
145 PBQPMatrix* buildCoalescingMatrix(const RegContainer &allowed1,
146 const RegContainer &allowed2,
147 PBQPNum cBenefit) const;
149 //! \brief Finds coalescing opportunities and returns them as a map.
151 //! Any entries in the map are guaranteed coalescable, even if their
152 //! corresponding live intervals overlap.
153 CoalesceMap findCoalesces();
155 //! \brief Finds the initial set of vreg intervals to allocate.
156 void findVRegIntervalsToAlloc();
158 //! \brief Constructs a PBQP problem representation of the register
159 //! allocation problem for this function.
161 //! @return a PBQP solver object for the register allocation problem.
162 pbqp* constructPBQPProblem();
164 //! \brief Adds a stack interval if the given live interval has been
165 //! spilled. Used to support stack slot coloring.
166 void addStackInterval(const LiveInterval *spilled, float &weight);
168 //! \brief Given a solved PBQP problem maps this solution back to a register
170 bool mapPBQPToRegAlloc(pbqp *problem);
172 //! \brief Postprocessing before final spilling. Sets basic block "live in"
174 void finalizeAlloc() const;
178 char PBQPRegAlloc::ID = 0;
182 template <typename RegContainer>
183 PBQPVector* PBQPRegAlloc::buildCostVector(unsigned vReg,
184 const RegContainer &allowed,
185 const CoalesceMap &coalesces,
186 PBQPNum spillCost) const {
188 typedef typename RegContainer::const_iterator AllowedItr;
190 // Allocate vector. Additional element (0th) used for spill option
191 PBQPVector *v = new PBQPVector(allowed.size() + 1);
195 // Iterate over the allowed registers inserting coalesce benefits if there
198 for (AllowedItr itr = allowed.begin(), end = allowed.end();
199 itr != end; ++itr, ++ai) {
201 unsigned pReg = *itr;
203 CoalesceMap::const_iterator cmItr =
204 coalesces.find(RegPair(vReg, pReg));
206 // No coalesce - on to the next preg.
207 if (cmItr == coalesces.end())
210 // We have a coalesce - insert the benefit.
211 (*v)[ai + 1] = -cmItr->second;
217 template <typename RegContainer>
218 PBQPMatrix* PBQPRegAlloc::buildInterferenceMatrix(
219 const RegContainer &allowed1, const RegContainer &allowed2) const {
221 typedef typename RegContainer::const_iterator RegContainerIterator;
223 // Construct a PBQP matrix representing the cost of allocation options. The
224 // rows and columns correspond to the allocation options for the two live
225 // intervals. Elements will be infinite where corresponding registers alias,
226 // since we cannot allocate aliasing registers to interfering live intervals.
227 // All other elements (non-aliasing combinations) will have zero cost. Note
228 // that the spill option (element 0,0) has zero cost, since we can allocate
229 // both intervals to memory safely (the cost for each individual allocation
230 // to memory is accounted for by the cost vectors for each live interval).
231 PBQPMatrix *m = new PBQPMatrix(allowed1.size() + 1, allowed2.size() + 1);
233 // Assume this is a zero matrix until proven otherwise. Zero matrices occur
234 // between interfering live ranges with non-overlapping register sets (e.g.
235 // non-overlapping reg classes, or disjoint sets of allowed regs within the
236 // same class). The term "overlapping" is used advisedly: sets which do not
237 // intersect, but contain registers which alias, will have non-zero matrices.
238 // We optimize zero matrices away to improve solver speed.
239 bool isZeroMatrix = true;
242 // Row index. Starts at 1, since the 0th row is for the spill option, which
246 // Iterate over allowed sets, insert infinities where required.
247 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end();
248 a1Itr != a1End; ++a1Itr) {
250 // Column index, starts at 1 as for row index.
252 unsigned reg1 = *a1Itr;
254 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end();
255 a2Itr != a2End; ++a2Itr) {
257 unsigned reg2 = *a2Itr;
259 // If the row/column regs are identical or alias insert an infinity.
260 if ((reg1 == reg2) || tri->areAliases(reg1, reg2)) {
261 (*m)[ri][ci] = std::numeric_limits<PBQPNum>::infinity();
262 isZeroMatrix = false;
271 // If this turns out to be a zero matrix...
273 // free it and return null.
278 // ...otherwise return the cost matrix.
282 template <typename RegContainer>
283 PBQPMatrix* PBQPRegAlloc::buildCoalescingMatrix(
284 const RegContainer &allowed1, const RegContainer &allowed2,
285 PBQPNum cBenefit) const {
287 typedef typename RegContainer::const_iterator RegContainerIterator;
289 // Construct a PBQP Matrix representing the benefits of coalescing. As with
290 // interference matrices the rows and columns represent allowed registers
291 // for the LiveIntervals which are (potentially) to be coalesced. The amount
292 // -cBenefit will be placed in any element representing the same register
293 // for both intervals.
294 PBQPMatrix *m = new PBQPMatrix(allowed1.size() + 1, allowed2.size() + 1);
296 // Reset costs to zero.
299 // Assume the matrix is zero till proven otherwise. Zero matrices will be
300 // optimized away as in the interference case.
301 bool isZeroMatrix = true;
303 // Row index. Starts at 1, since the 0th row is for the spill option, which
307 // Iterate over the allowed sets, insert coalescing benefits where
309 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end();
310 a1Itr != a1End; ++a1Itr) {
312 // Column index, starts at 1 as for row index.
314 unsigned reg1 = *a1Itr;
316 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end();
317 a2Itr != a2End; ++a2Itr) {
319 // If the row and column represent the same register insert a beneficial
320 // cost to preference this allocation - it would allow us to eliminate a
322 if (reg1 == *a2Itr) {
323 (*m)[ri][ci] = -cBenefit;
324 isZeroMatrix = false;
333 // If this turns out to be a zero matrix...
335 // ...free it and return null.
343 PBQPRegAlloc::CoalesceMap PBQPRegAlloc::findCoalesces() {
345 typedef MachineFunction::const_iterator MFIterator;
346 typedef MachineBasicBlock::const_iterator MBBIterator;
347 typedef LiveInterval::const_vni_iterator VNIIterator;
349 CoalesceMap coalescesFound;
351 // To find coalesces we need to iterate over the function looking for
352 // copy instructions.
353 for (MFIterator bbItr = mf->begin(), bbEnd = mf->end();
354 bbItr != bbEnd; ++bbItr) {
356 const MachineBasicBlock *mbb = &*bbItr;
358 for (MBBIterator iItr = mbb->begin(), iEnd = mbb->end();
359 iItr != iEnd; ++iItr) {
361 const MachineInstr *instr = &*iItr;
362 unsigned srcReg, dstReg, srcSubReg, dstSubReg;
364 // If this isn't a copy then continue to the next instruction.
365 if (!tii->isMoveInstr(*instr, srcReg, dstReg, srcSubReg, dstSubReg))
368 // If the registers are already the same our job is nice and easy.
369 if (dstReg == srcReg)
372 bool srcRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(srcReg),
373 dstRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(dstReg);
375 // If both registers are physical then we can't coalesce.
376 if (srcRegIsPhysical && dstRegIsPhysical)
379 // If it's a copy that includes a virtual register but the source and
380 // destination classes differ then we can't coalesce, so continue with
381 // the next instruction.
382 const TargetRegisterClass *srcRegClass = srcRegIsPhysical ?
383 tri->getPhysicalRegisterRegClass(srcReg) : mri->getRegClass(srcReg);
385 const TargetRegisterClass *dstRegClass = dstRegIsPhysical ?
386 tri->getPhysicalRegisterRegClass(dstReg) : mri->getRegClass(dstReg);
388 if (srcRegClass != dstRegClass)
391 // We also need any physical regs to be allocable, coalescing with
392 // a non-allocable register is invalid.
393 if (srcRegIsPhysical) {
394 if (std::find(srcRegClass->allocation_order_begin(*mf),
395 srcRegClass->allocation_order_end(*mf), srcReg) ==
396 srcRegClass->allocation_order_end(*mf))
400 if (dstRegIsPhysical) {
401 if (std::find(dstRegClass->allocation_order_begin(*mf),
402 dstRegClass->allocation_order_end(*mf), dstReg) ==
403 dstRegClass->allocation_order_end(*mf))
407 // If we've made it here we have a copy with compatible register classes.
408 // We can probably coalesce, but we need to consider overlap.
409 const LiveInterval *srcLI = &lis->getInterval(srcReg),
410 *dstLI = &lis->getInterval(dstReg);
412 if (srcLI->overlaps(*dstLI)) {
413 // Even in the case of an overlap we might still be able to coalesce,
414 // but we need to make sure that no definition of either range occurs
415 // while the other range is live.
417 // Otherwise start by assuming we're ok.
420 // Test all defs of the source range.
422 vniItr = srcLI->vni_begin(), vniEnd = srcLI->vni_end();
423 vniItr != vniEnd; ++vniItr) {
425 // If we find a def that kills the coalescing opportunity then
426 // record it and break from the loop.
427 if (dstLI->liveAt((*vniItr)->def)) {
433 // If we have a bad def give up, continue to the next instruction.
437 // Otherwise test definitions of the destination range.
439 vniItr = dstLI->vni_begin(), vniEnd = dstLI->vni_end();
440 vniItr != vniEnd; ++vniItr) {
442 // We want to make sure we skip the copy instruction itself.
443 if ((*vniItr)->copy == instr)
446 if (srcLI->liveAt((*vniItr)->def)) {
452 // As before a bad def we give up and continue to the next instr.
457 // If we make it to here then either the ranges didn't overlap, or they
458 // did, but none of their definitions would prevent us from coalescing.
459 // We're good to go with the coalesce.
461 float cBenefit = powf(10.0f, loopInfo->getLoopDepth(mbb)) / 5.0;
463 coalescesFound[RegPair(srcReg, dstReg)] = cBenefit;
464 coalescesFound[RegPair(dstReg, srcReg)] = cBenefit;
469 return coalescesFound;
472 void PBQPRegAlloc::findVRegIntervalsToAlloc() {
474 // Iterate over all live ranges.
475 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end();
478 // Ignore physical ones.
479 if (TargetRegisterInfo::isPhysicalRegister(itr->first))
482 LiveInterval *li = itr->second;
484 // If this live interval is non-empty we will use pbqp to allocate it.
485 // Empty intervals we allocate in a simple post-processing stage in
488 vregIntervalsToAlloc.insert(li);
491 emptyVRegIntervals.insert(li);
496 pbqp* PBQPRegAlloc::constructPBQPProblem() {
498 typedef std::vector<const LiveInterval*> LIVector;
499 typedef std::vector<unsigned> RegVector;
501 // This will store the physical intervals for easy reference.
502 LIVector physIntervals;
504 // Start by clearing the old node <-> live interval mappings & allowed sets
509 // Populate physIntervals, update preg use:
510 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end();
513 if (TargetRegisterInfo::isPhysicalRegister(itr->first)) {
514 physIntervals.push_back(itr->second);
515 mri->setPhysRegUsed(itr->second->reg);
519 // Iterate over vreg intervals, construct live interval <-> node number
521 for (LiveIntervalSet::const_iterator
522 itr = vregIntervalsToAlloc.begin(), end = vregIntervalsToAlloc.end();
524 const LiveInterval *li = *itr;
526 li2Node[li] = node2LI.size();
527 node2LI.push_back(li);
530 // Get the set of potential coalesces.
531 CoalesceMap coalesces(findCoalesces());
533 // Construct a PBQP solver for this problem
534 pbqp *solver = alloc_pbqp(vregIntervalsToAlloc.size());
536 // Resize allowedSets container appropriately.
537 allowedSets.resize(vregIntervalsToAlloc.size());
539 // Iterate over virtual register intervals to compute allowed sets...
540 for (unsigned node = 0; node < node2LI.size(); ++node) {
542 // Grab pointers to the interval and its register class.
543 const LiveInterval *li = node2LI[node];
544 const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
546 // Start by assuming all allocable registers in the class are allowed...
547 RegVector liAllowed(liRC->allocation_order_begin(*mf),
548 liRC->allocation_order_end(*mf));
550 // Eliminate the physical registers which overlap with this range, along
551 // with all their aliases.
552 for (LIVector::iterator pItr = physIntervals.begin(),
553 pEnd = physIntervals.end(); pItr != pEnd; ++pItr) {
555 if (!li->overlaps(**pItr))
558 unsigned pReg = (*pItr)->reg;
560 // If we get here then the live intervals overlap, but we're still ok
561 // if they're coalescable.
562 if (coalesces.find(RegPair(li->reg, pReg)) != coalesces.end())
565 // If we get here then we have a genuine exclusion.
567 // Remove the overlapping reg...
568 RegVector::iterator eraseItr =
569 std::find(liAllowed.begin(), liAllowed.end(), pReg);
571 if (eraseItr != liAllowed.end())
572 liAllowed.erase(eraseItr);
574 const unsigned *aliasItr = tri->getAliasSet(pReg);
577 // ...and its aliases.
578 for (; *aliasItr != 0; ++aliasItr) {
579 RegVector::iterator eraseItr =
580 std::find(liAllowed.begin(), liAllowed.end(), *aliasItr);
582 if (eraseItr != liAllowed.end()) {
583 liAllowed.erase(eraseItr);
589 // Copy the allowed set into a member vector for use when constructing cost
590 // vectors & matrices, and mapping PBQP solutions back to assignments.
591 allowedSets[node] = AllowedSet(liAllowed.begin(), liAllowed.end());
593 // Set the spill cost to the interval weight, or epsilon if the
594 // interval weight is zero
595 PBQPNum spillCost = (li->weight != 0.0) ?
596 li->weight : std::numeric_limits<PBQPNum>::min();
598 // Build a cost vector for this interval.
599 add_pbqp_nodecosts(solver, node,
600 buildCostVector(li->reg, allowedSets[node], coalesces,
606 // Now add the cost matrices...
607 for (unsigned node1 = 0; node1 < node2LI.size(); ++node1) {
608 const LiveInterval *li = node2LI[node1];
610 // Test for live range overlaps and insert interference matrices.
611 for (unsigned node2 = node1 + 1; node2 < node2LI.size(); ++node2) {
612 const LiveInterval *li2 = node2LI[node2];
614 CoalesceMap::const_iterator cmItr =
615 coalesces.find(RegPair(li->reg, li2->reg));
619 if (cmItr != coalesces.end()) {
620 m = buildCoalescingMatrix(allowedSets[node1], allowedSets[node2],
623 else if (li->overlaps(*li2)) {
624 m = buildInterferenceMatrix(allowedSets[node1], allowedSets[node2]);
628 add_pbqp_edgecosts(solver, node1, node2, m);
634 // We're done, PBQP problem constructed - return it.
638 void PBQPRegAlloc::addStackInterval(const LiveInterval *spilled, float &weight) {
639 int stackSlot = vrm->getStackSlot(spilled->reg);
641 if (stackSlot == VirtRegMap::NO_STACK_SLOT)
644 LiveInterval &stackInterval = lss->getOrCreateInterval(stackSlot);
645 stackInterval.weight += weight;
648 if (stackInterval.getNumValNums() != 0)
649 vni = stackInterval.getValNumInfo(0);
651 vni = stackInterval.getNextValue(-0U, 0, lss->getVNInfoAllocator());
653 LiveInterval &rhsInterval = lis->getInterval(spilled->reg);
654 stackInterval.MergeRangesInAsValue(rhsInterval, vni);
657 bool PBQPRegAlloc::mapPBQPToRegAlloc(pbqp *problem) {
659 // Set to true if we have any spills
660 bool anotherRoundNeeded = false;
662 // Clear the existing allocation.
665 // Iterate over the nodes mapping the PBQP solution to a register assignment.
666 for (unsigned node = 0; node < node2LI.size(); ++node) {
667 unsigned virtReg = node2LI[node]->reg,
668 allocSelection = get_pbqp_solution(problem, node);
670 // If the PBQP solution is non-zero it's a physical register...
671 if (allocSelection != 0) {
672 // Get the physical reg, subtracting 1 to account for the spill option.
673 unsigned physReg = allowedSets[node][allocSelection - 1];
675 DOUT << "VREG " << virtReg << " -> " << tri->getName(physReg) << "\n";
677 assert(physReg != 0);
679 // Add to the virt reg map and update the used phys regs.
680 vrm->assignVirt2Phys(virtReg, physReg);
682 // ...Otherwise it's a spill.
685 // Make sure we ignore this virtual reg on the next round
687 vregIntervalsToAlloc.erase(&lis->getInterval(virtReg));
691 // Insert spill ranges for this live range
692 const LiveInterval *spillInterval = node2LI[node];
693 double oldSpillWeight = spillInterval->weight;
694 SmallVector<LiveInterval*, 8> spillIs;
695 std::vector<LiveInterval*> newSpills =
696 lis->addIntervalsForSpills(*spillInterval, spillIs, loopInfo, *vrm,
698 addStackInterval(spillInterval, ssWeight);
700 DOUT << "VREG " << virtReg << " -> SPILLED (Cost: "
701 << oldSpillWeight << ", New vregs: ";
703 // Copy any newly inserted live intervals into the list of regs to
705 for (std::vector<LiveInterval*>::const_iterator
706 itr = newSpills.begin(), end = newSpills.end();
709 assert(!(*itr)->empty() && "Empty spill range.");
711 DOUT << (*itr)->reg << " ";
713 vregIntervalsToAlloc.insert(*itr);
718 // We need another round if spill intervals were added.
719 anotherRoundNeeded |= !newSpills.empty();
723 return !anotherRoundNeeded;
726 void PBQPRegAlloc::finalizeAlloc() const {
727 typedef LiveIntervals::iterator LIIterator;
728 typedef LiveInterval::Ranges::const_iterator LRIterator;
730 // First allocate registers for the empty intervals.
731 for (LiveIntervalSet::const_iterator
732 itr = emptyVRegIntervals.begin(), end = emptyVRegIntervals.end();
734 LiveInterval *li = *itr;
736 unsigned physReg = li->preference;
739 const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
740 physReg = *liRC->allocation_order_begin(*mf);
743 vrm->assignVirt2Phys(li->reg, physReg);
746 // Finally iterate over the basic blocks to compute and set the live-in sets.
747 SmallVector<MachineBasicBlock*, 8> liveInMBBs;
748 MachineBasicBlock *entryMBB = &*mf->begin();
750 for (LIIterator liItr = lis->begin(), liEnd = lis->end();
751 liItr != liEnd; ++liItr) {
753 const LiveInterval *li = liItr->second;
756 // Get the physical register for this interval
757 if (TargetRegisterInfo::isPhysicalRegister(li->reg)) {
760 else if (vrm->isAssignedReg(li->reg)) {
761 reg = vrm->getPhys(li->reg);
764 // Ranges which are assigned a stack slot only are ignored.
768 // Iterate over the ranges of the current interval...
769 for (LRIterator lrItr = li->begin(), lrEnd = li->end();
770 lrItr != lrEnd; ++lrItr) {
772 // Find the set of basic blocks which this range is live into...
773 if (lis->findLiveInMBBs(lrItr->start, lrItr->end, liveInMBBs)) {
774 // And add the physreg for this interval to their live-in sets.
775 for (unsigned i = 0; i < liveInMBBs.size(); ++i) {
776 if (liveInMBBs[i] != entryMBB) {
777 if (!liveInMBBs[i]->isLiveIn(reg)) {
778 liveInMBBs[i]->addLiveIn(reg);
789 bool PBQPRegAlloc::runOnMachineFunction(MachineFunction &MF) {
792 tm = &mf->getTarget();
793 tri = tm->getRegisterInfo();
794 tii = tm->getInstrInfo();
795 mri = &mf->getRegInfo();
797 lis = &getAnalysis<LiveIntervals>();
798 lss = &getAnalysis<LiveStacks>();
799 loopInfo = &getAnalysis<MachineLoopInfo>();
801 std::auto_ptr<VirtRegMap> vrmAutoPtr(new VirtRegMap(*mf));
802 vrm = vrmAutoPtr.get();
804 DOUT << "PBQP Register Allocating for " << mf->getFunction()->getName() << "\n";
806 // Allocator main loop:
808 // * Map current regalloc problem to a PBQP problem
809 // * Solve the PBQP problem
810 // * Map the solution back to a register allocation
811 // * Spill if necessary
813 // This process is continued till no more spills are generated.
815 // Find the vreg intervals in need of allocation.
816 findVRegIntervalsToAlloc();
818 // If there aren't any then we're done here.
819 if (vregIntervalsToAlloc.empty() && emptyVRegIntervals.empty())
822 // If there are non-empty intervals allocate them using pbqp.
823 if (!vregIntervalsToAlloc.empty()) {
825 bool pbqpAllocComplete = false;
828 while (!pbqpAllocComplete) {
829 DOUT << " PBQP Regalloc round " << round << ":\n";
831 pbqp *problem = constructPBQPProblem();
835 pbqpAllocComplete = mapPBQPToRegAlloc(problem);
843 // Finalise allocation, allocate empty ranges.
846 vregIntervalsToAlloc.clear();
847 emptyVRegIntervals.clear();
852 DOUT << "Post alloc VirtRegMap:\n" << *vrm << "\n";
855 std::auto_ptr<Spiller> spiller(createSpiller());
856 spiller->runOnMachineFunction(*mf, *vrm);
861 FunctionPass* llvm::createPBQPRegisterAllocator() {
862 return new PBQPRegAlloc();