1 //===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
11 // register allocator for LLVM. This allocator works by constructing a PBQP
12 // problem representing the register allocation problem under consideration,
13 // solving this using a PBQP solver, and mapping the solution back to a
14 // register assignment. If any variables are selected for spilling then spill
15 // code is inserted and the process repeated.
17 // The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
18 // for register allocation. For more information on PBQP for register
19 // allocation, see the following papers:
21 // (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
22 // PBQP. In Proceedings of the 7th Joint Modular Languages Conference
23 // (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
25 // (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
26 // architectures. In Proceedings of the Joint Conference on Languages,
27 // Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
30 //===----------------------------------------------------------------------===//
32 #include "llvm/CodeGen/RegAllocPBQP.h"
33 #include "RegisterCoalescer.h"
35 #include "llvm/Analysis/AliasAnalysis.h"
36 #include "llvm/CodeGen/CalcSpillWeights.h"
37 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
38 #include "llvm/CodeGen/LiveRangeEdit.h"
39 #include "llvm/CodeGen/LiveStackAnalysis.h"
40 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
41 #include "llvm/CodeGen/MachineDominators.h"
42 #include "llvm/CodeGen/MachineFunctionPass.h"
43 #include "llvm/CodeGen/MachineLoopInfo.h"
44 #include "llvm/CodeGen/MachineRegisterInfo.h"
45 #include "llvm/CodeGen/RegAllocRegistry.h"
46 #include "llvm/CodeGen/VirtRegMap.h"
47 #include "llvm/IR/Module.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/FileSystem.h"
50 #include "llvm/Support/Printable.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/Target/TargetInstrInfo.h"
53 #include "llvm/Target/TargetSubtargetInfo.h"
63 #define DEBUG_TYPE "regalloc"
65 static RegisterRegAlloc
66 RegisterPBQPRepAlloc("pbqp", "PBQP register allocator",
67 createDefaultPBQPRegisterAllocator);
70 PBQPCoalescing("pbqp-coalescing",
71 cl::desc("Attempt coalescing during PBQP register allocation."),
72 cl::init(false), cl::Hidden);
76 PBQPDumpGraphs("pbqp-dump-graphs",
77 cl::desc("Dump graphs for each function/round in the compilation unit."),
78 cl::init(false), cl::Hidden);
84 /// PBQP based allocators solve the register allocation problem by mapping
85 /// register allocation problems to Partitioned Boolean Quadratic
86 /// Programming problems.
87 class RegAllocPBQP : public MachineFunctionPass {
92 /// Construct a PBQP register allocator.
93 RegAllocPBQP(char *cPassID = nullptr)
94 : MachineFunctionPass(ID), customPassID(cPassID) {
95 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
96 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
97 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
98 initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
101 /// Return the pass name.
102 const char* getPassName() const override {
103 return "PBQP Register Allocator";
106 /// PBQP analysis usage.
107 void getAnalysisUsage(AnalysisUsage &au) const override;
109 /// Perform register allocation
110 bool runOnMachineFunction(MachineFunction &MF) override;
114 typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
115 typedef std::vector<const LiveInterval*> Node2LIMap;
116 typedef std::vector<unsigned> AllowedSet;
117 typedef std::vector<AllowedSet> AllowedSetMap;
118 typedef std::pair<unsigned, unsigned> RegPair;
119 typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;
120 typedef std::set<unsigned> RegSet;
124 RegSet VRegsToAlloc, EmptyIntervalVRegs;
126 /// \brief Finds the initial set of vreg intervals to allocate.
127 void findVRegIntervalsToAlloc(const MachineFunction &MF, LiveIntervals &LIS);
129 /// \brief Constructs an initial graph.
130 void initializeGraph(PBQPRAGraph &G, VirtRegMap &VRM, Spiller &VRegSpiller);
132 /// \brief Spill the given VReg.
133 void spillVReg(unsigned VReg, SmallVectorImpl<unsigned> &NewIntervals,
134 MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM,
135 Spiller &VRegSpiller);
137 /// \brief Given a solved PBQP problem maps this solution back to a register
139 bool mapPBQPToRegAlloc(const PBQPRAGraph &G,
140 const PBQP::Solution &Solution,
142 Spiller &VRegSpiller);
144 /// \brief Postprocessing before final spilling. Sets basic block "live in"
146 void finalizeAlloc(MachineFunction &MF, LiveIntervals &LIS,
147 VirtRegMap &VRM) const;
151 char RegAllocPBQP::ID = 0;
153 /// @brief Set spill costs for each node in the PBQP reg-alloc graph.
154 class SpillCosts : public PBQPRAConstraint {
156 void apply(PBQPRAGraph &G) override {
157 LiveIntervals &LIS = G.getMetadata().LIS;
159 // A minimum spill costs, so that register constraints can can be set
160 // without normalization in the [0.0:MinSpillCost( interval.
161 const PBQP::PBQPNum MinSpillCost = 10.0;
163 for (auto NId : G.nodeIds()) {
164 PBQP::PBQPNum SpillCost =
165 LIS.getInterval(G.getNodeMetadata(NId).getVReg()).weight;
166 if (SpillCost == 0.0)
167 SpillCost = std::numeric_limits<PBQP::PBQPNum>::min();
169 SpillCost += MinSpillCost;
170 PBQPRAGraph::RawVector NodeCosts(G.getNodeCosts(NId));
171 NodeCosts[PBQP::RegAlloc::getSpillOptionIdx()] = SpillCost;
172 G.setNodeCosts(NId, std::move(NodeCosts));
177 /// @brief Add interference edges between overlapping vregs.
178 class Interference : public PBQPRAConstraint {
181 typedef const PBQP::RegAlloc::AllowedRegVector* AllowedRegVecPtr;
182 typedef std::pair<AllowedRegVecPtr, AllowedRegVecPtr> IKey;
183 typedef DenseMap<IKey, PBQPRAGraph::MatrixPtr> IMatrixCache;
184 typedef DenseSet<IKey> DisjointAllowedRegsCache;
185 typedef std::pair<PBQP::GraphBase::NodeId, PBQP::GraphBase::NodeId> IEdgeKey;
186 typedef DenseSet<IEdgeKey> IEdgeCache;
188 bool haveDisjointAllowedRegs(const PBQPRAGraph &G, PBQPRAGraph::NodeId NId,
189 PBQPRAGraph::NodeId MId,
190 const DisjointAllowedRegsCache &D) const {
191 const auto *NRegs = &G.getNodeMetadata(NId).getAllowedRegs();
192 const auto *MRegs = &G.getNodeMetadata(MId).getAllowedRegs();
198 return D.count(IKey(NRegs, MRegs)) > 0;
200 return D.count(IKey(MRegs, NRegs)) > 0;
203 void setDisjointAllowedRegs(const PBQPRAGraph &G, PBQPRAGraph::NodeId NId,
204 PBQPRAGraph::NodeId MId,
205 DisjointAllowedRegsCache &D) {
206 const auto *NRegs = &G.getNodeMetadata(NId).getAllowedRegs();
207 const auto *MRegs = &G.getNodeMetadata(MId).getAllowedRegs();
209 assert(NRegs != MRegs && "AllowedRegs can not be disjoint with itself");
212 D.insert(IKey(NRegs, MRegs));
214 D.insert(IKey(MRegs, NRegs));
217 // Holds (Interval, CurrentSegmentID, and NodeId). The first two are required
218 // for the fast interference graph construction algorithm. The last is there
219 // to save us from looking up node ids via the VRegToNode map in the graph
221 typedef std::tuple<LiveInterval*, size_t, PBQP::GraphBase::NodeId>
224 static SlotIndex getStartPoint(const IntervalInfo &I) {
225 return std::get<0>(I)->segments[std::get<1>(I)].start;
228 static SlotIndex getEndPoint(const IntervalInfo &I) {
229 return std::get<0>(I)->segments[std::get<1>(I)].end;
232 static PBQP::GraphBase::NodeId getNodeId(const IntervalInfo &I) {
233 return std::get<2>(I);
236 static bool lowestStartPoint(const IntervalInfo &I1,
237 const IntervalInfo &I2) {
238 // Condition reversed because priority queue has the *highest* element at
239 // the front, rather than the lowest.
240 return getStartPoint(I1) > getStartPoint(I2);
243 static bool lowestEndPoint(const IntervalInfo &I1,
244 const IntervalInfo &I2) {
245 SlotIndex E1 = getEndPoint(I1);
246 SlotIndex E2 = getEndPoint(I2);
254 // If two intervals end at the same point, we need a way to break the tie or
255 // the set will assume they're actually equal and refuse to insert a
256 // "duplicate". Just compare the vregs - fast and guaranteed unique.
257 return std::get<0>(I1)->reg < std::get<0>(I2)->reg;
260 static bool isAtLastSegment(const IntervalInfo &I) {
261 return std::get<1>(I) == std::get<0>(I)->size() - 1;
264 static IntervalInfo nextSegment(const IntervalInfo &I) {
265 return std::make_tuple(std::get<0>(I), std::get<1>(I) + 1, std::get<2>(I));
270 void apply(PBQPRAGraph &G) override {
271 // The following is loosely based on the linear scan algorithm introduced in
272 // "Linear Scan Register Allocation" by Poletto and Sarkar. This version
273 // isn't linear, because the size of the active set isn't bound by the
274 // number of registers, but rather the size of the largest clique in the
275 // graph. Still, we expect this to be better than N^2.
276 LiveIntervals &LIS = G.getMetadata().LIS;
278 // Interferenc matrices are incredibly regular - they're only a function of
279 // the allowed sets, so we cache them to avoid the overhead of constructing
280 // and uniquing them.
283 // Finding an edge is expensive in the worst case (O(max_clique(G))). So
284 // cache locally edges we have already seen.
287 // Cache known disjoint allowed registers pairs
288 DisjointAllowedRegsCache D;
290 typedef std::set<IntervalInfo, decltype(&lowestEndPoint)> IntervalSet;
291 typedef std::priority_queue<IntervalInfo, std::vector<IntervalInfo>,
292 decltype(&lowestStartPoint)> IntervalQueue;
293 IntervalSet Active(lowestEndPoint);
294 IntervalQueue Inactive(lowestStartPoint);
296 // Start by building the inactive set.
297 for (auto NId : G.nodeIds()) {
298 unsigned VReg = G.getNodeMetadata(NId).getVReg();
299 LiveInterval &LI = LIS.getInterval(VReg);
300 assert(!LI.empty() && "PBQP graph contains node for empty interval");
301 Inactive.push(std::make_tuple(&LI, 0, NId));
304 while (!Inactive.empty()) {
305 // Tentatively grab the "next" interval - this choice may be overriden
307 IntervalInfo Cur = Inactive.top();
309 // Retire any active intervals that end before Cur starts.
310 IntervalSet::iterator RetireItr = Active.begin();
311 while (RetireItr != Active.end() &&
312 (getEndPoint(*RetireItr) <= getStartPoint(Cur))) {
313 // If this interval has subsequent segments, add the next one to the
315 if (!isAtLastSegment(*RetireItr))
316 Inactive.push(nextSegment(*RetireItr));
320 Active.erase(Active.begin(), RetireItr);
322 // One of the newly retired segments may actually start before the
323 // Cur segment, so re-grab the front of the inactive list.
324 Cur = Inactive.top();
327 // At this point we know that Cur overlaps all active intervals. Add the
328 // interference edges.
329 PBQP::GraphBase::NodeId NId = getNodeId(Cur);
330 for (const auto &A : Active) {
331 PBQP::GraphBase::NodeId MId = getNodeId(A);
333 // Do not add an edge when the nodes' allowed registers do not
334 // intersect: there is obviously no interference.
335 if (haveDisjointAllowedRegs(G, NId, MId, D))
338 // Check that we haven't already added this edge
339 IEdgeKey EK(std::min(NId, MId), std::max(NId, MId));
343 // This is a new edge - add it to the graph.
344 if (!createInterferenceEdge(G, NId, MId, C))
345 setDisjointAllowedRegs(G, NId, MId, D);
350 // Finally, add Cur to the Active set.
357 // Create an Interference edge and add it to the graph, unless it is
358 // a null matrix, meaning the nodes' allowed registers do not have any
359 // interference. This case occurs frequently between integer and floating
360 // point registers for example.
361 // return true iff both nodes interferes.
362 bool createInterferenceEdge(PBQPRAGraph &G,
363 PBQPRAGraph::NodeId NId, PBQPRAGraph::NodeId MId,
366 const TargetRegisterInfo &TRI =
367 *G.getMetadata().MF.getSubtarget().getRegisterInfo();
368 const auto &NRegs = G.getNodeMetadata(NId).getAllowedRegs();
369 const auto &MRegs = G.getNodeMetadata(MId).getAllowedRegs();
371 // Try looking the edge costs up in the IMatrixCache first.
372 IKey K(&NRegs, &MRegs);
373 IMatrixCache::iterator I = C.find(K);
375 G.addEdgeBypassingCostAllocator(NId, MId, I->second);
379 PBQPRAGraph::RawMatrix M(NRegs.size() + 1, MRegs.size() + 1, 0);
380 bool NodesInterfere = false;
381 for (unsigned I = 0; I != NRegs.size(); ++I) {
382 unsigned PRegN = NRegs[I];
383 for (unsigned J = 0; J != MRegs.size(); ++J) {
384 unsigned PRegM = MRegs[J];
385 if (TRI.regsOverlap(PRegN, PRegM)) {
386 M[I + 1][J + 1] = std::numeric_limits<PBQP::PBQPNum>::infinity();
387 NodesInterfere = true;
395 PBQPRAGraph::EdgeId EId = G.addEdge(NId, MId, std::move(M));
396 C[K] = G.getEdgeCostsPtr(EId);
403 class Coalescing : public PBQPRAConstraint {
405 void apply(PBQPRAGraph &G) override {
406 MachineFunction &MF = G.getMetadata().MF;
407 MachineBlockFrequencyInfo &MBFI = G.getMetadata().MBFI;
408 CoalescerPair CP(*MF.getSubtarget().getRegisterInfo());
410 // Scan the machine function and add a coalescing cost whenever CoalescerPair
412 for (const auto &MBB : MF) {
413 for (const auto &MI : MBB) {
415 // Skip not-coalescable or already coalesced copies.
416 if (!CP.setRegisters(&MI) || CP.getSrcReg() == CP.getDstReg())
419 unsigned DstReg = CP.getDstReg();
420 unsigned SrcReg = CP.getSrcReg();
422 const float Scale = 1.0f / MBFI.getEntryFreq();
423 PBQP::PBQPNum CBenefit = MBFI.getBlockFreq(&MBB).getFrequency() * Scale;
426 if (!MF.getRegInfo().isAllocatable(DstReg))
429 PBQPRAGraph::NodeId NId = G.getMetadata().getNodeIdForVReg(SrcReg);
431 const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed =
432 G.getNodeMetadata(NId).getAllowedRegs();
434 unsigned PRegOpt = 0;
435 while (PRegOpt < Allowed.size() && Allowed[PRegOpt] != DstReg)
438 if (PRegOpt < Allowed.size()) {
439 PBQPRAGraph::RawVector NewCosts(G.getNodeCosts(NId));
440 NewCosts[PRegOpt + 1] -= CBenefit;
441 G.setNodeCosts(NId, std::move(NewCosts));
444 PBQPRAGraph::NodeId N1Id = G.getMetadata().getNodeIdForVReg(DstReg);
445 PBQPRAGraph::NodeId N2Id = G.getMetadata().getNodeIdForVReg(SrcReg);
446 const PBQPRAGraph::NodeMetadata::AllowedRegVector *Allowed1 =
447 &G.getNodeMetadata(N1Id).getAllowedRegs();
448 const PBQPRAGraph::NodeMetadata::AllowedRegVector *Allowed2 =
449 &G.getNodeMetadata(N2Id).getAllowedRegs();
451 PBQPRAGraph::EdgeId EId = G.findEdge(N1Id, N2Id);
452 if (EId == G.invalidEdgeId()) {
453 PBQPRAGraph::RawMatrix Costs(Allowed1->size() + 1,
454 Allowed2->size() + 1, 0);
455 addVirtRegCoalesce(Costs, *Allowed1, *Allowed2, CBenefit);
456 G.addEdge(N1Id, N2Id, std::move(Costs));
458 if (G.getEdgeNode1Id(EId) == N2Id) {
459 std::swap(N1Id, N2Id);
460 std::swap(Allowed1, Allowed2);
462 PBQPRAGraph::RawMatrix Costs(G.getEdgeCosts(EId));
463 addVirtRegCoalesce(Costs, *Allowed1, *Allowed2, CBenefit);
464 G.updateEdgeCosts(EId, std::move(Costs));
473 void addVirtRegCoalesce(
474 PBQPRAGraph::RawMatrix &CostMat,
475 const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed1,
476 const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed2,
477 PBQP::PBQPNum Benefit) {
478 assert(CostMat.getRows() == Allowed1.size() + 1 && "Size mismatch.");
479 assert(CostMat.getCols() == Allowed2.size() + 1 && "Size mismatch.");
480 for (unsigned I = 0; I != Allowed1.size(); ++I) {
481 unsigned PReg1 = Allowed1[I];
482 for (unsigned J = 0; J != Allowed2.size(); ++J) {
483 unsigned PReg2 = Allowed2[J];
485 CostMat[I + 1][J + 1] -= Benefit;
492 } // End anonymous namespace.
494 // Out-of-line destructor/anchor for PBQPRAConstraint.
495 PBQPRAConstraint::~PBQPRAConstraint() {}
496 void PBQPRAConstraint::anchor() {}
497 void PBQPRAConstraintList::anchor() {}
499 void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
500 au.setPreservesCFG();
501 au.addRequired<AAResultsWrapperPass>();
502 au.addPreserved<AAResultsWrapperPass>();
503 au.addRequired<SlotIndexes>();
504 au.addPreserved<SlotIndexes>();
505 au.addRequired<LiveIntervals>();
506 au.addPreserved<LiveIntervals>();
507 //au.addRequiredID(SplitCriticalEdgesID);
509 au.addRequiredID(*customPassID);
510 au.addRequired<LiveStacks>();
511 au.addPreserved<LiveStacks>();
512 au.addRequired<MachineBlockFrequencyInfo>();
513 au.addPreserved<MachineBlockFrequencyInfo>();
514 au.addRequired<MachineLoopInfo>();
515 au.addPreserved<MachineLoopInfo>();
516 au.addRequired<MachineDominatorTree>();
517 au.addPreserved<MachineDominatorTree>();
518 au.addRequired<VirtRegMap>();
519 au.addPreserved<VirtRegMap>();
520 MachineFunctionPass::getAnalysisUsage(au);
523 void RegAllocPBQP::findVRegIntervalsToAlloc(const MachineFunction &MF,
524 LiveIntervals &LIS) {
525 const MachineRegisterInfo &MRI = MF.getRegInfo();
527 // Iterate over all live ranges.
528 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
529 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
530 if (MRI.reg_nodbg_empty(Reg))
532 LiveInterval &LI = LIS.getInterval(Reg);
534 // If this live interval is non-empty we will use pbqp to allocate it.
535 // Empty intervals we allocate in a simple post-processing stage in
538 VRegsToAlloc.insert(LI.reg);
540 EmptyIntervalVRegs.insert(LI.reg);
545 static bool isACalleeSavedRegister(unsigned reg, const TargetRegisterInfo &TRI,
546 const MachineFunction &MF) {
547 const MCPhysReg *CSR = TRI.getCalleeSavedRegs(&MF);
548 for (unsigned i = 0; CSR[i] != 0; ++i)
549 if (TRI.regsOverlap(reg, CSR[i]))
554 void RegAllocPBQP::initializeGraph(PBQPRAGraph &G, VirtRegMap &VRM,
555 Spiller &VRegSpiller) {
556 MachineFunction &MF = G.getMetadata().MF;
558 LiveIntervals &LIS = G.getMetadata().LIS;
559 const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
560 const TargetRegisterInfo &TRI =
561 *G.getMetadata().MF.getSubtarget().getRegisterInfo();
563 std::vector<unsigned> Worklist(VRegsToAlloc.begin(), VRegsToAlloc.end());
565 while (!Worklist.empty()) {
566 unsigned VReg = Worklist.back();
569 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
570 LiveInterval &VRegLI = LIS.getInterval(VReg);
572 // Record any overlaps with regmask operands.
573 BitVector RegMaskOverlaps;
574 LIS.checkRegMaskInterference(VRegLI, RegMaskOverlaps);
576 // Compute an initial allowed set for the current vreg.
577 std::vector<unsigned> VRegAllowed;
578 ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF);
579 for (unsigned I = 0; I != RawPRegOrder.size(); ++I) {
580 unsigned PReg = RawPRegOrder[I];
581 if (MRI.isReserved(PReg))
584 // vregLI crosses a regmask operand that clobbers preg.
585 if (!RegMaskOverlaps.empty() && !RegMaskOverlaps.test(PReg))
588 // vregLI overlaps fixed regunit interference.
589 bool Interference = false;
590 for (MCRegUnitIterator Units(PReg, &TRI); Units.isValid(); ++Units) {
591 if (VRegLI.overlaps(LIS.getRegUnit(*Units))) {
599 // preg is usable for this virtual register.
600 VRegAllowed.push_back(PReg);
603 // Check for vregs that have no allowed registers. These should be
604 // pre-spilled and the new vregs added to the worklist.
605 if (VRegAllowed.empty()) {
606 SmallVector<unsigned, 8> NewVRegs;
607 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller);
608 Worklist.insert(Worklist.end(), NewVRegs.begin(), NewVRegs.end());
612 PBQPRAGraph::RawVector NodeCosts(VRegAllowed.size() + 1, 0);
614 // Tweak cost of callee saved registers, as using then force spilling and
615 // restoring them. This would only happen in the prologue / epilogue though.
616 for (unsigned i = 0; i != VRegAllowed.size(); ++i)
617 if (isACalleeSavedRegister(VRegAllowed[i], TRI, MF))
618 NodeCosts[1 + i] += 1.0;
620 PBQPRAGraph::NodeId NId = G.addNode(std::move(NodeCosts));
621 G.getNodeMetadata(NId).setVReg(VReg);
622 G.getNodeMetadata(NId).setAllowedRegs(
623 G.getMetadata().getAllowedRegs(std::move(VRegAllowed)));
624 G.getMetadata().setNodeIdForVReg(VReg, NId);
628 void RegAllocPBQP::spillVReg(unsigned VReg,
629 SmallVectorImpl<unsigned> &NewIntervals,
630 MachineFunction &MF, LiveIntervals &LIS,
631 VirtRegMap &VRM, Spiller &VRegSpiller) {
633 VRegsToAlloc.erase(VReg);
634 LiveRangeEdit LRE(&LIS.getInterval(VReg), NewIntervals, MF, LIS, &VRM);
635 VRegSpiller.spill(LRE);
637 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
639 DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> SPILLED (Cost: "
640 << LRE.getParent().weight << ", New vregs: ");
642 // Copy any newly inserted live intervals into the list of regs to
644 for (LiveRangeEdit::iterator I = LRE.begin(), E = LRE.end();
646 const LiveInterval &LI = LIS.getInterval(*I);
647 assert(!LI.empty() && "Empty spill range.");
648 DEBUG(dbgs() << PrintReg(LI.reg, &TRI) << " ");
649 VRegsToAlloc.insert(LI.reg);
652 DEBUG(dbgs() << ")\n");
655 bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAGraph &G,
656 const PBQP::Solution &Solution,
658 Spiller &VRegSpiller) {
659 MachineFunction &MF = G.getMetadata().MF;
660 LiveIntervals &LIS = G.getMetadata().LIS;
661 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
664 // Set to true if we have any spills
665 bool AnotherRoundNeeded = false;
667 // Clear the existing allocation.
670 // Iterate over the nodes mapping the PBQP solution to a register
672 for (auto NId : G.nodeIds()) {
673 unsigned VReg = G.getNodeMetadata(NId).getVReg();
674 unsigned AllocOption = Solution.getSelection(NId);
676 if (AllocOption != PBQP::RegAlloc::getSpillOptionIdx()) {
677 unsigned PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOption - 1];
678 DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> "
679 << TRI.getName(PReg) << "\n");
680 assert(PReg != 0 && "Invalid preg selected.");
681 VRM.assignVirt2Phys(VReg, PReg);
683 // Spill VReg. If this introduces new intervals we'll need another round
685 SmallVector<unsigned, 8> NewVRegs;
686 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller);
687 AnotherRoundNeeded |= !NewVRegs.empty();
691 return !AnotherRoundNeeded;
694 void RegAllocPBQP::finalizeAlloc(MachineFunction &MF,
696 VirtRegMap &VRM) const {
697 MachineRegisterInfo &MRI = MF.getRegInfo();
699 // First allocate registers for the empty intervals.
700 for (RegSet::const_iterator
701 I = EmptyIntervalVRegs.begin(), E = EmptyIntervalVRegs.end();
703 LiveInterval &LI = LIS.getInterval(*I);
705 unsigned PReg = MRI.getSimpleHint(LI.reg);
708 const TargetRegisterClass &RC = *MRI.getRegClass(LI.reg);
709 PReg = RC.getRawAllocationOrder(MF).front();
712 VRM.assignVirt2Phys(LI.reg, PReg);
716 static inline float normalizePBQPSpillWeight(float UseDefFreq, unsigned Size,
718 // All intervals have a spill weight that is mostly proportional to the number
719 // of uses, with uses in loops having a bigger weight.
720 return NumInstr * normalizeSpillWeight(UseDefFreq, Size, 1);
723 bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
724 LiveIntervals &LIS = getAnalysis<LiveIntervals>();
725 MachineBlockFrequencyInfo &MBFI =
726 getAnalysis<MachineBlockFrequencyInfo>();
728 VirtRegMap &VRM = getAnalysis<VirtRegMap>();
730 calculateSpillWeightsAndHints(LIS, MF, &VRM, getAnalysis<MachineLoopInfo>(),
731 MBFI, normalizePBQPSpillWeight);
733 std::unique_ptr<Spiller> VRegSpiller(createInlineSpiller(*this, MF, VRM));
735 MF.getRegInfo().freezeReservedRegs(MF);
737 DEBUG(dbgs() << "PBQP Register Allocating for " << MF.getName() << "\n");
739 // Allocator main loop:
741 // * Map current regalloc problem to a PBQP problem
742 // * Solve the PBQP problem
743 // * Map the solution back to a register allocation
744 // * Spill if necessary
746 // This process is continued till no more spills are generated.
748 // Find the vreg intervals in need of allocation.
749 findVRegIntervalsToAlloc(MF, LIS);
752 const Function &F = *MF.getFunction();
753 std::string FullyQualifiedName =
754 F.getParent()->getModuleIdentifier() + "." + F.getName().str();
757 // If there are non-empty intervals allocate them using pbqp.
758 if (!VRegsToAlloc.empty()) {
760 const TargetSubtargetInfo &Subtarget = MF.getSubtarget();
761 std::unique_ptr<PBQPRAConstraintList> ConstraintsRoot =
762 llvm::make_unique<PBQPRAConstraintList>();
763 ConstraintsRoot->addConstraint(llvm::make_unique<SpillCosts>());
764 ConstraintsRoot->addConstraint(llvm::make_unique<Interference>());
766 ConstraintsRoot->addConstraint(llvm::make_unique<Coalescing>());
767 ConstraintsRoot->addConstraint(Subtarget.getCustomPBQPConstraints());
769 bool PBQPAllocComplete = false;
772 while (!PBQPAllocComplete) {
773 DEBUG(dbgs() << " PBQP Regalloc round " << Round << ":\n");
775 PBQPRAGraph G(PBQPRAGraph::GraphMetadata(MF, LIS, MBFI));
776 initializeGraph(G, VRM, *VRegSpiller);
777 ConstraintsRoot->apply(G);
780 if (PBQPDumpGraphs) {
781 std::ostringstream RS;
783 std::string GraphFileName = FullyQualifiedName + "." + RS.str() +
786 raw_fd_ostream OS(GraphFileName, EC, sys::fs::F_Text);
787 DEBUG(dbgs() << "Dumping graph for round " << Round << " to \""
788 << GraphFileName << "\"\n");
793 PBQP::Solution Solution = PBQP::RegAlloc::solve(G);
794 PBQPAllocComplete = mapPBQPToRegAlloc(G, Solution, VRM, *VRegSpiller);
799 // Finalise allocation, allocate empty ranges.
800 finalizeAlloc(MF, LIS, VRM);
801 VRegsToAlloc.clear();
802 EmptyIntervalVRegs.clear();
804 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << VRM << "\n");
809 /// Create Printable object for node and register info.
810 static Printable PrintNodeInfo(PBQP::RegAlloc::PBQPRAGraph::NodeId NId,
811 const PBQP::RegAlloc::PBQPRAGraph &G) {
812 return Printable([NId, &G](raw_ostream &OS) {
813 const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
814 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
815 unsigned VReg = G.getNodeMetadata(NId).getVReg();
816 const char *RegClassName = TRI->getRegClassName(MRI.getRegClass(VReg));
817 OS << NId << " (" << RegClassName << ':' << PrintReg(VReg, TRI) << ')';
821 void PBQP::RegAlloc::PBQPRAGraph::dump(raw_ostream &OS) const {
822 for (auto NId : nodeIds()) {
823 const Vector &Costs = getNodeCosts(NId);
824 assert(Costs.getLength() != 0 && "Empty vector in graph.");
825 OS << PrintNodeInfo(NId, *this) << ": " << Costs << '\n';
829 for (auto EId : edgeIds()) {
830 NodeId N1Id = getEdgeNode1Id(EId);
831 NodeId N2Id = getEdgeNode2Id(EId);
832 assert(N1Id != N2Id && "PBQP graphs should not have self-edges.");
833 const Matrix &M = getEdgeCosts(EId);
834 assert(M.getRows() != 0 && "No rows in matrix.");
835 assert(M.getCols() != 0 && "No cols in matrix.");
836 OS << PrintNodeInfo(N1Id, *this) << ' ' << M.getRows() << " rows / ";
837 OS << PrintNodeInfo(N2Id, *this) << ' ' << M.getCols() << " cols:\n";
842 void PBQP::RegAlloc::PBQPRAGraph::dump() const { dump(dbgs()); }
844 void PBQP::RegAlloc::PBQPRAGraph::printDot(raw_ostream &OS) const {
846 for (auto NId : nodeIds()) {
847 OS << " node" << NId << " [ label=\""
848 << PrintNodeInfo(NId, *this) << "\\n"
849 << getNodeCosts(NId) << "\" ]\n";
852 OS << " edge [ len=" << nodeIds().size() << " ]\n";
853 for (auto EId : edgeIds()) {
854 OS << " node" << getEdgeNode1Id(EId)
855 << " -- node" << getEdgeNode2Id(EId)
857 const Matrix &EdgeCosts = getEdgeCosts(EId);
858 for (unsigned i = 0; i < EdgeCosts.getRows(); ++i) {
859 OS << EdgeCosts.getRowAsVector(i) << "\\n";
866 FunctionPass *llvm::createPBQPRegisterAllocator(char *customPassID) {
867 return new RegAllocPBQP(customPassID);
870 FunctionPass* llvm::createDefaultPBQPRegisterAllocator() {
871 return createPBQPRegisterAllocator();