1 //===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
11 // register allocator for LLVM. This allocator works by constructing a PBQP
12 // problem representing the register allocation problem under consideration,
13 // solving this using a PBQP solver, and mapping the solution back to a
14 // register assignment. If any variables are selected for spilling then spill
15 // code is inserted and the process repeated.
17 // The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
18 // for register allocation. For more information on PBQP for register
19 // allocation, see the following papers:
21 // (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
22 // PBQP. In Proceedings of the 7th Joint Modular Languages Conference
23 // (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
25 // (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
26 // architectures. In Proceedings of the Joint Conference on Languages,
27 // Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
30 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "regalloc"
34 #include "PBQP/HeuristicSolver.h"
35 #include "PBQP/SimpleGraph.h"
36 #include "PBQP/Heuristics/Briggs.h"
37 #include "VirtRegMap.h"
38 #include "VirtRegRewriter.h"
39 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
40 #include "llvm/CodeGen/LiveStackAnalysis.h"
41 #include "llvm/CodeGen/MachineFunctionPass.h"
42 #include "llvm/CodeGen/MachineLoopInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/RegAllocRegistry.h"
45 #include "llvm/CodeGen/RegisterCoalescer.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/raw_ostream.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetMachine.h"
58 static RegisterRegAlloc
59 registerPBQPRepAlloc("pbqp", "PBQP register allocator.",
60 llvm::createPBQPRegisterAllocator);
65 /// PBQP based allocators solve the register allocation problem by mapping
66 /// register allocation problems to Partitioned Boolean Quadratic
67 /// Programming problems.
68 class VISIBILITY_HIDDEN PBQPRegAlloc : public MachineFunctionPass {
73 /// Construct a PBQP register allocator.
74 PBQPRegAlloc() : MachineFunctionPass(&ID) {}
76 /// Return the pass name.
77 virtual const char* getPassName() const {
78 return "PBQP Register Allocator";
81 /// PBQP analysis usage.
82 virtual void getAnalysisUsage(AnalysisUsage &au) const {
83 au.addRequired<LiveIntervals>();
84 //au.addRequiredID(SplitCriticalEdgesID);
85 au.addRequired<LiveStacks>();
86 au.addPreserved<LiveStacks>();
87 au.addRequired<MachineLoopInfo>();
88 au.addPreserved<MachineLoopInfo>();
89 au.addRequired<VirtRegMap>();
90 MachineFunctionPass::getAnalysisUsage(au);
93 /// Perform register allocation
94 virtual bool runOnMachineFunction(MachineFunction &MF);
97 typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
98 typedef std::vector<const LiveInterval*> Node2LIMap;
99 typedef std::vector<unsigned> AllowedSet;
100 typedef std::vector<AllowedSet> AllowedSetMap;
101 typedef std::set<unsigned> RegSet;
102 typedef std::pair<unsigned, unsigned> RegPair;
103 typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;
105 typedef std::set<LiveInterval*> LiveIntervalSet;
108 const TargetMachine *tm;
109 const TargetRegisterInfo *tri;
110 const TargetInstrInfo *tii;
111 const MachineLoopInfo *loopInfo;
112 MachineRegisterInfo *mri;
120 AllowedSetMap allowedSets;
121 LiveIntervalSet vregIntervalsToAlloc,
125 /// Builds a PBQP cost vector.
126 template <typename RegContainer>
127 PBQP::Vector buildCostVector(unsigned vReg,
128 const RegContainer &allowed,
129 const CoalesceMap &cealesces,
130 PBQP::PBQPNum spillCost) const;
132 /// \brief Builds a PBQP interference matrix.
134 /// @return Either a pointer to a non-zero PBQP matrix representing the
135 /// allocation option costs, or a null pointer for a zero matrix.
137 /// Expects allowed sets for two interfering LiveIntervals. These allowed
138 /// sets should contain only allocable registers from the LiveInterval's
139 /// register class, with any interfering pre-colored registers removed.
140 template <typename RegContainer>
141 PBQP::Matrix* buildInterferenceMatrix(const RegContainer &allowed1,
142 const RegContainer &allowed2) const;
145 /// Expects allowed sets for two potentially coalescable LiveIntervals,
146 /// and an estimated benefit due to coalescing. The allowed sets should
147 /// contain only allocable registers from the LiveInterval's register
148 /// classes, with any interfering pre-colored registers removed.
149 template <typename RegContainer>
150 PBQP::Matrix* buildCoalescingMatrix(const RegContainer &allowed1,
151 const RegContainer &allowed2,
152 PBQP::PBQPNum cBenefit) const;
154 /// \brief Finds coalescing opportunities and returns them as a map.
156 /// Any entries in the map are guaranteed coalescable, even if their
157 /// corresponding live intervals overlap.
158 CoalesceMap findCoalesces();
160 /// \brief Finds the initial set of vreg intervals to allocate.
161 void findVRegIntervalsToAlloc();
163 /// \brief Constructs a PBQP problem representation of the register
164 /// allocation problem for this function.
166 /// @return a PBQP solver object for the register allocation problem.
167 PBQP::SimpleGraph constructPBQPProblem();
169 /// \brief Adds a stack interval if the given live interval has been
170 /// spilled. Used to support stack slot coloring.
171 void addStackInterval(const LiveInterval *spilled,MachineRegisterInfo* mri);
173 /// \brief Given a solved PBQP problem maps this solution back to a register
175 bool mapPBQPToRegAlloc(const PBQP::Solution &solution);
177 /// \brief Postprocessing before final spilling. Sets basic block "live in"
179 void finalizeAlloc() const;
183 char PBQPRegAlloc::ID = 0;
187 template <typename RegContainer>
188 PBQP::Vector PBQPRegAlloc::buildCostVector(unsigned vReg,
189 const RegContainer &allowed,
190 const CoalesceMap &coalesces,
191 PBQP::PBQPNum spillCost) const {
193 typedef typename RegContainer::const_iterator AllowedItr;
195 // Allocate vector. Additional element (0th) used for spill option
196 PBQP::Vector v(allowed.size() + 1, 0);
200 // Iterate over the allowed registers inserting coalesce benefits if there
203 for (AllowedItr itr = allowed.begin(), end = allowed.end();
204 itr != end; ++itr, ++ai) {
206 unsigned pReg = *itr;
208 CoalesceMap::const_iterator cmItr =
209 coalesces.find(RegPair(vReg, pReg));
211 // No coalesce - on to the next preg.
212 if (cmItr == coalesces.end())
215 // We have a coalesce - insert the benefit.
216 v[ai + 1] = -cmItr->second;
222 template <typename RegContainer>
223 PBQP::Matrix* PBQPRegAlloc::buildInterferenceMatrix(
224 const RegContainer &allowed1, const RegContainer &allowed2) const {
226 typedef typename RegContainer::const_iterator RegContainerIterator;
228 // Construct a PBQP matrix representing the cost of allocation options. The
229 // rows and columns correspond to the allocation options for the two live
230 // intervals. Elements will be infinite where corresponding registers alias,
231 // since we cannot allocate aliasing registers to interfering live intervals.
232 // All other elements (non-aliasing combinations) will have zero cost. Note
233 // that the spill option (element 0,0) has zero cost, since we can allocate
234 // both intervals to memory safely (the cost for each individual allocation
235 // to memory is accounted for by the cost vectors for each live interval).
237 new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0);
239 // Assume this is a zero matrix until proven otherwise. Zero matrices occur
240 // between interfering live ranges with non-overlapping register sets (e.g.
241 // non-overlapping reg classes, or disjoint sets of allowed regs within the
242 // same class). The term "overlapping" is used advisedly: sets which do not
243 // intersect, but contain registers which alias, will have non-zero matrices.
244 // We optimize zero matrices away to improve solver speed.
245 bool isZeroMatrix = true;
248 // Row index. Starts at 1, since the 0th row is for the spill option, which
252 // Iterate over allowed sets, insert infinities where required.
253 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end();
254 a1Itr != a1End; ++a1Itr) {
256 // Column index, starts at 1 as for row index.
258 unsigned reg1 = *a1Itr;
260 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end();
261 a2Itr != a2End; ++a2Itr) {
263 unsigned reg2 = *a2Itr;
265 // If the row/column regs are identical or alias insert an infinity.
266 if ((reg1 == reg2) || tri->areAliases(reg1, reg2)) {
267 (*m)[ri][ci] = std::numeric_limits<PBQP::PBQPNum>::infinity();
268 isZeroMatrix = false;
277 // If this turns out to be a zero matrix...
279 // free it and return null.
284 // ...otherwise return the cost matrix.
288 template <typename RegContainer>
289 PBQP::Matrix* PBQPRegAlloc::buildCoalescingMatrix(
290 const RegContainer &allowed1, const RegContainer &allowed2,
291 PBQP::PBQPNum cBenefit) const {
293 typedef typename RegContainer::const_iterator RegContainerIterator;
295 // Construct a PBQP Matrix representing the benefits of coalescing. As with
296 // interference matrices the rows and columns represent allowed registers
297 // for the LiveIntervals which are (potentially) to be coalesced. The amount
298 // -cBenefit will be placed in any element representing the same register
299 // for both intervals.
301 new PBQP::Matrix(allowed1.size() + 1, allowed2.size() + 1, 0);
303 // Reset costs to zero.
306 // Assume the matrix is zero till proven otherwise. Zero matrices will be
307 // optimized away as in the interference case.
308 bool isZeroMatrix = true;
310 // Row index. Starts at 1, since the 0th row is for the spill option, which
314 // Iterate over the allowed sets, insert coalescing benefits where
316 for (RegContainerIterator a1Itr = allowed1.begin(), a1End = allowed1.end();
317 a1Itr != a1End; ++a1Itr) {
319 // Column index, starts at 1 as for row index.
321 unsigned reg1 = *a1Itr;
323 for (RegContainerIterator a2Itr = allowed2.begin(), a2End = allowed2.end();
324 a2Itr != a2End; ++a2Itr) {
326 // If the row and column represent the same register insert a beneficial
327 // cost to preference this allocation - it would allow us to eliminate a
329 if (reg1 == *a2Itr) {
330 (*m)[ri][ci] = -cBenefit;
331 isZeroMatrix = false;
340 // If this turns out to be a zero matrix...
342 // ...free it and return null.
350 PBQPRegAlloc::CoalesceMap PBQPRegAlloc::findCoalesces() {
352 typedef MachineFunction::const_iterator MFIterator;
353 typedef MachineBasicBlock::const_iterator MBBIterator;
354 typedef LiveInterval::const_vni_iterator VNIIterator;
356 CoalesceMap coalescesFound;
358 // To find coalesces we need to iterate over the function looking for
359 // copy instructions.
360 for (MFIterator bbItr = mf->begin(), bbEnd = mf->end();
361 bbItr != bbEnd; ++bbItr) {
363 const MachineBasicBlock *mbb = &*bbItr;
365 for (MBBIterator iItr = mbb->begin(), iEnd = mbb->end();
366 iItr != iEnd; ++iItr) {
368 const MachineInstr *instr = &*iItr;
369 unsigned srcReg, dstReg, srcSubReg, dstSubReg;
371 // If this isn't a copy then continue to the next instruction.
372 if (!tii->isMoveInstr(*instr, srcReg, dstReg, srcSubReg, dstSubReg))
375 // If the registers are already the same our job is nice and easy.
376 if (dstReg == srcReg)
379 bool srcRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(srcReg),
380 dstRegIsPhysical = TargetRegisterInfo::isPhysicalRegister(dstReg);
382 // If both registers are physical then we can't coalesce.
383 if (srcRegIsPhysical && dstRegIsPhysical)
386 // If it's a copy that includes a virtual register but the source and
387 // destination classes differ then we can't coalesce, so continue with
388 // the next instruction.
389 const TargetRegisterClass *srcRegClass = srcRegIsPhysical ?
390 tri->getPhysicalRegisterRegClass(srcReg) : mri->getRegClass(srcReg);
392 const TargetRegisterClass *dstRegClass = dstRegIsPhysical ?
393 tri->getPhysicalRegisterRegClass(dstReg) : mri->getRegClass(dstReg);
395 if (srcRegClass != dstRegClass)
398 // We also need any physical regs to be allocable, coalescing with
399 // a non-allocable register is invalid.
400 if (srcRegIsPhysical) {
401 if (std::find(srcRegClass->allocation_order_begin(*mf),
402 srcRegClass->allocation_order_end(*mf), srcReg) ==
403 srcRegClass->allocation_order_end(*mf))
407 if (dstRegIsPhysical) {
408 if (std::find(dstRegClass->allocation_order_begin(*mf),
409 dstRegClass->allocation_order_end(*mf), dstReg) ==
410 dstRegClass->allocation_order_end(*mf))
414 // If we've made it here we have a copy with compatible register classes.
415 // We can probably coalesce, but we need to consider overlap.
416 const LiveInterval *srcLI = &lis->getInterval(srcReg),
417 *dstLI = &lis->getInterval(dstReg);
419 if (srcLI->overlaps(*dstLI)) {
420 // Even in the case of an overlap we might still be able to coalesce,
421 // but we need to make sure that no definition of either range occurs
422 // while the other range is live.
424 // Otherwise start by assuming we're ok.
427 // Test all defs of the source range.
429 vniItr = srcLI->vni_begin(), vniEnd = srcLI->vni_end();
430 vniItr != vniEnd; ++vniItr) {
432 // If we find a def that kills the coalescing opportunity then
433 // record it and break from the loop.
434 if (dstLI->liveAt((*vniItr)->def)) {
440 // If we have a bad def give up, continue to the next instruction.
444 // Otherwise test definitions of the destination range.
446 vniItr = dstLI->vni_begin(), vniEnd = dstLI->vni_end();
447 vniItr != vniEnd; ++vniItr) {
449 // We want to make sure we skip the copy instruction itself.
450 if ((*vniItr)->getCopy() == instr)
453 if (srcLI->liveAt((*vniItr)->def)) {
459 // As before a bad def we give up and continue to the next instr.
464 // If we make it to here then either the ranges didn't overlap, or they
465 // did, but none of their definitions would prevent us from coalescing.
466 // We're good to go with the coalesce.
468 float cBenefit = powf(10.0f, loopInfo->getLoopDepth(mbb)) / 5.0;
470 coalescesFound[RegPair(srcReg, dstReg)] = cBenefit;
471 coalescesFound[RegPair(dstReg, srcReg)] = cBenefit;
476 return coalescesFound;
479 void PBQPRegAlloc::findVRegIntervalsToAlloc() {
481 // Iterate over all live ranges.
482 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end();
485 // Ignore physical ones.
486 if (TargetRegisterInfo::isPhysicalRegister(itr->first))
489 LiveInterval *li = itr->second;
491 // If this live interval is non-empty we will use pbqp to allocate it.
492 // Empty intervals we allocate in a simple post-processing stage in
495 vregIntervalsToAlloc.insert(li);
498 emptyVRegIntervals.insert(li);
503 PBQP::SimpleGraph PBQPRegAlloc::constructPBQPProblem() {
505 typedef std::vector<const LiveInterval*> LIVector;
506 typedef std::vector<unsigned> RegVector;
507 typedef std::vector<PBQP::SimpleGraph::NodeIterator> NodeVector;
509 // This will store the physical intervals for easy reference.
510 LIVector physIntervals;
512 // Start by clearing the old node <-> live interval mappings & allowed sets
517 // Populate physIntervals, update preg use:
518 for (LiveIntervals::iterator itr = lis->begin(), end = lis->end();
521 if (TargetRegisterInfo::isPhysicalRegister(itr->first)) {
522 physIntervals.push_back(itr->second);
523 mri->setPhysRegUsed(itr->second->reg);
527 // Iterate over vreg intervals, construct live interval <-> node number
529 for (LiveIntervalSet::const_iterator
530 itr = vregIntervalsToAlloc.begin(), end = vregIntervalsToAlloc.end();
532 const LiveInterval *li = *itr;
534 li2Node[li] = node2LI.size();
535 node2LI.push_back(li);
538 // Get the set of potential coalesces.
539 CoalesceMap coalesces;//(findCoalesces());
541 // Construct a PBQP solver for this problem
542 PBQP::SimpleGraph problem;
543 NodeVector problemNodes(vregIntervalsToAlloc.size());
545 // Resize allowedSets container appropriately.
546 allowedSets.resize(vregIntervalsToAlloc.size());
548 // Iterate over virtual register intervals to compute allowed sets...
549 for (unsigned node = 0; node < node2LI.size(); ++node) {
551 // Grab pointers to the interval and its register class.
552 const LiveInterval *li = node2LI[node];
553 const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
555 // Start by assuming all allocable registers in the class are allowed...
556 RegVector liAllowed(liRC->allocation_order_begin(*mf),
557 liRC->allocation_order_end(*mf));
559 // Eliminate the physical registers which overlap with this range, along
560 // with all their aliases.
561 for (LIVector::iterator pItr = physIntervals.begin(),
562 pEnd = physIntervals.end(); pItr != pEnd; ++pItr) {
564 if (!li->overlaps(**pItr))
567 unsigned pReg = (*pItr)->reg;
569 // If we get here then the live intervals overlap, but we're still ok
570 // if they're coalescable.
571 if (coalesces.find(RegPair(li->reg, pReg)) != coalesces.end())
574 // If we get here then we have a genuine exclusion.
576 // Remove the overlapping reg...
577 RegVector::iterator eraseItr =
578 std::find(liAllowed.begin(), liAllowed.end(), pReg);
580 if (eraseItr != liAllowed.end())
581 liAllowed.erase(eraseItr);
583 const unsigned *aliasItr = tri->getAliasSet(pReg);
586 // ...and its aliases.
587 for (; *aliasItr != 0; ++aliasItr) {
588 RegVector::iterator eraseItr =
589 std::find(liAllowed.begin(), liAllowed.end(), *aliasItr);
591 if (eraseItr != liAllowed.end()) {
592 liAllowed.erase(eraseItr);
598 // Copy the allowed set into a member vector for use when constructing cost
599 // vectors & matrices, and mapping PBQP solutions back to assignments.
600 allowedSets[node] = AllowedSet(liAllowed.begin(), liAllowed.end());
602 // Set the spill cost to the interval weight, or epsilon if the
603 // interval weight is zero
604 PBQP::PBQPNum spillCost = (li->weight != 0.0) ?
605 li->weight : std::numeric_limits<PBQP::PBQPNum>::min();
607 // Build a cost vector for this interval.
610 buildCostVector(li->reg, allowedSets[node], coalesces, spillCost));
615 // Now add the cost matrices...
616 for (unsigned node1 = 0; node1 < node2LI.size(); ++node1) {
617 const LiveInterval *li = node2LI[node1];
619 // Test for live range overlaps and insert interference matrices.
620 for (unsigned node2 = node1 + 1; node2 < node2LI.size(); ++node2) {
621 const LiveInterval *li2 = node2LI[node2];
623 CoalesceMap::const_iterator cmItr =
624 coalesces.find(RegPair(li->reg, li2->reg));
628 if (cmItr != coalesces.end()) {
629 m = buildCoalescingMatrix(allowedSets[node1], allowedSets[node2],
632 else if (li->overlaps(*li2)) {
633 m = buildInterferenceMatrix(allowedSets[node1], allowedSets[node2]);
637 problem.addEdge(problemNodes[node1],
646 problem.assignNodeIDs();
648 assert(problem.getNumNodes() == allowedSets.size());
649 for (unsigned i = 0; i < allowedSets.size(); ++i) {
650 assert(problem.getNodeItr(i) == problemNodes[i]);
653 std::cerr << "Allocating for " << problem.getNumNodes() << " nodes, "
654 << problem.getNumEdges() << " edges.\n";
656 problem.printDot(std::cerr);
658 // We're done, PBQP problem constructed - return it.
662 void PBQPRegAlloc::addStackInterval(const LiveInterval *spilled,
663 MachineRegisterInfo* mri) {
664 int stackSlot = vrm->getStackSlot(spilled->reg);
666 if (stackSlot == VirtRegMap::NO_STACK_SLOT)
669 const TargetRegisterClass *RC = mri->getRegClass(spilled->reg);
670 LiveInterval &stackInterval = lss->getOrCreateInterval(stackSlot, RC);
673 if (stackInterval.getNumValNums() != 0)
674 vni = stackInterval.getValNumInfo(0);
676 vni = stackInterval.getNextValue(0, 0, false, lss->getVNInfoAllocator());
678 LiveInterval &rhsInterval = lis->getInterval(spilled->reg);
679 stackInterval.MergeRangesInAsValue(rhsInterval, vni);
682 bool PBQPRegAlloc::mapPBQPToRegAlloc(const PBQP::Solution &solution) {
684 static unsigned round = 0;
687 // Set to true if we have any spills
688 bool anotherRoundNeeded = false;
690 // Clear the existing allocation.
693 // Iterate over the nodes mapping the PBQP solution to a register assignment.
694 for (unsigned node = 0; node < node2LI.size(); ++node) {
695 unsigned virtReg = node2LI[node]->reg,
696 allocSelection = solution.getSelection(node);
699 // If the PBQP solution is non-zero it's a physical register...
700 if (allocSelection != 0) {
701 // Get the physical reg, subtracting 1 to account for the spill option.
702 unsigned physReg = allowedSets[node][allocSelection - 1];
704 DOUT << "VREG " << virtReg << " -> " << tri->getName(physReg) << "\n";
706 assert(physReg != 0);
708 // Add to the virt reg map and update the used phys regs.
709 vrm->assignVirt2Phys(virtReg, physReg);
711 // ...Otherwise it's a spill.
714 // Make sure we ignore this virtual reg on the next round
716 vregIntervalsToAlloc.erase(&lis->getInterval(virtReg));
718 // Insert spill ranges for this live range
719 const LiveInterval *spillInterval = node2LI[node];
720 double oldSpillWeight = spillInterval->weight;
721 SmallVector<LiveInterval*, 8> spillIs;
722 std::vector<LiveInterval*> newSpills =
723 lis->addIntervalsForSpills(*spillInterval, spillIs, loopInfo, *vrm);
724 addStackInterval(spillInterval, mri);
726 DOUT << "VREG " << virtReg << " -> SPILLED (Cost: "
727 << oldSpillWeight << ", New vregs: ";
729 // Copy any newly inserted live intervals into the list of regs to
731 for (std::vector<LiveInterval*>::const_iterator
732 itr = newSpills.begin(), end = newSpills.end();
735 assert(!(*itr)->empty() && "Empty spill range.");
737 DOUT << (*itr)->reg << " ";
739 vregIntervalsToAlloc.insert(*itr);
744 // We need another round if spill intervals were added.
745 anotherRoundNeeded |= !newSpills.empty();
749 return !anotherRoundNeeded;
752 void PBQPRegAlloc::finalizeAlloc() const {
753 typedef LiveIntervals::iterator LIIterator;
754 typedef LiveInterval::Ranges::const_iterator LRIterator;
756 // First allocate registers for the empty intervals.
757 for (LiveIntervalSet::const_iterator
758 itr = emptyVRegIntervals.begin(), end = emptyVRegIntervals.end();
760 LiveInterval *li = *itr;
762 unsigned physReg = vrm->getRegAllocPref(li->reg);
765 const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
766 physReg = *liRC->allocation_order_begin(*mf);
769 vrm->assignVirt2Phys(li->reg, physReg);
772 // Finally iterate over the basic blocks to compute and set the live-in sets.
773 SmallVector<MachineBasicBlock*, 8> liveInMBBs;
774 MachineBasicBlock *entryMBB = &*mf->begin();
776 for (LIIterator liItr = lis->begin(), liEnd = lis->end();
777 liItr != liEnd; ++liItr) {
779 const LiveInterval *li = liItr->second;
782 // Get the physical register for this interval
783 if (TargetRegisterInfo::isPhysicalRegister(li->reg)) {
786 else if (vrm->isAssignedReg(li->reg)) {
787 reg = vrm->getPhys(li->reg);
790 // Ranges which are assigned a stack slot only are ignored.
795 // Filter out zero regs - they're for intervals that were spilled.
799 // Iterate over the ranges of the current interval...
800 for (LRIterator lrItr = li->begin(), lrEnd = li->end();
801 lrItr != lrEnd; ++lrItr) {
803 // Find the set of basic blocks which this range is live into...
804 if (lis->findLiveInMBBs(lrItr->start, lrItr->end, liveInMBBs)) {
805 // And add the physreg for this interval to their live-in sets.
806 for (unsigned i = 0; i < liveInMBBs.size(); ++i) {
807 if (liveInMBBs[i] != entryMBB) {
808 if (!liveInMBBs[i]->isLiveIn(reg)) {
809 liveInMBBs[i]->addLiveIn(reg);
820 bool PBQPRegAlloc::runOnMachineFunction(MachineFunction &MF) {
823 tm = &mf->getTarget();
824 tri = tm->getRegisterInfo();
825 tii = tm->getInstrInfo();
826 mri = &mf->getRegInfo();
828 lis = &getAnalysis<LiveIntervals>();
829 lss = &getAnalysis<LiveStacks>();
830 loopInfo = &getAnalysis<MachineLoopInfo>();
832 vrm = &getAnalysis<VirtRegMap>();
834 DEBUG(errs() << "PBQP2 Register Allocating for " << mf->getFunction()->getName() << "\n");
836 // Allocator main loop:
838 // * Map current regalloc problem to a PBQP problem
839 // * Solve the PBQP problem
840 // * Map the solution back to a register allocation
841 // * Spill if necessary
843 // This process is continued till no more spills are generated.
845 // Find the vreg intervals in need of allocation.
846 findVRegIntervalsToAlloc();
848 // If there aren't any then we're done here.
849 if (vregIntervalsToAlloc.empty() && emptyVRegIntervals.empty())
852 // If there are non-empty intervals allocate them using pbqp.
853 if (!vregIntervalsToAlloc.empty()) {
855 bool pbqpAllocComplete = false;
858 while (!pbqpAllocComplete) {
859 DEBUG(errs() << " PBQP Regalloc round " << round << ":\n");
861 PBQP::SimpleGraph problem = constructPBQPProblem();
862 PBQP::HeuristicSolver<PBQP::Heuristics::Briggs> solver;
863 problem.assignNodeIDs();
864 PBQP::Solution solution = solver.solve(problem);
866 std::cerr << "Solution:\n";
867 for (unsigned i = 0; i < solution.numNodes(); ++i) {
868 std::cerr << " " << i << " -> " << solution.getSelection(i) << "\n";
871 pbqpAllocComplete = mapPBQPToRegAlloc(solution);
877 // Finalise allocation, allocate empty ranges.
880 vregIntervalsToAlloc.clear();
881 emptyVRegIntervals.clear();
886 DEBUG(errs() << "Post alloc VirtRegMap:\n" << *vrm << "\n");
889 std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
891 rewriter->runOnMachineFunction(*mf, *vrm, lis);
896 FunctionPass* llvm::createPBQPRegisterAllocator() {
897 return new PBQPRegAlloc();