1 //===-- RegAllocSimple.cpp - A simple generic register allocator ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register allocator. *Very* simple: It immediate
11 // spills every value right after it is computed, and it reloads all used
12 // operands from the spill area to temporary registers before each instruction.
13 // It does not keep values in registers across instructions.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "regalloc"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "Support/Debug.h"
26 #include "Support/Statistic.h"
31 Statistic<> NumSpilled ("ra-simple", "Number of registers spilled");
32 Statistic<> NumReloaded("ra-simple", "Number of registers reloaded");
34 class RegAllocSimple : public MachineFunctionPass {
36 const TargetMachine *TM;
37 const MRegisterInfo *RegInfo;
39 // StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
40 // these values are spilled
41 std::map<unsigned, int> StackSlotForVirtReg;
43 // RegsUsed - Keep track of what registers are currently in use. This is a
45 std::vector<bool> RegsUsed;
47 // RegClassIdx - Maps RegClass => which index we can take a register
48 // from. Since this is a simple register allocator, when we need a register
49 // of a certain class, we just take the next available one.
50 std::map<const TargetRegisterClass*, unsigned> RegClassIdx;
53 virtual const char *getPassName() const {
54 return "Simple Register Allocator";
57 /// runOnMachineFunction - Register allocate the whole function
58 bool runOnMachineFunction(MachineFunction &Fn);
60 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequiredID(PHIEliminationID); // Eliminate PHI nodes
62 MachineFunctionPass::getAnalysisUsage(AU);
65 /// AllocateBasicBlock - Register allocate the specified basic block.
66 void AllocateBasicBlock(MachineBasicBlock &MBB);
68 /// getStackSpaceFor - This returns the offset of the specified virtual
69 /// register on the stack, allocating space if necessary.
70 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
72 /// Given a virtual register, return a compatible physical register that is
75 /// Side effect: marks that register as being used until manually cleared
77 unsigned getFreeReg(unsigned virtualReg);
79 /// Moves value from memory into that register
80 unsigned reloadVirtReg(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator &I, unsigned VirtReg);
83 /// Saves reg value on the stack (maps virtual register to stack value)
84 void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
85 unsigned VirtReg, unsigned PhysReg);
90 /// getStackSpaceFor - This allocates space for the specified virtual
91 /// register to be held on the stack.
92 int RegAllocSimple::getStackSpaceFor(unsigned VirtReg,
93 const TargetRegisterClass *RC) {
94 // Find the location VirtReg would belong...
95 std::map<unsigned, int>::iterator I =
96 StackSlotForVirtReg.lower_bound(VirtReg);
98 if (I != StackSlotForVirtReg.end() && I->first == VirtReg)
99 return I->second; // Already has space allocated?
101 // Allocate a new stack object for this spill location...
102 int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC);
104 // Assign the slot...
105 StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx));
110 unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
111 const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(virtualReg);
112 TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
113 TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
116 unsigned regIdx = RegClassIdx[RC]++;
117 assert(RI+regIdx != RE && "Not enough registers!");
118 unsigned PhysReg = *(RI+regIdx);
120 if (!RegsUsed[PhysReg])
125 unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
126 MachineBasicBlock::iterator &I,
128 const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
129 int FrameIdx = getStackSpaceFor(VirtReg, RC);
130 unsigned PhysReg = getFreeReg(VirtReg);
132 // Add move instruction(s)
134 RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
138 void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
139 MachineBasicBlock::iterator &I,
140 unsigned VirtReg, unsigned PhysReg) {
141 const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
142 int FrameIdx = getStackSpaceFor(VirtReg, RC);
144 // Add move instruction(s)
146 RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC);
150 void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
151 // loop over each instruction
152 for (MachineBasicBlock::iterator MI = MBB.begin(); MI != MBB.end(); ++MI) {
153 // Made to combat the incorrect allocation of r2 = add r1, r1
154 std::map<unsigned, unsigned> Virt2PhysRegMap;
156 RegsUsed.resize(RegInfo->getNumRegs());
158 // a preliminary pass that will invalidate any registers that
159 // are used by the instruction (including implicit uses)
160 unsigned Opcode = MI->getOpcode();
161 const TargetInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode);
162 const unsigned *Regs = Desc.ImplicitUses;
164 RegsUsed[*Regs++] = true;
166 Regs = Desc.ImplicitDefs;
168 RegsUsed[*Regs++] = true;
170 // Loop over uses, move from memory into registers
171 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
172 MachineOperand &op = MI->getOperand(i);
174 if (op.isRegister() && MRegisterInfo::isVirtualRegister(op.getReg())) {
175 unsigned virtualReg = (unsigned) op.getReg();
176 DEBUG(std::cerr << "op: " << op << "\n");
177 DEBUG(std::cerr << "\t inst[" << i << "]: ";
178 MI->print(std::cerr, *TM));
180 // make sure the same virtual register maps to the same physical
181 // register in any given instruction
182 unsigned physReg = Virt2PhysRegMap[virtualReg];
185 if (!TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) || i) {
186 physReg = getFreeReg(virtualReg);
188 // must be same register number as the first operand
189 // This maps a = b + c into b += c, and saves b into a's spot
190 assert(MI->getOperand(1).isRegister() &&
191 MI->getOperand(1).getReg() &&
192 MI->getOperand(1).isUse() &&
193 "Two address instruction invalid!");
195 physReg = MI->getOperand(1).getReg();
198 spillVirtReg(MBB, MI, virtualReg, physReg);
200 MI->getOperand(1).setDef();
201 MI->RemoveOperand(0);
202 break; // This is the last operand to process
205 spillVirtReg(MBB, MI, virtualReg, physReg);
208 physReg = reloadVirtReg(MBB, MI, virtualReg);
209 Virt2PhysRegMap[virtualReg] = physReg;
212 MI->SetMachineOperandReg(i, physReg);
213 DEBUG(std::cerr << "virt: " << virtualReg <<
214 ", phys: " << op.getReg() << "\n");
223 /// runOnMachineFunction - Register allocate the whole function
225 bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
226 DEBUG(std::cerr << "Machine Function " << "\n");
228 TM = &MF->getTarget();
229 RegInfo = TM->getRegisterInfo();
231 // Loop over all of the basic blocks, eliminating virtual register references
232 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
234 AllocateBasicBlock(*MBB);
236 StackSlotForVirtReg.clear();
240 FunctionPass *llvm::createSimpleRegisterAllocator() {
241 return new RegAllocSimple();