1 //===-- RegisterClassInfo.cpp - Dynamic Register Class Info ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the RegisterClassInfo class which provides dynamic
11 // information about target register classes. Callee saved and reserved
12 // registers depends on calling conventions and other dynamic information, so
13 // some things cannot be determined statically.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "regalloc"
18 #include "RegisterClassInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/raw_ostream.h"
27 static cl::opt<unsigned>
28 StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
29 cl::desc("Limit all regclasses to N registers"));
31 RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0)
34 void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
38 // Allocate new array the first time we see a new target.
39 if (MF->getTarget().getRegisterInfo() != TRI) {
40 TRI = MF->getTarget().getRegisterInfo();
41 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
45 // Does this MF have different CSRs?
46 const uint16_t *CSR = TRI->getCalleeSavedRegs(MF);
47 if (Update || CSR != CalleeSaved) {
48 // Build a CSRNum map. Every CSR alias gets an entry pointing to the last
51 CSRNum.resize(TRI->getNumRegs(), 0);
52 for (unsigned N = 0; unsigned Reg = CSR[N]; ++N)
53 for (const uint16_t *AS = TRI->getOverlaps(Reg);
54 unsigned Alias = *AS; ++AS)
55 CSRNum[Alias] = N + 1; // 0 means no CSR, 1 means CalleeSaved[0], ...
60 // Different reserved registers?
61 BitVector RR = TRI->getReservedRegs(*MF);
66 // Invalidate cached information from previous function.
71 /// compute - Compute the preferred allocation order for RC with reserved
72 /// registers filtered out. Volatile registers come first followed by CSR
73 /// aliases ordered according to the CSR order specified by the target.
74 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
75 RCInfo &RCI = RegClass[RC->getID()];
77 // Raw register count, including all reserved regs.
78 unsigned NumRegs = RC->getNumRegs();
81 RCI.Order.reset(new unsigned[NumRegs]);
84 SmallVector<unsigned, 16> CSRAlias;
86 // FIXME: Once targets reserve registers instead of removing them from the
87 // allocation order, we can simply use begin/end here.
88 ArrayRef<uint16_t> RawOrder = RC->getRawAllocationOrder(*MF);
89 for (unsigned i = 0; i != RawOrder.size(); ++i) {
90 unsigned PhysReg = RawOrder[i];
91 // Remove reserved registers from the allocation order.
92 if (Reserved.test(PhysReg))
95 // PhysReg aliases a CSR, save it for later.
96 CSRAlias.push_back(PhysReg);
98 RCI.Order[N++] = PhysReg;
100 RCI.NumRegs = N + CSRAlias.size();
101 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
103 // CSR aliases go after the volatile registers, preserve the target's order.
104 std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N]);
106 // Register allocator stress test. Clip register class to N registers.
107 if (StressRA && RCI.NumRegs > StressRA)
108 RCI.NumRegs = StressRA;
110 // Check if RC is a proper sub-class.
111 if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC))
112 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
113 RCI.ProperSubClass = true;
116 dbgs() << "AllocationOrder(" << RC->getName() << ") = [";
117 for (unsigned I = 0; I != RCI.NumRegs; ++I)
118 dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
119 dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
122 // RCI is now up-to-date.