1 //===- RegisterCoalescer.cpp - Generic Register Coalescing Interface -------==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the generic RegisterCoalescer interface which
11 // is used as the common interface used by all clients and
12 // implementations of register coalescing.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "regalloc"
17 #include "RegisterCoalescer.h"
18 #include "LiveDebugVariables.h"
19 #include "RegisterClassInfo.h"
20 #include "VirtRegMap.h"
22 #include "llvm/Pass.h"
23 #include "llvm/Value.h"
24 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
30 #include "llvm/Analysis/AliasAnalysis.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineLoopInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/ErrorHandling.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include "llvm/ADT/OwningPtr.h"
44 #include "llvm/ADT/SmallSet.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/STLExtras.h"
51 STATISTIC(numJoins , "Number of interval joins performed");
52 STATISTIC(numCrossRCs , "Number of cross class joins performed");
53 STATISTIC(numCommutes , "Number of instruction commuting performed");
54 STATISTIC(numExtends , "Number of copies extended");
55 STATISTIC(NumReMats , "Number of instructions re-materialized");
56 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
57 STATISTIC(numAborts , "Number of times interval joining aborted");
58 STATISTIC(NumInflated , "Number of register classes inflated");
61 EnableJoining("join-liveintervals",
62 cl::desc("Coalesce copies (default=true)"),
66 EnablePhysicalJoin("join-physregs",
67 cl::desc("Join physical register copies"),
68 cl::init(false), cl::Hidden);
71 VerifyCoalescing("verify-coalescing",
72 cl::desc("Verify machine instrs before and after register coalescing"),
76 class RegisterCoalescer : public MachineFunctionPass {
78 MachineRegisterInfo* MRI;
79 const TargetMachine* TM;
80 const TargetRegisterInfo* TRI;
81 const TargetInstrInfo* TII;
83 LiveDebugVariables *LDV;
84 const MachineLoopInfo* Loops;
86 RegisterClassInfo RegClassInfo;
88 /// JoinedCopies - Keep track of copies eliminated due to coalescing.
90 SmallPtrSet<MachineInstr*, 32> JoinedCopies;
92 /// ReMatCopies - Keep track of copies eliminated due to remat.
94 SmallPtrSet<MachineInstr*, 32> ReMatCopies;
96 /// ReMatDefs - Keep track of definition instructions which have
98 SmallPtrSet<MachineInstr*, 8> ReMatDefs;
100 /// joinAllIntervals - join compatible live intervals
101 void joinAllIntervals();
103 /// copyCoalesceInMBB - Coalesce copies in the specified MBB, putting
104 /// copies that cannot yet be coalesced into the "TryAgain" list.
105 void copyCoalesceInMBB(MachineBasicBlock *MBB,
106 std::vector<MachineInstr*> &TryAgain);
108 /// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
109 /// which are the src/dst of the copy instruction CopyMI. This returns
110 /// true if the copy was successfully coalesced away. If it is not
111 /// currently possible to coalesce this interval, but it may be possible if
112 /// other things get coalesced, then it returns true by reference in
114 bool joinCopy(MachineInstr *TheCopy, bool &Again);
116 /// joinIntervals - Attempt to join these two intervals. On failure, this
117 /// returns false. The output "SrcInt" will not have been modified, so we
118 /// can use this information below to update aliases.
119 bool joinIntervals(CoalescerPair &CP);
121 /// Attempt joining with a reserved physreg.
122 bool joinReservedPhysReg(CoalescerPair &CP);
124 /// Check for interference with a normal unreserved physreg.
125 bool canJoinPhysReg(CoalescerPair &CP);
127 /// adjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
128 /// the source value number is defined by a copy from the destination reg
129 /// see if we can merge these two destination reg valno# into a single
130 /// value number, eliminating a copy.
131 bool adjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
133 /// hasOtherReachingDefs - Return true if there are definitions of IntB
134 /// other than BValNo val# that can reach uses of AValno val# of IntA.
135 bool hasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
136 VNInfo *AValNo, VNInfo *BValNo);
138 /// removeCopyByCommutingDef - We found a non-trivially-coalescable copy.
139 /// If the source value number is defined by a commutable instruction and
140 /// its other operand is coalesced to the copy dest register, see if we
141 /// can transform the copy into a noop by commuting the definition.
142 bool removeCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
144 /// reMaterializeTrivialDef - If the source of a copy is defined by a
145 /// trivial computation, replace the copy by rematerialize the definition.
146 /// If PreserveSrcInt is true, make sure SrcInt is valid after the call.
147 bool reMaterializeTrivialDef(LiveInterval &SrcInt, bool PreserveSrcInt,
148 unsigned DstReg, MachineInstr *CopyMI);
150 /// shouldJoinPhys - Return true if a physreg copy should be joined.
151 bool shouldJoinPhys(CoalescerPair &CP);
153 /// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
154 /// update the subregister number if it is not zero. If DstReg is a
155 /// physical register and the existing subregister number of the def / use
156 /// being updated is not zero, make sure to set it to the correct physical
158 void updateRegDefsUses(const CoalescerPair &CP);
160 /// removeDeadDef - If a def of a live interval is now determined dead,
161 /// remove the val# it defines. If the live interval becomes empty, remove
163 bool removeDeadDef(LiveInterval &li, MachineInstr *DefMI);
165 /// markAsJoined - Remember that CopyMI has already been joined.
166 void markAsJoined(MachineInstr *CopyMI);
168 /// eliminateUndefCopy - Handle copies of undef values.
169 bool eliminateUndefCopy(MachineInstr *CopyMI, const CoalescerPair &CP);
172 static char ID; // Class identification, replacement for typeinfo
173 RegisterCoalescer() : MachineFunctionPass(ID) {
174 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
177 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
179 virtual void releaseMemory();
181 /// runOnMachineFunction - pass entry point
182 virtual bool runOnMachineFunction(MachineFunction&);
184 /// print - Implement the dump method.
185 virtual void print(raw_ostream &O, const Module* = 0) const;
187 } /// end anonymous namespace
189 char &llvm::RegisterCoalescerID = RegisterCoalescer::ID;
191 INITIALIZE_PASS_BEGIN(RegisterCoalescer, "simple-register-coalescing",
192 "Simple Register Coalescing", false, false)
193 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
194 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
195 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
196 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
197 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
198 INITIALIZE_PASS_END(RegisterCoalescer, "simple-register-coalescing",
199 "Simple Register Coalescing", false, false)
201 char RegisterCoalescer::ID = 0;
203 static unsigned compose(const TargetRegisterInfo &tri, unsigned a, unsigned b) {
206 return tri.composeSubRegIndices(a, b);
209 static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI,
210 unsigned &Src, unsigned &Dst,
211 unsigned &SrcSub, unsigned &DstSub) {
213 Dst = MI->getOperand(0).getReg();
214 DstSub = MI->getOperand(0).getSubReg();
215 Src = MI->getOperand(1).getReg();
216 SrcSub = MI->getOperand(1).getSubReg();
217 } else if (MI->isSubregToReg()) {
218 Dst = MI->getOperand(0).getReg();
219 DstSub = compose(tri, MI->getOperand(0).getSubReg(),
220 MI->getOperand(3).getImm());
221 Src = MI->getOperand(2).getReg();
222 SrcSub = MI->getOperand(2).getSubReg();
228 bool CoalescerPair::setRegisters(const MachineInstr *MI) {
232 Flipped = CrossClass = false;
234 unsigned Src, Dst, SrcSub, DstSub;
235 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
237 Partial = SrcSub || DstSub;
239 // If one register is a physreg, it must be Dst.
240 if (TargetRegisterInfo::isPhysicalRegister(Src)) {
241 if (TargetRegisterInfo::isPhysicalRegister(Dst))
244 std::swap(SrcSub, DstSub);
248 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
250 if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
251 // Eliminate DstSub on a physreg.
253 Dst = TRI.getSubReg(Dst, DstSub);
254 if (!Dst) return false;
258 // Eliminate SrcSub by picking a corresponding Dst superregister.
260 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
261 if (!Dst) return false;
263 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
267 // Both registers are virtual.
268 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
269 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
271 // Both registers have subreg indices.
272 if (SrcSub && DstSub) {
273 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
278 // We cannot handle the case where both Src and Dst would be a
279 // sub-register. Yet.
280 if (SrcIdx && DstIdx) {
281 DEBUG(dbgs() << "\tCannot handle " << NewRC->getName()
282 << " with subregs " << TRI.getSubRegIndexName(SrcIdx)
283 << " and " << TRI.getSubRegIndexName(DstIdx) << '\n');
287 // SrcReg will be merged with a sub-register of DstReg.
289 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
291 // DstReg will be merged with a sub-register of SrcReg.
293 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
295 // This is a straight copy without sub-registers.
296 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
299 // The combined constraint may be impossible to satisfy.
303 // Prefer SrcReg to be a sub-register of DstReg.
304 // FIXME: Coalescer should support subregs symmetrically.
305 if (DstIdx && !SrcIdx) {
307 std::swap(SrcIdx, DstIdx);
311 CrossClass = NewRC != DstRC || NewRC != SrcRC;
313 // Check our invariants
314 assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual");
315 assert(!(TargetRegisterInfo::isPhysicalRegister(Dst) && DstSub) &&
316 "Cannot have a physical SubIdx");
322 bool CoalescerPair::flip() {
323 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
325 std::swap(SrcReg, DstReg);
326 std::swap(SrcIdx, DstIdx);
331 bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
334 unsigned Src, Dst, SrcSub, DstSub;
335 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
338 // Find the virtual register that is SrcReg.
341 std::swap(SrcSub, DstSub);
342 } else if (Src != SrcReg) {
346 // Now check that Dst matches DstReg.
347 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
348 if (!TargetRegisterInfo::isPhysicalRegister(Dst))
350 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.");
351 // DstSub could be set for a physreg from INSERT_SUBREG.
353 Dst = TRI.getSubReg(Dst, DstSub);
356 return DstReg == Dst;
357 // This is a partial register copy. Check that the parts match.
358 return TRI.getSubReg(DstReg, SrcSub) == Dst;
360 // DstReg is virtual.
363 // Registers match, do the subregisters line up?
364 return compose(TRI, SrcIdx, SrcSub) == compose(TRI, DstIdx, DstSub);
368 void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const {
369 AU.setPreservesCFG();
370 AU.addRequired<AliasAnalysis>();
371 AU.addRequired<LiveIntervals>();
372 AU.addPreserved<LiveIntervals>();
373 AU.addRequired<LiveDebugVariables>();
374 AU.addPreserved<LiveDebugVariables>();
375 AU.addPreserved<SlotIndexes>();
376 AU.addRequired<MachineLoopInfo>();
377 AU.addPreserved<MachineLoopInfo>();
378 AU.addPreservedID(MachineDominatorsID);
379 MachineFunctionPass::getAnalysisUsage(AU);
382 void RegisterCoalescer::markAsJoined(MachineInstr *CopyMI) {
383 /// Joined copies are not deleted immediately, but kept in JoinedCopies.
384 JoinedCopies.insert(CopyMI);
386 /// Mark all register operands of CopyMI as <undef> so they won't affect dead
387 /// code elimination.
388 for (MachineInstr::mop_iterator I = CopyMI->operands_begin(),
389 E = CopyMI->operands_end(); I != E; ++I)
394 /// adjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
395 /// being the source and IntB being the dest, thus this defines a value number
396 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
397 /// see if we can merge these two pieces of B into a single value number,
398 /// eliminating a copy. For example:
402 /// B1 = A3 <- this copy
404 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
405 /// value number to be replaced with B0 (which simplifies the B liveinterval).
407 /// This returns true if an interval was modified.
409 bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP,
410 MachineInstr *CopyMI) {
411 assert(!CP.isPartial() && "This doesn't work for partial copies.");
413 // Bail if there is no dst interval - can happen when merging physical subreg
415 if (!LIS->hasInterval(CP.getDstReg()))
419 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
421 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
422 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
424 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
425 // the example above.
426 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
427 if (BLR == IntB.end()) return false;
428 VNInfo *BValNo = BLR->valno;
430 // Get the location that B is defined at. Two options: either this value has
431 // an unknown definition point or it is defined at CopyIdx. If unknown, we
433 if (BValNo->def != CopyIdx) return false;
435 // AValNo is the value number in A that defines the copy, A3 in the example.
436 SlotIndex CopyUseIdx = CopyIdx.getRegSlot(true);
437 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
438 // The live range might not exist after fun with physreg coalescing.
439 if (ALR == IntA.end()) return false;
440 VNInfo *AValNo = ALR->valno;
442 // If AValNo is defined as a copy from IntB, we can potentially process this.
443 // Get the instruction that defines this value number.
444 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
445 if (!CP.isCoalescable(ACopyMI))
448 // Get the LiveRange in IntB that this value number starts with.
449 LiveInterval::iterator ValLR =
450 IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot());
451 if (ValLR == IntB.end())
454 // Make sure that the end of the live range is inside the same block as
456 MachineInstr *ValLREndInst =
457 LIS->getInstructionFromIndex(ValLR->end.getPrevSlot());
458 if (!ValLREndInst || ValLREndInst->getParent() != CopyMI->getParent())
461 // Okay, we now know that ValLR ends in the same block that the CopyMI
462 // live-range starts. If there are no intervening live ranges between them in
463 // IntB, we can merge them.
464 if (ValLR+1 != BLR) return false;
466 // If a live interval is a physical register, conservatively check if any
467 // of its aliases is overlapping the live interval of the virtual register.
468 // If so, do not coalesce.
469 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
470 for (const uint16_t *AS = TRI->getAliasSet(IntB.reg); *AS; ++AS)
471 if (LIS->hasInterval(*AS) && IntA.overlaps(LIS->getInterval(*AS))) {
473 dbgs() << "\t\tInterfere with alias ";
474 LIS->getInterval(*AS).print(dbgs(), TRI);
481 dbgs() << "Extending: ";
482 IntB.print(dbgs(), TRI);
485 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
486 // We are about to delete CopyMI, so need to remove it as the 'instruction
487 // that defines this value #'. Update the valnum with the new defining
489 BValNo->def = FillerStart;
491 // Okay, we can merge them. We need to insert a new liverange:
492 // [ValLR.end, BLR.begin) of either value number, then we merge the
493 // two value numbers.
494 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
496 // If the IntB live range is assigned to a physical register, and if that
497 // physreg has sub-registers, update their live intervals as well.
498 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
499 for (const uint16_t *SR = TRI->getSubRegisters(IntB.reg); *SR; ++SR) {
500 if (!LIS->hasInterval(*SR))
502 LiveInterval &SRLI = LIS->getInterval(*SR);
503 SRLI.addRange(LiveRange(FillerStart, FillerEnd,
504 SRLI.getNextValue(FillerStart,
505 LIS->getVNInfoAllocator())));
509 // Okay, merge "B1" into the same value number as "B0".
510 if (BValNo != ValLR->valno) {
511 // If B1 is killed by a PHI, then the merged live range must also be killed
512 // by the same PHI, as B0 and B1 can not overlap.
513 bool HasPHIKill = BValNo->hasPHIKill();
514 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
516 ValLR->valno->setHasPHIKill(true);
519 dbgs() << " result = ";
520 IntB.print(dbgs(), TRI);
524 // If the source instruction was killing the source register before the
525 // merge, unset the isKill marker given the live range has been extended.
526 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
528 ValLREndInst->getOperand(UIdx).setIsKill(false);
531 // Rewrite the copy. If the copy instruction was killing the destination
532 // register before the merge, find the last use and trim the live range. That
533 // will also add the isKill marker.
534 CopyMI->substituteRegister(IntA.reg, IntB.reg, 0, *TRI);
535 if (ALR->end == CopyIdx)
536 LIS->shrinkToUses(&IntA);
542 /// hasOtherReachingDefs - Return true if there are definitions of IntB
543 /// other than BValNo val# that can reach uses of AValno val# of IntA.
544 bool RegisterCoalescer::hasOtherReachingDefs(LiveInterval &IntA,
548 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
550 if (AI->valno != AValNo) continue;
551 LiveInterval::Ranges::iterator BI =
552 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
553 if (BI != IntB.ranges.begin())
555 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
556 if (BI->valno == BValNo)
558 if (BI->start <= AI->start && BI->end > AI->start)
560 if (BI->start > AI->start && BI->start < AI->end)
567 /// removeCopyByCommutingDef - We found a non-trivially-coalescable copy with
568 /// IntA being the source and IntB being the dest, thus this defines a value
569 /// number in IntB. If the source value number (in IntA) is defined by a
570 /// commutable instruction and its other operand is coalesced to the copy dest
571 /// register, see if we can transform the copy into a noop by commuting the
572 /// definition. For example,
574 /// A3 = op A2 B0<kill>
576 /// B1 = A3 <- this copy
578 /// = op A3 <- more uses
582 /// B2 = op B0 A2<kill>
584 /// B1 = B2 <- now an identify copy
586 /// = op B2 <- more uses
588 /// This returns true if an interval was modified.
590 bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
591 MachineInstr *CopyMI) {
592 // FIXME: For now, only eliminate the copy by commuting its def when the
593 // source register is a virtual register. We want to guard against cases
594 // where the copy is a back edge copy and commuting the def lengthen the
595 // live interval of the source register to the entire loop.
596 if (CP.isPhys() && CP.isFlipped())
599 // Bail if there is no dst interval.
600 if (!LIS->hasInterval(CP.getDstReg()))
603 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
606 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
608 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
610 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
611 // the example above.
612 VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx);
613 if (!BValNo || BValNo->def != CopyIdx)
616 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
618 // AValNo is the value number in A that defines the copy, A3 in the example.
619 VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getRegSlot(true));
620 assert(AValNo && "COPY source not live");
622 // If other defs can reach uses of this def, then it's not safe to perform
624 if (AValNo->isPHIDef() || AValNo->isUnused() || AValNo->hasPHIKill())
626 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
629 if (!DefMI->isCommutable())
631 // If DefMI is a two-address instruction then commuting it will change the
632 // destination register.
633 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
634 assert(DefIdx != -1);
636 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
638 unsigned Op1, Op2, NewDstIdx;
639 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
643 else if (Op2 == UseOpIdx)
648 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
649 unsigned NewReg = NewDstMO.getReg();
650 if (NewReg != IntB.reg || !NewDstMO.isKill())
653 // Make sure there are no other definitions of IntB that would reach the
654 // uses which the new definition can reach.
655 if (hasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
658 // Abort if the aliases of IntB.reg have values that are not simply the
659 // clobbers from the superreg.
660 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
661 for (const uint16_t *AS = TRI->getAliasSet(IntB.reg); *AS; ++AS)
662 if (LIS->hasInterval(*AS) &&
663 hasOtherReachingDefs(IntA, LIS->getInterval(*AS), AValNo, 0))
666 // If some of the uses of IntA.reg is already coalesced away, return false.
667 // It's not possible to determine whether it's safe to perform the coalescing.
668 for (MachineRegisterInfo::use_nodbg_iterator UI =
669 MRI->use_nodbg_begin(IntA.reg),
670 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
671 MachineInstr *UseMI = &*UI;
672 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
673 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
674 if (ULR == IntA.end())
676 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
680 DEBUG(dbgs() << "\tremoveCopyByCommutingDef: " << AValNo->def << '\t'
683 // At this point we have decided that it is legal to do this
684 // transformation. Start by commuting the instruction.
685 MachineBasicBlock *MBB = DefMI->getParent();
686 MachineInstr *NewMI = TII->commuteInstruction(DefMI);
689 if (TargetRegisterInfo::isVirtualRegister(IntA.reg) &&
690 TargetRegisterInfo::isVirtualRegister(IntB.reg) &&
691 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
693 if (NewMI != DefMI) {
694 LIS->ReplaceMachineInstrInMaps(DefMI, NewMI);
695 MachineBasicBlock::iterator Pos = DefMI;
696 MBB->insert(Pos, NewMI);
699 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
700 NewMI->getOperand(OpIdx).setIsKill();
702 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
711 // Update uses of IntA of the specific Val# with IntB.
712 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg),
713 UE = MRI->use_end(); UI != UE;) {
714 MachineOperand &UseMO = UI.getOperand();
715 MachineInstr *UseMI = &*UI;
717 if (JoinedCopies.count(UseMI))
719 if (UseMI->isDebugValue()) {
720 // FIXME These don't have an instruction index. Not clear we have enough
721 // info to decide whether to do this replacement or not. For now do it.
722 UseMO.setReg(NewReg);
725 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
726 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
727 if (ULR == IntA.end() || ULR->valno != AValNo)
729 if (TargetRegisterInfo::isPhysicalRegister(NewReg))
730 UseMO.substPhysReg(NewReg, *TRI);
732 UseMO.setReg(NewReg);
735 if (!UseMI->isCopy())
737 if (UseMI->getOperand(0).getReg() != IntB.reg ||
738 UseMI->getOperand(0).getSubReg())
741 // This copy will become a noop. If it's defining a new val#, merge it into
743 SlotIndex DefIdx = UseIdx.getRegSlot();
744 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
747 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
748 assert(DVNI->def == DefIdx);
749 BValNo = IntB.MergeValueNumberInto(BValNo, DVNI);
753 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
755 VNInfo *ValNo = BValNo;
756 ValNo->def = AValNo->def;
757 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
759 if (AI->valno != AValNo) continue;
760 IntB.addRange(LiveRange(AI->start, AI->end, ValNo));
762 DEBUG(dbgs() << "\t\textended: " << IntB << '\n');
764 IntA.removeValNo(AValNo);
765 DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n');
770 /// reMaterializeTrivialDef - If the source of a copy is defined by a trivial
771 /// computation, replace the copy by rematerialize the definition.
772 bool RegisterCoalescer::reMaterializeTrivialDef(LiveInterval &SrcInt,
775 MachineInstr *CopyMI) {
776 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(true);
777 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
778 assert(SrcLR != SrcInt.end() && "Live range not found!");
779 VNInfo *ValNo = SrcLR->valno;
780 if (ValNo->isPHIDef() || ValNo->isUnused())
782 MachineInstr *DefMI = LIS->getInstructionFromIndex(ValNo->def);
785 assert(DefMI && "Defining instruction disappeared");
786 if (!DefMI->isAsCheapAsAMove())
788 if (!TII->isTriviallyReMaterializable(DefMI, AA))
790 bool SawStore = false;
791 if (!DefMI->isSafeToMove(TII, AA, SawStore))
793 const MCInstrDesc &MCID = DefMI->getDesc();
794 if (MCID.getNumDefs() != 1)
796 if (!DefMI->isImplicitDef()) {
797 // Make sure the copy destination register class fits the instruction
798 // definition register class. The mismatch can happen as a result of earlier
799 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
800 const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI, *MF);
801 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
802 if (MRI->getRegClass(DstReg) != RC)
804 } else if (!RC->contains(DstReg))
808 MachineBasicBlock *MBB = CopyMI->getParent();
809 MachineBasicBlock::iterator MII =
810 llvm::next(MachineBasicBlock::iterator(CopyMI));
811 TII->reMaterialize(*MBB, MII, DstReg, 0, DefMI, *TRI);
812 MachineInstr *NewMI = prior(MII);
814 // NewMI may have dead implicit defs (E.g. EFLAGS for MOV<bits>r0 on X86).
815 // We need to remember these so we can add intervals once we insert
816 // NewMI into SlotIndexes.
817 SmallVector<unsigned, 4> NewMIImplDefs;
818 for (unsigned i = NewMI->getDesc().getNumOperands(),
819 e = NewMI->getNumOperands(); i != e; ++i) {
820 MachineOperand &MO = NewMI->getOperand(i);
822 assert(MO.isDef() && MO.isImplicit() && MO.isDead() &&
823 TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
824 NewMIImplDefs.push_back(MO.getReg());
828 // CopyMI may have implicit operands, transfer them over to the newly
829 // rematerialized instruction. And update implicit def interval valnos.
830 for (unsigned i = CopyMI->getDesc().getNumOperands(),
831 e = CopyMI->getNumOperands(); i != e; ++i) {
832 MachineOperand &MO = CopyMI->getOperand(i);
834 assert(MO.isImplicit() && "No explicit operands after implict operands.");
835 // Discard VReg implicit defs.
836 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
837 NewMI->addOperand(MO);
842 LIS->ReplaceMachineInstrInMaps(CopyMI, NewMI);
844 SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
845 for (unsigned i = 0, e = NewMIImplDefs.size(); i != e; ++i) {
846 unsigned reg = NewMIImplDefs[i];
847 LiveInterval &li = LIS->getInterval(reg);
848 VNInfo *DeadDefVN = li.getNextValue(NewMIIdx.getRegSlot(),
849 LIS->getVNInfoAllocator());
850 LiveRange lr(NewMIIdx.getRegSlot(), NewMIIdx.getDeadSlot(), DeadDefVN);
854 CopyMI->eraseFromParent();
855 ReMatCopies.insert(CopyMI);
856 ReMatDefs.insert(DefMI);
857 DEBUG(dbgs() << "Remat: " << *NewMI);
860 // The source interval can become smaller because we removed a use.
862 LIS->shrinkToUses(&SrcInt);
867 /// eliminateUndefCopy - ProcessImpicitDefs may leave some copies of <undef>
868 /// values, it only removes local variables. When we have a copy like:
870 /// %vreg1 = COPY %vreg2<undef>
872 /// We delete the copy and remove the corresponding value number from %vreg1.
873 /// Any uses of that value number are marked as <undef>.
874 bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI,
875 const CoalescerPair &CP) {
876 SlotIndex Idx = LIS->getInstructionIndex(CopyMI);
877 LiveInterval *SrcInt = &LIS->getInterval(CP.getSrcReg());
878 if (SrcInt->liveAt(Idx))
880 LiveInterval *DstInt = &LIS->getInterval(CP.getDstReg());
881 if (DstInt->liveAt(Idx))
884 // No intervals are live-in to CopyMI - it is undef.
889 VNInfo *DeadVNI = DstInt->getVNInfoAt(Idx.getRegSlot());
890 assert(DeadVNI && "No value defined in DstInt");
891 DstInt->removeValNo(DeadVNI);
893 // Find new undef uses.
894 for (MachineRegisterInfo::reg_nodbg_iterator
895 I = MRI->reg_nodbg_begin(DstInt->reg), E = MRI->reg_nodbg_end();
897 MachineOperand &MO = I.getOperand();
898 if (MO.isDef() || MO.isUndef())
900 MachineInstr *MI = MO.getParent();
901 SlotIndex Idx = LIS->getInstructionIndex(MI);
902 if (DstInt->liveAt(Idx))
905 DEBUG(dbgs() << "\tnew undef: " << Idx << '\t' << *MI);
910 /// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
911 /// update the subregister number if it is not zero. If DstReg is a
912 /// physical register and the existing subregister number of the def / use
913 /// being updated is not zero, make sure to set it to the correct physical
915 void RegisterCoalescer::updateRegDefsUses(const CoalescerPair &CP) {
916 bool DstIsPhys = CP.isPhys();
917 unsigned SrcReg = CP.getSrcReg();
918 unsigned DstReg = CP.getDstReg();
919 unsigned SubIdx = CP.getSrcIdx();
921 // Update LiveDebugVariables.
922 LDV->renameRegister(SrcReg, DstReg, SubIdx);
924 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg);
925 MachineInstr *UseMI = I.skipInstruction();) {
926 // A PhysReg copy that won't be coalesced can perhaps be rematerialized
929 if (UseMI->isFullCopy() &&
930 UseMI->getOperand(1).getReg() == SrcReg &&
931 UseMI->getOperand(0).getReg() != SrcReg &&
932 UseMI->getOperand(0).getReg() != DstReg &&
933 !JoinedCopies.count(UseMI) &&
934 reMaterializeTrivialDef(LIS->getInterval(SrcReg), false,
935 UseMI->getOperand(0).getReg(), UseMI))
939 SmallVector<unsigned,8> Ops;
941 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
943 // Replace SrcReg with DstReg in all UseMI operands.
944 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
945 MachineOperand &MO = UseMI->getOperand(Ops[i]);
947 // Make sure we don't create read-modify-write defs accidentally. We
948 // assume here that a SrcReg def cannot be joined into a live DstReg. If
949 // RegisterCoalescer starts tracking partially live registers, we will
950 // need to check the actual LiveInterval to determine if DstReg is live
952 if (SubIdx && !Reads)
956 MO.substPhysReg(DstReg, *TRI);
958 MO.substVirtReg(DstReg, SubIdx, *TRI);
961 // This instruction is a copy that will be removed.
962 if (JoinedCopies.count(UseMI))
966 dbgs() << "\t\tupdated: ";
967 if (!UseMI->isDebugValue())
968 dbgs() << LIS->getInstructionIndex(UseMI) << "\t";
974 /// removeIntervalIfEmpty - Check if the live interval of a physical register
975 /// is empty, if so remove it and also remove the empty intervals of its
976 /// sub-registers. Return true if live interval is removed.
977 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *LIS,
978 const TargetRegisterInfo *TRI) {
980 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
981 for (const uint16_t* SR = TRI->getSubRegisters(li.reg); *SR; ++SR) {
982 if (!LIS->hasInterval(*SR))
984 LiveInterval &sli = LIS->getInterval(*SR);
986 LIS->removeInterval(*SR);
988 LIS->removeInterval(li.reg);
994 /// removeDeadDef - If a def of a live interval is now determined dead, remove
995 /// the val# it defines. If the live interval becomes empty, remove it as well.
996 bool RegisterCoalescer::removeDeadDef(LiveInterval &li, MachineInstr *DefMI) {
997 SlotIndex DefIdx = LIS->getInstructionIndex(DefMI).getRegSlot();
998 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
999 if (DefIdx != MLR->valno->def)
1001 li.removeValNo(MLR->valno);
1002 return removeIntervalIfEmpty(li, LIS, TRI);
1005 /// shouldJoinPhys - Return true if a copy involving a physreg should be joined.
1006 /// We need to be careful about coalescing a source physical register with a
1007 /// virtual register. Once the coalescing is done, it cannot be broken and these
1008 /// are not spillable! If the destination interval uses are far away, think
1009 /// twice about coalescing them!
1010 bool RegisterCoalescer::shouldJoinPhys(CoalescerPair &CP) {
1011 bool Allocatable = LIS->isAllocatable(CP.getDstReg());
1012 LiveInterval &JoinVInt = LIS->getInterval(CP.getSrcReg());
1014 /// Always join simple intervals that are defined by a single copy from a
1015 /// reserved register. This doesn't increase register pressure, so it is
1016 /// always beneficial.
1017 if (!Allocatable && CP.isFlipped() && JoinVInt.containsOneValue())
1020 if (!EnablePhysicalJoin) {
1021 DEBUG(dbgs() << "\tPhysreg joins disabled.\n");
1025 // Only coalesce to allocatable physreg, we don't want to risk modifying
1026 // reserved registers.
1028 DEBUG(dbgs() << "\tRegister is an unallocatable physreg.\n");
1029 return false; // Not coalescable.
1032 // Don't join with physregs that have a ridiculous number of live
1033 // ranges. The data structure performance is really bad when that
1035 if (LIS->hasInterval(CP.getDstReg()) &&
1036 LIS->getInterval(CP.getDstReg()).ranges.size() > 1000) {
1039 << "\tPhysical register live interval too complicated, abort!\n");
1043 // FIXME: Why are we skipping this test for partial copies?
1044 // CodeGen/X86/phys_subreg_coalesce-3.ll needs it.
1045 if (!CP.isPartial()) {
1046 const TargetRegisterClass *RC = MRI->getRegClass(CP.getSrcReg());
1047 unsigned Threshold = RegClassInfo.getNumAllocatableRegs(RC) * 2;
1048 unsigned Length = LIS->getApproximateInstructionCount(JoinVInt);
1049 if (Length > Threshold) {
1051 DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
1059 /// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1060 /// which are the src/dst of the copy instruction CopyMI. This returns true
1061 /// if the copy was successfully coalesced away. If it is not currently
1062 /// possible to coalesce this interval, but it may be possible if other
1063 /// things get coalesced, then it returns true by reference in 'Again'.
1064 bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
1067 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1068 return false; // Already done.
1070 DEBUG(dbgs() << LIS->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
1072 CoalescerPair CP(*TII, *TRI);
1073 if (!CP.setRegisters(CopyMI)) {
1074 DEBUG(dbgs() << "\tNot coalescable.\n");
1078 // If they are already joined we continue.
1079 if (CP.getSrcReg() == CP.getDstReg()) {
1080 markAsJoined(CopyMI);
1081 DEBUG(dbgs() << "\tCopy already coalesced.\n");
1082 return false; // Not coalescable.
1085 // Eliminate undefs.
1086 if (!CP.isPhys() && eliminateUndefCopy(CopyMI, CP)) {
1087 markAsJoined(CopyMI);
1088 DEBUG(dbgs() << "\tEliminated copy of <undef> value.\n");
1089 return false; // Not coalescable.
1092 DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI)
1093 << " with " << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx())
1096 // Enforce policies.
1098 if (!shouldJoinPhys(CP)) {
1099 // Before giving up coalescing, if definition of source is defined by
1100 // trivial computation, try rematerializing it.
1101 if (!CP.isFlipped() &&
1102 reMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()), true,
1103 CP.getDstReg(), CopyMI))
1109 if (CP.isCrossClass())
1110 dbgs() << "\tCross-class to " << CP.getNewRC()->getName() << ".\n";
1113 // When possible, let DstReg be the larger interval.
1114 if (!CP.getSrcIdx() && LIS->getInterval(CP.getSrcReg()).ranges.size() >
1115 LIS->getInterval(CP.getDstReg()).ranges.size())
1119 // Okay, attempt to join these two intervals. On failure, this returns false.
1120 // Otherwise, if one of the intervals being joined is a physreg, this method
1121 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1122 // been modified, so we can use this information below to update aliases.
1123 if (!joinIntervals(CP)) {
1124 // Coalescing failed.
1126 // If definition of source is defined by trivial computation, try
1127 // rematerializing it.
1128 if (!CP.isFlipped() &&
1129 reMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()), true,
1130 CP.getDstReg(), CopyMI))
1133 // If we can eliminate the copy without merging the live ranges, do so now.
1134 if (!CP.isPartial()) {
1135 if (adjustCopiesBackFrom(CP, CopyMI) ||
1136 removeCopyByCommutingDef(CP, CopyMI)) {
1137 markAsJoined(CopyMI);
1138 DEBUG(dbgs() << "\tTrivial!\n");
1143 // Otherwise, we are unable to join the intervals.
1144 DEBUG(dbgs() << "\tInterference!\n");
1145 Again = true; // May be possible to coalesce later.
1149 // Coalescing to a virtual register that is of a sub-register class of the
1150 // other. Make sure the resulting register is set to the right register class.
1151 if (CP.isCrossClass()) {
1153 MRI->setRegClass(CP.getDstReg(), CP.getNewRC());
1156 // Remember to delete the copy instruction.
1157 markAsJoined(CopyMI);
1159 updateRegDefsUses(CP);
1161 // If we have extended the live range of a physical register, make sure we
1162 // update live-in lists as well.
1164 SmallVector<MachineBasicBlock*, 16> BlockSeq;
1165 // joinIntervals invalidates the VNInfos in SrcInt, but we only need the
1166 // ranges for this, and they are preserved.
1167 LiveInterval &SrcInt = LIS->getInterval(CP.getSrcReg());
1168 for (LiveInterval::const_iterator I = SrcInt.begin(), E = SrcInt.end();
1170 LIS->findLiveInMBBs(I->start, I->end, BlockSeq);
1171 for (unsigned idx = 0, size = BlockSeq.size(); idx != size; ++idx) {
1172 MachineBasicBlock &block = *BlockSeq[idx];
1173 if (!block.isLiveIn(CP.getDstReg()))
1174 block.addLiveIn(CP.getDstReg());
1180 // SrcReg is guaranteed to be the register whose live interval that is
1182 LIS->removeInterval(CP.getSrcReg());
1184 // Update regalloc hint.
1185 TRI->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
1188 LiveInterval &DstInt = LIS->getInterval(CP.getDstReg());
1189 dbgs() << "\tJoined. Result = ";
1190 DstInt.print(dbgs(), TRI);
1198 /// Attempt joining with a reserved physreg.
1199 bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
1200 assert(CP.isPhys() && "Must be a physreg copy");
1201 assert(RegClassInfo.isReserved(CP.getDstReg()) && "Not a reserved register");
1202 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1203 DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), TRI); dbgs() << "\n"; });
1205 assert(CP.isFlipped() && RHS.containsOneValue() &&
1206 "Invalid join with reserved register");
1208 // Optimization for reserved registers like ESP. We can only merge with a
1209 // reserved physreg if RHS has a single value that is a copy of CP.DstReg().
1210 // The live range of the reserved register will look like a set of dead defs
1211 // - we don't properly track the live range of reserved registers.
1213 // Deny any overlapping intervals. This depends on all the reserved
1214 // register live ranges to look like dead defs.
1215 for (const uint16_t *AS = TRI->getOverlaps(CP.getDstReg()); *AS; ++AS) {
1216 if (!LIS->hasInterval(*AS)) {
1217 // Make sure at least DstReg itself exists before attempting a join.
1218 if (*AS == CP.getDstReg())
1219 LIS->getOrCreateInterval(CP.getDstReg());
1222 if (RHS.overlaps(LIS->getInterval(*AS))) {
1223 DEBUG(dbgs() << "\t\tInterference: " << PrintReg(*AS, TRI) << '\n');
1227 // Skip any value computations, we are not adding new values to the
1228 // reserved register. Also skip merging the live ranges, the reserved
1229 // register live range doesn't need to be accurate as long as all the
1234 bool RegisterCoalescer::canJoinPhysReg(CoalescerPair &CP) {
1235 assert(CP.isPhys() && "Must be a physreg copy");
1236 // If a live interval is a physical register, check for interference with any
1237 // aliases. The interference check implemented here is a bit more
1238 // conservative than the full interfeence check below. We allow overlapping
1239 // live ranges only when one is a copy of the other.
1240 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1241 DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), TRI); dbgs() << "\n"; });
1243 // Check if a register mask clobbers DstReg.
1244 BitVector UsableRegs;
1245 if (LIS->checkRegMaskInterference(RHS, UsableRegs) &&
1246 !UsableRegs.test(CP.getDstReg())) {
1247 DEBUG(dbgs() << "\t\tRegister mask interference.\n");
1251 for (const uint16_t *AS = TRI->getAliasSet(CP.getDstReg()); *AS; ++AS){
1252 if (!LIS->hasInterval(*AS))
1254 const LiveInterval &LHS = LIS->getInterval(*AS);
1255 LiveInterval::const_iterator LI = LHS.begin();
1256 for (LiveInterval::const_iterator RI = RHS.begin(), RE = RHS.end();
1258 LI = std::lower_bound(LI, LHS.end(), RI->start);
1259 // Does LHS have an overlapping live range starting before RI?
1260 if ((LI != LHS.begin() && LI[-1].end > RI->start) &&
1261 (RI->start != RI->valno->def ||
1262 !CP.isCoalescable(LIS->getInstructionFromIndex(RI->start)))) {
1264 dbgs() << "\t\tInterference from alias: ";
1265 LHS.print(dbgs(), TRI);
1266 dbgs() << "\n\t\tOverlap at " << RI->start << " and no copy.\n";
1271 // Check that LHS ranges beginning in this range are copies.
1272 for (; LI != LHS.end() && LI->start < RI->end; ++LI) {
1273 if (LI->start != LI->valno->def ||
1274 !CP.isCoalescable(LIS->getInstructionFromIndex(LI->start))) {
1276 dbgs() << "\t\tInterference from alias: ";
1277 LHS.print(dbgs(), TRI);
1278 dbgs() << "\n\t\tDef at " << LI->start << " is not a copy.\n";
1288 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1289 /// compute what the resultant value numbers for each value in the input two
1290 /// ranges will be. This is complicated by copies between the two which can
1291 /// and will commonly cause multiple value numbers to be merged into one.
1293 /// VN is the value number that we're trying to resolve. InstDefiningValue
1294 /// keeps track of the new InstDefiningValue assignment for the result
1295 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1296 /// whether a value in this or other is a copy from the opposite set.
1297 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1298 /// already been assigned.
1300 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1301 /// contains the value number the copy is from.
1303 static unsigned ComputeUltimateVN(VNInfo *VNI,
1304 SmallVector<VNInfo*, 16> &NewVNInfo,
1305 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1306 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1307 SmallVector<int, 16> &ThisValNoAssignments,
1308 SmallVector<int, 16> &OtherValNoAssignments) {
1309 unsigned VN = VNI->id;
1311 // If the VN has already been computed, just return it.
1312 if (ThisValNoAssignments[VN] >= 0)
1313 return ThisValNoAssignments[VN];
1314 assert(ThisValNoAssignments[VN] != -2 && "Cyclic value numbers");
1316 // If this val is not a copy from the other val, then it must be a new value
1317 // number in the destination.
1318 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1319 if (I == ThisFromOther.end()) {
1320 NewVNInfo.push_back(VNI);
1321 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1323 VNInfo *OtherValNo = I->second;
1325 // Otherwise, this *is* a copy from the RHS. If the other side has already
1326 // been computed, return it.
1327 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1328 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1330 // Mark this value number as currently being computed, then ask what the
1331 // ultimate value # of the other value is.
1332 ThisValNoAssignments[VN] = -2;
1333 unsigned UltimateVN =
1334 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1335 OtherValNoAssignments, ThisValNoAssignments);
1336 return ThisValNoAssignments[VN] = UltimateVN;
1340 // Find out if we have something like
1343 // if so, we can pretend this is actually
1346 // which allows us to coalesce A and B.
1347 // VNI is the definition of B. LR is the life range of A that includes
1348 // the slot just before B. If we return true, we add "B = X" to DupCopies.
1349 // This implies that A dominates B.
1350 static bool RegistersDefinedFromSameValue(LiveIntervals &li,
1351 const TargetRegisterInfo &tri,
1355 SmallVector<MachineInstr*, 8> &DupCopies) {
1356 // FIXME: This is very conservative. For example, we don't handle
1357 // physical registers.
1359 MachineInstr *MI = li.getInstructionFromIndex(VNI->def);
1361 if (!MI || !MI->isFullCopy() || CP.isPartial() || CP.isPhys())
1364 unsigned Dst = MI->getOperand(0).getReg();
1365 unsigned Src = MI->getOperand(1).getReg();
1367 if (!TargetRegisterInfo::isVirtualRegister(Src) ||
1368 !TargetRegisterInfo::isVirtualRegister(Dst))
1371 unsigned A = CP.getDstReg();
1372 unsigned B = CP.getSrcReg();
1378 VNInfo *Other = LR->valno;
1379 const MachineInstr *OtherMI = li.getInstructionFromIndex(Other->def);
1381 if (!OtherMI || !OtherMI->isFullCopy())
1384 unsigned OtherDst = OtherMI->getOperand(0).getReg();
1385 unsigned OtherSrc = OtherMI->getOperand(1).getReg();
1387 if (!TargetRegisterInfo::isVirtualRegister(OtherSrc) ||
1388 !TargetRegisterInfo::isVirtualRegister(OtherDst))
1391 assert(OtherDst == B);
1393 if (Src != OtherSrc)
1396 // If the copies use two different value numbers of X, we cannot merge
1398 LiveInterval &SrcInt = li.getInterval(Src);
1399 // getVNInfoBefore returns NULL for undef copies. In this case, the
1400 // optimization is still safe.
1401 if (SrcInt.getVNInfoBefore(Other->def) != SrcInt.getVNInfoBefore(VNI->def))
1404 DupCopies.push_back(MI);
1409 /// joinIntervals - Attempt to join these two intervals. On failure, this
1411 bool RegisterCoalescer::joinIntervals(CoalescerPair &CP) {
1412 // Handle physreg joins separately.
1414 if (RegClassInfo.isReserved(CP.getDstReg()))
1415 return joinReservedPhysReg(CP);
1416 if (!canJoinPhysReg(CP))
1420 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1421 DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), TRI); dbgs() << "\n"; });
1423 // Compute the final value assignment, assuming that the live ranges can be
1425 SmallVector<int, 16> LHSValNoAssignments;
1426 SmallVector<int, 16> RHSValNoAssignments;
1427 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
1428 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
1429 SmallVector<VNInfo*, 16> NewVNInfo;
1431 SmallVector<MachineInstr*, 8> DupCopies;
1433 LiveInterval &LHS = LIS->getOrCreateInterval(CP.getDstReg());
1434 DEBUG({ dbgs() << "\t\tLHS = "; LHS.print(dbgs(), TRI); dbgs() << "\n"; });
1436 // Loop over the value numbers of the LHS, seeing if any are defined from
1438 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1441 if (VNI->isUnused() || VNI->isPHIDef())
1443 MachineInstr *MI = LIS->getInstructionFromIndex(VNI->def);
1444 assert(MI && "Missing def");
1445 if (!MI->isCopyLike()) // Src not defined by a copy?
1448 // Figure out the value # from the RHS.
1449 LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1450 // The copy could be to an aliased physreg.
1453 // DstReg is known to be a register in the LHS interval. If the src is
1454 // from the RHS interval, we can use its value #.
1455 if (!CP.isCoalescable(MI) &&
1456 !RegistersDefinedFromSameValue(*LIS, *TRI, CP, VNI, lr, DupCopies))
1459 LHSValsDefinedFromRHS[VNI] = lr->valno;
1462 // Loop over the value numbers of the RHS, seeing if any are defined from
1464 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1467 if (VNI->isUnused() || VNI->isPHIDef())
1469 MachineInstr *MI = LIS->getInstructionFromIndex(VNI->def);
1470 assert(MI && "Missing def");
1471 if (!MI->isCopyLike()) // Src not defined by a copy?
1474 // Figure out the value # from the LHS.
1475 LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1476 // The copy could be to an aliased physreg.
1479 // DstReg is known to be a register in the RHS interval. If the src is
1480 // from the LHS interval, we can use its value #.
1481 if (!CP.isCoalescable(MI) &&
1482 !RegistersDefinedFromSameValue(*LIS, *TRI, CP, VNI, lr, DupCopies))
1485 RHSValsDefinedFromLHS[VNI] = lr->valno;
1488 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1489 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1490 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1492 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1495 unsigned VN = VNI->id;
1496 if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1498 ComputeUltimateVN(VNI, NewVNInfo,
1499 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1500 LHSValNoAssignments, RHSValNoAssignments);
1502 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1505 unsigned VN = VNI->id;
1506 if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1508 // If this value number isn't a copy from the LHS, it's a new number.
1509 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
1510 NewVNInfo.push_back(VNI);
1511 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
1515 ComputeUltimateVN(VNI, NewVNInfo,
1516 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1517 RHSValNoAssignments, LHSValNoAssignments);
1520 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1521 // interval lists to see if these intervals are coalescable.
1522 LiveInterval::const_iterator I = LHS.begin();
1523 LiveInterval::const_iterator IE = LHS.end();
1524 LiveInterval::const_iterator J = RHS.begin();
1525 LiveInterval::const_iterator JE = RHS.end();
1527 // Skip ahead until the first place of potential sharing.
1528 if (I != IE && J != JE) {
1529 if (I->start < J->start) {
1530 I = std::upper_bound(I, IE, J->start);
1531 if (I != LHS.begin()) --I;
1532 } else if (J->start < I->start) {
1533 J = std::upper_bound(J, JE, I->start);
1534 if (J != RHS.begin()) --J;
1538 while (I != IE && J != JE) {
1539 // Determine if these two live ranges overlap.
1541 if (I->start < J->start) {
1542 Overlaps = I->end > J->start;
1544 Overlaps = J->end > I->start;
1547 // If so, check value # info to determine if they are really different.
1549 // If the live range overlap will map to the same value number in the
1550 // result liverange, we can still coalesce them. If not, we can't.
1551 if (LHSValNoAssignments[I->valno->id] !=
1552 RHSValNoAssignments[J->valno->id])
1556 if (I->end < J->end)
1562 // Update kill info. Some live ranges are extended due to copy coalescing.
1563 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
1564 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
1565 VNInfo *VNI = I->first;
1566 unsigned LHSValID = LHSValNoAssignments[VNI->id];
1567 if (VNI->hasPHIKill())
1568 NewVNInfo[LHSValID]->setHasPHIKill(true);
1571 // Update kill info. Some live ranges are extended due to copy coalescing.
1572 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
1573 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
1574 VNInfo *VNI = I->first;
1575 unsigned RHSValID = RHSValNoAssignments[VNI->id];
1576 if (VNI->hasPHIKill())
1577 NewVNInfo[RHSValID]->setHasPHIKill(true);
1580 if (LHSValNoAssignments.empty())
1581 LHSValNoAssignments.push_back(-1);
1582 if (RHSValNoAssignments.empty())
1583 RHSValNoAssignments.push_back(-1);
1585 SmallVector<unsigned, 8> SourceRegisters;
1586 for (SmallVector<MachineInstr*, 8>::iterator I = DupCopies.begin(),
1587 E = DupCopies.end(); I != E; ++I) {
1588 MachineInstr *MI = *I;
1590 // We have pretended that the assignment to B in
1593 // was actually a copy from A. Now that we decided to coalesce A and B,
1594 // transform the code into
1597 // and mark the X as coalesced to keep the illusion.
1598 unsigned Src = MI->getOperand(1).getReg();
1599 SourceRegisters.push_back(Src);
1600 MI->getOperand(0).substVirtReg(Src, 0, *TRI);
1605 // If B = X was the last use of X in a liverange, we have to shrink it now
1606 // that B = X is gone.
1607 for (SmallVector<unsigned, 8>::iterator I = SourceRegisters.begin(),
1608 E = SourceRegisters.end(); I != E; ++I) {
1609 LIS->shrinkToUses(&LIS->getInterval(*I));
1612 // If we get here, we know that we can coalesce the live ranges. Ask the
1613 // intervals to coalesce themselves now.
1614 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
1620 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1621 // depth of the basic block (the unsigned), and then on the MBB number.
1622 struct DepthMBBCompare {
1623 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1624 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1625 // Deeper loops first
1626 if (LHS.first != RHS.first)
1627 return LHS.first > RHS.first;
1629 // Prefer blocks that are more connected in the CFG. This takes care of
1630 // the most difficult copies first while intervals are short.
1631 unsigned cl = LHS.second->pred_size() + LHS.second->succ_size();
1632 unsigned cr = RHS.second->pred_size() + RHS.second->succ_size();
1636 // As a last resort, sort by block number.
1637 return LHS.second->getNumber() < RHS.second->getNumber();
1643 RegisterCoalescer::copyCoalesceInMBB(MachineBasicBlock *MBB,
1644 std::vector<MachineInstr*> &TryAgain) {
1645 DEBUG(dbgs() << MBB->getName() << ":\n");
1647 SmallVector<MachineInstr*, 8> VirtCopies;
1648 SmallVector<MachineInstr*, 8> PhysCopies;
1649 SmallVector<MachineInstr*, 8> ImpDefCopies;
1650 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1652 MachineInstr *Inst = MII++;
1654 // If this isn't a copy nor a extract_subreg, we can't join intervals.
1655 unsigned SrcReg, DstReg;
1656 if (Inst->isCopy()) {
1657 DstReg = Inst->getOperand(0).getReg();
1658 SrcReg = Inst->getOperand(1).getReg();
1659 } else if (Inst->isSubregToReg()) {
1660 DstReg = Inst->getOperand(0).getReg();
1661 SrcReg = Inst->getOperand(2).getReg();
1665 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1666 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1667 if (LIS->hasInterval(SrcReg) && LIS->getInterval(SrcReg).empty())
1668 ImpDefCopies.push_back(Inst);
1669 else if (SrcIsPhys || DstIsPhys)
1670 PhysCopies.push_back(Inst);
1672 VirtCopies.push_back(Inst);
1675 // Try coalescing implicit copies and insert_subreg <undef> first,
1676 // followed by copies to / from physical registers, then finally copies
1677 // from virtual registers to virtual registers.
1678 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
1679 MachineInstr *TheCopy = ImpDefCopies[i];
1681 if (!joinCopy(TheCopy, Again))
1683 TryAgain.push_back(TheCopy);
1685 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
1686 MachineInstr *TheCopy = PhysCopies[i];
1688 if (!joinCopy(TheCopy, Again))
1690 TryAgain.push_back(TheCopy);
1692 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
1693 MachineInstr *TheCopy = VirtCopies[i];
1695 if (!joinCopy(TheCopy, Again))
1697 TryAgain.push_back(TheCopy);
1701 void RegisterCoalescer::joinAllIntervals() {
1702 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
1704 std::vector<MachineInstr*> TryAgainList;
1705 if (Loops->empty()) {
1706 // If there are no loops in the function, join intervals in function order.
1707 for (MachineFunction::iterator I = MF->begin(), E = MF->end();
1709 copyCoalesceInMBB(I, TryAgainList);
1711 // Otherwise, join intervals in inner loops before other intervals.
1712 // Unfortunately we can't just iterate over loop hierarchy here because
1713 // there may be more MBB's than BB's. Collect MBB's for sorting.
1715 // Join intervals in the function prolog first. We want to join physical
1716 // registers with virtual registers before the intervals got too long.
1717 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1718 for (MachineFunction::iterator I = MF->begin(), E = MF->end();I != E;++I){
1719 MachineBasicBlock *MBB = I;
1720 MBBs.push_back(std::make_pair(Loops->getLoopDepth(MBB), I));
1723 // Sort by loop depth.
1724 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1726 // Finally, join intervals in loop nest order.
1727 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1728 copyCoalesceInMBB(MBBs[i].second, TryAgainList);
1731 // Joining intervals can allow other intervals to be joined. Iteratively join
1732 // until we make no progress.
1733 bool ProgressMade = true;
1734 while (ProgressMade) {
1735 ProgressMade = false;
1737 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1738 MachineInstr *&TheCopy = TryAgainList[i];
1743 bool Success = joinCopy(TheCopy, Again);
1744 if (Success || !Again) {
1745 TheCopy= 0; // Mark this one as done.
1746 ProgressMade = true;
1752 void RegisterCoalescer::releaseMemory() {
1753 JoinedCopies.clear();
1754 ReMatCopies.clear();
1758 bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
1760 MRI = &fn.getRegInfo();
1761 TM = &fn.getTarget();
1762 TRI = TM->getRegisterInfo();
1763 TII = TM->getInstrInfo();
1764 LIS = &getAnalysis<LiveIntervals>();
1765 LDV = &getAnalysis<LiveDebugVariables>();
1766 AA = &getAnalysis<AliasAnalysis>();
1767 Loops = &getAnalysis<MachineLoopInfo>();
1769 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
1770 << "********** Function: "
1771 << ((Value*)MF->getFunction())->getName() << '\n');
1773 if (VerifyCoalescing)
1774 MF->verify(this, "Before register coalescing");
1776 RegClassInfo.runOnMachineFunction(fn);
1778 // Join (coalesce) intervals if requested.
1779 if (EnableJoining) {
1782 dbgs() << "********** INTERVALS POST JOINING **********\n";
1783 for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end();
1785 I->second->print(dbgs(), TRI);
1791 // Perform a final pass over the instructions and compute spill weights
1792 // and remove identity moves.
1793 SmallVector<unsigned, 4> DeadDefs, InflateRegs;
1794 for (MachineFunction::iterator mbbi = MF->begin(), mbbe = MF->end();
1795 mbbi != mbbe; ++mbbi) {
1796 MachineBasicBlock* mbb = mbbi;
1797 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
1799 MachineInstr *MI = mii;
1800 if (JoinedCopies.count(MI)) {
1801 // Delete all coalesced copies.
1802 bool DoDelete = true;
1803 assert(MI->isCopyLike() && "Unrecognized copy instruction");
1804 unsigned SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
1805 unsigned DstReg = MI->getOperand(0).getReg();
1807 // Collect candidates for register class inflation.
1808 if (TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1809 RegClassInfo.isProperSubClass(MRI->getRegClass(SrcReg)))
1810 InflateRegs.push_back(SrcReg);
1811 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
1812 RegClassInfo.isProperSubClass(MRI->getRegClass(DstReg)))
1813 InflateRegs.push_back(DstReg);
1815 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
1816 MI->getNumOperands() > 2)
1817 // Do not delete extract_subreg, insert_subreg of physical
1818 // registers unless the definition is dead. e.g.
1819 // %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
1820 // or else the scavenger may complain. LowerSubregs will
1821 // delete them later.
1824 if (MI->allDefsAreDead()) {
1825 if (TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1826 LIS->hasInterval(SrcReg))
1827 LIS->shrinkToUses(&LIS->getInterval(SrcReg));
1831 // We need the instruction to adjust liveness, so make it a KILL.
1832 if (MI->isSubregToReg()) {
1833 MI->RemoveOperand(3);
1834 MI->RemoveOperand(1);
1836 MI->setDesc(TII->get(TargetOpcode::KILL));
1837 mii = llvm::next(mii);
1839 LIS->RemoveMachineInstrFromMaps(MI);
1840 mii = mbbi->erase(mii);
1846 // Now check if this is a remat'ed def instruction which is now dead.
1847 if (ReMatDefs.count(MI)) {
1849 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1850 const MachineOperand &MO = MI->getOperand(i);
1853 unsigned Reg = MO.getReg();
1856 DeadDefs.push_back(Reg);
1857 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1858 // Remat may also enable register class inflation.
1859 if (RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)))
1860 InflateRegs.push_back(Reg);
1864 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
1865 !MRI->use_nodbg_empty(Reg)) {
1871 while (!DeadDefs.empty()) {
1872 unsigned DeadDef = DeadDefs.back();
1873 DeadDefs.pop_back();
1874 removeDeadDef(LIS->getInterval(DeadDef), MI);
1876 LIS->RemoveMachineInstrFromMaps(mii);
1877 mii = mbbi->erase(mii);
1885 // Check for now unnecessary kill flags.
1886 if (LIS->isNotInMIMap(MI)) continue;
1887 SlotIndex DefIdx = LIS->getInstructionIndex(MI).getRegSlot();
1888 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1889 MachineOperand &MO = MI->getOperand(i);
1890 if (!MO.isReg() || !MO.isKill()) continue;
1891 unsigned reg = MO.getReg();
1892 if (!reg || !LIS->hasInterval(reg)) continue;
1893 if (!LIS->getInterval(reg).killedAt(DefIdx)) {
1894 MO.setIsKill(false);
1897 // When leaving a kill flag on a physreg, check if any subregs should
1899 if (!TargetRegisterInfo::isPhysicalRegister(reg))
1901 for (const uint16_t *SR = TRI->getSubRegisters(reg);
1902 unsigned S = *SR; ++SR)
1903 if (LIS->hasInterval(S) && LIS->getInterval(S).liveAt(DefIdx))
1904 MI->addRegisterDefined(S, TRI);
1909 // After deleting a lot of copies, register classes may be less constrained.
1910 // Removing sub-register opreands may alow GR32_ABCD -> GR32 and DPR_VFP2 ->
1912 array_pod_sort(InflateRegs.begin(), InflateRegs.end());
1913 InflateRegs.erase(std::unique(InflateRegs.begin(), InflateRegs.end()),
1915 DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size() << " regs.\n");
1916 for (unsigned i = 0, e = InflateRegs.size(); i != e; ++i) {
1917 unsigned Reg = InflateRegs[i];
1918 if (MRI->reg_nodbg_empty(Reg))
1920 if (MRI->recomputeRegClass(Reg, *TM)) {
1921 DEBUG(dbgs() << PrintReg(Reg) << " inflated to "
1922 << MRI->getRegClass(Reg)->getName() << '\n');
1929 if (VerifyCoalescing)
1930 MF->verify(this, "After register coalescing");
1934 /// print - Implement the dump method.
1935 void RegisterCoalescer::print(raw_ostream &O, const Module* m) const {