1 //===- RegisterCoalescer.cpp - Generic Register Coalescing Interface -------==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the generic RegisterCoalescer interface which
11 // is used as the common interface used by all clients and
12 // implementations of register coalescing.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "regalloc"
17 #include "RegisterCoalescer.h"
18 #include "LiveDebugVariables.h"
19 #include "VirtRegMap.h"
21 #include "llvm/Pass.h"
22 #include "llvm/Value.h"
23 #include "llvm/ADT/OwningPtr.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallSet.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Analysis/AliasAnalysis.h"
28 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
29 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
30 #include "llvm/CodeGen/LiveRangeEdit.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineInstr.h"
34 #include "llvm/CodeGen/MachineLoopInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/CodeGen/RegisterClassInfo.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/ErrorHandling.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Target/TargetRegisterInfo.h"
48 #include "llvm/Target/TargetSubtargetInfo.h"
53 STATISTIC(numJoins , "Number of interval joins performed");
54 STATISTIC(numCrossRCs , "Number of cross class joins performed");
55 STATISTIC(numCommutes , "Number of instruction commuting performed");
56 STATISTIC(numExtends , "Number of copies extended");
57 STATISTIC(NumReMats , "Number of instructions re-materialized");
58 STATISTIC(NumInflated , "Number of register classes inflated");
59 STATISTIC(NumLaneConflicts, "Number of dead lane conflicts tested");
60 STATISTIC(NumLaneResolves, "Number of dead lane conflicts resolved");
63 EnableJoining("join-liveintervals",
64 cl::desc("Coalesce copies (default=true)"),
67 // Temporary flag to test critical edge unsplitting.
69 EnableJoinSplits("join-splitedges",
70 cl::desc("Coalesce copies on split edges (default=subtarget)"), cl::Hidden);
72 // Temporary flag to test global copy optimization.
73 static cl::opt<cl::boolOrDefault>
74 EnableGlobalCopies("join-globalcopies",
75 cl::desc("Coalesce copies that span blocks (default=subtarget)"),
76 cl::init(cl::BOU_UNSET), cl::Hidden);
79 VerifyCoalescing("verify-coalescing",
80 cl::desc("Verify machine instrs before and after register coalescing"),
84 class RegisterCoalescer : public MachineFunctionPass,
85 private LiveRangeEdit::Delegate {
87 MachineRegisterInfo* MRI;
88 const TargetMachine* TM;
89 const TargetRegisterInfo* TRI;
90 const TargetInstrInfo* TII;
92 LiveDebugVariables *LDV;
93 const MachineLoopInfo* Loops;
95 RegisterClassInfo RegClassInfo;
97 /// \brief True if the coalescer should aggressively coalesce global copies
98 /// in favor of keeping local copies.
99 bool JoinGlobalCopies;
101 /// \brief True if the coalescer should aggressively coalesce fall-thru
102 /// blocks exclusively containing copies.
105 /// WorkList - Copy instructions yet to be coalesced.
106 SmallVector<MachineInstr*, 8> WorkList;
107 SmallVector<MachineInstr*, 8> LocalWorkList;
109 /// ErasedInstrs - Set of instruction pointers that have been erased, and
110 /// that may be present in WorkList.
111 SmallPtrSet<MachineInstr*, 8> ErasedInstrs;
113 /// Dead instructions that are about to be deleted.
114 SmallVector<MachineInstr*, 8> DeadDefs;
116 /// Virtual registers to be considered for register class inflation.
117 SmallVector<unsigned, 8> InflateRegs;
119 /// Recursively eliminate dead defs in DeadDefs.
120 void eliminateDeadDefs();
122 /// LiveRangeEdit callback.
123 void LRE_WillEraseInstruction(MachineInstr *MI);
125 /// coalesceLocals - coalesce the LocalWorkList.
126 void coalesceLocals();
128 /// joinAllIntervals - join compatible live intervals
129 void joinAllIntervals();
131 /// copyCoalesceInMBB - Coalesce copies in the specified MBB, putting
132 /// copies that cannot yet be coalesced into WorkList.
133 void copyCoalesceInMBB(MachineBasicBlock *MBB);
135 /// copyCoalesceWorkList - Try to coalesce all copies in CurrList. Return
136 /// true if any progress was made.
137 bool copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList);
139 /// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
140 /// which are the src/dst of the copy instruction CopyMI. This returns
141 /// true if the copy was successfully coalesced away. If it is not
142 /// currently possible to coalesce this interval, but it may be possible if
143 /// other things get coalesced, then it returns true by reference in
145 bool joinCopy(MachineInstr *TheCopy, bool &Again);
147 /// joinIntervals - Attempt to join these two intervals. On failure, this
148 /// returns false. The output "SrcInt" will not have been modified, so we
149 /// can use this information below to update aliases.
150 bool joinIntervals(CoalescerPair &CP);
152 /// Attempt joining two virtual registers. Return true on success.
153 bool joinVirtRegs(CoalescerPair &CP);
155 /// Attempt joining with a reserved physreg.
156 bool joinReservedPhysReg(CoalescerPair &CP);
158 /// adjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
159 /// the source value number is defined by a copy from the destination reg
160 /// see if we can merge these two destination reg valno# into a single
161 /// value number, eliminating a copy.
162 bool adjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
164 /// hasOtherReachingDefs - Return true if there are definitions of IntB
165 /// other than BValNo val# that can reach uses of AValno val# of IntA.
166 bool hasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
167 VNInfo *AValNo, VNInfo *BValNo);
169 /// removeCopyByCommutingDef - We found a non-trivially-coalescable copy.
170 /// If the source value number is defined by a commutable instruction and
171 /// its other operand is coalesced to the copy dest register, see if we
172 /// can transform the copy into a noop by commuting the definition.
173 bool removeCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
175 /// reMaterializeTrivialDef - If the source of a copy is defined by a
176 /// trivial computation, replace the copy by rematerialize the definition.
177 bool reMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg,
178 MachineInstr *CopyMI);
180 /// canJoinPhys - Return true if a physreg copy should be joined.
181 bool canJoinPhys(const CoalescerPair &CP);
183 /// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
184 /// update the subregister number if it is not zero. If DstReg is a
185 /// physical register and the existing subregister number of the def / use
186 /// being updated is not zero, make sure to set it to the correct physical
188 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
190 /// eliminateUndefCopy - Handle copies of undef values.
191 bool eliminateUndefCopy(MachineInstr *CopyMI, const CoalescerPair &CP);
194 static char ID; // Class identification, replacement for typeinfo
195 RegisterCoalescer() : MachineFunctionPass(ID) {
196 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
199 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
201 virtual void releaseMemory();
203 /// runOnMachineFunction - pass entry point
204 virtual bool runOnMachineFunction(MachineFunction&);
206 /// print - Implement the dump method.
207 virtual void print(raw_ostream &O, const Module* = 0) const;
209 } /// end anonymous namespace
211 char &llvm::RegisterCoalescerID = RegisterCoalescer::ID;
213 INITIALIZE_PASS_BEGIN(RegisterCoalescer, "simple-register-coalescing",
214 "Simple Register Coalescing", false, false)
215 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
216 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
217 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
218 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
219 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
220 INITIALIZE_PASS_END(RegisterCoalescer, "simple-register-coalescing",
221 "Simple Register Coalescing", false, false)
223 char RegisterCoalescer::ID = 0;
225 static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI,
226 unsigned &Src, unsigned &Dst,
227 unsigned &SrcSub, unsigned &DstSub) {
229 Dst = MI->getOperand(0).getReg();
230 DstSub = MI->getOperand(0).getSubReg();
231 Src = MI->getOperand(1).getReg();
232 SrcSub = MI->getOperand(1).getSubReg();
233 } else if (MI->isSubregToReg()) {
234 Dst = MI->getOperand(0).getReg();
235 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(),
236 MI->getOperand(3).getImm());
237 Src = MI->getOperand(2).getReg();
238 SrcSub = MI->getOperand(2).getSubReg();
244 // Return true if this block should be vacated by the coalescer to eliminate
245 // branches. The important cases to handle in the coalescer are critical edges
246 // split during phi elimination which contain only copies. Simple blocks that
247 // contain non-branches should also be vacated, but this can be handled by an
248 // earlier pass similar to early if-conversion.
249 static bool isSplitEdge(const MachineBasicBlock *MBB) {
250 if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
253 for (MachineBasicBlock::const_iterator MII = MBB->begin(), E = MBB->end();
255 if (!MII->isCopyLike() && !MII->isUnconditionalBranch())
261 bool CoalescerPair::setRegisters(const MachineInstr *MI) {
265 Flipped = CrossClass = false;
267 unsigned Src, Dst, SrcSub, DstSub;
268 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
270 Partial = SrcSub || DstSub;
272 // If one register is a physreg, it must be Dst.
273 if (TargetRegisterInfo::isPhysicalRegister(Src)) {
274 if (TargetRegisterInfo::isPhysicalRegister(Dst))
277 std::swap(SrcSub, DstSub);
281 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
283 if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
284 // Eliminate DstSub on a physreg.
286 Dst = TRI.getSubReg(Dst, DstSub);
287 if (!Dst) return false;
291 // Eliminate SrcSub by picking a corresponding Dst superregister.
293 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
294 if (!Dst) return false;
296 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
300 // Both registers are virtual.
301 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
302 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
304 // Both registers have subreg indices.
305 if (SrcSub && DstSub) {
306 // Copies between different sub-registers are never coalescable.
307 if (Src == Dst && SrcSub != DstSub)
310 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
315 // SrcReg will be merged with a sub-register of DstReg.
317 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
319 // DstReg will be merged with a sub-register of SrcReg.
321 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
323 // This is a straight copy without sub-registers.
324 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
327 // The combined constraint may be impossible to satisfy.
331 // Prefer SrcReg to be a sub-register of DstReg.
332 // FIXME: Coalescer should support subregs symmetrically.
333 if (DstIdx && !SrcIdx) {
335 std::swap(SrcIdx, DstIdx);
339 CrossClass = NewRC != DstRC || NewRC != SrcRC;
341 // Check our invariants
342 assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual");
343 assert(!(TargetRegisterInfo::isPhysicalRegister(Dst) && DstSub) &&
344 "Cannot have a physical SubIdx");
350 bool CoalescerPair::flip() {
351 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
353 std::swap(SrcReg, DstReg);
354 std::swap(SrcIdx, DstIdx);
359 bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
362 unsigned Src, Dst, SrcSub, DstSub;
363 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
366 // Find the virtual register that is SrcReg.
369 std::swap(SrcSub, DstSub);
370 } else if (Src != SrcReg) {
374 // Now check that Dst matches DstReg.
375 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
376 if (!TargetRegisterInfo::isPhysicalRegister(Dst))
378 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.");
379 // DstSub could be set for a physreg from INSERT_SUBREG.
381 Dst = TRI.getSubReg(Dst, DstSub);
384 return DstReg == Dst;
385 // This is a partial register copy. Check that the parts match.
386 return TRI.getSubReg(DstReg, SrcSub) == Dst;
388 // DstReg is virtual.
391 // Registers match, do the subregisters line up?
392 return TRI.composeSubRegIndices(SrcIdx, SrcSub) ==
393 TRI.composeSubRegIndices(DstIdx, DstSub);
397 void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const {
398 AU.setPreservesCFG();
399 AU.addRequired<AliasAnalysis>();
400 AU.addRequired<LiveIntervals>();
401 AU.addPreserved<LiveIntervals>();
402 AU.addRequired<LiveDebugVariables>();
403 AU.addPreserved<LiveDebugVariables>();
404 AU.addPreserved<SlotIndexes>();
405 AU.addRequired<MachineLoopInfo>();
406 AU.addPreserved<MachineLoopInfo>();
407 AU.addPreservedID(MachineDominatorsID);
408 MachineFunctionPass::getAnalysisUsage(AU);
411 void RegisterCoalescer::eliminateDeadDefs() {
412 SmallVector<LiveInterval*, 8> NewRegs;
413 LiveRangeEdit(0, NewRegs, *MF, *LIS, 0, this).eliminateDeadDefs(DeadDefs);
416 // Callback from eliminateDeadDefs().
417 void RegisterCoalescer::LRE_WillEraseInstruction(MachineInstr *MI) {
418 // MI may be in WorkList. Make sure we don't visit it.
419 ErasedInstrs.insert(MI);
422 /// adjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
423 /// being the source and IntB being the dest, thus this defines a value number
424 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
425 /// see if we can merge these two pieces of B into a single value number,
426 /// eliminating a copy. For example:
430 /// B1 = A3 <- this copy
432 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
433 /// value number to be replaced with B0 (which simplifies the B liveinterval).
435 /// This returns true if an interval was modified.
437 bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP,
438 MachineInstr *CopyMI) {
439 assert(!CP.isPartial() && "This doesn't work for partial copies.");
440 assert(!CP.isPhys() && "This doesn't work for physreg copies.");
443 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
445 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
446 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
448 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
449 // the example above.
450 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
451 if (BLR == IntB.end()) return false;
452 VNInfo *BValNo = BLR->valno;
454 // Get the location that B is defined at. Two options: either this value has
455 // an unknown definition point or it is defined at CopyIdx. If unknown, we
457 if (BValNo->def != CopyIdx) return false;
459 // AValNo is the value number in A that defines the copy, A3 in the example.
460 SlotIndex CopyUseIdx = CopyIdx.getRegSlot(true);
461 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
462 // The live range might not exist after fun with physreg coalescing.
463 if (ALR == IntA.end()) return false;
464 VNInfo *AValNo = ALR->valno;
466 // If AValNo is defined as a copy from IntB, we can potentially process this.
467 // Get the instruction that defines this value number.
468 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
469 // Don't allow any partial copies, even if isCoalescable() allows them.
470 if (!CP.isCoalescable(ACopyMI) || !ACopyMI->isFullCopy())
473 // Get the LiveRange in IntB that this value number starts with.
474 LiveInterval::iterator ValLR =
475 IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot());
476 if (ValLR == IntB.end())
479 // Make sure that the end of the live range is inside the same block as
481 MachineInstr *ValLREndInst =
482 LIS->getInstructionFromIndex(ValLR->end.getPrevSlot());
483 if (!ValLREndInst || ValLREndInst->getParent() != CopyMI->getParent())
486 // Okay, we now know that ValLR ends in the same block that the CopyMI
487 // live-range starts. If there are no intervening live ranges between them in
488 // IntB, we can merge them.
489 if (ValLR+1 != BLR) return false;
491 DEBUG(dbgs() << "Extending: " << PrintReg(IntB.reg, TRI));
493 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
494 // We are about to delete CopyMI, so need to remove it as the 'instruction
495 // that defines this value #'. Update the valnum with the new defining
497 BValNo->def = FillerStart;
499 // Okay, we can merge them. We need to insert a new liverange:
500 // [ValLR.end, BLR.begin) of either value number, then we merge the
501 // two value numbers.
502 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
504 // Okay, merge "B1" into the same value number as "B0".
505 if (BValNo != ValLR->valno)
506 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
507 DEBUG(dbgs() << " result = " << IntB << '\n');
509 // If the source instruction was killing the source register before the
510 // merge, unset the isKill marker given the live range has been extended.
511 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
513 ValLREndInst->getOperand(UIdx).setIsKill(false);
516 // Rewrite the copy. If the copy instruction was killing the destination
517 // register before the merge, find the last use and trim the live range. That
518 // will also add the isKill marker.
519 CopyMI->substituteRegister(IntA.reg, IntB.reg, 0, *TRI);
520 if (ALR->end == CopyIdx)
521 LIS->shrinkToUses(&IntA);
527 /// hasOtherReachingDefs - Return true if there are definitions of IntB
528 /// other than BValNo val# that can reach uses of AValno val# of IntA.
529 bool RegisterCoalescer::hasOtherReachingDefs(LiveInterval &IntA,
533 // If AValNo has PHI kills, conservatively assume that IntB defs can reach
535 if (LIS->hasPHIKill(IntA, AValNo))
538 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
540 if (AI->valno != AValNo) continue;
541 LiveInterval::Ranges::iterator BI =
542 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
543 if (BI != IntB.ranges.begin())
545 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
546 if (BI->valno == BValNo)
548 if (BI->start <= AI->start && BI->end > AI->start)
550 if (BI->start > AI->start && BI->start < AI->end)
557 /// removeCopyByCommutingDef - We found a non-trivially-coalescable copy with
558 /// IntA being the source and IntB being the dest, thus this defines a value
559 /// number in IntB. If the source value number (in IntA) is defined by a
560 /// commutable instruction and its other operand is coalesced to the copy dest
561 /// register, see if we can transform the copy into a noop by commuting the
562 /// definition. For example,
564 /// A3 = op A2 B0<kill>
566 /// B1 = A3 <- this copy
568 /// = op A3 <- more uses
572 /// B2 = op B0 A2<kill>
574 /// B1 = B2 <- now an identify copy
576 /// = op B2 <- more uses
578 /// This returns true if an interval was modified.
580 bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
581 MachineInstr *CopyMI) {
582 assert (!CP.isPhys());
584 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
587 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
589 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
591 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
592 // the example above.
593 VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx);
594 if (!BValNo || BValNo->def != CopyIdx)
597 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
599 // AValNo is the value number in A that defines the copy, A3 in the example.
600 VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getRegSlot(true));
601 assert(AValNo && "COPY source not live");
602 if (AValNo->isPHIDef() || AValNo->isUnused())
604 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
607 if (!DefMI->isCommutable())
609 // If DefMI is a two-address instruction then commuting it will change the
610 // destination register.
611 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
612 assert(DefIdx != -1);
614 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
616 unsigned Op1, Op2, NewDstIdx;
617 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
621 else if (Op2 == UseOpIdx)
626 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
627 unsigned NewReg = NewDstMO.getReg();
628 if (NewReg != IntB.reg || !LiveRangeQuery(IntB, AValNo->def).isKill())
631 // Make sure there are no other definitions of IntB that would reach the
632 // uses which the new definition can reach.
633 if (hasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
636 // If some of the uses of IntA.reg is already coalesced away, return false.
637 // It's not possible to determine whether it's safe to perform the coalescing.
638 for (MachineRegisterInfo::use_nodbg_iterator UI =
639 MRI->use_nodbg_begin(IntA.reg),
640 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
641 MachineInstr *UseMI = &*UI;
642 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
643 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
644 if (ULR == IntA.end() || ULR->valno != AValNo)
646 // If this use is tied to a def, we can't rewrite the register.
647 if (UseMI->isRegTiedToDefOperand(UI.getOperandNo()))
651 DEBUG(dbgs() << "\tremoveCopyByCommutingDef: " << AValNo->def << '\t'
654 // At this point we have decided that it is legal to do this
655 // transformation. Start by commuting the instruction.
656 MachineBasicBlock *MBB = DefMI->getParent();
657 MachineInstr *NewMI = TII->commuteInstruction(DefMI);
660 if (TargetRegisterInfo::isVirtualRegister(IntA.reg) &&
661 TargetRegisterInfo::isVirtualRegister(IntB.reg) &&
662 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
664 if (NewMI != DefMI) {
665 LIS->ReplaceMachineInstrInMaps(DefMI, NewMI);
666 MachineBasicBlock::iterator Pos = DefMI;
667 MBB->insert(Pos, NewMI);
670 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
671 NewMI->getOperand(OpIdx).setIsKill();
673 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
682 // Update uses of IntA of the specific Val# with IntB.
683 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg),
684 UE = MRI->use_end(); UI != UE;) {
685 MachineOperand &UseMO = UI.getOperand();
686 MachineInstr *UseMI = &*UI;
688 if (UseMI->isDebugValue()) {
689 // FIXME These don't have an instruction index. Not clear we have enough
690 // info to decide whether to do this replacement or not. For now do it.
691 UseMO.setReg(NewReg);
694 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
695 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
696 if (ULR == IntA.end() || ULR->valno != AValNo)
698 // Kill flags are no longer accurate. They are recomputed after RA.
699 UseMO.setIsKill(false);
700 if (TargetRegisterInfo::isPhysicalRegister(NewReg))
701 UseMO.substPhysReg(NewReg, *TRI);
703 UseMO.setReg(NewReg);
706 if (!UseMI->isCopy())
708 if (UseMI->getOperand(0).getReg() != IntB.reg ||
709 UseMI->getOperand(0).getSubReg())
712 // This copy will become a noop. If it's defining a new val#, merge it into
714 SlotIndex DefIdx = UseIdx.getRegSlot();
715 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
718 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
719 assert(DVNI->def == DefIdx);
720 BValNo = IntB.MergeValueNumberInto(BValNo, DVNI);
721 ErasedInstrs.insert(UseMI);
722 LIS->RemoveMachineInstrFromMaps(UseMI);
723 UseMI->eraseFromParent();
726 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
728 VNInfo *ValNo = BValNo;
729 ValNo->def = AValNo->def;
730 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
732 if (AI->valno != AValNo) continue;
733 IntB.addRange(LiveRange(AI->start, AI->end, ValNo));
735 DEBUG(dbgs() << "\t\textended: " << IntB << '\n');
737 IntA.removeValNo(AValNo);
738 DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n');
743 /// reMaterializeTrivialDef - If the source of a copy is defined by a trivial
744 /// computation, replace the copy by rematerialize the definition.
745 bool RegisterCoalescer::reMaterializeTrivialDef(LiveInterval &SrcInt,
747 MachineInstr *CopyMI) {
748 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(true);
749 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
750 assert(SrcLR != SrcInt.end() && "Live range not found!");
751 VNInfo *ValNo = SrcLR->valno;
752 if (ValNo->isPHIDef() || ValNo->isUnused())
754 MachineInstr *DefMI = LIS->getInstructionFromIndex(ValNo->def);
757 assert(DefMI && "Defining instruction disappeared");
758 if (!DefMI->isAsCheapAsAMove())
760 if (!TII->isTriviallyReMaterializable(DefMI, AA))
762 bool SawStore = false;
763 if (!DefMI->isSafeToMove(TII, AA, SawStore))
765 const MCInstrDesc &MCID = DefMI->getDesc();
766 if (MCID.getNumDefs() != 1)
768 if (!DefMI->isImplicitDef()) {
769 // Make sure the copy destination register class fits the instruction
770 // definition register class. The mismatch can happen as a result of earlier
771 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
772 const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI, *MF);
773 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
774 if (MRI->getRegClass(DstReg) != RC)
776 } else if (!RC->contains(DstReg))
780 MachineBasicBlock *MBB = CopyMI->getParent();
781 MachineBasicBlock::iterator MII =
782 llvm::next(MachineBasicBlock::iterator(CopyMI));
783 TII->reMaterialize(*MBB, MII, DstReg, 0, DefMI, *TRI);
784 MachineInstr *NewMI = prior(MII);
786 // NewMI may have dead implicit defs (E.g. EFLAGS for MOV<bits>r0 on X86).
787 // We need to remember these so we can add intervals once we insert
788 // NewMI into SlotIndexes.
789 SmallVector<unsigned, 4> NewMIImplDefs;
790 for (unsigned i = NewMI->getDesc().getNumOperands(),
791 e = NewMI->getNumOperands(); i != e; ++i) {
792 MachineOperand &MO = NewMI->getOperand(i);
794 assert(MO.isDef() && MO.isImplicit() && MO.isDead() &&
795 TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
796 NewMIImplDefs.push_back(MO.getReg());
800 // CopyMI may have implicit operands, transfer them over to the newly
801 // rematerialized instruction. And update implicit def interval valnos.
802 for (unsigned i = CopyMI->getDesc().getNumOperands(),
803 e = CopyMI->getNumOperands(); i != e; ++i) {
804 MachineOperand &MO = CopyMI->getOperand(i);
806 assert(MO.isImplicit() && "No explicit operands after implict operands.");
807 // Discard VReg implicit defs.
808 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
809 NewMI->addOperand(MO);
814 LIS->ReplaceMachineInstrInMaps(CopyMI, NewMI);
816 SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
817 for (unsigned i = 0, e = NewMIImplDefs.size(); i != e; ++i) {
818 unsigned Reg = NewMIImplDefs[i];
819 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
820 if (LiveInterval *LI = LIS->getCachedRegUnit(*Units))
821 LI->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
824 CopyMI->eraseFromParent();
825 ErasedInstrs.insert(CopyMI);
826 DEBUG(dbgs() << "Remat: " << *NewMI);
829 // The source interval can become smaller because we removed a use.
830 LIS->shrinkToUses(&SrcInt, &DeadDefs);
831 if (!DeadDefs.empty())
837 /// eliminateUndefCopy - ProcessImpicitDefs may leave some copies of <undef>
838 /// values, it only removes local variables. When we have a copy like:
840 /// %vreg1 = COPY %vreg2<undef>
842 /// We delete the copy and remove the corresponding value number from %vreg1.
843 /// Any uses of that value number are marked as <undef>.
844 bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI,
845 const CoalescerPair &CP) {
846 SlotIndex Idx = LIS->getInstructionIndex(CopyMI);
847 LiveInterval *SrcInt = &LIS->getInterval(CP.getSrcReg());
848 if (SrcInt->liveAt(Idx))
850 LiveInterval *DstInt = &LIS->getInterval(CP.getDstReg());
851 if (DstInt->liveAt(Idx))
854 // No intervals are live-in to CopyMI - it is undef.
859 VNInfo *DeadVNI = DstInt->getVNInfoAt(Idx.getRegSlot());
860 assert(DeadVNI && "No value defined in DstInt");
861 DstInt->removeValNo(DeadVNI);
863 // Find new undef uses.
864 for (MachineRegisterInfo::reg_nodbg_iterator
865 I = MRI->reg_nodbg_begin(DstInt->reg), E = MRI->reg_nodbg_end();
867 MachineOperand &MO = I.getOperand();
868 if (MO.isDef() || MO.isUndef())
870 MachineInstr *MI = MO.getParent();
871 SlotIndex Idx = LIS->getInstructionIndex(MI);
872 if (DstInt->liveAt(Idx))
875 DEBUG(dbgs() << "\tnew undef: " << Idx << '\t' << *MI);
880 /// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
881 /// update the subregister number if it is not zero. If DstReg is a
882 /// physical register and the existing subregister number of the def / use
883 /// being updated is not zero, make sure to set it to the correct physical
885 void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg,
888 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
889 LiveInterval *DstInt = DstIsPhys ? 0 : &LIS->getInterval(DstReg);
891 // Update LiveDebugVariables.
892 LDV->renameRegister(SrcReg, DstReg, SubIdx);
894 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg);
895 MachineInstr *UseMI = I.skipInstruction();) {
896 SmallVector<unsigned,8> Ops;
898 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
900 // If SrcReg wasn't read, it may still be the case that DstReg is live-in
901 // because SrcReg is a sub-register.
902 if (DstInt && !Reads && SubIdx)
903 Reads = DstInt->liveAt(LIS->getInstructionIndex(UseMI));
905 // Replace SrcReg with DstReg in all UseMI operands.
906 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
907 MachineOperand &MO = UseMI->getOperand(Ops[i]);
909 // Adjust <undef> flags in case of sub-register joins. We don't want to
910 // turn a full def into a read-modify-write sub-register def and vice
912 if (SubIdx && MO.isDef())
913 MO.setIsUndef(!Reads);
916 MO.substPhysReg(DstReg, *TRI);
918 MO.substVirtReg(DstReg, SubIdx, *TRI);
922 dbgs() << "\t\tupdated: ";
923 if (!UseMI->isDebugValue())
924 dbgs() << LIS->getInstructionIndex(UseMI) << "\t";
930 /// canJoinPhys - Return true if a copy involving a physreg should be joined.
931 bool RegisterCoalescer::canJoinPhys(const CoalescerPair &CP) {
932 /// Always join simple intervals that are defined by a single copy from a
933 /// reserved register. This doesn't increase register pressure, so it is
934 /// always beneficial.
935 if (!MRI->isReserved(CP.getDstReg())) {
936 DEBUG(dbgs() << "\tCan only merge into reserved registers.\n");
940 LiveInterval &JoinVInt = LIS->getInterval(CP.getSrcReg());
941 if (CP.isFlipped() && JoinVInt.containsOneValue())
944 DEBUG(dbgs() << "\tCannot join defs into reserved register.\n");
948 /// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
949 /// which are the src/dst of the copy instruction CopyMI. This returns true
950 /// if the copy was successfully coalesced away. If it is not currently
951 /// possible to coalesce this interval, but it may be possible if other
952 /// things get coalesced, then it returns true by reference in 'Again'.
953 bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
956 DEBUG(dbgs() << LIS->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
958 CoalescerPair CP(*TRI);
959 if (!CP.setRegisters(CopyMI)) {
960 DEBUG(dbgs() << "\tNot coalescable.\n");
964 // Dead code elimination. This really should be handled by MachineDCE, but
965 // sometimes dead copies slip through, and we can't generate invalid live
967 if (!CP.isPhys() && CopyMI->allDefsAreDead()) {
968 DEBUG(dbgs() << "\tCopy is dead.\n");
969 DeadDefs.push_back(CopyMI);
975 if (!CP.isPhys() && eliminateUndefCopy(CopyMI, CP)) {
976 DEBUG(dbgs() << "\tEliminated copy of <undef> value.\n");
977 LIS->RemoveMachineInstrFromMaps(CopyMI);
978 CopyMI->eraseFromParent();
979 return false; // Not coalescable.
982 // Coalesced copies are normally removed immediately, but transformations
983 // like removeCopyByCommutingDef() can inadvertently create identity copies.
984 // When that happens, just join the values and remove the copy.
985 if (CP.getSrcReg() == CP.getDstReg()) {
986 LiveInterval &LI = LIS->getInterval(CP.getSrcReg());
987 DEBUG(dbgs() << "\tCopy already coalesced: " << LI << '\n');
988 LiveRangeQuery LRQ(LI, LIS->getInstructionIndex(CopyMI));
989 if (VNInfo *DefVNI = LRQ.valueDefined()) {
990 VNInfo *ReadVNI = LRQ.valueIn();
991 assert(ReadVNI && "No value before copy and no <undef> flag.");
992 assert(ReadVNI != DefVNI && "Cannot read and define the same value.");
993 LI.MergeValueNumberInto(DefVNI, ReadVNI);
994 DEBUG(dbgs() << "\tMerged values: " << LI << '\n');
996 LIS->RemoveMachineInstrFromMaps(CopyMI);
997 CopyMI->eraseFromParent();
1001 // Enforce policies.
1003 DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI)
1004 << " with " << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx())
1006 if (!canJoinPhys(CP)) {
1007 // Before giving up coalescing, if definition of source is defined by
1008 // trivial computation, try rematerializing it.
1009 if (!CP.isFlipped() &&
1010 reMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()),
1011 CP.getDstReg(), CopyMI))
1017 dbgs() << "\tConsidering merging to " << CP.getNewRC()->getName()
1019 if (CP.getDstIdx() && CP.getSrcIdx())
1020 dbgs() << PrintReg(CP.getDstReg()) << " in "
1021 << TRI->getSubRegIndexName(CP.getDstIdx()) << " and "
1022 << PrintReg(CP.getSrcReg()) << " in "
1023 << TRI->getSubRegIndexName(CP.getSrcIdx()) << '\n';
1025 dbgs() << PrintReg(CP.getSrcReg(), TRI) << " in "
1026 << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n';
1029 // When possible, let DstReg be the larger interval.
1030 if (!CP.isPartial() && LIS->getInterval(CP.getSrcReg()).ranges.size() >
1031 LIS->getInterval(CP.getDstReg()).ranges.size())
1035 // Okay, attempt to join these two intervals. On failure, this returns false.
1036 // Otherwise, if one of the intervals being joined is a physreg, this method
1037 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1038 // been modified, so we can use this information below to update aliases.
1039 if (!joinIntervals(CP)) {
1040 // Coalescing failed.
1042 // If definition of source is defined by trivial computation, try
1043 // rematerializing it.
1044 if (!CP.isFlipped() &&
1045 reMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()),
1046 CP.getDstReg(), CopyMI))
1049 // If we can eliminate the copy without merging the live ranges, do so now.
1050 if (!CP.isPartial() && !CP.isPhys()) {
1051 if (adjustCopiesBackFrom(CP, CopyMI) ||
1052 removeCopyByCommutingDef(CP, CopyMI)) {
1053 LIS->RemoveMachineInstrFromMaps(CopyMI);
1054 CopyMI->eraseFromParent();
1055 DEBUG(dbgs() << "\tTrivial!\n");
1060 // Otherwise, we are unable to join the intervals.
1061 DEBUG(dbgs() << "\tInterference!\n");
1062 Again = true; // May be possible to coalesce later.
1066 // Coalescing to a virtual register that is of a sub-register class of the
1067 // other. Make sure the resulting register is set to the right register class.
1068 if (CP.isCrossClass()) {
1070 MRI->setRegClass(CP.getDstReg(), CP.getNewRC());
1073 // Removing sub-register copies can ease the register class constraints.
1074 // Make sure we attempt to inflate the register class of DstReg.
1075 if (!CP.isPhys() && RegClassInfo.isProperSubClass(CP.getNewRC()))
1076 InflateRegs.push_back(CP.getDstReg());
1078 // CopyMI has been erased by joinIntervals at this point. Remove it from
1079 // ErasedInstrs since copyCoalesceWorkList() won't add a successful join back
1080 // to the work list. This keeps ErasedInstrs from growing needlessly.
1081 ErasedInstrs.erase(CopyMI);
1083 // Rewrite all SrcReg operands to DstReg.
1084 // Also update DstReg operands to include DstIdx if it is set.
1086 updateRegDefsUses(CP.getDstReg(), CP.getDstReg(), CP.getDstIdx());
1087 updateRegDefsUses(CP.getSrcReg(), CP.getDstReg(), CP.getSrcIdx());
1089 // SrcReg is guaranteed to be the register whose live interval that is
1091 LIS->removeInterval(CP.getSrcReg());
1093 // Update regalloc hint.
1094 TRI->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
1097 dbgs() << "\tJoined. Result = " << PrintReg(CP.getDstReg(), TRI);
1099 dbgs() << LIS->getInterval(CP.getDstReg());
1107 /// Attempt joining with a reserved physreg.
1108 bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
1109 assert(CP.isPhys() && "Must be a physreg copy");
1110 assert(MRI->isReserved(CP.getDstReg()) && "Not a reserved register");
1111 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1112 DEBUG(dbgs() << "\t\tRHS = " << PrintReg(CP.getSrcReg()) << ' ' << RHS
1115 assert(CP.isFlipped() && RHS.containsOneValue() &&
1116 "Invalid join with reserved register");
1118 // Optimization for reserved registers like ESP. We can only merge with a
1119 // reserved physreg if RHS has a single value that is a copy of CP.DstReg().
1120 // The live range of the reserved register will look like a set of dead defs
1121 // - we don't properly track the live range of reserved registers.
1123 // Deny any overlapping intervals. This depends on all the reserved
1124 // register live ranges to look like dead defs.
1125 for (MCRegUnitIterator UI(CP.getDstReg(), TRI); UI.isValid(); ++UI)
1126 if (RHS.overlaps(LIS->getRegUnit(*UI))) {
1127 DEBUG(dbgs() << "\t\tInterference: " << PrintRegUnit(*UI, TRI) << '\n');
1131 // Skip any value computations, we are not adding new values to the
1132 // reserved register. Also skip merging the live ranges, the reserved
1133 // register live range doesn't need to be accurate as long as all the
1136 // Delete the identity copy.
1137 MachineInstr *CopyMI = MRI->getVRegDef(RHS.reg);
1138 LIS->RemoveMachineInstrFromMaps(CopyMI);
1139 CopyMI->eraseFromParent();
1141 // We don't track kills for reserved registers.
1142 MRI->clearKillFlags(CP.getSrcReg());
1147 //===----------------------------------------------------------------------===//
1148 // Interference checking and interval joining
1149 //===----------------------------------------------------------------------===//
1151 // In the easiest case, the two live ranges being joined are disjoint, and
1152 // there is no interference to consider. It is quite common, though, to have
1153 // overlapping live ranges, and we need to check if the interference can be
1156 // The live range of a single SSA value forms a sub-tree of the dominator tree.
1157 // This means that two SSA values overlap if and only if the def of one value
1158 // is contained in the live range of the other value. As a special case, the
1159 // overlapping values can be defined at the same index.
1161 // The interference from an overlapping def can be resolved in these cases:
1163 // 1. Coalescable copies. The value is defined by a copy that would become an
1164 // identity copy after joining SrcReg and DstReg. The copy instruction will
1165 // be removed, and the value will be merged with the source value.
1167 // There can be several copies back and forth, causing many values to be
1168 // merged into one. We compute a list of ultimate values in the joined live
1169 // range as well as a mappings from the old value numbers.
1171 // 2. IMPLICIT_DEF. This instruction is only inserted to ensure all PHI
1172 // predecessors have a live out value. It doesn't cause real interference,
1173 // and can be merged into the value it overlaps. Like a coalescable copy, it
1174 // can be erased after joining.
1176 // 3. Copy of external value. The overlapping def may be a copy of a value that
1177 // is already in the other register. This is like a coalescable copy, but
1178 // the live range of the source register must be trimmed after erasing the
1179 // copy instruction:
1182 // %dst = COPY %ext <-- Remove this COPY, trim the live range of %ext.
1184 // 4. Clobbering undefined lanes. Vector registers are sometimes built by
1185 // defining one lane at a time:
1187 // %dst:ssub0<def,read-undef> = FOO
1189 // %dst:ssub1<def> = COPY %src
1191 // The live range of %src overlaps the %dst value defined by FOO, but
1192 // merging %src into %dst:ssub1 is only going to clobber the ssub1 lane
1193 // which was undef anyway.
1195 // The value mapping is more complicated in this case. The final live range
1196 // will have different value numbers for both FOO and BAR, but there is no
1197 // simple mapping from old to new values. It may even be necessary to add
1200 // 5. Clobbering dead lanes. A def may clobber a lane of a vector register that
1201 // is live, but never read. This can happen because we don't compute
1202 // individual live ranges per lane.
1206 // %dst:ssub1<def> = COPY %src
1208 // This kind of interference is only resolved locally. If the clobbered
1209 // lane value escapes the block, the join is aborted.
1212 /// Track information about values in a single virtual register about to be
1213 /// joined. Objects of this class are always created in pairs - one for each
1214 /// side of the CoalescerPair.
1218 // Location of this register in the final joined register.
1219 // Either CP.DstIdx or CP.SrcIdx.
1222 // Values that will be present in the final live range.
1223 SmallVectorImpl<VNInfo*> &NewVNInfo;
1225 const CoalescerPair &CP;
1227 SlotIndexes *Indexes;
1228 const TargetRegisterInfo *TRI;
1230 // Value number assignments. Maps value numbers in LI to entries in NewVNInfo.
1231 // This is suitable for passing to LiveInterval::join().
1232 SmallVector<int, 8> Assignments;
1234 // Conflict resolution for overlapping values.
1235 enum ConflictResolution {
1236 // No overlap, simply keep this value.
1239 // Merge this value into OtherVNI and erase the defining instruction.
1240 // Used for IMPLICIT_DEF, coalescable copies, and copies from external
1244 // Merge this value into OtherVNI but keep the defining instruction.
1245 // This is for the special case where OtherVNI is defined by the same
1249 // Keep this value, and have it replace OtherVNI where possible. This
1250 // complicates value mapping since OtherVNI maps to two different values
1251 // before and after this def.
1252 // Used when clobbering undefined or dead lanes.
1255 // Unresolved conflict. Visit later when all values have been mapped.
1258 // Unresolvable conflict. Abort the join.
1262 // Per-value info for LI. The lane bit masks are all relative to the final
1263 // joined register, so they can be compared directly between SrcReg and
1266 ConflictResolution Resolution;
1268 // Lanes written by this def, 0 for unanalyzed values.
1269 unsigned WriteLanes;
1271 // Lanes with defined values in this register. Other lanes are undef and
1273 unsigned ValidLanes;
1275 // Value in LI being redefined by this def.
1278 // Value in the other live range that overlaps this def, if any.
1281 // Is this value an IMPLICIT_DEF?
1284 // True when the live range of this value will be pruned because of an
1285 // overlapping CR_Replace value in the other live range.
1288 // True once Pruned above has been computed.
1289 bool PrunedComputed;
1291 Val() : Resolution(CR_Keep), WriteLanes(0), ValidLanes(0),
1292 RedefVNI(0), OtherVNI(0), IsImplicitDef(false), Pruned(false),
1293 PrunedComputed(false) {}
1295 bool isAnalyzed() const { return WriteLanes != 0; }
1298 // One entry per value number in LI.
1299 SmallVector<Val, 8> Vals;
1301 unsigned computeWriteLanes(const MachineInstr *DefMI, bool &Redef);
1302 VNInfo *stripCopies(VNInfo *VNI);
1303 ConflictResolution analyzeValue(unsigned ValNo, JoinVals &Other);
1304 void computeAssignment(unsigned ValNo, JoinVals &Other);
1305 bool taintExtent(unsigned, unsigned, JoinVals&,
1306 SmallVectorImpl<std::pair<SlotIndex, unsigned> >&);
1307 bool usesLanes(MachineInstr *MI, unsigned, unsigned, unsigned);
1308 bool isPrunedValue(unsigned ValNo, JoinVals &Other);
1311 JoinVals(LiveInterval &li, unsigned subIdx,
1312 SmallVectorImpl<VNInfo*> &newVNInfo,
1313 const CoalescerPair &cp,
1315 const TargetRegisterInfo *tri)
1316 : LI(li), SubIdx(subIdx), NewVNInfo(newVNInfo), CP(cp), LIS(lis),
1317 Indexes(LIS->getSlotIndexes()), TRI(tri),
1318 Assignments(LI.getNumValNums(), -1), Vals(LI.getNumValNums())
1321 /// Analyze defs in LI and compute a value mapping in NewVNInfo.
1322 /// Returns false if any conflicts were impossible to resolve.
1323 bool mapValues(JoinVals &Other);
1325 /// Try to resolve conflicts that require all values to be mapped.
1326 /// Returns false if any conflicts were impossible to resolve.
1327 bool resolveConflicts(JoinVals &Other);
1329 /// Prune the live range of values in Other.LI where they would conflict with
1330 /// CR_Replace values in LI. Collect end points for restoring the live range
1332 void pruneValues(JoinVals &Other, SmallVectorImpl<SlotIndex> &EndPoints);
1334 /// Erase any machine instructions that have been coalesced away.
1335 /// Add erased instructions to ErasedInstrs.
1336 /// Add foreign virtual registers to ShrinkRegs if their live range ended at
1337 /// the erased instrs.
1338 void eraseInstrs(SmallPtrSet<MachineInstr*, 8> &ErasedInstrs,
1339 SmallVectorImpl<unsigned> &ShrinkRegs);
1341 /// Get the value assignments suitable for passing to LiveInterval::join.
1342 const int *getAssignments() const { return Assignments.data(); }
1344 } // end anonymous namespace
1346 /// Compute the bitmask of lanes actually written by DefMI.
1347 /// Set Redef if there are any partial register definitions that depend on the
1348 /// previous value of the register.
1349 unsigned JoinVals::computeWriteLanes(const MachineInstr *DefMI, bool &Redef) {
1351 for (ConstMIOperands MO(DefMI); MO.isValid(); ++MO) {
1352 if (!MO->isReg() || MO->getReg() != LI.reg || !MO->isDef())
1354 L |= TRI->getSubRegIndexLaneMask(
1355 TRI->composeSubRegIndices(SubIdx, MO->getSubReg()));
1362 /// Find the ultimate value that VNI was copied from.
1363 VNInfo *JoinVals::stripCopies(VNInfo *VNI) {
1364 while (!VNI->isPHIDef()) {
1365 MachineInstr *MI = Indexes->getInstructionFromIndex(VNI->def);
1366 assert(MI && "No defining instruction");
1367 if (!MI->isFullCopy())
1369 unsigned Reg = MI->getOperand(1).getReg();
1370 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1372 LiveRangeQuery LRQ(LIS->getInterval(Reg), VNI->def);
1375 VNI = LRQ.valueIn();
1380 /// Analyze ValNo in this live range, and set all fields of Vals[ValNo].
1381 /// Return a conflict resolution when possible, but leave the hard cases as
1383 /// Recursively calls computeAssignment() on this and Other, guaranteeing that
1384 /// both OtherVNI and RedefVNI have been analyzed and mapped before returning.
1385 /// The recursion always goes upwards in the dominator tree, making loops
1387 JoinVals::ConflictResolution
1388 JoinVals::analyzeValue(unsigned ValNo, JoinVals &Other) {
1389 Val &V = Vals[ValNo];
1390 assert(!V.isAnalyzed() && "Value has already been analyzed!");
1391 VNInfo *VNI = LI.getValNumInfo(ValNo);
1392 if (VNI->isUnused()) {
1397 // Get the instruction defining this value, compute the lanes written.
1398 const MachineInstr *DefMI = 0;
1399 if (VNI->isPHIDef()) {
1400 // Conservatively assume that all lanes in a PHI are valid.
1401 V.ValidLanes = V.WriteLanes = TRI->getSubRegIndexLaneMask(SubIdx);
1403 DefMI = Indexes->getInstructionFromIndex(VNI->def);
1405 V.ValidLanes = V.WriteLanes = computeWriteLanes(DefMI, Redef);
1407 // If this is a read-modify-write instruction, there may be more valid
1408 // lanes than the ones written by this instruction.
1409 // This only covers partial redef operands. DefMI may have normal use
1410 // operands reading the register. They don't contribute valid lanes.
1412 // This adds ssub1 to the set of valid lanes in %src:
1414 // %src:ssub1<def> = FOO
1416 // This leaves only ssub1 valid, making any other lanes undef:
1418 // %src:ssub1<def,read-undef> = FOO %src:ssub2
1420 // The <read-undef> flag on the def operand means that old lane values are
1423 V.RedefVNI = LiveRangeQuery(LI, VNI->def).valueIn();
1424 assert(V.RedefVNI && "Instruction is reading nonexistent value");
1425 computeAssignment(V.RedefVNI->id, Other);
1426 V.ValidLanes |= Vals[V.RedefVNI->id].ValidLanes;
1429 // An IMPLICIT_DEF writes undef values.
1430 if (DefMI->isImplicitDef()) {
1431 V.IsImplicitDef = true;
1432 V.ValidLanes &= ~V.WriteLanes;
1436 // Find the value in Other that overlaps VNI->def, if any.
1437 LiveRangeQuery OtherLRQ(Other.LI, VNI->def);
1439 // It is possible that both values are defined by the same instruction, or
1440 // the values are PHIs defined in the same block. When that happens, the two
1441 // values should be merged into one, but not into any preceding value.
1442 // The first value defined or visited gets CR_Keep, the other gets CR_Merge.
1443 if (VNInfo *OtherVNI = OtherLRQ.valueDefined()) {
1444 assert(SlotIndex::isSameInstr(VNI->def, OtherVNI->def) && "Broken LRQ");
1446 // One value stays, the other is merged. Keep the earlier one, or the first
1448 if (OtherVNI->def < VNI->def)
1449 Other.computeAssignment(OtherVNI->id, *this);
1450 else if (VNI->def < OtherVNI->def && OtherLRQ.valueIn()) {
1451 // This is an early-clobber def overlapping a live-in value in the other
1452 // register. Not mergeable.
1453 V.OtherVNI = OtherLRQ.valueIn();
1454 return CR_Impossible;
1456 V.OtherVNI = OtherVNI;
1457 Val &OtherV = Other.Vals[OtherVNI->id];
1458 // Keep this value, check for conflicts when analyzing OtherVNI.
1459 if (!OtherV.isAnalyzed())
1461 // Both sides have been analyzed now.
1462 // Allow overlapping PHI values. Any real interference would show up in a
1463 // predecessor, the PHI itself can't introduce any conflicts.
1464 if (VNI->isPHIDef())
1466 if (V.ValidLanes & OtherV.ValidLanes)
1467 // Overlapping lanes can't be resolved.
1468 return CR_Impossible;
1473 // No simultaneous def. Is Other live at the def?
1474 V.OtherVNI = OtherLRQ.valueIn();
1476 // No overlap, no conflict.
1479 assert(!SlotIndex::isSameInstr(VNI->def, V.OtherVNI->def) && "Broken LRQ");
1481 // We have overlapping values, or possibly a kill of Other.
1482 // Recursively compute assignments up the dominator tree.
1483 Other.computeAssignment(V.OtherVNI->id, *this);
1484 const Val &OtherV = Other.Vals[V.OtherVNI->id];
1486 // Allow overlapping PHI values. Any real interference would show up in a
1487 // predecessor, the PHI itself can't introduce any conflicts.
1488 if (VNI->isPHIDef())
1491 // Check for simple erasable conflicts.
1492 if (DefMI->isImplicitDef())
1495 // Include the non-conflict where DefMI is a coalescable copy that kills
1496 // OtherVNI. We still want the copy erased and value numbers merged.
1497 if (CP.isCoalescable(DefMI)) {
1498 // Some of the lanes copied from OtherVNI may be undef, making them undef
1500 V.ValidLanes &= ~V.WriteLanes | OtherV.ValidLanes;
1504 // This may not be a real conflict if DefMI simply kills Other and defines
1506 if (OtherLRQ.isKill() && OtherLRQ.endPoint() <= VNI->def)
1509 // Handle the case where VNI and OtherVNI can be proven to be identical:
1511 // %other = COPY %ext
1512 // %this = COPY %ext <-- Erase this copy
1514 if (DefMI->isFullCopy() && !CP.isPartial() &&
1515 stripCopies(VNI) == stripCopies(V.OtherVNI))
1518 // If the lanes written by this instruction were all undef in OtherVNI, it is
1519 // still safe to join the live ranges. This can't be done with a simple value
1520 // mapping, though - OtherVNI will map to multiple values:
1522 // 1 %dst:ssub0 = FOO <-- OtherVNI
1523 // 2 %src = BAR <-- VNI
1524 // 3 %dst:ssub1 = COPY %src<kill> <-- Eliminate this copy.
1526 // 5 QUUX %src<kill>
1528 // Here OtherVNI will map to itself in [1;2), but to VNI in [2;5). CR_Replace
1529 // handles this complex value mapping.
1530 if ((V.WriteLanes & OtherV.ValidLanes) == 0)
1533 // If the other live range is killed by DefMI and the live ranges are still
1534 // overlapping, it must be because we're looking at an early clobber def:
1536 // %dst<def,early-clobber> = ASM %src<kill>
1538 // In this case, it is illegal to merge the two live ranges since the early
1539 // clobber def would clobber %src before it was read.
1540 if (OtherLRQ.isKill()) {
1541 // This case where the def doesn't overlap the kill is handled above.
1542 assert(VNI->def.isEarlyClobber() &&
1543 "Only early clobber defs can overlap a kill");
1544 return CR_Impossible;
1547 // VNI is clobbering live lanes in OtherVNI, but there is still the
1548 // possibility that no instructions actually read the clobbered lanes.
1549 // If we're clobbering all the lanes in OtherVNI, at least one must be read.
1550 // Otherwise Other.LI wouldn't be live here.
1551 if ((TRI->getSubRegIndexLaneMask(Other.SubIdx) & ~V.WriteLanes) == 0)
1552 return CR_Impossible;
1554 // We need to verify that no instructions are reading the clobbered lanes. To
1555 // save compile time, we'll only check that locally. Don't allow the tainted
1556 // value to escape the basic block.
1557 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
1558 if (OtherLRQ.endPoint() >= Indexes->getMBBEndIdx(MBB))
1559 return CR_Impossible;
1561 // There are still some things that could go wrong besides clobbered lanes
1562 // being read, for example OtherVNI may be only partially redefined in MBB,
1563 // and some clobbered lanes could escape the block. Save this analysis for
1564 // resolveConflicts() when all values have been mapped. We need to know
1565 // RedefVNI and WriteLanes for any later defs in MBB, and we can't compute
1566 // that now - the recursive analyzeValue() calls must go upwards in the
1568 return CR_Unresolved;
1571 /// Compute the value assignment for ValNo in LI.
1572 /// This may be called recursively by analyzeValue(), but never for a ValNo on
1574 void JoinVals::computeAssignment(unsigned ValNo, JoinVals &Other) {
1575 Val &V = Vals[ValNo];
1576 if (V.isAnalyzed()) {
1577 // Recursion should always move up the dominator tree, so ValNo is not
1578 // supposed to reappear before it has been assigned.
1579 assert(Assignments[ValNo] != -1 && "Bad recursion?");
1582 switch ((V.Resolution = analyzeValue(ValNo, Other))) {
1585 // Merge this ValNo into OtherVNI.
1586 assert(V.OtherVNI && "OtherVNI not assigned, can't merge.");
1587 assert(Other.Vals[V.OtherVNI->id].isAnalyzed() && "Missing recursion");
1588 Assignments[ValNo] = Other.Assignments[V.OtherVNI->id];
1589 DEBUG(dbgs() << "\t\tmerge " << PrintReg(LI.reg) << ':' << ValNo << '@'
1590 << LI.getValNumInfo(ValNo)->def << " into "
1591 << PrintReg(Other.LI.reg) << ':' << V.OtherVNI->id << '@'
1592 << V.OtherVNI->def << " --> @"
1593 << NewVNInfo[Assignments[ValNo]]->def << '\n');
1597 // The other value is going to be pruned if this join is successful.
1598 assert(V.OtherVNI && "OtherVNI not assigned, can't prune");
1599 Other.Vals[V.OtherVNI->id].Pruned = true;
1602 // This value number needs to go in the final joined live range.
1603 Assignments[ValNo] = NewVNInfo.size();
1604 NewVNInfo.push_back(LI.getValNumInfo(ValNo));
1609 bool JoinVals::mapValues(JoinVals &Other) {
1610 for (unsigned i = 0, e = LI.getNumValNums(); i != e; ++i) {
1611 computeAssignment(i, Other);
1612 if (Vals[i].Resolution == CR_Impossible) {
1613 DEBUG(dbgs() << "\t\tinterference at " << PrintReg(LI.reg) << ':' << i
1614 << '@' << LI.getValNumInfo(i)->def << '\n');
1621 /// Assuming ValNo is going to clobber some valid lanes in Other.LI, compute
1622 /// the extent of the tainted lanes in the block.
1624 /// Multiple values in Other.LI can be affected since partial redefinitions can
1625 /// preserve previously tainted lanes.
1627 /// 1 %dst = VLOAD <-- Define all lanes in %dst
1628 /// 2 %src = FOO <-- ValNo to be joined with %dst:ssub0
1629 /// 3 %dst:ssub1 = BAR <-- Partial redef doesn't clear taint in ssub0
1630 /// 4 %dst:ssub0 = COPY %src <-- Conflict resolved, ssub0 wasn't read
1632 /// For each ValNo in Other that is affected, add an (EndIndex, TaintedLanes)
1633 /// entry to TaintedVals.
1635 /// Returns false if the tainted lanes extend beyond the basic block.
1637 taintExtent(unsigned ValNo, unsigned TaintedLanes, JoinVals &Other,
1638 SmallVectorImpl<std::pair<SlotIndex, unsigned> > &TaintExtent) {
1639 VNInfo *VNI = LI.getValNumInfo(ValNo);
1640 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
1641 SlotIndex MBBEnd = Indexes->getMBBEndIdx(MBB);
1643 // Scan Other.LI from VNI.def to MBBEnd.
1644 LiveInterval::iterator OtherI = Other.LI.find(VNI->def);
1645 assert(OtherI != Other.LI.end() && "No conflict?");
1647 // OtherI is pointing to a tainted value. Abort the join if the tainted
1648 // lanes escape the block.
1649 SlotIndex End = OtherI->end;
1650 if (End >= MBBEnd) {
1651 DEBUG(dbgs() << "\t\ttaints global " << PrintReg(Other.LI.reg) << ':'
1652 << OtherI->valno->id << '@' << OtherI->start << '\n');
1655 DEBUG(dbgs() << "\t\ttaints local " << PrintReg(Other.LI.reg) << ':'
1656 << OtherI->valno->id << '@' << OtherI->start
1657 << " to " << End << '\n');
1658 // A dead def is not a problem.
1661 TaintExtent.push_back(std::make_pair(End, TaintedLanes));
1663 // Check for another def in the MBB.
1664 if (++OtherI == Other.LI.end() || OtherI->start >= MBBEnd)
1667 // Lanes written by the new def are no longer tainted.
1668 const Val &OV = Other.Vals[OtherI->valno->id];
1669 TaintedLanes &= ~OV.WriteLanes;
1672 } while (TaintedLanes);
1676 /// Return true if MI uses any of the given Lanes from Reg.
1677 /// This does not include partial redefinitions of Reg.
1678 bool JoinVals::usesLanes(MachineInstr *MI, unsigned Reg, unsigned SubIdx,
1680 if (MI->isDebugValue())
1682 for (ConstMIOperands MO(MI); MO.isValid(); ++MO) {
1683 if (!MO->isReg() || MO->isDef() || MO->getReg() != Reg)
1685 if (!MO->readsReg())
1687 if (Lanes & TRI->getSubRegIndexLaneMask(
1688 TRI->composeSubRegIndices(SubIdx, MO->getSubReg())))
1694 bool JoinVals::resolveConflicts(JoinVals &Other) {
1695 for (unsigned i = 0, e = LI.getNumValNums(); i != e; ++i) {
1697 assert (V.Resolution != CR_Impossible && "Unresolvable conflict");
1698 if (V.Resolution != CR_Unresolved)
1700 DEBUG(dbgs() << "\t\tconflict at " << PrintReg(LI.reg) << ':' << i
1701 << '@' << LI.getValNumInfo(i)->def << '\n');
1703 assert(V.OtherVNI && "Inconsistent conflict resolution.");
1704 VNInfo *VNI = LI.getValNumInfo(i);
1705 const Val &OtherV = Other.Vals[V.OtherVNI->id];
1707 // VNI is known to clobber some lanes in OtherVNI. If we go ahead with the
1708 // join, those lanes will be tainted with a wrong value. Get the extent of
1709 // the tainted lanes.
1710 unsigned TaintedLanes = V.WriteLanes & OtherV.ValidLanes;
1711 SmallVector<std::pair<SlotIndex, unsigned>, 8> TaintExtent;
1712 if (!taintExtent(i, TaintedLanes, Other, TaintExtent))
1713 // Tainted lanes would extend beyond the basic block.
1716 assert(!TaintExtent.empty() && "There should be at least one conflict.");
1718 // Now look at the instructions from VNI->def to TaintExtent (inclusive).
1719 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
1720 MachineBasicBlock::iterator MI = MBB->begin();
1721 if (!VNI->isPHIDef()) {
1722 MI = Indexes->getInstructionFromIndex(VNI->def);
1723 // No need to check the instruction defining VNI for reads.
1726 assert(!SlotIndex::isSameInstr(VNI->def, TaintExtent.front().first) &&
1727 "Interference ends on VNI->def. Should have been handled earlier");
1728 MachineInstr *LastMI =
1729 Indexes->getInstructionFromIndex(TaintExtent.front().first);
1730 assert(LastMI && "Range must end at a proper instruction");
1731 unsigned TaintNum = 0;
1733 assert(MI != MBB->end() && "Bad LastMI");
1734 if (usesLanes(MI, Other.LI.reg, Other.SubIdx, TaintedLanes)) {
1735 DEBUG(dbgs() << "\t\ttainted lanes used by: " << *MI);
1738 // LastMI is the last instruction to use the current value.
1739 if (&*MI == LastMI) {
1740 if (++TaintNum == TaintExtent.size())
1742 LastMI = Indexes->getInstructionFromIndex(TaintExtent[TaintNum].first);
1743 assert(LastMI && "Range must end at a proper instruction");
1744 TaintedLanes = TaintExtent[TaintNum].second;
1749 // The tainted lanes are unused.
1750 V.Resolution = CR_Replace;
1756 // Determine if ValNo is a copy of a value number in LI or Other.LI that will
1760 // %src = COPY %dst <-- This value to be pruned.
1761 // %dst = COPY %src <-- This value is a copy of a pruned value.
1763 bool JoinVals::isPrunedValue(unsigned ValNo, JoinVals &Other) {
1764 Val &V = Vals[ValNo];
1765 if (V.Pruned || V.PrunedComputed)
1768 if (V.Resolution != CR_Erase && V.Resolution != CR_Merge)
1771 // Follow copies up the dominator tree and check if any intermediate value
1773 V.PrunedComputed = true;
1774 V.Pruned = Other.isPrunedValue(V.OtherVNI->id, *this);
1778 void JoinVals::pruneValues(JoinVals &Other,
1779 SmallVectorImpl<SlotIndex> &EndPoints) {
1780 for (unsigned i = 0, e = LI.getNumValNums(); i != e; ++i) {
1781 SlotIndex Def = LI.getValNumInfo(i)->def;
1782 switch (Vals[i].Resolution) {
1786 // This value takes precedence over the value in Other.LI.
1787 LIS->pruneValue(&Other.LI, Def, &EndPoints);
1788 // Check if we're replacing an IMPLICIT_DEF value. The IMPLICIT_DEF
1789 // instructions are only inserted to provide a live-out value for PHI
1790 // predecessors, so the instruction should simply go away once its value
1791 // has been replaced.
1792 Val &OtherV = Other.Vals[Vals[i].OtherVNI->id];
1793 bool EraseImpDef = OtherV.IsImplicitDef && OtherV.Resolution == CR_Keep;
1794 if (!Def.isBlock()) {
1795 // Remove <def,read-undef> flags. This def is now a partial redef.
1796 // Also remove <def,dead> flags since the joined live range will
1797 // continue past this instruction.
1798 for (MIOperands MO(Indexes->getInstructionFromIndex(Def));
1800 if (MO->isReg() && MO->isDef() && MO->getReg() == LI.reg) {
1801 MO->setIsUndef(EraseImpDef);
1802 MO->setIsDead(false);
1804 // This value will reach instructions below, but we need to make sure
1805 // the live range also reaches the instruction at Def.
1807 EndPoints.push_back(Def);
1809 DEBUG(dbgs() << "\t\tpruned " << PrintReg(Other.LI.reg) << " at " << Def
1810 << ": " << Other.LI << '\n');
1815 if (isPrunedValue(i, Other)) {
1816 // This value is ultimately a copy of a pruned value in LI or Other.LI.
1817 // We can no longer trust the value mapping computed by
1818 // computeAssignment(), the value that was originally copied could have
1820 LIS->pruneValue(&LI, Def, &EndPoints);
1821 DEBUG(dbgs() << "\t\tpruned all of " << PrintReg(LI.reg) << " at "
1822 << Def << ": " << LI << '\n');
1827 llvm_unreachable("Unresolved conflicts");
1832 void JoinVals::eraseInstrs(SmallPtrSet<MachineInstr*, 8> &ErasedInstrs,
1833 SmallVectorImpl<unsigned> &ShrinkRegs) {
1834 for (unsigned i = 0, e = LI.getNumValNums(); i != e; ++i) {
1835 // Get the def location before markUnused() below invalidates it.
1836 SlotIndex Def = LI.getValNumInfo(i)->def;
1837 switch (Vals[i].Resolution) {
1839 // If an IMPLICIT_DEF value is pruned, it doesn't serve a purpose any
1840 // longer. The IMPLICIT_DEF instructions are only inserted by
1841 // PHIElimination to guarantee that all PHI predecessors have a value.
1842 if (!Vals[i].IsImplicitDef || !Vals[i].Pruned)
1844 // Remove value number i from LI. Note that this VNInfo is still present
1845 // in NewVNInfo, so it will appear as an unused value number in the final
1847 LI.getValNumInfo(i)->markUnused();
1848 LI.removeValNo(LI.getValNumInfo(i));
1849 DEBUG(dbgs() << "\t\tremoved " << i << '@' << Def << ": " << LI << '\n');
1853 MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
1854 assert(MI && "No instruction to erase");
1856 unsigned Reg = MI->getOperand(1).getReg();
1857 if (TargetRegisterInfo::isVirtualRegister(Reg) &&
1858 Reg != CP.getSrcReg() && Reg != CP.getDstReg())
1859 ShrinkRegs.push_back(Reg);
1861 ErasedInstrs.insert(MI);
1862 DEBUG(dbgs() << "\t\terased:\t" << Def << '\t' << *MI);
1863 LIS->RemoveMachineInstrFromMaps(MI);
1864 MI->eraseFromParent();
1873 bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
1874 SmallVector<VNInfo*, 16> NewVNInfo;
1875 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1876 LiveInterval &LHS = LIS->getInterval(CP.getDstReg());
1877 JoinVals RHSVals(RHS, CP.getSrcIdx(), NewVNInfo, CP, LIS, TRI);
1878 JoinVals LHSVals(LHS, CP.getDstIdx(), NewVNInfo, CP, LIS, TRI);
1880 DEBUG(dbgs() << "\t\tRHS = " << PrintReg(CP.getSrcReg()) << ' ' << RHS
1881 << "\n\t\tLHS = " << PrintReg(CP.getDstReg()) << ' ' << LHS
1884 // First compute NewVNInfo and the simple value mappings.
1885 // Detect impossible conflicts early.
1886 if (!LHSVals.mapValues(RHSVals) || !RHSVals.mapValues(LHSVals))
1889 // Some conflicts can only be resolved after all values have been mapped.
1890 if (!LHSVals.resolveConflicts(RHSVals) || !RHSVals.resolveConflicts(LHSVals))
1893 // All clear, the live ranges can be merged.
1895 // The merging algorithm in LiveInterval::join() can't handle conflicting
1896 // value mappings, so we need to remove any live ranges that overlap a
1897 // CR_Replace resolution. Collect a set of end points that can be used to
1898 // restore the live range after joining.
1899 SmallVector<SlotIndex, 8> EndPoints;
1900 LHSVals.pruneValues(RHSVals, EndPoints);
1901 RHSVals.pruneValues(LHSVals, EndPoints);
1903 // Erase COPY and IMPLICIT_DEF instructions. This may cause some external
1904 // registers to require trimming.
1905 SmallVector<unsigned, 8> ShrinkRegs;
1906 LHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs);
1907 RHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs);
1908 while (!ShrinkRegs.empty())
1909 LIS->shrinkToUses(&LIS->getInterval(ShrinkRegs.pop_back_val()));
1911 // Join RHS into LHS.
1912 LHS.join(RHS, LHSVals.getAssignments(), RHSVals.getAssignments(), NewVNInfo,
1915 // Kill flags are going to be wrong if the live ranges were overlapping.
1916 // Eventually, we should simply clear all kill flags when computing live
1917 // ranges. They are reinserted after register allocation.
1918 MRI->clearKillFlags(LHS.reg);
1919 MRI->clearKillFlags(RHS.reg);
1921 if (EndPoints.empty())
1924 // Recompute the parts of the live range we had to remove because of
1925 // CR_Replace conflicts.
1926 DEBUG(dbgs() << "\t\trestoring liveness to " << EndPoints.size()
1927 << " points: " << LHS << '\n');
1928 LIS->extendToIndices(&LHS, EndPoints);
1932 /// joinIntervals - Attempt to join these two intervals. On failure, this
1934 bool RegisterCoalescer::joinIntervals(CoalescerPair &CP) {
1935 return CP.isPhys() ? joinReservedPhysReg(CP) : joinVirtRegs(CP);
1939 // Information concerning MBB coalescing priority.
1940 struct MBBPriorityInfo {
1941 MachineBasicBlock *MBB;
1945 MBBPriorityInfo(MachineBasicBlock *mbb, unsigned depth, bool issplit)
1946 : MBB(mbb), Depth(depth), IsSplit(issplit) {}
1950 // C-style comparator that sorts first based on the loop depth of the basic
1951 // block (the unsigned), and then on the MBB number.
1953 // EnableGlobalCopies assumes that the primary sort key is loop depth.
1954 static int compareMBBPriority(const void *L, const void *R) {
1955 const MBBPriorityInfo *LHS = static_cast<const MBBPriorityInfo*>(L);
1956 const MBBPriorityInfo *RHS = static_cast<const MBBPriorityInfo*>(R);
1957 // Deeper loops first
1958 if (LHS->Depth != RHS->Depth)
1959 return LHS->Depth > RHS->Depth ? -1 : 1;
1961 // Try to unsplit critical edges next.
1962 if (LHS->IsSplit != RHS->IsSplit)
1963 return LHS->IsSplit ? -1 : 1;
1965 // Prefer blocks that are more connected in the CFG. This takes care of
1966 // the most difficult copies first while intervals are short.
1967 unsigned cl = LHS->MBB->pred_size() + LHS->MBB->succ_size();
1968 unsigned cr = RHS->MBB->pred_size() + RHS->MBB->succ_size();
1970 return cl > cr ? -1 : 1;
1972 // As a last resort, sort by block number.
1973 return LHS->MBB->getNumber() < RHS->MBB->getNumber() ? -1 : 1;
1976 /// \returns true if the given copy uses or defines a local live range.
1977 static bool isLocalCopy(MachineInstr *Copy, const LiveIntervals *LIS) {
1978 if (!Copy->isCopy())
1981 unsigned SrcReg = Copy->getOperand(1).getReg();
1982 unsigned DstReg = Copy->getOperand(0).getReg();
1983 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)
1984 || TargetRegisterInfo::isPhysicalRegister(DstReg))
1987 return LIS->intervalIsInOneMBB(LIS->getInterval(SrcReg))
1988 || LIS->intervalIsInOneMBB(LIS->getInterval(DstReg));
1991 // Try joining WorkList copies starting from index From.
1992 // Null out any successful joins.
1993 bool RegisterCoalescer::
1994 copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList) {
1995 bool Progress = false;
1996 for (unsigned i = 0, e = CurrList.size(); i != e; ++i) {
1999 // Skip instruction pointers that have already been erased, for example by
2000 // dead code elimination.
2001 if (ErasedInstrs.erase(CurrList[i])) {
2006 bool Success = joinCopy(CurrList[i], Again);
2007 Progress |= Success;
2008 if (Success || !Again)
2015 RegisterCoalescer::copyCoalesceInMBB(MachineBasicBlock *MBB) {
2016 DEBUG(dbgs() << MBB->getName() << ":\n");
2018 // Collect all copy-like instructions in MBB. Don't start coalescing anything
2019 // yet, it might invalidate the iterator.
2020 const unsigned PrevSize = WorkList.size();
2021 if (JoinGlobalCopies) {
2022 // Coalesce copies bottom-up to coalesce local defs before local uses. They
2023 // are not inherently easier to resolve, but slightly preferable until we
2024 // have local live range splitting. In particular this is required by
2025 // cmp+jmp macro fusion.
2026 for (MachineBasicBlock::reverse_iterator
2027 MII = MBB->rbegin(), E = MBB->rend(); MII != E; ++MII) {
2028 if (!MII->isCopyLike())
2030 if (isLocalCopy(&(*MII), LIS))
2031 LocalWorkList.push_back(&(*MII));
2033 WorkList.push_back(&(*MII));
2037 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
2039 if (MII->isCopyLike())
2040 WorkList.push_back(MII);
2042 // Try coalescing the collected copies immediately, and remove the nulls.
2043 // This prevents the WorkList from getting too large since most copies are
2044 // joinable on the first attempt.
2045 MutableArrayRef<MachineInstr*>
2046 CurrList(WorkList.begin() + PrevSize, WorkList.end());
2047 if (copyCoalesceWorkList(CurrList))
2048 WorkList.erase(std::remove(WorkList.begin() + PrevSize, WorkList.end(),
2049 (MachineInstr*)0), WorkList.end());
2052 void RegisterCoalescer::coalesceLocals() {
2053 copyCoalesceWorkList(LocalWorkList);
2054 for (unsigned j = 0, je = LocalWorkList.size(); j != je; ++j) {
2055 if (LocalWorkList[j])
2056 WorkList.push_back(LocalWorkList[j]);
2058 LocalWorkList.clear();
2061 void RegisterCoalescer::joinAllIntervals() {
2062 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
2063 assert(WorkList.empty() && LocalWorkList.empty() && "Old data still around.");
2065 std::vector<MBBPriorityInfo> MBBs;
2066 MBBs.reserve(MF->size());
2067 for (MachineFunction::iterator I = MF->begin(), E = MF->end();I != E;++I){
2068 MachineBasicBlock *MBB = I;
2069 MBBs.push_back(MBBPriorityInfo(MBB, Loops->getLoopDepth(MBB),
2070 JoinSplitEdges && isSplitEdge(MBB)));
2072 array_pod_sort(MBBs.begin(), MBBs.end(), compareMBBPriority);
2074 // Coalesce intervals in MBB priority order.
2075 unsigned CurrDepth = UINT_MAX;
2076 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
2077 // Try coalescing the collected local copies for deeper loops.
2078 if (JoinGlobalCopies && MBBs[i].Depth < CurrDepth) {
2080 CurrDepth = MBBs[i].Depth;
2082 copyCoalesceInMBB(MBBs[i].MBB);
2086 // Joining intervals can allow other intervals to be joined. Iteratively join
2087 // until we make no progress.
2088 while (copyCoalesceWorkList(WorkList))
2092 void RegisterCoalescer::releaseMemory() {
2093 ErasedInstrs.clear();
2096 InflateRegs.clear();
2099 bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
2101 MRI = &fn.getRegInfo();
2102 TM = &fn.getTarget();
2103 TRI = TM->getRegisterInfo();
2104 TII = TM->getInstrInfo();
2105 LIS = &getAnalysis<LiveIntervals>();
2106 LDV = &getAnalysis<LiveDebugVariables>();
2107 AA = &getAnalysis<AliasAnalysis>();
2108 Loops = &getAnalysis<MachineLoopInfo>();
2110 const TargetSubtargetInfo &ST = TM->getSubtarget<TargetSubtargetInfo>();
2111 if (EnableGlobalCopies == cl::BOU_UNSET)
2112 JoinGlobalCopies = ST.enableMachineScheduler();
2114 JoinGlobalCopies = (EnableGlobalCopies == cl::BOU_TRUE);
2116 // The MachineScheduler does not currently require JoinSplitEdges. This will
2117 // either be enabled unconditionally or replaced by a more general live range
2118 // splitting optimization.
2119 JoinSplitEdges = EnableJoinSplits;
2121 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
2122 << "********** Function: " << MF->getName() << '\n');
2124 if (VerifyCoalescing)
2125 MF->verify(this, "Before register coalescing");
2127 RegClassInfo.runOnMachineFunction(fn);
2129 // Join (coalesce) intervals if requested.
2133 // After deleting a lot of copies, register classes may be less constrained.
2134 // Removing sub-register operands may allow GR32_ABCD -> GR32 and DPR_VFP2 ->
2136 array_pod_sort(InflateRegs.begin(), InflateRegs.end());
2137 InflateRegs.erase(std::unique(InflateRegs.begin(), InflateRegs.end()),
2139 DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size() << " regs.\n");
2140 for (unsigned i = 0, e = InflateRegs.size(); i != e; ++i) {
2141 unsigned Reg = InflateRegs[i];
2142 if (MRI->reg_nodbg_empty(Reg))
2144 if (MRI->recomputeRegClass(Reg, *TM)) {
2145 DEBUG(dbgs() << PrintReg(Reg) << " inflated to "
2146 << MRI->getRegClass(Reg)->getName() << '\n');
2153 if (VerifyCoalescing)
2154 MF->verify(this, "After register coalescing");
2158 /// print - Implement the dump method.
2159 void RegisterCoalescer::print(raw_ostream &O, const Module* m) const {