1 //===- RegisterCoalescer.cpp - Generic Register Coalescing Interface -------==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the generic RegisterCoalescer interface which
11 // is used as the common interface used by all clients and
12 // implementations of register coalescing.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "regalloc"
17 #include "RegisterCoalescer.h"
18 #include "LiveDebugVariables.h"
19 #include "llvm/ADT/OwningPtr.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallSet.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
25 #include "llvm/CodeGen/LiveRangeEdit.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstr.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/CodeGen/RegisterClassInfo.h"
32 #include "llvm/CodeGen/VirtRegMap.h"
33 #include "llvm/Pass.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/Target/TargetRegisterInfo.h"
42 #include "llvm/Target/TargetSubtargetInfo.h"
43 #include "llvm/Value.h"
48 STATISTIC(numJoins , "Number of interval joins performed");
49 STATISTIC(numCrossRCs , "Number of cross class joins performed");
50 STATISTIC(numCommutes , "Number of instruction commuting performed");
51 STATISTIC(numExtends , "Number of copies extended");
52 STATISTIC(NumReMats , "Number of instructions re-materialized");
53 STATISTIC(NumInflated , "Number of register classes inflated");
54 STATISTIC(NumLaneConflicts, "Number of dead lane conflicts tested");
55 STATISTIC(NumLaneResolves, "Number of dead lane conflicts resolved");
58 EnableJoining("join-liveintervals",
59 cl::desc("Coalesce copies (default=true)"),
62 // Temporary flag to test critical edge unsplitting.
64 EnableJoinSplits("join-splitedges",
65 cl::desc("Coalesce copies on split edges (default=subtarget)"), cl::Hidden);
67 // Temporary flag to test global copy optimization.
68 static cl::opt<cl::boolOrDefault>
69 EnableGlobalCopies("join-globalcopies",
70 cl::desc("Coalesce copies that span blocks (default=subtarget)"),
71 cl::init(cl::BOU_UNSET), cl::Hidden);
74 VerifyCoalescing("verify-coalescing",
75 cl::desc("Verify machine instrs before and after register coalescing"),
79 class RegisterCoalescer : public MachineFunctionPass,
80 private LiveRangeEdit::Delegate {
82 MachineRegisterInfo* MRI;
83 const TargetMachine* TM;
84 const TargetRegisterInfo* TRI;
85 const TargetInstrInfo* TII;
87 LiveDebugVariables *LDV;
88 const MachineLoopInfo* Loops;
90 RegisterClassInfo RegClassInfo;
92 /// \brief True if the coalescer should aggressively coalesce global copies
93 /// in favor of keeping local copies.
94 bool JoinGlobalCopies;
96 /// \brief True if the coalescer should aggressively coalesce fall-thru
97 /// blocks exclusively containing copies.
100 /// WorkList - Copy instructions yet to be coalesced.
101 SmallVector<MachineInstr*, 8> WorkList;
102 SmallVector<MachineInstr*, 8> LocalWorkList;
104 /// ErasedInstrs - Set of instruction pointers that have been erased, and
105 /// that may be present in WorkList.
106 SmallPtrSet<MachineInstr*, 8> ErasedInstrs;
108 /// Dead instructions that are about to be deleted.
109 SmallVector<MachineInstr*, 8> DeadDefs;
111 /// Virtual registers to be considered for register class inflation.
112 SmallVector<unsigned, 8> InflateRegs;
114 /// Recursively eliminate dead defs in DeadDefs.
115 void eliminateDeadDefs();
117 /// LiveRangeEdit callback.
118 void LRE_WillEraseInstruction(MachineInstr *MI);
120 /// coalesceLocals - coalesce the LocalWorkList.
121 void coalesceLocals();
123 /// joinAllIntervals - join compatible live intervals
124 void joinAllIntervals();
126 /// copyCoalesceInMBB - Coalesce copies in the specified MBB, putting
127 /// copies that cannot yet be coalesced into WorkList.
128 void copyCoalesceInMBB(MachineBasicBlock *MBB);
130 /// copyCoalesceWorkList - Try to coalesce all copies in CurrList. Return
131 /// true if any progress was made.
132 bool copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList);
134 /// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
135 /// which are the src/dst of the copy instruction CopyMI. This returns
136 /// true if the copy was successfully coalesced away. If it is not
137 /// currently possible to coalesce this interval, but it may be possible if
138 /// other things get coalesced, then it returns true by reference in
140 bool joinCopy(MachineInstr *TheCopy, bool &Again);
142 /// joinIntervals - Attempt to join these two intervals. On failure, this
143 /// returns false. The output "SrcInt" will not have been modified, so we
144 /// can use this information below to update aliases.
145 bool joinIntervals(CoalescerPair &CP);
147 /// Attempt joining two virtual registers. Return true on success.
148 bool joinVirtRegs(CoalescerPair &CP);
150 /// Attempt joining with a reserved physreg.
151 bool joinReservedPhysReg(CoalescerPair &CP);
153 /// adjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
154 /// the source value number is defined by a copy from the destination reg
155 /// see if we can merge these two destination reg valno# into a single
156 /// value number, eliminating a copy.
157 bool adjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
159 /// hasOtherReachingDefs - Return true if there are definitions of IntB
160 /// other than BValNo val# that can reach uses of AValno val# of IntA.
161 bool hasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
162 VNInfo *AValNo, VNInfo *BValNo);
164 /// removeCopyByCommutingDef - We found a non-trivially-coalescable copy.
165 /// If the source value number is defined by a commutable instruction and
166 /// its other operand is coalesced to the copy dest register, see if we
167 /// can transform the copy into a noop by commuting the definition.
168 bool removeCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
170 /// reMaterializeTrivialDef - If the source of a copy is defined by a
171 /// trivial computation, replace the copy by rematerialize the definition.
172 bool reMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg,
173 MachineInstr *CopyMI);
175 /// canJoinPhys - Return true if a physreg copy should be joined.
176 bool canJoinPhys(const CoalescerPair &CP);
178 /// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
179 /// update the subregister number if it is not zero. If DstReg is a
180 /// physical register and the existing subregister number of the def / use
181 /// being updated is not zero, make sure to set it to the correct physical
183 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
185 /// eliminateUndefCopy - Handle copies of undef values.
186 bool eliminateUndefCopy(MachineInstr *CopyMI, const CoalescerPair &CP);
189 static char ID; // Class identification, replacement for typeinfo
190 RegisterCoalescer() : MachineFunctionPass(ID) {
191 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
194 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
196 virtual void releaseMemory();
198 /// runOnMachineFunction - pass entry point
199 virtual bool runOnMachineFunction(MachineFunction&);
201 /// print - Implement the dump method.
202 virtual void print(raw_ostream &O, const Module* = 0) const;
204 } /// end anonymous namespace
206 char &llvm::RegisterCoalescerID = RegisterCoalescer::ID;
208 INITIALIZE_PASS_BEGIN(RegisterCoalescer, "simple-register-coalescing",
209 "Simple Register Coalescing", false, false)
210 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
211 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
212 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
213 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
214 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
215 INITIALIZE_PASS_END(RegisterCoalescer, "simple-register-coalescing",
216 "Simple Register Coalescing", false, false)
218 char RegisterCoalescer::ID = 0;
220 static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI,
221 unsigned &Src, unsigned &Dst,
222 unsigned &SrcSub, unsigned &DstSub) {
224 Dst = MI->getOperand(0).getReg();
225 DstSub = MI->getOperand(0).getSubReg();
226 Src = MI->getOperand(1).getReg();
227 SrcSub = MI->getOperand(1).getSubReg();
228 } else if (MI->isSubregToReg()) {
229 Dst = MI->getOperand(0).getReg();
230 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(),
231 MI->getOperand(3).getImm());
232 Src = MI->getOperand(2).getReg();
233 SrcSub = MI->getOperand(2).getSubReg();
239 // Return true if this block should be vacated by the coalescer to eliminate
240 // branches. The important cases to handle in the coalescer are critical edges
241 // split during phi elimination which contain only copies. Simple blocks that
242 // contain non-branches should also be vacated, but this can be handled by an
243 // earlier pass similar to early if-conversion.
244 static bool isSplitEdge(const MachineBasicBlock *MBB) {
245 if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
248 for (MachineBasicBlock::const_iterator MII = MBB->begin(), E = MBB->end();
250 if (!MII->isCopyLike() && !MII->isUnconditionalBranch())
256 bool CoalescerPair::setRegisters(const MachineInstr *MI) {
260 Flipped = CrossClass = false;
262 unsigned Src, Dst, SrcSub, DstSub;
263 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
265 Partial = SrcSub || DstSub;
267 // If one register is a physreg, it must be Dst.
268 if (TargetRegisterInfo::isPhysicalRegister(Src)) {
269 if (TargetRegisterInfo::isPhysicalRegister(Dst))
272 std::swap(SrcSub, DstSub);
276 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
278 if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
279 // Eliminate DstSub on a physreg.
281 Dst = TRI.getSubReg(Dst, DstSub);
282 if (!Dst) return false;
286 // Eliminate SrcSub by picking a corresponding Dst superregister.
288 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
289 if (!Dst) return false;
291 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
295 // Both registers are virtual.
296 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
297 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
299 // Both registers have subreg indices.
300 if (SrcSub && DstSub) {
301 // Copies between different sub-registers are never coalescable.
302 if (Src == Dst && SrcSub != DstSub)
305 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
310 // SrcReg will be merged with a sub-register of DstReg.
312 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
314 // DstReg will be merged with a sub-register of SrcReg.
316 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
318 // This is a straight copy without sub-registers.
319 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
322 // The combined constraint may be impossible to satisfy.
326 // Prefer SrcReg to be a sub-register of DstReg.
327 // FIXME: Coalescer should support subregs symmetrically.
328 if (DstIdx && !SrcIdx) {
330 std::swap(SrcIdx, DstIdx);
334 CrossClass = NewRC != DstRC || NewRC != SrcRC;
336 // Check our invariants
337 assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual");
338 assert(!(TargetRegisterInfo::isPhysicalRegister(Dst) && DstSub) &&
339 "Cannot have a physical SubIdx");
345 bool CoalescerPair::flip() {
346 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
348 std::swap(SrcReg, DstReg);
349 std::swap(SrcIdx, DstIdx);
354 bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
357 unsigned Src, Dst, SrcSub, DstSub;
358 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
361 // Find the virtual register that is SrcReg.
364 std::swap(SrcSub, DstSub);
365 } else if (Src != SrcReg) {
369 // Now check that Dst matches DstReg.
370 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
371 if (!TargetRegisterInfo::isPhysicalRegister(Dst))
373 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.");
374 // DstSub could be set for a physreg from INSERT_SUBREG.
376 Dst = TRI.getSubReg(Dst, DstSub);
379 return DstReg == Dst;
380 // This is a partial register copy. Check that the parts match.
381 return TRI.getSubReg(DstReg, SrcSub) == Dst;
383 // DstReg is virtual.
386 // Registers match, do the subregisters line up?
387 return TRI.composeSubRegIndices(SrcIdx, SrcSub) ==
388 TRI.composeSubRegIndices(DstIdx, DstSub);
392 void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const {
393 AU.setPreservesCFG();
394 AU.addRequired<AliasAnalysis>();
395 AU.addRequired<LiveIntervals>();
396 AU.addPreserved<LiveIntervals>();
397 AU.addRequired<LiveDebugVariables>();
398 AU.addPreserved<LiveDebugVariables>();
399 AU.addPreserved<SlotIndexes>();
400 AU.addRequired<MachineLoopInfo>();
401 AU.addPreserved<MachineLoopInfo>();
402 AU.addPreservedID(MachineDominatorsID);
403 MachineFunctionPass::getAnalysisUsage(AU);
406 void RegisterCoalescer::eliminateDeadDefs() {
407 SmallVector<LiveInterval*, 8> NewRegs;
408 LiveRangeEdit(0, NewRegs, *MF, *LIS, 0, this).eliminateDeadDefs(DeadDefs);
411 // Callback from eliminateDeadDefs().
412 void RegisterCoalescer::LRE_WillEraseInstruction(MachineInstr *MI) {
413 // MI may be in WorkList. Make sure we don't visit it.
414 ErasedInstrs.insert(MI);
417 /// adjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
418 /// being the source and IntB being the dest, thus this defines a value number
419 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
420 /// see if we can merge these two pieces of B into a single value number,
421 /// eliminating a copy. For example:
425 /// B1 = A3 <- this copy
427 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
428 /// value number to be replaced with B0 (which simplifies the B liveinterval).
430 /// This returns true if an interval was modified.
432 bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP,
433 MachineInstr *CopyMI) {
434 assert(!CP.isPartial() && "This doesn't work for partial copies.");
435 assert(!CP.isPhys() && "This doesn't work for physreg copies.");
438 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
440 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
441 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
443 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
444 // the example above.
445 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
446 if (BLR == IntB.end()) return false;
447 VNInfo *BValNo = BLR->valno;
449 // Get the location that B is defined at. Two options: either this value has
450 // an unknown definition point or it is defined at CopyIdx. If unknown, we
452 if (BValNo->def != CopyIdx) return false;
454 // AValNo is the value number in A that defines the copy, A3 in the example.
455 SlotIndex CopyUseIdx = CopyIdx.getRegSlot(true);
456 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
457 // The live range might not exist after fun with physreg coalescing.
458 if (ALR == IntA.end()) return false;
459 VNInfo *AValNo = ALR->valno;
461 // If AValNo is defined as a copy from IntB, we can potentially process this.
462 // Get the instruction that defines this value number.
463 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
464 // Don't allow any partial copies, even if isCoalescable() allows them.
465 if (!CP.isCoalescable(ACopyMI) || !ACopyMI->isFullCopy())
468 // Get the LiveRange in IntB that this value number starts with.
469 LiveInterval::iterator ValLR =
470 IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot());
471 if (ValLR == IntB.end())
474 // Make sure that the end of the live range is inside the same block as
476 MachineInstr *ValLREndInst =
477 LIS->getInstructionFromIndex(ValLR->end.getPrevSlot());
478 if (!ValLREndInst || ValLREndInst->getParent() != CopyMI->getParent())
481 // Okay, we now know that ValLR ends in the same block that the CopyMI
482 // live-range starts. If there are no intervening live ranges between them in
483 // IntB, we can merge them.
484 if (ValLR+1 != BLR) return false;
486 DEBUG(dbgs() << "Extending: " << PrintReg(IntB.reg, TRI));
488 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
489 // We are about to delete CopyMI, so need to remove it as the 'instruction
490 // that defines this value #'. Update the valnum with the new defining
492 BValNo->def = FillerStart;
494 // Okay, we can merge them. We need to insert a new liverange:
495 // [ValLR.end, BLR.begin) of either value number, then we merge the
496 // two value numbers.
497 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
499 // Okay, merge "B1" into the same value number as "B0".
500 if (BValNo != ValLR->valno)
501 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
502 DEBUG(dbgs() << " result = " << IntB << '\n');
504 // If the source instruction was killing the source register before the
505 // merge, unset the isKill marker given the live range has been extended.
506 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
508 ValLREndInst->getOperand(UIdx).setIsKill(false);
511 // Rewrite the copy. If the copy instruction was killing the destination
512 // register before the merge, find the last use and trim the live range. That
513 // will also add the isKill marker.
514 CopyMI->substituteRegister(IntA.reg, IntB.reg, 0, *TRI);
515 if (ALR->end == CopyIdx)
516 LIS->shrinkToUses(&IntA);
522 /// hasOtherReachingDefs - Return true if there are definitions of IntB
523 /// other than BValNo val# that can reach uses of AValno val# of IntA.
524 bool RegisterCoalescer::hasOtherReachingDefs(LiveInterval &IntA,
528 // If AValNo has PHI kills, conservatively assume that IntB defs can reach
530 if (LIS->hasPHIKill(IntA, AValNo))
533 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
535 if (AI->valno != AValNo) continue;
536 LiveInterval::Ranges::iterator BI =
537 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
538 if (BI != IntB.ranges.begin())
540 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
541 if (BI->valno == BValNo)
543 if (BI->start <= AI->start && BI->end > AI->start)
545 if (BI->start > AI->start && BI->start < AI->end)
552 /// removeCopyByCommutingDef - We found a non-trivially-coalescable copy with
553 /// IntA being the source and IntB being the dest, thus this defines a value
554 /// number in IntB. If the source value number (in IntA) is defined by a
555 /// commutable instruction and its other operand is coalesced to the copy dest
556 /// register, see if we can transform the copy into a noop by commuting the
557 /// definition. For example,
559 /// A3 = op A2 B0<kill>
561 /// B1 = A3 <- this copy
563 /// = op A3 <- more uses
567 /// B2 = op B0 A2<kill>
569 /// B1 = B2 <- now an identify copy
571 /// = op B2 <- more uses
573 /// This returns true if an interval was modified.
575 bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
576 MachineInstr *CopyMI) {
577 assert (!CP.isPhys());
579 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
582 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
584 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
586 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
587 // the example above.
588 VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx);
589 if (!BValNo || BValNo->def != CopyIdx)
592 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
594 // AValNo is the value number in A that defines the copy, A3 in the example.
595 VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getRegSlot(true));
596 assert(AValNo && "COPY source not live");
597 if (AValNo->isPHIDef() || AValNo->isUnused())
599 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
602 if (!DefMI->isCommutable())
604 // If DefMI is a two-address instruction then commuting it will change the
605 // destination register.
606 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
607 assert(DefIdx != -1);
609 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
611 unsigned Op1, Op2, NewDstIdx;
612 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
616 else if (Op2 == UseOpIdx)
621 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
622 unsigned NewReg = NewDstMO.getReg();
623 if (NewReg != IntB.reg || !LiveRangeQuery(IntB, AValNo->def).isKill())
626 // Make sure there are no other definitions of IntB that would reach the
627 // uses which the new definition can reach.
628 if (hasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
631 // If some of the uses of IntA.reg is already coalesced away, return false.
632 // It's not possible to determine whether it's safe to perform the coalescing.
633 for (MachineRegisterInfo::use_nodbg_iterator UI =
634 MRI->use_nodbg_begin(IntA.reg),
635 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
636 MachineInstr *UseMI = &*UI;
637 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
638 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
639 if (ULR == IntA.end() || ULR->valno != AValNo)
641 // If this use is tied to a def, we can't rewrite the register.
642 if (UseMI->isRegTiedToDefOperand(UI.getOperandNo()))
646 DEBUG(dbgs() << "\tremoveCopyByCommutingDef: " << AValNo->def << '\t'
649 // At this point we have decided that it is legal to do this
650 // transformation. Start by commuting the instruction.
651 MachineBasicBlock *MBB = DefMI->getParent();
652 MachineInstr *NewMI = TII->commuteInstruction(DefMI);
655 if (TargetRegisterInfo::isVirtualRegister(IntA.reg) &&
656 TargetRegisterInfo::isVirtualRegister(IntB.reg) &&
657 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
659 if (NewMI != DefMI) {
660 LIS->ReplaceMachineInstrInMaps(DefMI, NewMI);
661 MachineBasicBlock::iterator Pos = DefMI;
662 MBB->insert(Pos, NewMI);
665 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
666 NewMI->getOperand(OpIdx).setIsKill();
668 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
677 // Update uses of IntA of the specific Val# with IntB.
678 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg),
679 UE = MRI->use_end(); UI != UE;) {
680 MachineOperand &UseMO = UI.getOperand();
681 MachineInstr *UseMI = &*UI;
683 if (UseMI->isDebugValue()) {
684 // FIXME These don't have an instruction index. Not clear we have enough
685 // info to decide whether to do this replacement or not. For now do it.
686 UseMO.setReg(NewReg);
689 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
690 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
691 if (ULR == IntA.end() || ULR->valno != AValNo)
693 // Kill flags are no longer accurate. They are recomputed after RA.
694 UseMO.setIsKill(false);
695 if (TargetRegisterInfo::isPhysicalRegister(NewReg))
696 UseMO.substPhysReg(NewReg, *TRI);
698 UseMO.setReg(NewReg);
701 if (!UseMI->isCopy())
703 if (UseMI->getOperand(0).getReg() != IntB.reg ||
704 UseMI->getOperand(0).getSubReg())
707 // This copy will become a noop. If it's defining a new val#, merge it into
709 SlotIndex DefIdx = UseIdx.getRegSlot();
710 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
713 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
714 assert(DVNI->def == DefIdx);
715 BValNo = IntB.MergeValueNumberInto(BValNo, DVNI);
716 ErasedInstrs.insert(UseMI);
717 LIS->RemoveMachineInstrFromMaps(UseMI);
718 UseMI->eraseFromParent();
721 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
723 VNInfo *ValNo = BValNo;
724 ValNo->def = AValNo->def;
725 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
727 if (AI->valno != AValNo) continue;
728 IntB.addRange(LiveRange(AI->start, AI->end, ValNo));
730 DEBUG(dbgs() << "\t\textended: " << IntB << '\n');
732 IntA.removeValNo(AValNo);
733 DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n');
738 /// reMaterializeTrivialDef - If the source of a copy is defined by a trivial
739 /// computation, replace the copy by rematerialize the definition.
740 bool RegisterCoalescer::reMaterializeTrivialDef(LiveInterval &SrcInt,
742 MachineInstr *CopyMI) {
743 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(true);
744 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
745 assert(SrcLR != SrcInt.end() && "Live range not found!");
746 VNInfo *ValNo = SrcLR->valno;
747 if (ValNo->isPHIDef() || ValNo->isUnused())
749 MachineInstr *DefMI = LIS->getInstructionFromIndex(ValNo->def);
752 assert(DefMI && "Defining instruction disappeared");
753 if (!DefMI->isAsCheapAsAMove())
755 if (!TII->isTriviallyReMaterializable(DefMI, AA))
757 bool SawStore = false;
758 if (!DefMI->isSafeToMove(TII, AA, SawStore))
760 const MCInstrDesc &MCID = DefMI->getDesc();
761 if (MCID.getNumDefs() != 1)
763 if (!DefMI->isImplicitDef()) {
764 // Make sure the copy destination register class fits the instruction
765 // definition register class. The mismatch can happen as a result of earlier
766 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
767 const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI, *MF);
768 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
769 if (MRI->getRegClass(DstReg) != RC)
771 } else if (!RC->contains(DstReg))
775 MachineBasicBlock *MBB = CopyMI->getParent();
776 MachineBasicBlock::iterator MII =
777 llvm::next(MachineBasicBlock::iterator(CopyMI));
778 TII->reMaterialize(*MBB, MII, DstReg, 0, DefMI, *TRI);
779 MachineInstr *NewMI = prior(MII);
781 // NewMI may have dead implicit defs (E.g. EFLAGS for MOV<bits>r0 on X86).
782 // We need to remember these so we can add intervals once we insert
783 // NewMI into SlotIndexes.
784 SmallVector<unsigned, 4> NewMIImplDefs;
785 for (unsigned i = NewMI->getDesc().getNumOperands(),
786 e = NewMI->getNumOperands(); i != e; ++i) {
787 MachineOperand &MO = NewMI->getOperand(i);
789 assert(MO.isDef() && MO.isImplicit() && MO.isDead() &&
790 TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
791 NewMIImplDefs.push_back(MO.getReg());
795 // CopyMI may have implicit operands, transfer them over to the newly
796 // rematerialized instruction. And update implicit def interval valnos.
797 for (unsigned i = CopyMI->getDesc().getNumOperands(),
798 e = CopyMI->getNumOperands(); i != e; ++i) {
799 MachineOperand &MO = CopyMI->getOperand(i);
801 assert(MO.isImplicit() && "No explicit operands after implict operands.");
802 // Discard VReg implicit defs.
803 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
804 NewMI->addOperand(MO);
809 LIS->ReplaceMachineInstrInMaps(CopyMI, NewMI);
811 SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
812 for (unsigned i = 0, e = NewMIImplDefs.size(); i != e; ++i) {
813 unsigned Reg = NewMIImplDefs[i];
814 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
815 if (LiveInterval *LI = LIS->getCachedRegUnit(*Units))
816 LI->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
819 CopyMI->eraseFromParent();
820 ErasedInstrs.insert(CopyMI);
821 DEBUG(dbgs() << "Remat: " << *NewMI);
824 // The source interval can become smaller because we removed a use.
825 LIS->shrinkToUses(&SrcInt, &DeadDefs);
826 if (!DeadDefs.empty())
832 /// eliminateUndefCopy - ProcessImpicitDefs may leave some copies of <undef>
833 /// values, it only removes local variables. When we have a copy like:
835 /// %vreg1 = COPY %vreg2<undef>
837 /// We delete the copy and remove the corresponding value number from %vreg1.
838 /// Any uses of that value number are marked as <undef>.
839 bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI,
840 const CoalescerPair &CP) {
841 SlotIndex Idx = LIS->getInstructionIndex(CopyMI);
842 LiveInterval *SrcInt = &LIS->getInterval(CP.getSrcReg());
843 if (SrcInt->liveAt(Idx))
845 LiveInterval *DstInt = &LIS->getInterval(CP.getDstReg());
846 if (DstInt->liveAt(Idx))
849 // No intervals are live-in to CopyMI - it is undef.
854 VNInfo *DeadVNI = DstInt->getVNInfoAt(Idx.getRegSlot());
855 assert(DeadVNI && "No value defined in DstInt");
856 DstInt->removeValNo(DeadVNI);
858 // Find new undef uses.
859 for (MachineRegisterInfo::reg_nodbg_iterator
860 I = MRI->reg_nodbg_begin(DstInt->reg), E = MRI->reg_nodbg_end();
862 MachineOperand &MO = I.getOperand();
863 if (MO.isDef() || MO.isUndef())
865 MachineInstr *MI = MO.getParent();
866 SlotIndex Idx = LIS->getInstructionIndex(MI);
867 if (DstInt->liveAt(Idx))
870 DEBUG(dbgs() << "\tnew undef: " << Idx << '\t' << *MI);
875 /// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
876 /// update the subregister number if it is not zero. If DstReg is a
877 /// physical register and the existing subregister number of the def / use
878 /// being updated is not zero, make sure to set it to the correct physical
880 void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg,
883 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
884 LiveInterval *DstInt = DstIsPhys ? 0 : &LIS->getInterval(DstReg);
886 // Update LiveDebugVariables.
887 LDV->renameRegister(SrcReg, DstReg, SubIdx);
889 SmallPtrSet<MachineInstr*, 8> Visited;
890 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg);
891 MachineInstr *UseMI = I.skipInstruction();) {
892 // Each instruction can only be rewritten once because sub-register
893 // composition is not always idempotent. When SrcReg != DstReg, rewriting
894 // the UseMI operands removes them from the SrcReg use-def chain, but when
895 // SrcReg is DstReg we could encounter UseMI twice if it has multiple
896 // operands mentioning the virtual register.
897 if (SrcReg == DstReg && !Visited.insert(UseMI))
900 SmallVector<unsigned,8> Ops;
902 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
904 // If SrcReg wasn't read, it may still be the case that DstReg is live-in
905 // because SrcReg is a sub-register.
906 if (DstInt && !Reads && SubIdx)
907 Reads = DstInt->liveAt(LIS->getInstructionIndex(UseMI));
909 // Replace SrcReg with DstReg in all UseMI operands.
910 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
911 MachineOperand &MO = UseMI->getOperand(Ops[i]);
913 // Adjust <undef> flags in case of sub-register joins. We don't want to
914 // turn a full def into a read-modify-write sub-register def and vice
916 if (SubIdx && MO.isDef())
917 MO.setIsUndef(!Reads);
920 MO.substPhysReg(DstReg, *TRI);
922 MO.substVirtReg(DstReg, SubIdx, *TRI);
926 dbgs() << "\t\tupdated: ";
927 if (!UseMI->isDebugValue())
928 dbgs() << LIS->getInstructionIndex(UseMI) << "\t";
934 /// canJoinPhys - Return true if a copy involving a physreg should be joined.
935 bool RegisterCoalescer::canJoinPhys(const CoalescerPair &CP) {
936 /// Always join simple intervals that are defined by a single copy from a
937 /// reserved register. This doesn't increase register pressure, so it is
938 /// always beneficial.
939 if (!MRI->isReserved(CP.getDstReg())) {
940 DEBUG(dbgs() << "\tCan only merge into reserved registers.\n");
944 LiveInterval &JoinVInt = LIS->getInterval(CP.getSrcReg());
945 if (CP.isFlipped() && JoinVInt.containsOneValue())
948 DEBUG(dbgs() << "\tCannot join defs into reserved register.\n");
952 /// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
953 /// which are the src/dst of the copy instruction CopyMI. This returns true
954 /// if the copy was successfully coalesced away. If it is not currently
955 /// possible to coalesce this interval, but it may be possible if other
956 /// things get coalesced, then it returns true by reference in 'Again'.
957 bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
960 DEBUG(dbgs() << LIS->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
962 CoalescerPair CP(*TRI);
963 if (!CP.setRegisters(CopyMI)) {
964 DEBUG(dbgs() << "\tNot coalescable.\n");
968 // Dead code elimination. This really should be handled by MachineDCE, but
969 // sometimes dead copies slip through, and we can't generate invalid live
971 if (!CP.isPhys() && CopyMI->allDefsAreDead()) {
972 DEBUG(dbgs() << "\tCopy is dead.\n");
973 DeadDefs.push_back(CopyMI);
979 if (!CP.isPhys() && eliminateUndefCopy(CopyMI, CP)) {
980 DEBUG(dbgs() << "\tEliminated copy of <undef> value.\n");
981 LIS->RemoveMachineInstrFromMaps(CopyMI);
982 CopyMI->eraseFromParent();
983 return false; // Not coalescable.
986 // Coalesced copies are normally removed immediately, but transformations
987 // like removeCopyByCommutingDef() can inadvertently create identity copies.
988 // When that happens, just join the values and remove the copy.
989 if (CP.getSrcReg() == CP.getDstReg()) {
990 LiveInterval &LI = LIS->getInterval(CP.getSrcReg());
991 DEBUG(dbgs() << "\tCopy already coalesced: " << LI << '\n');
992 LiveRangeQuery LRQ(LI, LIS->getInstructionIndex(CopyMI));
993 if (VNInfo *DefVNI = LRQ.valueDefined()) {
994 VNInfo *ReadVNI = LRQ.valueIn();
995 assert(ReadVNI && "No value before copy and no <undef> flag.");
996 assert(ReadVNI != DefVNI && "Cannot read and define the same value.");
997 LI.MergeValueNumberInto(DefVNI, ReadVNI);
998 DEBUG(dbgs() << "\tMerged values: " << LI << '\n');
1000 LIS->RemoveMachineInstrFromMaps(CopyMI);
1001 CopyMI->eraseFromParent();
1005 // Enforce policies.
1007 DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI)
1008 << " with " << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx())
1010 if (!canJoinPhys(CP)) {
1011 // Before giving up coalescing, if definition of source is defined by
1012 // trivial computation, try rematerializing it.
1013 if (!CP.isFlipped() &&
1014 reMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()),
1015 CP.getDstReg(), CopyMI))
1021 dbgs() << "\tConsidering merging to " << CP.getNewRC()->getName()
1023 if (CP.getDstIdx() && CP.getSrcIdx())
1024 dbgs() << PrintReg(CP.getDstReg()) << " in "
1025 << TRI->getSubRegIndexName(CP.getDstIdx()) << " and "
1026 << PrintReg(CP.getSrcReg()) << " in "
1027 << TRI->getSubRegIndexName(CP.getSrcIdx()) << '\n';
1029 dbgs() << PrintReg(CP.getSrcReg(), TRI) << " in "
1030 << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n';
1033 // When possible, let DstReg be the larger interval.
1034 if (!CP.isPartial() && LIS->getInterval(CP.getSrcReg()).ranges.size() >
1035 LIS->getInterval(CP.getDstReg()).ranges.size())
1039 // Okay, attempt to join these two intervals. On failure, this returns false.
1040 // Otherwise, if one of the intervals being joined is a physreg, this method
1041 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1042 // been modified, so we can use this information below to update aliases.
1043 if (!joinIntervals(CP)) {
1044 // Coalescing failed.
1046 // If definition of source is defined by trivial computation, try
1047 // rematerializing it.
1048 if (!CP.isFlipped() &&
1049 reMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()),
1050 CP.getDstReg(), CopyMI))
1053 // If we can eliminate the copy without merging the live ranges, do so now.
1054 if (!CP.isPartial() && !CP.isPhys()) {
1055 if (adjustCopiesBackFrom(CP, CopyMI) ||
1056 removeCopyByCommutingDef(CP, CopyMI)) {
1057 LIS->RemoveMachineInstrFromMaps(CopyMI);
1058 CopyMI->eraseFromParent();
1059 DEBUG(dbgs() << "\tTrivial!\n");
1064 // Otherwise, we are unable to join the intervals.
1065 DEBUG(dbgs() << "\tInterference!\n");
1066 Again = true; // May be possible to coalesce later.
1070 // Coalescing to a virtual register that is of a sub-register class of the
1071 // other. Make sure the resulting register is set to the right register class.
1072 if (CP.isCrossClass()) {
1074 MRI->setRegClass(CP.getDstReg(), CP.getNewRC());
1077 // Removing sub-register copies can ease the register class constraints.
1078 // Make sure we attempt to inflate the register class of DstReg.
1079 if (!CP.isPhys() && RegClassInfo.isProperSubClass(CP.getNewRC()))
1080 InflateRegs.push_back(CP.getDstReg());
1082 // CopyMI has been erased by joinIntervals at this point. Remove it from
1083 // ErasedInstrs since copyCoalesceWorkList() won't add a successful join back
1084 // to the work list. This keeps ErasedInstrs from growing needlessly.
1085 ErasedInstrs.erase(CopyMI);
1087 // Rewrite all SrcReg operands to DstReg.
1088 // Also update DstReg operands to include DstIdx if it is set.
1090 updateRegDefsUses(CP.getDstReg(), CP.getDstReg(), CP.getDstIdx());
1091 updateRegDefsUses(CP.getSrcReg(), CP.getDstReg(), CP.getSrcIdx());
1093 // SrcReg is guaranteed to be the register whose live interval that is
1095 LIS->removeInterval(CP.getSrcReg());
1097 // Update regalloc hint.
1098 TRI->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
1101 dbgs() << "\tJoined. Result = " << PrintReg(CP.getDstReg(), TRI);
1103 dbgs() << LIS->getInterval(CP.getDstReg());
1111 /// Attempt joining with a reserved physreg.
1112 bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
1113 assert(CP.isPhys() && "Must be a physreg copy");
1114 assert(MRI->isReserved(CP.getDstReg()) && "Not a reserved register");
1115 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1116 DEBUG(dbgs() << "\t\tRHS = " << PrintReg(CP.getSrcReg()) << ' ' << RHS
1119 assert(CP.isFlipped() && RHS.containsOneValue() &&
1120 "Invalid join with reserved register");
1122 // Optimization for reserved registers like ESP. We can only merge with a
1123 // reserved physreg if RHS has a single value that is a copy of CP.DstReg().
1124 // The live range of the reserved register will look like a set of dead defs
1125 // - we don't properly track the live range of reserved registers.
1127 // Deny any overlapping intervals. This depends on all the reserved
1128 // register live ranges to look like dead defs.
1129 for (MCRegUnitIterator UI(CP.getDstReg(), TRI); UI.isValid(); ++UI)
1130 if (RHS.overlaps(LIS->getRegUnit(*UI))) {
1131 DEBUG(dbgs() << "\t\tInterference: " << PrintRegUnit(*UI, TRI) << '\n');
1135 // Skip any value computations, we are not adding new values to the
1136 // reserved register. Also skip merging the live ranges, the reserved
1137 // register live range doesn't need to be accurate as long as all the
1140 // Delete the identity copy.
1141 MachineInstr *CopyMI = MRI->getVRegDef(RHS.reg);
1142 LIS->RemoveMachineInstrFromMaps(CopyMI);
1143 CopyMI->eraseFromParent();
1145 // We don't track kills for reserved registers.
1146 MRI->clearKillFlags(CP.getSrcReg());
1151 //===----------------------------------------------------------------------===//
1152 // Interference checking and interval joining
1153 //===----------------------------------------------------------------------===//
1155 // In the easiest case, the two live ranges being joined are disjoint, and
1156 // there is no interference to consider. It is quite common, though, to have
1157 // overlapping live ranges, and we need to check if the interference can be
1160 // The live range of a single SSA value forms a sub-tree of the dominator tree.
1161 // This means that two SSA values overlap if and only if the def of one value
1162 // is contained in the live range of the other value. As a special case, the
1163 // overlapping values can be defined at the same index.
1165 // The interference from an overlapping def can be resolved in these cases:
1167 // 1. Coalescable copies. The value is defined by a copy that would become an
1168 // identity copy after joining SrcReg and DstReg. The copy instruction will
1169 // be removed, and the value will be merged with the source value.
1171 // There can be several copies back and forth, causing many values to be
1172 // merged into one. We compute a list of ultimate values in the joined live
1173 // range as well as a mappings from the old value numbers.
1175 // 2. IMPLICIT_DEF. This instruction is only inserted to ensure all PHI
1176 // predecessors have a live out value. It doesn't cause real interference,
1177 // and can be merged into the value it overlaps. Like a coalescable copy, it
1178 // can be erased after joining.
1180 // 3. Copy of external value. The overlapping def may be a copy of a value that
1181 // is already in the other register. This is like a coalescable copy, but
1182 // the live range of the source register must be trimmed after erasing the
1183 // copy instruction:
1186 // %dst = COPY %ext <-- Remove this COPY, trim the live range of %ext.
1188 // 4. Clobbering undefined lanes. Vector registers are sometimes built by
1189 // defining one lane at a time:
1191 // %dst:ssub0<def,read-undef> = FOO
1193 // %dst:ssub1<def> = COPY %src
1195 // The live range of %src overlaps the %dst value defined by FOO, but
1196 // merging %src into %dst:ssub1 is only going to clobber the ssub1 lane
1197 // which was undef anyway.
1199 // The value mapping is more complicated in this case. The final live range
1200 // will have different value numbers for both FOO and BAR, but there is no
1201 // simple mapping from old to new values. It may even be necessary to add
1204 // 5. Clobbering dead lanes. A def may clobber a lane of a vector register that
1205 // is live, but never read. This can happen because we don't compute
1206 // individual live ranges per lane.
1210 // %dst:ssub1<def> = COPY %src
1212 // This kind of interference is only resolved locally. If the clobbered
1213 // lane value escapes the block, the join is aborted.
1216 /// Track information about values in a single virtual register about to be
1217 /// joined. Objects of this class are always created in pairs - one for each
1218 /// side of the CoalescerPair.
1222 // Location of this register in the final joined register.
1223 // Either CP.DstIdx or CP.SrcIdx.
1226 // Values that will be present in the final live range.
1227 SmallVectorImpl<VNInfo*> &NewVNInfo;
1229 const CoalescerPair &CP;
1231 SlotIndexes *Indexes;
1232 const TargetRegisterInfo *TRI;
1234 // Value number assignments. Maps value numbers in LI to entries in NewVNInfo.
1235 // This is suitable for passing to LiveInterval::join().
1236 SmallVector<int, 8> Assignments;
1238 // Conflict resolution for overlapping values.
1239 enum ConflictResolution {
1240 // No overlap, simply keep this value.
1243 // Merge this value into OtherVNI and erase the defining instruction.
1244 // Used for IMPLICIT_DEF, coalescable copies, and copies from external
1248 // Merge this value into OtherVNI but keep the defining instruction.
1249 // This is for the special case where OtherVNI is defined by the same
1253 // Keep this value, and have it replace OtherVNI where possible. This
1254 // complicates value mapping since OtherVNI maps to two different values
1255 // before and after this def.
1256 // Used when clobbering undefined or dead lanes.
1259 // Unresolved conflict. Visit later when all values have been mapped.
1262 // Unresolvable conflict. Abort the join.
1266 // Per-value info for LI. The lane bit masks are all relative to the final
1267 // joined register, so they can be compared directly between SrcReg and
1270 ConflictResolution Resolution;
1272 // Lanes written by this def, 0 for unanalyzed values.
1273 unsigned WriteLanes;
1275 // Lanes with defined values in this register. Other lanes are undef and
1277 unsigned ValidLanes;
1279 // Value in LI being redefined by this def.
1282 // Value in the other live range that overlaps this def, if any.
1285 // Is this value an IMPLICIT_DEF?
1288 // True when the live range of this value will be pruned because of an
1289 // overlapping CR_Replace value in the other live range.
1292 // True once Pruned above has been computed.
1293 bool PrunedComputed;
1295 Val() : Resolution(CR_Keep), WriteLanes(0), ValidLanes(0),
1296 RedefVNI(0), OtherVNI(0), IsImplicitDef(false), Pruned(false),
1297 PrunedComputed(false) {}
1299 bool isAnalyzed() const { return WriteLanes != 0; }
1302 // One entry per value number in LI.
1303 SmallVector<Val, 8> Vals;
1305 unsigned computeWriteLanes(const MachineInstr *DefMI, bool &Redef);
1306 VNInfo *stripCopies(VNInfo *VNI);
1307 ConflictResolution analyzeValue(unsigned ValNo, JoinVals &Other);
1308 void computeAssignment(unsigned ValNo, JoinVals &Other);
1309 bool taintExtent(unsigned, unsigned, JoinVals&,
1310 SmallVectorImpl<std::pair<SlotIndex, unsigned> >&);
1311 bool usesLanes(MachineInstr *MI, unsigned, unsigned, unsigned);
1312 bool isPrunedValue(unsigned ValNo, JoinVals &Other);
1315 JoinVals(LiveInterval &li, unsigned subIdx,
1316 SmallVectorImpl<VNInfo*> &newVNInfo,
1317 const CoalescerPair &cp,
1319 const TargetRegisterInfo *tri)
1320 : LI(li), SubIdx(subIdx), NewVNInfo(newVNInfo), CP(cp), LIS(lis),
1321 Indexes(LIS->getSlotIndexes()), TRI(tri),
1322 Assignments(LI.getNumValNums(), -1), Vals(LI.getNumValNums())
1325 /// Analyze defs in LI and compute a value mapping in NewVNInfo.
1326 /// Returns false if any conflicts were impossible to resolve.
1327 bool mapValues(JoinVals &Other);
1329 /// Try to resolve conflicts that require all values to be mapped.
1330 /// Returns false if any conflicts were impossible to resolve.
1331 bool resolveConflicts(JoinVals &Other);
1333 /// Prune the live range of values in Other.LI where they would conflict with
1334 /// CR_Replace values in LI. Collect end points for restoring the live range
1336 void pruneValues(JoinVals &Other, SmallVectorImpl<SlotIndex> &EndPoints);
1338 /// Erase any machine instructions that have been coalesced away.
1339 /// Add erased instructions to ErasedInstrs.
1340 /// Add foreign virtual registers to ShrinkRegs if their live range ended at
1341 /// the erased instrs.
1342 void eraseInstrs(SmallPtrSet<MachineInstr*, 8> &ErasedInstrs,
1343 SmallVectorImpl<unsigned> &ShrinkRegs);
1345 /// Get the value assignments suitable for passing to LiveInterval::join.
1346 const int *getAssignments() const { return Assignments.data(); }
1348 } // end anonymous namespace
1350 /// Compute the bitmask of lanes actually written by DefMI.
1351 /// Set Redef if there are any partial register definitions that depend on the
1352 /// previous value of the register.
1353 unsigned JoinVals::computeWriteLanes(const MachineInstr *DefMI, bool &Redef) {
1355 for (ConstMIOperands MO(DefMI); MO.isValid(); ++MO) {
1356 if (!MO->isReg() || MO->getReg() != LI.reg || !MO->isDef())
1358 L |= TRI->getSubRegIndexLaneMask(
1359 TRI->composeSubRegIndices(SubIdx, MO->getSubReg()));
1366 /// Find the ultimate value that VNI was copied from.
1367 VNInfo *JoinVals::stripCopies(VNInfo *VNI) {
1368 while (!VNI->isPHIDef()) {
1369 MachineInstr *MI = Indexes->getInstructionFromIndex(VNI->def);
1370 assert(MI && "No defining instruction");
1371 if (!MI->isFullCopy())
1373 unsigned Reg = MI->getOperand(1).getReg();
1374 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1376 LiveRangeQuery LRQ(LIS->getInterval(Reg), VNI->def);
1379 VNI = LRQ.valueIn();
1384 /// Analyze ValNo in this live range, and set all fields of Vals[ValNo].
1385 /// Return a conflict resolution when possible, but leave the hard cases as
1387 /// Recursively calls computeAssignment() on this and Other, guaranteeing that
1388 /// both OtherVNI and RedefVNI have been analyzed and mapped before returning.
1389 /// The recursion always goes upwards in the dominator tree, making loops
1391 JoinVals::ConflictResolution
1392 JoinVals::analyzeValue(unsigned ValNo, JoinVals &Other) {
1393 Val &V = Vals[ValNo];
1394 assert(!V.isAnalyzed() && "Value has already been analyzed!");
1395 VNInfo *VNI = LI.getValNumInfo(ValNo);
1396 if (VNI->isUnused()) {
1401 // Get the instruction defining this value, compute the lanes written.
1402 const MachineInstr *DefMI = 0;
1403 if (VNI->isPHIDef()) {
1404 // Conservatively assume that all lanes in a PHI are valid.
1405 V.ValidLanes = V.WriteLanes = TRI->getSubRegIndexLaneMask(SubIdx);
1407 DefMI = Indexes->getInstructionFromIndex(VNI->def);
1409 V.ValidLanes = V.WriteLanes = computeWriteLanes(DefMI, Redef);
1411 // If this is a read-modify-write instruction, there may be more valid
1412 // lanes than the ones written by this instruction.
1413 // This only covers partial redef operands. DefMI may have normal use
1414 // operands reading the register. They don't contribute valid lanes.
1416 // This adds ssub1 to the set of valid lanes in %src:
1418 // %src:ssub1<def> = FOO
1420 // This leaves only ssub1 valid, making any other lanes undef:
1422 // %src:ssub1<def,read-undef> = FOO %src:ssub2
1424 // The <read-undef> flag on the def operand means that old lane values are
1427 V.RedefVNI = LiveRangeQuery(LI, VNI->def).valueIn();
1428 assert(V.RedefVNI && "Instruction is reading nonexistent value");
1429 computeAssignment(V.RedefVNI->id, Other);
1430 V.ValidLanes |= Vals[V.RedefVNI->id].ValidLanes;
1433 // An IMPLICIT_DEF writes undef values.
1434 if (DefMI->isImplicitDef()) {
1435 V.IsImplicitDef = true;
1436 V.ValidLanes &= ~V.WriteLanes;
1440 // Find the value in Other that overlaps VNI->def, if any.
1441 LiveRangeQuery OtherLRQ(Other.LI, VNI->def);
1443 // It is possible that both values are defined by the same instruction, or
1444 // the values are PHIs defined in the same block. When that happens, the two
1445 // values should be merged into one, but not into any preceding value.
1446 // The first value defined or visited gets CR_Keep, the other gets CR_Merge.
1447 if (VNInfo *OtherVNI = OtherLRQ.valueDefined()) {
1448 assert(SlotIndex::isSameInstr(VNI->def, OtherVNI->def) && "Broken LRQ");
1450 // One value stays, the other is merged. Keep the earlier one, or the first
1452 if (OtherVNI->def < VNI->def)
1453 Other.computeAssignment(OtherVNI->id, *this);
1454 else if (VNI->def < OtherVNI->def && OtherLRQ.valueIn()) {
1455 // This is an early-clobber def overlapping a live-in value in the other
1456 // register. Not mergeable.
1457 V.OtherVNI = OtherLRQ.valueIn();
1458 return CR_Impossible;
1460 V.OtherVNI = OtherVNI;
1461 Val &OtherV = Other.Vals[OtherVNI->id];
1462 // Keep this value, check for conflicts when analyzing OtherVNI.
1463 if (!OtherV.isAnalyzed())
1465 // Both sides have been analyzed now.
1466 // Allow overlapping PHI values. Any real interference would show up in a
1467 // predecessor, the PHI itself can't introduce any conflicts.
1468 if (VNI->isPHIDef())
1470 if (V.ValidLanes & OtherV.ValidLanes)
1471 // Overlapping lanes can't be resolved.
1472 return CR_Impossible;
1477 // No simultaneous def. Is Other live at the def?
1478 V.OtherVNI = OtherLRQ.valueIn();
1480 // No overlap, no conflict.
1483 assert(!SlotIndex::isSameInstr(VNI->def, V.OtherVNI->def) && "Broken LRQ");
1485 // We have overlapping values, or possibly a kill of Other.
1486 // Recursively compute assignments up the dominator tree.
1487 Other.computeAssignment(V.OtherVNI->id, *this);
1488 const Val &OtherV = Other.Vals[V.OtherVNI->id];
1490 // Allow overlapping PHI values. Any real interference would show up in a
1491 // predecessor, the PHI itself can't introduce any conflicts.
1492 if (VNI->isPHIDef())
1495 // Check for simple erasable conflicts.
1496 if (DefMI->isImplicitDef())
1499 // Include the non-conflict where DefMI is a coalescable copy that kills
1500 // OtherVNI. We still want the copy erased and value numbers merged.
1501 if (CP.isCoalescable(DefMI)) {
1502 // Some of the lanes copied from OtherVNI may be undef, making them undef
1504 V.ValidLanes &= ~V.WriteLanes | OtherV.ValidLanes;
1508 // This may not be a real conflict if DefMI simply kills Other and defines
1510 if (OtherLRQ.isKill() && OtherLRQ.endPoint() <= VNI->def)
1513 // Handle the case where VNI and OtherVNI can be proven to be identical:
1515 // %other = COPY %ext
1516 // %this = COPY %ext <-- Erase this copy
1518 if (DefMI->isFullCopy() && !CP.isPartial() &&
1519 stripCopies(VNI) == stripCopies(V.OtherVNI))
1522 // If the lanes written by this instruction were all undef in OtherVNI, it is
1523 // still safe to join the live ranges. This can't be done with a simple value
1524 // mapping, though - OtherVNI will map to multiple values:
1526 // 1 %dst:ssub0 = FOO <-- OtherVNI
1527 // 2 %src = BAR <-- VNI
1528 // 3 %dst:ssub1 = COPY %src<kill> <-- Eliminate this copy.
1530 // 5 QUUX %src<kill>
1532 // Here OtherVNI will map to itself in [1;2), but to VNI in [2;5). CR_Replace
1533 // handles this complex value mapping.
1534 if ((V.WriteLanes & OtherV.ValidLanes) == 0)
1537 // If the other live range is killed by DefMI and the live ranges are still
1538 // overlapping, it must be because we're looking at an early clobber def:
1540 // %dst<def,early-clobber> = ASM %src<kill>
1542 // In this case, it is illegal to merge the two live ranges since the early
1543 // clobber def would clobber %src before it was read.
1544 if (OtherLRQ.isKill()) {
1545 // This case where the def doesn't overlap the kill is handled above.
1546 assert(VNI->def.isEarlyClobber() &&
1547 "Only early clobber defs can overlap a kill");
1548 return CR_Impossible;
1551 // VNI is clobbering live lanes in OtherVNI, but there is still the
1552 // possibility that no instructions actually read the clobbered lanes.
1553 // If we're clobbering all the lanes in OtherVNI, at least one must be read.
1554 // Otherwise Other.LI wouldn't be live here.
1555 if ((TRI->getSubRegIndexLaneMask(Other.SubIdx) & ~V.WriteLanes) == 0)
1556 return CR_Impossible;
1558 // We need to verify that no instructions are reading the clobbered lanes. To
1559 // save compile time, we'll only check that locally. Don't allow the tainted
1560 // value to escape the basic block.
1561 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
1562 if (OtherLRQ.endPoint() >= Indexes->getMBBEndIdx(MBB))
1563 return CR_Impossible;
1565 // There are still some things that could go wrong besides clobbered lanes
1566 // being read, for example OtherVNI may be only partially redefined in MBB,
1567 // and some clobbered lanes could escape the block. Save this analysis for
1568 // resolveConflicts() when all values have been mapped. We need to know
1569 // RedefVNI and WriteLanes for any later defs in MBB, and we can't compute
1570 // that now - the recursive analyzeValue() calls must go upwards in the
1572 return CR_Unresolved;
1575 /// Compute the value assignment for ValNo in LI.
1576 /// This may be called recursively by analyzeValue(), but never for a ValNo on
1578 void JoinVals::computeAssignment(unsigned ValNo, JoinVals &Other) {
1579 Val &V = Vals[ValNo];
1580 if (V.isAnalyzed()) {
1581 // Recursion should always move up the dominator tree, so ValNo is not
1582 // supposed to reappear before it has been assigned.
1583 assert(Assignments[ValNo] != -1 && "Bad recursion?");
1586 switch ((V.Resolution = analyzeValue(ValNo, Other))) {
1589 // Merge this ValNo into OtherVNI.
1590 assert(V.OtherVNI && "OtherVNI not assigned, can't merge.");
1591 assert(Other.Vals[V.OtherVNI->id].isAnalyzed() && "Missing recursion");
1592 Assignments[ValNo] = Other.Assignments[V.OtherVNI->id];
1593 DEBUG(dbgs() << "\t\tmerge " << PrintReg(LI.reg) << ':' << ValNo << '@'
1594 << LI.getValNumInfo(ValNo)->def << " into "
1595 << PrintReg(Other.LI.reg) << ':' << V.OtherVNI->id << '@'
1596 << V.OtherVNI->def << " --> @"
1597 << NewVNInfo[Assignments[ValNo]]->def << '\n');
1601 // The other value is going to be pruned if this join is successful.
1602 assert(V.OtherVNI && "OtherVNI not assigned, can't prune");
1603 Other.Vals[V.OtherVNI->id].Pruned = true;
1606 // This value number needs to go in the final joined live range.
1607 Assignments[ValNo] = NewVNInfo.size();
1608 NewVNInfo.push_back(LI.getValNumInfo(ValNo));
1613 bool JoinVals::mapValues(JoinVals &Other) {
1614 for (unsigned i = 0, e = LI.getNumValNums(); i != e; ++i) {
1615 computeAssignment(i, Other);
1616 if (Vals[i].Resolution == CR_Impossible) {
1617 DEBUG(dbgs() << "\t\tinterference at " << PrintReg(LI.reg) << ':' << i
1618 << '@' << LI.getValNumInfo(i)->def << '\n');
1625 /// Assuming ValNo is going to clobber some valid lanes in Other.LI, compute
1626 /// the extent of the tainted lanes in the block.
1628 /// Multiple values in Other.LI can be affected since partial redefinitions can
1629 /// preserve previously tainted lanes.
1631 /// 1 %dst = VLOAD <-- Define all lanes in %dst
1632 /// 2 %src = FOO <-- ValNo to be joined with %dst:ssub0
1633 /// 3 %dst:ssub1 = BAR <-- Partial redef doesn't clear taint in ssub0
1634 /// 4 %dst:ssub0 = COPY %src <-- Conflict resolved, ssub0 wasn't read
1636 /// For each ValNo in Other that is affected, add an (EndIndex, TaintedLanes)
1637 /// entry to TaintedVals.
1639 /// Returns false if the tainted lanes extend beyond the basic block.
1641 taintExtent(unsigned ValNo, unsigned TaintedLanes, JoinVals &Other,
1642 SmallVectorImpl<std::pair<SlotIndex, unsigned> > &TaintExtent) {
1643 VNInfo *VNI = LI.getValNumInfo(ValNo);
1644 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
1645 SlotIndex MBBEnd = Indexes->getMBBEndIdx(MBB);
1647 // Scan Other.LI from VNI.def to MBBEnd.
1648 LiveInterval::iterator OtherI = Other.LI.find(VNI->def);
1649 assert(OtherI != Other.LI.end() && "No conflict?");
1651 // OtherI is pointing to a tainted value. Abort the join if the tainted
1652 // lanes escape the block.
1653 SlotIndex End = OtherI->end;
1654 if (End >= MBBEnd) {
1655 DEBUG(dbgs() << "\t\ttaints global " << PrintReg(Other.LI.reg) << ':'
1656 << OtherI->valno->id << '@' << OtherI->start << '\n');
1659 DEBUG(dbgs() << "\t\ttaints local " << PrintReg(Other.LI.reg) << ':'
1660 << OtherI->valno->id << '@' << OtherI->start
1661 << " to " << End << '\n');
1662 // A dead def is not a problem.
1665 TaintExtent.push_back(std::make_pair(End, TaintedLanes));
1667 // Check for another def in the MBB.
1668 if (++OtherI == Other.LI.end() || OtherI->start >= MBBEnd)
1671 // Lanes written by the new def are no longer tainted.
1672 const Val &OV = Other.Vals[OtherI->valno->id];
1673 TaintedLanes &= ~OV.WriteLanes;
1676 } while (TaintedLanes);
1680 /// Return true if MI uses any of the given Lanes from Reg.
1681 /// This does not include partial redefinitions of Reg.
1682 bool JoinVals::usesLanes(MachineInstr *MI, unsigned Reg, unsigned SubIdx,
1684 if (MI->isDebugValue())
1686 for (ConstMIOperands MO(MI); MO.isValid(); ++MO) {
1687 if (!MO->isReg() || MO->isDef() || MO->getReg() != Reg)
1689 if (!MO->readsReg())
1691 if (Lanes & TRI->getSubRegIndexLaneMask(
1692 TRI->composeSubRegIndices(SubIdx, MO->getSubReg())))
1698 bool JoinVals::resolveConflicts(JoinVals &Other) {
1699 for (unsigned i = 0, e = LI.getNumValNums(); i != e; ++i) {
1701 assert (V.Resolution != CR_Impossible && "Unresolvable conflict");
1702 if (V.Resolution != CR_Unresolved)
1704 DEBUG(dbgs() << "\t\tconflict at " << PrintReg(LI.reg) << ':' << i
1705 << '@' << LI.getValNumInfo(i)->def << '\n');
1707 assert(V.OtherVNI && "Inconsistent conflict resolution.");
1708 VNInfo *VNI = LI.getValNumInfo(i);
1709 const Val &OtherV = Other.Vals[V.OtherVNI->id];
1711 // VNI is known to clobber some lanes in OtherVNI. If we go ahead with the
1712 // join, those lanes will be tainted with a wrong value. Get the extent of
1713 // the tainted lanes.
1714 unsigned TaintedLanes = V.WriteLanes & OtherV.ValidLanes;
1715 SmallVector<std::pair<SlotIndex, unsigned>, 8> TaintExtent;
1716 if (!taintExtent(i, TaintedLanes, Other, TaintExtent))
1717 // Tainted lanes would extend beyond the basic block.
1720 assert(!TaintExtent.empty() && "There should be at least one conflict.");
1722 // Now look at the instructions from VNI->def to TaintExtent (inclusive).
1723 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
1724 MachineBasicBlock::iterator MI = MBB->begin();
1725 if (!VNI->isPHIDef()) {
1726 MI = Indexes->getInstructionFromIndex(VNI->def);
1727 // No need to check the instruction defining VNI for reads.
1730 assert(!SlotIndex::isSameInstr(VNI->def, TaintExtent.front().first) &&
1731 "Interference ends on VNI->def. Should have been handled earlier");
1732 MachineInstr *LastMI =
1733 Indexes->getInstructionFromIndex(TaintExtent.front().first);
1734 assert(LastMI && "Range must end at a proper instruction");
1735 unsigned TaintNum = 0;
1737 assert(MI != MBB->end() && "Bad LastMI");
1738 if (usesLanes(MI, Other.LI.reg, Other.SubIdx, TaintedLanes)) {
1739 DEBUG(dbgs() << "\t\ttainted lanes used by: " << *MI);
1742 // LastMI is the last instruction to use the current value.
1743 if (&*MI == LastMI) {
1744 if (++TaintNum == TaintExtent.size())
1746 LastMI = Indexes->getInstructionFromIndex(TaintExtent[TaintNum].first);
1747 assert(LastMI && "Range must end at a proper instruction");
1748 TaintedLanes = TaintExtent[TaintNum].second;
1753 // The tainted lanes are unused.
1754 V.Resolution = CR_Replace;
1760 // Determine if ValNo is a copy of a value number in LI or Other.LI that will
1764 // %src = COPY %dst <-- This value to be pruned.
1765 // %dst = COPY %src <-- This value is a copy of a pruned value.
1767 bool JoinVals::isPrunedValue(unsigned ValNo, JoinVals &Other) {
1768 Val &V = Vals[ValNo];
1769 if (V.Pruned || V.PrunedComputed)
1772 if (V.Resolution != CR_Erase && V.Resolution != CR_Merge)
1775 // Follow copies up the dominator tree and check if any intermediate value
1777 V.PrunedComputed = true;
1778 V.Pruned = Other.isPrunedValue(V.OtherVNI->id, *this);
1782 void JoinVals::pruneValues(JoinVals &Other,
1783 SmallVectorImpl<SlotIndex> &EndPoints) {
1784 for (unsigned i = 0, e = LI.getNumValNums(); i != e; ++i) {
1785 SlotIndex Def = LI.getValNumInfo(i)->def;
1786 switch (Vals[i].Resolution) {
1790 // This value takes precedence over the value in Other.LI.
1791 LIS->pruneValue(&Other.LI, Def, &EndPoints);
1792 // Check if we're replacing an IMPLICIT_DEF value. The IMPLICIT_DEF
1793 // instructions are only inserted to provide a live-out value for PHI
1794 // predecessors, so the instruction should simply go away once its value
1795 // has been replaced.
1796 Val &OtherV = Other.Vals[Vals[i].OtherVNI->id];
1797 bool EraseImpDef = OtherV.IsImplicitDef && OtherV.Resolution == CR_Keep;
1798 if (!Def.isBlock()) {
1799 // Remove <def,read-undef> flags. This def is now a partial redef.
1800 // Also remove <def,dead> flags since the joined live range will
1801 // continue past this instruction.
1802 for (MIOperands MO(Indexes->getInstructionFromIndex(Def));
1804 if (MO->isReg() && MO->isDef() && MO->getReg() == LI.reg) {
1805 MO->setIsUndef(EraseImpDef);
1806 MO->setIsDead(false);
1808 // This value will reach instructions below, but we need to make sure
1809 // the live range also reaches the instruction at Def.
1811 EndPoints.push_back(Def);
1813 DEBUG(dbgs() << "\t\tpruned " << PrintReg(Other.LI.reg) << " at " << Def
1814 << ": " << Other.LI << '\n');
1819 if (isPrunedValue(i, Other)) {
1820 // This value is ultimately a copy of a pruned value in LI or Other.LI.
1821 // We can no longer trust the value mapping computed by
1822 // computeAssignment(), the value that was originally copied could have
1824 LIS->pruneValue(&LI, Def, &EndPoints);
1825 DEBUG(dbgs() << "\t\tpruned all of " << PrintReg(LI.reg) << " at "
1826 << Def << ": " << LI << '\n');
1831 llvm_unreachable("Unresolved conflicts");
1836 void JoinVals::eraseInstrs(SmallPtrSet<MachineInstr*, 8> &ErasedInstrs,
1837 SmallVectorImpl<unsigned> &ShrinkRegs) {
1838 for (unsigned i = 0, e = LI.getNumValNums(); i != e; ++i) {
1839 // Get the def location before markUnused() below invalidates it.
1840 SlotIndex Def = LI.getValNumInfo(i)->def;
1841 switch (Vals[i].Resolution) {
1843 // If an IMPLICIT_DEF value is pruned, it doesn't serve a purpose any
1844 // longer. The IMPLICIT_DEF instructions are only inserted by
1845 // PHIElimination to guarantee that all PHI predecessors have a value.
1846 if (!Vals[i].IsImplicitDef || !Vals[i].Pruned)
1848 // Remove value number i from LI. Note that this VNInfo is still present
1849 // in NewVNInfo, so it will appear as an unused value number in the final
1851 LI.getValNumInfo(i)->markUnused();
1852 LI.removeValNo(LI.getValNumInfo(i));
1853 DEBUG(dbgs() << "\t\tremoved " << i << '@' << Def << ": " << LI << '\n');
1857 MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
1858 assert(MI && "No instruction to erase");
1860 unsigned Reg = MI->getOperand(1).getReg();
1861 if (TargetRegisterInfo::isVirtualRegister(Reg) &&
1862 Reg != CP.getSrcReg() && Reg != CP.getDstReg())
1863 ShrinkRegs.push_back(Reg);
1865 ErasedInstrs.insert(MI);
1866 DEBUG(dbgs() << "\t\terased:\t" << Def << '\t' << *MI);
1867 LIS->RemoveMachineInstrFromMaps(MI);
1868 MI->eraseFromParent();
1877 bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
1878 SmallVector<VNInfo*, 16> NewVNInfo;
1879 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1880 LiveInterval &LHS = LIS->getInterval(CP.getDstReg());
1881 JoinVals RHSVals(RHS, CP.getSrcIdx(), NewVNInfo, CP, LIS, TRI);
1882 JoinVals LHSVals(LHS, CP.getDstIdx(), NewVNInfo, CP, LIS, TRI);
1884 DEBUG(dbgs() << "\t\tRHS = " << PrintReg(CP.getSrcReg()) << ' ' << RHS
1885 << "\n\t\tLHS = " << PrintReg(CP.getDstReg()) << ' ' << LHS
1888 // First compute NewVNInfo and the simple value mappings.
1889 // Detect impossible conflicts early.
1890 if (!LHSVals.mapValues(RHSVals) || !RHSVals.mapValues(LHSVals))
1893 // Some conflicts can only be resolved after all values have been mapped.
1894 if (!LHSVals.resolveConflicts(RHSVals) || !RHSVals.resolveConflicts(LHSVals))
1897 // All clear, the live ranges can be merged.
1899 // The merging algorithm in LiveInterval::join() can't handle conflicting
1900 // value mappings, so we need to remove any live ranges that overlap a
1901 // CR_Replace resolution. Collect a set of end points that can be used to
1902 // restore the live range after joining.
1903 SmallVector<SlotIndex, 8> EndPoints;
1904 LHSVals.pruneValues(RHSVals, EndPoints);
1905 RHSVals.pruneValues(LHSVals, EndPoints);
1907 // Erase COPY and IMPLICIT_DEF instructions. This may cause some external
1908 // registers to require trimming.
1909 SmallVector<unsigned, 8> ShrinkRegs;
1910 LHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs);
1911 RHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs);
1912 while (!ShrinkRegs.empty())
1913 LIS->shrinkToUses(&LIS->getInterval(ShrinkRegs.pop_back_val()));
1915 // Join RHS into LHS.
1916 LHS.join(RHS, LHSVals.getAssignments(), RHSVals.getAssignments(), NewVNInfo,
1919 // Kill flags are going to be wrong if the live ranges were overlapping.
1920 // Eventually, we should simply clear all kill flags when computing live
1921 // ranges. They are reinserted after register allocation.
1922 MRI->clearKillFlags(LHS.reg);
1923 MRI->clearKillFlags(RHS.reg);
1925 if (EndPoints.empty())
1928 // Recompute the parts of the live range we had to remove because of
1929 // CR_Replace conflicts.
1930 DEBUG(dbgs() << "\t\trestoring liveness to " << EndPoints.size()
1931 << " points: " << LHS << '\n');
1932 LIS->extendToIndices(&LHS, EndPoints);
1936 /// joinIntervals - Attempt to join these two intervals. On failure, this
1938 bool RegisterCoalescer::joinIntervals(CoalescerPair &CP) {
1939 return CP.isPhys() ? joinReservedPhysReg(CP) : joinVirtRegs(CP);
1943 // Information concerning MBB coalescing priority.
1944 struct MBBPriorityInfo {
1945 MachineBasicBlock *MBB;
1949 MBBPriorityInfo(MachineBasicBlock *mbb, unsigned depth, bool issplit)
1950 : MBB(mbb), Depth(depth), IsSplit(issplit) {}
1954 // C-style comparator that sorts first based on the loop depth of the basic
1955 // block (the unsigned), and then on the MBB number.
1957 // EnableGlobalCopies assumes that the primary sort key is loop depth.
1958 static int compareMBBPriority(const void *L, const void *R) {
1959 const MBBPriorityInfo *LHS = static_cast<const MBBPriorityInfo*>(L);
1960 const MBBPriorityInfo *RHS = static_cast<const MBBPriorityInfo*>(R);
1961 // Deeper loops first
1962 if (LHS->Depth != RHS->Depth)
1963 return LHS->Depth > RHS->Depth ? -1 : 1;
1965 // Try to unsplit critical edges next.
1966 if (LHS->IsSplit != RHS->IsSplit)
1967 return LHS->IsSplit ? -1 : 1;
1969 // Prefer blocks that are more connected in the CFG. This takes care of
1970 // the most difficult copies first while intervals are short.
1971 unsigned cl = LHS->MBB->pred_size() + LHS->MBB->succ_size();
1972 unsigned cr = RHS->MBB->pred_size() + RHS->MBB->succ_size();
1974 return cl > cr ? -1 : 1;
1976 // As a last resort, sort by block number.
1977 return LHS->MBB->getNumber() < RHS->MBB->getNumber() ? -1 : 1;
1980 /// \returns true if the given copy uses or defines a local live range.
1981 static bool isLocalCopy(MachineInstr *Copy, const LiveIntervals *LIS) {
1982 if (!Copy->isCopy())
1985 unsigned SrcReg = Copy->getOperand(1).getReg();
1986 unsigned DstReg = Copy->getOperand(0).getReg();
1987 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)
1988 || TargetRegisterInfo::isPhysicalRegister(DstReg))
1991 return LIS->intervalIsInOneMBB(LIS->getInterval(SrcReg))
1992 || LIS->intervalIsInOneMBB(LIS->getInterval(DstReg));
1995 // Try joining WorkList copies starting from index From.
1996 // Null out any successful joins.
1997 bool RegisterCoalescer::
1998 copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList) {
1999 bool Progress = false;
2000 for (unsigned i = 0, e = CurrList.size(); i != e; ++i) {
2003 // Skip instruction pointers that have already been erased, for example by
2004 // dead code elimination.
2005 if (ErasedInstrs.erase(CurrList[i])) {
2010 bool Success = joinCopy(CurrList[i], Again);
2011 Progress |= Success;
2012 if (Success || !Again)
2019 RegisterCoalescer::copyCoalesceInMBB(MachineBasicBlock *MBB) {
2020 DEBUG(dbgs() << MBB->getName() << ":\n");
2022 // Collect all copy-like instructions in MBB. Don't start coalescing anything
2023 // yet, it might invalidate the iterator.
2024 const unsigned PrevSize = WorkList.size();
2025 if (JoinGlobalCopies) {
2026 // Coalesce copies bottom-up to coalesce local defs before local uses. They
2027 // are not inherently easier to resolve, but slightly preferable until we
2028 // have local live range splitting. In particular this is required by
2029 // cmp+jmp macro fusion.
2030 for (MachineBasicBlock::reverse_iterator
2031 MII = MBB->rbegin(), E = MBB->rend(); MII != E; ++MII) {
2032 if (!MII->isCopyLike())
2034 if (isLocalCopy(&(*MII), LIS))
2035 LocalWorkList.push_back(&(*MII));
2037 WorkList.push_back(&(*MII));
2041 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
2043 if (MII->isCopyLike())
2044 WorkList.push_back(MII);
2046 // Try coalescing the collected copies immediately, and remove the nulls.
2047 // This prevents the WorkList from getting too large since most copies are
2048 // joinable on the first attempt.
2049 MutableArrayRef<MachineInstr*>
2050 CurrList(WorkList.begin() + PrevSize, WorkList.end());
2051 if (copyCoalesceWorkList(CurrList))
2052 WorkList.erase(std::remove(WorkList.begin() + PrevSize, WorkList.end(),
2053 (MachineInstr*)0), WorkList.end());
2056 void RegisterCoalescer::coalesceLocals() {
2057 copyCoalesceWorkList(LocalWorkList);
2058 for (unsigned j = 0, je = LocalWorkList.size(); j != je; ++j) {
2059 if (LocalWorkList[j])
2060 WorkList.push_back(LocalWorkList[j]);
2062 LocalWorkList.clear();
2065 void RegisterCoalescer::joinAllIntervals() {
2066 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
2067 assert(WorkList.empty() && LocalWorkList.empty() && "Old data still around.");
2069 std::vector<MBBPriorityInfo> MBBs;
2070 MBBs.reserve(MF->size());
2071 for (MachineFunction::iterator I = MF->begin(), E = MF->end();I != E;++I){
2072 MachineBasicBlock *MBB = I;
2073 MBBs.push_back(MBBPriorityInfo(MBB, Loops->getLoopDepth(MBB),
2074 JoinSplitEdges && isSplitEdge(MBB)));
2076 array_pod_sort(MBBs.begin(), MBBs.end(), compareMBBPriority);
2078 // Coalesce intervals in MBB priority order.
2079 unsigned CurrDepth = UINT_MAX;
2080 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
2081 // Try coalescing the collected local copies for deeper loops.
2082 if (JoinGlobalCopies && MBBs[i].Depth < CurrDepth) {
2084 CurrDepth = MBBs[i].Depth;
2086 copyCoalesceInMBB(MBBs[i].MBB);
2090 // Joining intervals can allow other intervals to be joined. Iteratively join
2091 // until we make no progress.
2092 while (copyCoalesceWorkList(WorkList))
2096 void RegisterCoalescer::releaseMemory() {
2097 ErasedInstrs.clear();
2100 InflateRegs.clear();
2103 bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
2105 MRI = &fn.getRegInfo();
2106 TM = &fn.getTarget();
2107 TRI = TM->getRegisterInfo();
2108 TII = TM->getInstrInfo();
2109 LIS = &getAnalysis<LiveIntervals>();
2110 LDV = &getAnalysis<LiveDebugVariables>();
2111 AA = &getAnalysis<AliasAnalysis>();
2112 Loops = &getAnalysis<MachineLoopInfo>();
2114 const TargetSubtargetInfo &ST = TM->getSubtarget<TargetSubtargetInfo>();
2115 if (EnableGlobalCopies == cl::BOU_UNSET)
2116 JoinGlobalCopies = ST.enableMachineScheduler();
2118 JoinGlobalCopies = (EnableGlobalCopies == cl::BOU_TRUE);
2120 // The MachineScheduler does not currently require JoinSplitEdges. This will
2121 // either be enabled unconditionally or replaced by a more general live range
2122 // splitting optimization.
2123 JoinSplitEdges = EnableJoinSplits;
2125 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
2126 << "********** Function: " << MF->getName() << '\n');
2128 if (VerifyCoalescing)
2129 MF->verify(this, "Before register coalescing");
2131 RegClassInfo.runOnMachineFunction(fn);
2133 // Join (coalesce) intervals if requested.
2137 // After deleting a lot of copies, register classes may be less constrained.
2138 // Removing sub-register operands may allow GR32_ABCD -> GR32 and DPR_VFP2 ->
2140 array_pod_sort(InflateRegs.begin(), InflateRegs.end());
2141 InflateRegs.erase(std::unique(InflateRegs.begin(), InflateRegs.end()),
2143 DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size() << " regs.\n");
2144 for (unsigned i = 0, e = InflateRegs.size(); i != e; ++i) {
2145 unsigned Reg = InflateRegs[i];
2146 if (MRI->reg_nodbg_empty(Reg))
2148 if (MRI->recomputeRegClass(Reg, *TM)) {
2149 DEBUG(dbgs() << PrintReg(Reg) << " inflated to "
2150 << MRI->getRegClass(Reg)->getName() << '\n');
2157 if (VerifyCoalescing)
2158 MF->verify(this, "After register coalescing");
2162 /// print - Implement the dump method.
2163 void RegisterCoalescer::print(raw_ostream &O, const Module* m) const {