1 //===- RegisterCoalescer.cpp - Generic Register Coalescing Interface -------==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the generic RegisterCoalescer interface which
11 // is used as the common interface used by all clients and
12 // implementations of register coalescing.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "regalloc"
17 #include "RegisterCoalescer.h"
18 #include "LiveDebugVariables.h"
19 #include "RegisterClassInfo.h"
20 #include "VirtRegMap.h"
22 #include "llvm/Pass.h"
23 #include "llvm/Value.h"
24 #include "llvm/ADT/OwningPtr.h"
25 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/ADT/SmallSet.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Analysis/AliasAnalysis.h"
29 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
30 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
31 #include "llvm/CodeGen/LiveRangeEdit.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineInstr.h"
34 #include "llvm/CodeGen/MachineInstr.h"
35 #include "llvm/CodeGen/MachineLoopInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/ErrorHandling.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Target/TargetRegisterInfo.h"
52 STATISTIC(numJoins , "Number of interval joins performed");
53 STATISTIC(numCrossRCs , "Number of cross class joins performed");
54 STATISTIC(numCommutes , "Number of instruction commuting performed");
55 STATISTIC(numExtends , "Number of copies extended");
56 STATISTIC(NumReMats , "Number of instructions re-materialized");
57 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
58 STATISTIC(NumInflated , "Number of register classes inflated");
61 EnableJoining("join-liveintervals",
62 cl::desc("Coalesce copies (default=true)"),
66 VerifyCoalescing("verify-coalescing",
67 cl::desc("Verify machine instrs before and after register coalescing"),
71 class RegisterCoalescer : public MachineFunctionPass,
72 private LiveRangeEdit::Delegate {
74 MachineRegisterInfo* MRI;
75 const TargetMachine* TM;
76 const TargetRegisterInfo* TRI;
77 const TargetInstrInfo* TII;
79 LiveDebugVariables *LDV;
80 const MachineLoopInfo* Loops;
82 RegisterClassInfo RegClassInfo;
84 /// JoinedCopies - Keep track of copies eliminated due to coalescing.
86 SmallPtrSet<MachineInstr*, 32> JoinedCopies;
88 /// ReMatDefs - Keep track of definition instructions which have
90 SmallPtrSet<MachineInstr*, 8> ReMatDefs;
92 /// WorkList - Copy instructions yet to be coalesced.
93 SmallVector<MachineInstr*, 8> WorkList;
95 /// ErasedInstrs - Set of instruction pointers that have been erased, and
96 /// that may be present in WorkList.
97 SmallPtrSet<MachineInstr*, 8> ErasedInstrs;
99 /// Dead instructions that are about to be deleted.
100 SmallVector<MachineInstr*, 8> DeadDefs;
102 /// Recursively eliminate dead defs in DeadDefs.
103 void eliminateDeadDefs();
105 /// LiveRangeEdit callback.
106 void LRE_WillEraseInstruction(MachineInstr *MI);
108 /// joinAllIntervals - join compatible live intervals
109 void joinAllIntervals();
111 /// copyCoalesceInMBB - Coalesce copies in the specified MBB, putting
112 /// copies that cannot yet be coalesced into WorkList.
113 void copyCoalesceInMBB(MachineBasicBlock *MBB);
115 /// copyCoalesceWorkList - Try to coalesce all copies in WorkList after
116 /// position From. Return true if any progress was made.
117 bool copyCoalesceWorkList(unsigned From = 0);
119 /// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
120 /// which are the src/dst of the copy instruction CopyMI. This returns
121 /// true if the copy was successfully coalesced away. If it is not
122 /// currently possible to coalesce this interval, but it may be possible if
123 /// other things get coalesced, then it returns true by reference in
125 bool joinCopy(MachineInstr *TheCopy, bool &Again);
127 /// joinIntervals - Attempt to join these two intervals. On failure, this
128 /// returns false. The output "SrcInt" will not have been modified, so we
129 /// can use this information below to update aliases.
130 bool joinIntervals(CoalescerPair &CP);
132 /// Attempt joining with a reserved physreg.
133 bool joinReservedPhysReg(CoalescerPair &CP);
135 /// adjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
136 /// the source value number is defined by a copy from the destination reg
137 /// see if we can merge these two destination reg valno# into a single
138 /// value number, eliminating a copy.
139 bool adjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
141 /// hasOtherReachingDefs - Return true if there are definitions of IntB
142 /// other than BValNo val# that can reach uses of AValno val# of IntA.
143 bool hasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
144 VNInfo *AValNo, VNInfo *BValNo);
146 /// removeCopyByCommutingDef - We found a non-trivially-coalescable copy.
147 /// If the source value number is defined by a commutable instruction and
148 /// its other operand is coalesced to the copy dest register, see if we
149 /// can transform the copy into a noop by commuting the definition.
150 bool removeCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
152 /// reMaterializeTrivialDef - If the source of a copy is defined by a
153 /// trivial computation, replace the copy by rematerialize the definition.
154 bool reMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg,
155 MachineInstr *CopyMI);
157 /// canJoinPhys - Return true if a physreg copy should be joined.
158 bool canJoinPhys(CoalescerPair &CP);
160 /// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
161 /// update the subregister number if it is not zero. If DstReg is a
162 /// physical register and the existing subregister number of the def / use
163 /// being updated is not zero, make sure to set it to the correct physical
165 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
167 /// removeDeadDef - If a def of a live interval is now determined dead,
168 /// remove the val# it defines. If the live interval becomes empty, remove
170 bool removeDeadDef(LiveInterval &li, MachineInstr *DefMI);
172 /// markAsJoined - Remember that CopyMI has already been joined.
173 void markAsJoined(MachineInstr *CopyMI);
175 /// eliminateUndefCopy - Handle copies of undef values.
176 bool eliminateUndefCopy(MachineInstr *CopyMI, const CoalescerPair &CP);
179 static char ID; // Class identification, replacement for typeinfo
180 RegisterCoalescer() : MachineFunctionPass(ID) {
181 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
184 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
186 virtual void releaseMemory();
188 /// runOnMachineFunction - pass entry point
189 virtual bool runOnMachineFunction(MachineFunction&);
191 /// print - Implement the dump method.
192 virtual void print(raw_ostream &O, const Module* = 0) const;
194 } /// end anonymous namespace
196 char &llvm::RegisterCoalescerID = RegisterCoalescer::ID;
198 INITIALIZE_PASS_BEGIN(RegisterCoalescer, "simple-register-coalescing",
199 "Simple Register Coalescing", false, false)
200 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
201 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
202 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
203 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
204 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
205 INITIALIZE_PASS_END(RegisterCoalescer, "simple-register-coalescing",
206 "Simple Register Coalescing", false, false)
208 char RegisterCoalescer::ID = 0;
210 static unsigned compose(const TargetRegisterInfo &tri, unsigned a, unsigned b) {
213 return tri.composeSubRegIndices(a, b);
216 static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI,
217 unsigned &Src, unsigned &Dst,
218 unsigned &SrcSub, unsigned &DstSub) {
220 Dst = MI->getOperand(0).getReg();
221 DstSub = MI->getOperand(0).getSubReg();
222 Src = MI->getOperand(1).getReg();
223 SrcSub = MI->getOperand(1).getSubReg();
224 } else if (MI->isSubregToReg()) {
225 Dst = MI->getOperand(0).getReg();
226 DstSub = compose(tri, MI->getOperand(0).getSubReg(),
227 MI->getOperand(3).getImm());
228 Src = MI->getOperand(2).getReg();
229 SrcSub = MI->getOperand(2).getSubReg();
235 bool CoalescerPair::setRegisters(const MachineInstr *MI) {
239 Flipped = CrossClass = false;
241 unsigned Src, Dst, SrcSub, DstSub;
242 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
244 Partial = SrcSub || DstSub;
246 // If one register is a physreg, it must be Dst.
247 if (TargetRegisterInfo::isPhysicalRegister(Src)) {
248 if (TargetRegisterInfo::isPhysicalRegister(Dst))
251 std::swap(SrcSub, DstSub);
255 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
257 if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
258 // Eliminate DstSub on a physreg.
260 Dst = TRI.getSubReg(Dst, DstSub);
261 if (!Dst) return false;
265 // Eliminate SrcSub by picking a corresponding Dst superregister.
267 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
268 if (!Dst) return false;
270 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
274 // Both registers are virtual.
275 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
276 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
278 // Both registers have subreg indices.
279 if (SrcSub && DstSub) {
280 // Copies between different sub-registers are never coalescable.
281 if (Src == Dst && SrcSub != DstSub)
284 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
289 // SrcReg will be merged with a sub-register of DstReg.
291 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
293 // DstReg will be merged with a sub-register of SrcReg.
295 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
297 // This is a straight copy without sub-registers.
298 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
301 // The combined constraint may be impossible to satisfy.
305 // Prefer SrcReg to be a sub-register of DstReg.
306 // FIXME: Coalescer should support subregs symmetrically.
307 if (DstIdx && !SrcIdx) {
309 std::swap(SrcIdx, DstIdx);
313 CrossClass = NewRC != DstRC || NewRC != SrcRC;
315 // Check our invariants
316 assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual");
317 assert(!(TargetRegisterInfo::isPhysicalRegister(Dst) && DstSub) &&
318 "Cannot have a physical SubIdx");
324 bool CoalescerPair::flip() {
325 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
327 std::swap(SrcReg, DstReg);
328 std::swap(SrcIdx, DstIdx);
333 bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
336 unsigned Src, Dst, SrcSub, DstSub;
337 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
340 // Find the virtual register that is SrcReg.
343 std::swap(SrcSub, DstSub);
344 } else if (Src != SrcReg) {
348 // Now check that Dst matches DstReg.
349 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
350 if (!TargetRegisterInfo::isPhysicalRegister(Dst))
352 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.");
353 // DstSub could be set for a physreg from INSERT_SUBREG.
355 Dst = TRI.getSubReg(Dst, DstSub);
358 return DstReg == Dst;
359 // This is a partial register copy. Check that the parts match.
360 return TRI.getSubReg(DstReg, SrcSub) == Dst;
362 // DstReg is virtual.
365 // Registers match, do the subregisters line up?
366 return compose(TRI, SrcIdx, SrcSub) == compose(TRI, DstIdx, DstSub);
370 void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const {
371 AU.setPreservesCFG();
372 AU.addRequired<AliasAnalysis>();
373 AU.addRequired<LiveIntervals>();
374 AU.addPreserved<LiveIntervals>();
375 AU.addRequired<LiveDebugVariables>();
376 AU.addPreserved<LiveDebugVariables>();
377 AU.addPreserved<SlotIndexes>();
378 AU.addRequired<MachineLoopInfo>();
379 AU.addPreserved<MachineLoopInfo>();
380 AU.addPreservedID(MachineDominatorsID);
381 MachineFunctionPass::getAnalysisUsage(AU);
384 void RegisterCoalescer::markAsJoined(MachineInstr *CopyMI) {
385 /// Joined copies are not deleted immediately, but kept in JoinedCopies.
386 JoinedCopies.insert(CopyMI);
388 /// Mark all register operands of CopyMI as <undef> so they won't affect dead
389 /// code elimination.
390 for (MachineInstr::mop_iterator I = CopyMI->operands_begin(),
391 E = CopyMI->operands_end(); I != E; ++I)
396 void RegisterCoalescer::eliminateDeadDefs() {
397 SmallVector<LiveInterval*, 8> NewRegs;
398 LiveRangeEdit(0, NewRegs, *MF, *LIS, 0, this).eliminateDeadDefs(DeadDefs);
401 // Callback from eliminateDeadDefs().
402 void RegisterCoalescer::LRE_WillEraseInstruction(MachineInstr *MI) {
403 // MI may be in WorkList. Make sure we don't visit it.
404 ErasedInstrs.insert(MI);
407 /// adjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
408 /// being the source and IntB being the dest, thus this defines a value number
409 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
410 /// see if we can merge these two pieces of B into a single value number,
411 /// eliminating a copy. For example:
415 /// B1 = A3 <- this copy
417 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
418 /// value number to be replaced with B0 (which simplifies the B liveinterval).
420 /// This returns true if an interval was modified.
422 bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP,
423 MachineInstr *CopyMI) {
424 assert(!CP.isPartial() && "This doesn't work for partial copies.");
426 // Bail if there is no dst interval - can happen when merging physical subreg
428 if (!LIS->hasInterval(CP.getDstReg()))
432 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
434 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
435 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
437 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
438 // the example above.
439 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
440 if (BLR == IntB.end()) return false;
441 VNInfo *BValNo = BLR->valno;
443 // Get the location that B is defined at. Two options: either this value has
444 // an unknown definition point or it is defined at CopyIdx. If unknown, we
446 if (BValNo->def != CopyIdx) return false;
448 // AValNo is the value number in A that defines the copy, A3 in the example.
449 SlotIndex CopyUseIdx = CopyIdx.getRegSlot(true);
450 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
451 // The live range might not exist after fun with physreg coalescing.
452 if (ALR == IntA.end()) return false;
453 VNInfo *AValNo = ALR->valno;
455 // If AValNo is defined as a copy from IntB, we can potentially process this.
456 // Get the instruction that defines this value number.
457 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
458 if (!CP.isCoalescable(ACopyMI))
461 // Get the LiveRange in IntB that this value number starts with.
462 LiveInterval::iterator ValLR =
463 IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot());
464 if (ValLR == IntB.end())
467 // Make sure that the end of the live range is inside the same block as
469 MachineInstr *ValLREndInst =
470 LIS->getInstructionFromIndex(ValLR->end.getPrevSlot());
471 if (!ValLREndInst || ValLREndInst->getParent() != CopyMI->getParent())
474 // Okay, we now know that ValLR ends in the same block that the CopyMI
475 // live-range starts. If there are no intervening live ranges between them in
476 // IntB, we can merge them.
477 if (ValLR+1 != BLR) return false;
479 // If a live interval is a physical register, conservatively check if any
480 // of its aliases is overlapping the live interval of the virtual register.
481 // If so, do not coalesce.
482 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
483 for (const uint16_t *AS = TRI->getAliasSet(IntB.reg); *AS; ++AS)
484 if (LIS->hasInterval(*AS) && IntA.overlaps(LIS->getInterval(*AS))) {
486 dbgs() << "\t\tInterfere with alias ";
487 LIS->getInterval(*AS).print(dbgs(), TRI);
494 dbgs() << "Extending: ";
495 IntB.print(dbgs(), TRI);
498 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
499 // We are about to delete CopyMI, so need to remove it as the 'instruction
500 // that defines this value #'. Update the valnum with the new defining
502 BValNo->def = FillerStart;
504 // Okay, we can merge them. We need to insert a new liverange:
505 // [ValLR.end, BLR.begin) of either value number, then we merge the
506 // two value numbers.
507 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
509 // If the IntB live range is assigned to a physical register, and if that
510 // physreg has sub-registers, update their live intervals as well.
511 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
512 for (const uint16_t *SR = TRI->getSubRegisters(IntB.reg); *SR; ++SR) {
513 if (!LIS->hasInterval(*SR))
515 LiveInterval &SRLI = LIS->getInterval(*SR);
516 SRLI.addRange(LiveRange(FillerStart, FillerEnd,
517 SRLI.getNextValue(FillerStart,
518 LIS->getVNInfoAllocator())));
522 // Okay, merge "B1" into the same value number as "B0".
523 if (BValNo != ValLR->valno) {
524 // If B1 is killed by a PHI, then the merged live range must also be killed
525 // by the same PHI, as B0 and B1 can not overlap.
526 bool HasPHIKill = BValNo->hasPHIKill();
527 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
529 ValLR->valno->setHasPHIKill(true);
532 dbgs() << " result = ";
533 IntB.print(dbgs(), TRI);
537 // If the source instruction was killing the source register before the
538 // merge, unset the isKill marker given the live range has been extended.
539 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
541 ValLREndInst->getOperand(UIdx).setIsKill(false);
544 // Rewrite the copy. If the copy instruction was killing the destination
545 // register before the merge, find the last use and trim the live range. That
546 // will also add the isKill marker.
547 CopyMI->substituteRegister(IntA.reg, IntB.reg, 0, *TRI);
548 if (ALR->end == CopyIdx)
549 LIS->shrinkToUses(&IntA);
555 /// hasOtherReachingDefs - Return true if there are definitions of IntB
556 /// other than BValNo val# that can reach uses of AValno val# of IntA.
557 bool RegisterCoalescer::hasOtherReachingDefs(LiveInterval &IntA,
561 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
563 if (AI->valno != AValNo) continue;
564 LiveInterval::Ranges::iterator BI =
565 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
566 if (BI != IntB.ranges.begin())
568 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
569 if (BI->valno == BValNo)
571 if (BI->start <= AI->start && BI->end > AI->start)
573 if (BI->start > AI->start && BI->start < AI->end)
580 /// removeCopyByCommutingDef - We found a non-trivially-coalescable copy with
581 /// IntA being the source and IntB being the dest, thus this defines a value
582 /// number in IntB. If the source value number (in IntA) is defined by a
583 /// commutable instruction and its other operand is coalesced to the copy dest
584 /// register, see if we can transform the copy into a noop by commuting the
585 /// definition. For example,
587 /// A3 = op A2 B0<kill>
589 /// B1 = A3 <- this copy
591 /// = op A3 <- more uses
595 /// B2 = op B0 A2<kill>
597 /// B1 = B2 <- now an identify copy
599 /// = op B2 <- more uses
601 /// This returns true if an interval was modified.
603 bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
604 MachineInstr *CopyMI) {
605 // FIXME: For now, only eliminate the copy by commuting its def when the
606 // source register is a virtual register. We want to guard against cases
607 // where the copy is a back edge copy and commuting the def lengthen the
608 // live interval of the source register to the entire loop.
609 if (CP.isPhys() && CP.isFlipped())
612 // Bail if there is no dst interval.
613 if (!LIS->hasInterval(CP.getDstReg()))
616 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
619 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
621 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
623 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
624 // the example above.
625 VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx);
626 if (!BValNo || BValNo->def != CopyIdx)
629 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
631 // AValNo is the value number in A that defines the copy, A3 in the example.
632 VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getRegSlot(true));
633 assert(AValNo && "COPY source not live");
635 // If other defs can reach uses of this def, then it's not safe to perform
637 if (AValNo->isPHIDef() || AValNo->isUnused() || AValNo->hasPHIKill())
639 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
642 if (!DefMI->isCommutable())
644 // If DefMI is a two-address instruction then commuting it will change the
645 // destination register.
646 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
647 assert(DefIdx != -1);
649 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
651 unsigned Op1, Op2, NewDstIdx;
652 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
656 else if (Op2 == UseOpIdx)
661 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
662 unsigned NewReg = NewDstMO.getReg();
663 if (NewReg != IntB.reg || !NewDstMO.isKill())
666 // Make sure there are no other definitions of IntB that would reach the
667 // uses which the new definition can reach.
668 if (hasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
671 // Abort if the aliases of IntB.reg have values that are not simply the
672 // clobbers from the superreg.
673 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
674 for (const uint16_t *AS = TRI->getAliasSet(IntB.reg); *AS; ++AS)
675 if (LIS->hasInterval(*AS) &&
676 hasOtherReachingDefs(IntA, LIS->getInterval(*AS), AValNo, 0))
679 // If some of the uses of IntA.reg is already coalesced away, return false.
680 // It's not possible to determine whether it's safe to perform the coalescing.
681 for (MachineRegisterInfo::use_nodbg_iterator UI =
682 MRI->use_nodbg_begin(IntA.reg),
683 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
684 MachineInstr *UseMI = &*UI;
685 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
686 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
687 if (ULR == IntA.end())
689 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
693 DEBUG(dbgs() << "\tremoveCopyByCommutingDef: " << AValNo->def << '\t'
696 // At this point we have decided that it is legal to do this
697 // transformation. Start by commuting the instruction.
698 MachineBasicBlock *MBB = DefMI->getParent();
699 MachineInstr *NewMI = TII->commuteInstruction(DefMI);
702 if (TargetRegisterInfo::isVirtualRegister(IntA.reg) &&
703 TargetRegisterInfo::isVirtualRegister(IntB.reg) &&
704 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
706 if (NewMI != DefMI) {
707 LIS->ReplaceMachineInstrInMaps(DefMI, NewMI);
708 MachineBasicBlock::iterator Pos = DefMI;
709 MBB->insert(Pos, NewMI);
712 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
713 NewMI->getOperand(OpIdx).setIsKill();
715 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
724 // Update uses of IntA of the specific Val# with IntB.
725 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg),
726 UE = MRI->use_end(); UI != UE;) {
727 MachineOperand &UseMO = UI.getOperand();
728 MachineInstr *UseMI = &*UI;
730 if (JoinedCopies.count(UseMI))
732 if (UseMI->isDebugValue()) {
733 // FIXME These don't have an instruction index. Not clear we have enough
734 // info to decide whether to do this replacement or not. For now do it.
735 UseMO.setReg(NewReg);
738 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
739 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
740 if (ULR == IntA.end() || ULR->valno != AValNo)
742 if (TargetRegisterInfo::isPhysicalRegister(NewReg))
743 UseMO.substPhysReg(NewReg, *TRI);
745 UseMO.setReg(NewReg);
748 if (!UseMI->isCopy())
750 if (UseMI->getOperand(0).getReg() != IntB.reg ||
751 UseMI->getOperand(0).getSubReg())
754 // This copy will become a noop. If it's defining a new val#, merge it into
756 SlotIndex DefIdx = UseIdx.getRegSlot();
757 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
760 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
761 assert(DVNI->def == DefIdx);
762 BValNo = IntB.MergeValueNumberInto(BValNo, DVNI);
766 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
768 VNInfo *ValNo = BValNo;
769 ValNo->def = AValNo->def;
770 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
772 if (AI->valno != AValNo) continue;
773 IntB.addRange(LiveRange(AI->start, AI->end, ValNo));
775 DEBUG(dbgs() << "\t\textended: " << IntB << '\n');
777 IntA.removeValNo(AValNo);
778 DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n');
783 /// reMaterializeTrivialDef - If the source of a copy is defined by a trivial
784 /// computation, replace the copy by rematerialize the definition.
785 bool RegisterCoalescer::reMaterializeTrivialDef(LiveInterval &SrcInt,
787 MachineInstr *CopyMI) {
788 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(true);
789 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
790 assert(SrcLR != SrcInt.end() && "Live range not found!");
791 VNInfo *ValNo = SrcLR->valno;
792 if (ValNo->isPHIDef() || ValNo->isUnused())
794 MachineInstr *DefMI = LIS->getInstructionFromIndex(ValNo->def);
797 assert(DefMI && "Defining instruction disappeared");
798 if (!DefMI->isAsCheapAsAMove())
800 if (!TII->isTriviallyReMaterializable(DefMI, AA))
802 bool SawStore = false;
803 if (!DefMI->isSafeToMove(TII, AA, SawStore))
805 const MCInstrDesc &MCID = DefMI->getDesc();
806 if (MCID.getNumDefs() != 1)
808 if (!DefMI->isImplicitDef()) {
809 // Make sure the copy destination register class fits the instruction
810 // definition register class. The mismatch can happen as a result of earlier
811 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
812 const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI, *MF);
813 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
814 if (MRI->getRegClass(DstReg) != RC)
816 } else if (!RC->contains(DstReg))
820 MachineBasicBlock *MBB = CopyMI->getParent();
821 MachineBasicBlock::iterator MII =
822 llvm::next(MachineBasicBlock::iterator(CopyMI));
823 TII->reMaterialize(*MBB, MII, DstReg, 0, DefMI, *TRI);
824 MachineInstr *NewMI = prior(MII);
826 // NewMI may have dead implicit defs (E.g. EFLAGS for MOV<bits>r0 on X86).
827 // We need to remember these so we can add intervals once we insert
828 // NewMI into SlotIndexes.
829 SmallVector<unsigned, 4> NewMIImplDefs;
830 for (unsigned i = NewMI->getDesc().getNumOperands(),
831 e = NewMI->getNumOperands(); i != e; ++i) {
832 MachineOperand &MO = NewMI->getOperand(i);
834 assert(MO.isDef() && MO.isImplicit() && MO.isDead() &&
835 TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
836 NewMIImplDefs.push_back(MO.getReg());
840 // CopyMI may have implicit operands, transfer them over to the newly
841 // rematerialized instruction. And update implicit def interval valnos.
842 for (unsigned i = CopyMI->getDesc().getNumOperands(),
843 e = CopyMI->getNumOperands(); i != e; ++i) {
844 MachineOperand &MO = CopyMI->getOperand(i);
846 assert(MO.isImplicit() && "No explicit operands after implict operands.");
847 // Discard VReg implicit defs.
848 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
849 NewMI->addOperand(MO);
854 LIS->ReplaceMachineInstrInMaps(CopyMI, NewMI);
856 SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
857 for (unsigned i = 0, e = NewMIImplDefs.size(); i != e; ++i) {
858 unsigned reg = NewMIImplDefs[i];
859 LiveInterval &li = LIS->getInterval(reg);
860 VNInfo *DeadDefVN = li.getNextValue(NewMIIdx.getRegSlot(),
861 LIS->getVNInfoAllocator());
862 LiveRange lr(NewMIIdx.getRegSlot(), NewMIIdx.getDeadSlot(), DeadDefVN);
866 CopyMI->eraseFromParent();
867 ErasedInstrs.insert(CopyMI);
868 ReMatDefs.insert(DefMI);
869 DEBUG(dbgs() << "Remat: " << *NewMI);
872 // The source interval can become smaller because we removed a use.
873 LIS->shrinkToUses(&SrcInt);
878 /// eliminateUndefCopy - ProcessImpicitDefs may leave some copies of <undef>
879 /// values, it only removes local variables. When we have a copy like:
881 /// %vreg1 = COPY %vreg2<undef>
883 /// We delete the copy and remove the corresponding value number from %vreg1.
884 /// Any uses of that value number are marked as <undef>.
885 bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI,
886 const CoalescerPair &CP) {
887 SlotIndex Idx = LIS->getInstructionIndex(CopyMI);
888 LiveInterval *SrcInt = &LIS->getInterval(CP.getSrcReg());
889 if (SrcInt->liveAt(Idx))
891 LiveInterval *DstInt = &LIS->getInterval(CP.getDstReg());
892 if (DstInt->liveAt(Idx))
895 // No intervals are live-in to CopyMI - it is undef.
900 VNInfo *DeadVNI = DstInt->getVNInfoAt(Idx.getRegSlot());
901 assert(DeadVNI && "No value defined in DstInt");
902 DstInt->removeValNo(DeadVNI);
904 // Find new undef uses.
905 for (MachineRegisterInfo::reg_nodbg_iterator
906 I = MRI->reg_nodbg_begin(DstInt->reg), E = MRI->reg_nodbg_end();
908 MachineOperand &MO = I.getOperand();
909 if (MO.isDef() || MO.isUndef())
911 MachineInstr *MI = MO.getParent();
912 SlotIndex Idx = LIS->getInstructionIndex(MI);
913 if (DstInt->liveAt(Idx))
916 DEBUG(dbgs() << "\tnew undef: " << Idx << '\t' << *MI);
921 /// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
922 /// update the subregister number if it is not zero. If DstReg is a
923 /// physical register and the existing subregister number of the def / use
924 /// being updated is not zero, make sure to set it to the correct physical
926 void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg,
929 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
930 LiveInterval &DstInt = LIS->getInterval(DstReg);
932 // Update LiveDebugVariables.
933 LDV->renameRegister(SrcReg, DstReg, SubIdx);
935 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg);
936 MachineInstr *UseMI = I.skipInstruction();) {
937 bool AlreadyJoined = JoinedCopies.count(UseMI);
938 SmallVector<unsigned,8> Ops;
940 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
942 // If SrcReg wasn't read, it may still be the case that DstReg is live-in
943 // because SrcReg is a sub-register.
944 if (!Reads && SubIdx && !AlreadyJoined)
945 Reads = DstInt.liveAt(LIS->getInstructionIndex(UseMI));
947 // Replace SrcReg with DstReg in all UseMI operands.
948 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
949 MachineOperand &MO = UseMI->getOperand(Ops[i]);
951 // Adjust <undef> flags in case of sub-register joins. We don't want to
952 // turn a full def into a read-modify-write sub-register def and vice
954 if (SubIdx && !AlreadyJoined && MO.isDef())
955 MO.setIsUndef(!Reads);
958 MO.substPhysReg(DstReg, *TRI);
960 MO.substVirtReg(DstReg, SubIdx, *TRI);
963 // This instruction is a copy that will be removed.
968 dbgs() << "\t\tupdated: ";
969 if (!UseMI->isDebugValue())
970 dbgs() << LIS->getInstructionIndex(UseMI) << "\t";
976 /// removeIntervalIfEmpty - Check if the live interval of a physical register
977 /// is empty, if so remove it and also remove the empty intervals of its
978 /// sub-registers. Return true if live interval is removed.
979 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *LIS,
980 const TargetRegisterInfo *TRI) {
982 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
983 for (const uint16_t* SR = TRI->getSubRegisters(li.reg); *SR; ++SR) {
984 if (!LIS->hasInterval(*SR))
986 LiveInterval &sli = LIS->getInterval(*SR);
988 LIS->removeInterval(*SR);
990 LIS->removeInterval(li.reg);
996 /// removeDeadDef - If a def of a live interval is now determined dead, remove
997 /// the val# it defines. If the live interval becomes empty, remove it as well.
998 bool RegisterCoalescer::removeDeadDef(LiveInterval &li, MachineInstr *DefMI) {
999 SlotIndex DefIdx = LIS->getInstructionIndex(DefMI).getRegSlot();
1000 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
1001 if (DefIdx != MLR->valno->def)
1003 li.removeValNo(MLR->valno);
1004 return removeIntervalIfEmpty(li, LIS, TRI);
1007 /// canJoinPhys - Return true if a copy involving a physreg should be joined.
1008 bool RegisterCoalescer::canJoinPhys(CoalescerPair &CP) {
1009 /// Always join simple intervals that are defined by a single copy from a
1010 /// reserved register. This doesn't increase register pressure, so it is
1011 /// always beneficial.
1012 if (!RegClassInfo.isReserved(CP.getDstReg())) {
1013 DEBUG(dbgs() << "\tCan only merge into reserved registers.\n");
1017 LiveInterval &JoinVInt = LIS->getInterval(CP.getSrcReg());
1018 if (CP.isFlipped() && JoinVInt.containsOneValue())
1021 DEBUG(dbgs() << "\tCannot join defs into reserved register.\n");
1025 /// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1026 /// which are the src/dst of the copy instruction CopyMI. This returns true
1027 /// if the copy was successfully coalesced away. If it is not currently
1028 /// possible to coalesce this interval, but it may be possible if other
1029 /// things get coalesced, then it returns true by reference in 'Again'.
1030 bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
1033 if (JoinedCopies.count(CopyMI))
1034 return false; // Already done.
1036 DEBUG(dbgs() << LIS->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
1038 CoalescerPair CP(*TII, *TRI);
1039 if (!CP.setRegisters(CopyMI)) {
1040 DEBUG(dbgs() << "\tNot coalescable.\n");
1044 // Dead code elimination. This really should be handled by MachineDCE, but
1045 // sometimes dead copies slip through, and we can't generate invalid live
1047 if (!CP.isPhys() && CopyMI->allDefsAreDead()) {
1048 DEBUG(dbgs() << "\tCopy is dead.\n");
1049 DeadDefs.push_back(CopyMI);
1050 eliminateDeadDefs();
1054 // If they are already joined we continue.
1055 if (CP.getSrcReg() == CP.getDstReg()) {
1056 DEBUG(dbgs() << "\tCopy already coalesced.\n");
1057 LIS->RemoveMachineInstrFromMaps(CopyMI);
1058 CopyMI->eraseFromParent();
1059 return false; // Not coalescable.
1062 // Eliminate undefs.
1063 if (!CP.isPhys() && eliminateUndefCopy(CopyMI, CP)) {
1064 DEBUG(dbgs() << "\tEliminated copy of <undef> value.\n");
1065 LIS->RemoveMachineInstrFromMaps(CopyMI);
1066 CopyMI->eraseFromParent();
1067 return false; // Not coalescable.
1070 // Enforce policies.
1072 DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI)
1073 << " with " << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx())
1075 if (!canJoinPhys(CP)) {
1076 // Before giving up coalescing, if definition of source is defined by
1077 // trivial computation, try rematerializing it.
1078 if (!CP.isFlipped() &&
1079 reMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()),
1080 CP.getDstReg(), CopyMI))
1086 dbgs() << "\tConsidering merging to " << CP.getNewRC()->getName()
1088 if (CP.getDstIdx() && CP.getSrcIdx())
1089 dbgs() << PrintReg(CP.getDstReg()) << " in "
1090 << TRI->getSubRegIndexName(CP.getDstIdx()) << " and "
1091 << PrintReg(CP.getSrcReg()) << " in "
1092 << TRI->getSubRegIndexName(CP.getSrcIdx()) << '\n';
1094 dbgs() << PrintReg(CP.getSrcReg(), TRI) << " in "
1095 << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n';
1098 // When possible, let DstReg be the larger interval.
1099 if (!CP.isPartial() && LIS->getInterval(CP.getSrcReg()).ranges.size() >
1100 LIS->getInterval(CP.getDstReg()).ranges.size())
1104 // Okay, attempt to join these two intervals. On failure, this returns false.
1105 // Otherwise, if one of the intervals being joined is a physreg, this method
1106 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1107 // been modified, so we can use this information below to update aliases.
1108 if (!joinIntervals(CP)) {
1109 // Coalescing failed.
1111 // If definition of source is defined by trivial computation, try
1112 // rematerializing it.
1113 if (!CP.isFlipped() &&
1114 reMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()),
1115 CP.getDstReg(), CopyMI))
1118 // If we can eliminate the copy without merging the live ranges, do so now.
1119 if (!CP.isPartial()) {
1120 if (adjustCopiesBackFrom(CP, CopyMI) ||
1121 removeCopyByCommutingDef(CP, CopyMI)) {
1122 markAsJoined(CopyMI);
1123 DEBUG(dbgs() << "\tTrivial!\n");
1128 // Otherwise, we are unable to join the intervals.
1129 DEBUG(dbgs() << "\tInterference!\n");
1130 Again = true; // May be possible to coalesce later.
1134 // Coalescing to a virtual register that is of a sub-register class of the
1135 // other. Make sure the resulting register is set to the right register class.
1136 if (CP.isCrossClass()) {
1138 MRI->setRegClass(CP.getDstReg(), CP.getNewRC());
1141 // Remember to delete the copy instruction.
1142 markAsJoined(CopyMI);
1144 // Rewrite all SrcReg operands to DstReg.
1145 // Also update DstReg operands to include DstIdx if it is set.
1147 updateRegDefsUses(CP.getDstReg(), CP.getDstReg(), CP.getDstIdx());
1148 updateRegDefsUses(CP.getSrcReg(), CP.getDstReg(), CP.getSrcIdx());
1150 // SrcReg is guaranteed to be the register whose live interval that is
1152 LIS->removeInterval(CP.getSrcReg());
1154 // Update regalloc hint.
1155 TRI->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
1158 LiveInterval &DstInt = LIS->getInterval(CP.getDstReg());
1159 dbgs() << "\tJoined. Result = ";
1160 DstInt.print(dbgs(), TRI);
1168 /// Attempt joining with a reserved physreg.
1169 bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
1170 assert(CP.isPhys() && "Must be a physreg copy");
1171 assert(RegClassInfo.isReserved(CP.getDstReg()) && "Not a reserved register");
1172 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1173 DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), TRI); dbgs() << "\n"; });
1175 assert(CP.isFlipped() && RHS.containsOneValue() &&
1176 "Invalid join with reserved register");
1178 // Optimization for reserved registers like ESP. We can only merge with a
1179 // reserved physreg if RHS has a single value that is a copy of CP.DstReg().
1180 // The live range of the reserved register will look like a set of dead defs
1181 // - we don't properly track the live range of reserved registers.
1183 // Deny any overlapping intervals. This depends on all the reserved
1184 // register live ranges to look like dead defs.
1185 for (const uint16_t *AS = TRI->getOverlaps(CP.getDstReg()); *AS; ++AS) {
1186 if (!LIS->hasInterval(*AS)) {
1187 // Make sure at least DstReg itself exists before attempting a join.
1188 if (*AS == CP.getDstReg())
1189 LIS->getOrCreateInterval(CP.getDstReg());
1192 if (RHS.overlaps(LIS->getInterval(*AS))) {
1193 DEBUG(dbgs() << "\t\tInterference: " << PrintReg(*AS, TRI) << '\n');
1197 // Skip any value computations, we are not adding new values to the
1198 // reserved register. Also skip merging the live ranges, the reserved
1199 // register live range doesn't need to be accurate as long as all the
1204 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1205 /// compute what the resultant value numbers for each value in the input two
1206 /// ranges will be. This is complicated by copies between the two which can
1207 /// and will commonly cause multiple value numbers to be merged into one.
1209 /// VN is the value number that we're trying to resolve. InstDefiningValue
1210 /// keeps track of the new InstDefiningValue assignment for the result
1211 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1212 /// whether a value in this or other is a copy from the opposite set.
1213 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1214 /// already been assigned.
1216 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1217 /// contains the value number the copy is from.
1219 static unsigned ComputeUltimateVN(VNInfo *VNI,
1220 SmallVector<VNInfo*, 16> &NewVNInfo,
1221 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1222 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1223 SmallVector<int, 16> &ThisValNoAssignments,
1224 SmallVector<int, 16> &OtherValNoAssignments) {
1225 unsigned VN = VNI->id;
1227 // If the VN has already been computed, just return it.
1228 if (ThisValNoAssignments[VN] >= 0)
1229 return ThisValNoAssignments[VN];
1230 assert(ThisValNoAssignments[VN] != -2 && "Cyclic value numbers");
1232 // If this val is not a copy from the other val, then it must be a new value
1233 // number in the destination.
1234 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1235 if (I == ThisFromOther.end()) {
1236 NewVNInfo.push_back(VNI);
1237 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1239 VNInfo *OtherValNo = I->second;
1241 // Otherwise, this *is* a copy from the RHS. If the other side has already
1242 // been computed, return it.
1243 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1244 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1246 // Mark this value number as currently being computed, then ask what the
1247 // ultimate value # of the other value is.
1248 ThisValNoAssignments[VN] = -2;
1249 unsigned UltimateVN =
1250 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1251 OtherValNoAssignments, ThisValNoAssignments);
1252 return ThisValNoAssignments[VN] = UltimateVN;
1256 // Find out if we have something like
1259 // if so, we can pretend this is actually
1262 // which allows us to coalesce A and B.
1263 // VNI is the definition of B. LR is the life range of A that includes
1264 // the slot just before B. If we return true, we add "B = X" to DupCopies.
1265 // This implies that A dominates B.
1266 static bool RegistersDefinedFromSameValue(LiveIntervals &li,
1267 const TargetRegisterInfo &tri,
1271 SmallVector<MachineInstr*, 8> &DupCopies) {
1272 // FIXME: This is very conservative. For example, we don't handle
1273 // physical registers.
1275 MachineInstr *MI = li.getInstructionFromIndex(VNI->def);
1277 if (!MI || !MI->isFullCopy() || CP.isPartial() || CP.isPhys())
1280 unsigned Dst = MI->getOperand(0).getReg();
1281 unsigned Src = MI->getOperand(1).getReg();
1283 if (!TargetRegisterInfo::isVirtualRegister(Src) ||
1284 !TargetRegisterInfo::isVirtualRegister(Dst))
1287 unsigned A = CP.getDstReg();
1288 unsigned B = CP.getSrcReg();
1294 VNInfo *Other = LR->valno;
1295 const MachineInstr *OtherMI = li.getInstructionFromIndex(Other->def);
1297 if (!OtherMI || !OtherMI->isFullCopy())
1300 unsigned OtherDst = OtherMI->getOperand(0).getReg();
1301 unsigned OtherSrc = OtherMI->getOperand(1).getReg();
1303 if (!TargetRegisterInfo::isVirtualRegister(OtherSrc) ||
1304 !TargetRegisterInfo::isVirtualRegister(OtherDst))
1307 assert(OtherDst == B);
1309 if (Src != OtherSrc)
1312 // If the copies use two different value numbers of X, we cannot merge
1314 LiveInterval &SrcInt = li.getInterval(Src);
1315 // getVNInfoBefore returns NULL for undef copies. In this case, the
1316 // optimization is still safe.
1317 if (SrcInt.getVNInfoBefore(Other->def) != SrcInt.getVNInfoBefore(VNI->def))
1320 DupCopies.push_back(MI);
1325 /// joinIntervals - Attempt to join these two intervals. On failure, this
1327 bool RegisterCoalescer::joinIntervals(CoalescerPair &CP) {
1328 // Handle physreg joins separately.
1330 return joinReservedPhysReg(CP);
1332 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1333 DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), TRI); dbgs() << "\n"; });
1335 // Compute the final value assignment, assuming that the live ranges can be
1337 SmallVector<int, 16> LHSValNoAssignments;
1338 SmallVector<int, 16> RHSValNoAssignments;
1339 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
1340 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
1341 SmallVector<VNInfo*, 16> NewVNInfo;
1343 SmallVector<MachineInstr*, 8> DupCopies;
1345 LiveInterval &LHS = LIS->getOrCreateInterval(CP.getDstReg());
1346 DEBUG({ dbgs() << "\t\tLHS = "; LHS.print(dbgs(), TRI); dbgs() << "\n"; });
1348 // Loop over the value numbers of the LHS, seeing if any are defined from
1350 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1353 if (VNI->isUnused() || VNI->isPHIDef())
1355 MachineInstr *MI = LIS->getInstructionFromIndex(VNI->def);
1356 assert(MI && "Missing def");
1357 if (!MI->isCopyLike()) // Src not defined by a copy?
1360 // Figure out the value # from the RHS.
1361 LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1362 // The copy could be to an aliased physreg.
1365 // DstReg is known to be a register in the LHS interval. If the src is
1366 // from the RHS interval, we can use its value #.
1367 if (!CP.isCoalescable(MI) &&
1368 !RegistersDefinedFromSameValue(*LIS, *TRI, CP, VNI, lr, DupCopies))
1371 LHSValsDefinedFromRHS[VNI] = lr->valno;
1374 // Loop over the value numbers of the RHS, seeing if any are defined from
1376 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1379 if (VNI->isUnused() || VNI->isPHIDef())
1381 MachineInstr *MI = LIS->getInstructionFromIndex(VNI->def);
1382 assert(MI && "Missing def");
1383 if (!MI->isCopyLike()) // Src not defined by a copy?
1386 // Figure out the value # from the LHS.
1387 LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1388 // The copy could be to an aliased physreg.
1391 // DstReg is known to be a register in the RHS interval. If the src is
1392 // from the LHS interval, we can use its value #.
1393 if (!CP.isCoalescable(MI) &&
1394 !RegistersDefinedFromSameValue(*LIS, *TRI, CP, VNI, lr, DupCopies))
1397 RHSValsDefinedFromLHS[VNI] = lr->valno;
1400 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1401 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1402 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1404 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1407 unsigned VN = VNI->id;
1408 if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1410 ComputeUltimateVN(VNI, NewVNInfo,
1411 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1412 LHSValNoAssignments, RHSValNoAssignments);
1414 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1417 unsigned VN = VNI->id;
1418 if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1420 // If this value number isn't a copy from the LHS, it's a new number.
1421 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
1422 NewVNInfo.push_back(VNI);
1423 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
1427 ComputeUltimateVN(VNI, NewVNInfo,
1428 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1429 RHSValNoAssignments, LHSValNoAssignments);
1432 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1433 // interval lists to see if these intervals are coalescable.
1434 LiveInterval::const_iterator I = LHS.begin();
1435 LiveInterval::const_iterator IE = LHS.end();
1436 LiveInterval::const_iterator J = RHS.begin();
1437 LiveInterval::const_iterator JE = RHS.end();
1439 // Skip ahead until the first place of potential sharing.
1440 if (I != IE && J != JE) {
1441 if (I->start < J->start) {
1442 I = std::upper_bound(I, IE, J->start);
1443 if (I != LHS.begin()) --I;
1444 } else if (J->start < I->start) {
1445 J = std::upper_bound(J, JE, I->start);
1446 if (J != RHS.begin()) --J;
1450 while (I != IE && J != JE) {
1451 // Determine if these two live ranges overlap.
1453 if (I->start < J->start) {
1454 Overlaps = I->end > J->start;
1456 Overlaps = J->end > I->start;
1459 // If so, check value # info to determine if they are really different.
1461 // If the live range overlap will map to the same value number in the
1462 // result liverange, we can still coalesce them. If not, we can't.
1463 if (LHSValNoAssignments[I->valno->id] !=
1464 RHSValNoAssignments[J->valno->id])
1468 if (I->end < J->end)
1474 // Update kill info. Some live ranges are extended due to copy coalescing.
1475 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
1476 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
1477 VNInfo *VNI = I->first;
1478 unsigned LHSValID = LHSValNoAssignments[VNI->id];
1479 if (VNI->hasPHIKill())
1480 NewVNInfo[LHSValID]->setHasPHIKill(true);
1483 // Update kill info. Some live ranges are extended due to copy coalescing.
1484 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
1485 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
1486 VNInfo *VNI = I->first;
1487 unsigned RHSValID = RHSValNoAssignments[VNI->id];
1488 if (VNI->hasPHIKill())
1489 NewVNInfo[RHSValID]->setHasPHIKill(true);
1492 if (LHSValNoAssignments.empty())
1493 LHSValNoAssignments.push_back(-1);
1494 if (RHSValNoAssignments.empty())
1495 RHSValNoAssignments.push_back(-1);
1497 SmallVector<unsigned, 8> SourceRegisters;
1498 for (SmallVector<MachineInstr*, 8>::iterator I = DupCopies.begin(),
1499 E = DupCopies.end(); I != E; ++I) {
1500 MachineInstr *MI = *I;
1502 // We have pretended that the assignment to B in
1505 // was actually a copy from A. Now that we decided to coalesce A and B,
1506 // transform the code into
1509 // and mark the X as coalesced to keep the illusion.
1510 unsigned Src = MI->getOperand(1).getReg();
1511 SourceRegisters.push_back(Src);
1512 MI->getOperand(0).substVirtReg(Src, 0, *TRI);
1517 // If B = X was the last use of X in a liverange, we have to shrink it now
1518 // that B = X is gone.
1519 for (SmallVector<unsigned, 8>::iterator I = SourceRegisters.begin(),
1520 E = SourceRegisters.end(); I != E; ++I) {
1521 LIS->shrinkToUses(&LIS->getInterval(*I));
1524 // If we get here, we know that we can coalesce the live ranges. Ask the
1525 // intervals to coalesce themselves now.
1526 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
1532 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1533 // depth of the basic block (the unsigned), and then on the MBB number.
1534 struct DepthMBBCompare {
1535 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1536 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1537 // Deeper loops first
1538 if (LHS.first != RHS.first)
1539 return LHS.first > RHS.first;
1541 // Prefer blocks that are more connected in the CFG. This takes care of
1542 // the most difficult copies first while intervals are short.
1543 unsigned cl = LHS.second->pred_size() + LHS.second->succ_size();
1544 unsigned cr = RHS.second->pred_size() + RHS.second->succ_size();
1548 // As a last resort, sort by block number.
1549 return LHS.second->getNumber() < RHS.second->getNumber();
1554 // Try joining WorkList copies starting from index From.
1555 // Null out any successful joins.
1556 bool RegisterCoalescer::copyCoalesceWorkList(unsigned From) {
1557 assert(From <= WorkList.size() && "Out of range");
1558 bool Progress = false;
1559 for (unsigned i = From, e = WorkList.size(); i != e; ++i) {
1562 // Skip instruction pointers that have already been erased, for example by
1563 // dead code elimination.
1564 if (ErasedInstrs.erase(WorkList[i])) {
1569 bool Success = joinCopy(WorkList[i], Again);
1570 Progress |= Success;
1571 if (Success || !Again)
1578 RegisterCoalescer::copyCoalesceInMBB(MachineBasicBlock *MBB) {
1579 DEBUG(dbgs() << MBB->getName() << ":\n");
1581 // Collect all copy-like instructions in MBB. Don't start coalescing anything
1582 // yet, it might invalidate the iterator.
1583 const unsigned PrevSize = WorkList.size();
1584 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1586 if (MII->isCopyLike())
1587 WorkList.push_back(MII);
1589 // Try coalescing the collected copies immediately, and remove the nulls.
1590 // This prevents the WorkList from getting too large since most copies are
1591 // joinable on the first attempt.
1592 if (copyCoalesceWorkList(PrevSize))
1593 WorkList.erase(std::remove(WorkList.begin() + PrevSize, WorkList.end(),
1594 (MachineInstr*)0), WorkList.end());
1597 void RegisterCoalescer::joinAllIntervals() {
1598 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
1599 assert(WorkList.empty() && "Old data still around.");
1601 if (Loops->empty()) {
1602 // If there are no loops in the function, join intervals in function order.
1603 for (MachineFunction::iterator I = MF->begin(), E = MF->end();
1605 copyCoalesceInMBB(I);
1607 // Otherwise, join intervals in inner loops before other intervals.
1608 // Unfortunately we can't just iterate over loop hierarchy here because
1609 // there may be more MBB's than BB's. Collect MBB's for sorting.
1611 // Join intervals in the function prolog first. We want to join physical
1612 // registers with virtual registers before the intervals got too long.
1613 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1614 for (MachineFunction::iterator I = MF->begin(), E = MF->end();I != E;++I){
1615 MachineBasicBlock *MBB = I;
1616 MBBs.push_back(std::make_pair(Loops->getLoopDepth(MBB), I));
1619 // Sort by loop depth.
1620 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1622 // Finally, join intervals in loop nest order.
1623 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1624 copyCoalesceInMBB(MBBs[i].second);
1627 // Joining intervals can allow other intervals to be joined. Iteratively join
1628 // until we make no progress.
1629 while (copyCoalesceWorkList())
1633 void RegisterCoalescer::releaseMemory() {
1634 JoinedCopies.clear();
1635 ErasedInstrs.clear();
1641 bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
1643 MRI = &fn.getRegInfo();
1644 TM = &fn.getTarget();
1645 TRI = TM->getRegisterInfo();
1646 TII = TM->getInstrInfo();
1647 LIS = &getAnalysis<LiveIntervals>();
1648 LDV = &getAnalysis<LiveDebugVariables>();
1649 AA = &getAnalysis<AliasAnalysis>();
1650 Loops = &getAnalysis<MachineLoopInfo>();
1652 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
1653 << "********** Function: "
1654 << ((Value*)MF->getFunction())->getName() << '\n');
1656 if (VerifyCoalescing)
1657 MF->verify(this, "Before register coalescing");
1659 RegClassInfo.runOnMachineFunction(fn);
1661 // Join (coalesce) intervals if requested.
1662 if (EnableJoining) {
1665 dbgs() << "********** INTERVALS POST JOINING **********\n";
1666 for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end();
1668 I->second->print(dbgs(), TRI);
1674 // Perform a final pass over the instructions and compute spill weights
1675 // and remove identity moves.
1676 SmallVector<unsigned, 4> DeadDefs, InflateRegs;
1677 for (MachineFunction::iterator mbbi = MF->begin(), mbbe = MF->end();
1678 mbbi != mbbe; ++mbbi) {
1679 MachineBasicBlock* mbb = mbbi;
1680 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
1682 MachineInstr *MI = mii;
1683 if (JoinedCopies.count(MI)) {
1684 // Delete all coalesced copies.
1685 bool DoDelete = true;
1686 assert(MI->isCopyLike() && "Unrecognized copy instruction");
1687 unsigned SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
1688 unsigned DstReg = MI->getOperand(0).getReg();
1690 // Collect candidates for register class inflation.
1691 if (TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1692 RegClassInfo.isProperSubClass(MRI->getRegClass(SrcReg)))
1693 InflateRegs.push_back(SrcReg);
1694 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
1695 RegClassInfo.isProperSubClass(MRI->getRegClass(DstReg)))
1696 InflateRegs.push_back(DstReg);
1698 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
1699 MI->getNumOperands() > 2)
1700 // Do not delete extract_subreg, insert_subreg of physical
1701 // registers unless the definition is dead. e.g.
1702 // %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
1703 // or else the scavenger may complain. LowerSubregs will
1704 // delete them later.
1707 if (MI->allDefsAreDead()) {
1708 if (TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1709 LIS->hasInterval(SrcReg))
1710 LIS->shrinkToUses(&LIS->getInterval(SrcReg));
1714 // We need the instruction to adjust liveness, so make it a KILL.
1715 if (MI->isSubregToReg()) {
1716 MI->RemoveOperand(3);
1717 MI->RemoveOperand(1);
1719 MI->setDesc(TII->get(TargetOpcode::KILL));
1720 mii = llvm::next(mii);
1722 LIS->RemoveMachineInstrFromMaps(MI);
1723 mii = mbbi->erase(mii);
1729 // Now check if this is a remat'ed def instruction which is now dead.
1730 if (ReMatDefs.count(MI)) {
1732 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1733 const MachineOperand &MO = MI->getOperand(i);
1736 unsigned Reg = MO.getReg();
1739 DeadDefs.push_back(Reg);
1740 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1741 // Remat may also enable register class inflation.
1742 if (RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)))
1743 InflateRegs.push_back(Reg);
1747 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
1748 !MRI->use_nodbg_empty(Reg)) {
1754 while (!DeadDefs.empty()) {
1755 unsigned DeadDef = DeadDefs.back();
1756 DeadDefs.pop_back();
1757 removeDeadDef(LIS->getInterval(DeadDef), MI);
1759 LIS->RemoveMachineInstrFromMaps(mii);
1760 mii = mbbi->erase(mii);
1768 // Check for now unnecessary kill flags.
1769 if (LIS->isNotInMIMap(MI)) continue;
1770 SlotIndex DefIdx = LIS->getInstructionIndex(MI).getRegSlot();
1771 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1772 MachineOperand &MO = MI->getOperand(i);
1773 if (!MO.isReg() || !MO.isKill()) continue;
1774 unsigned reg = MO.getReg();
1775 if (!reg || !LIS->hasInterval(reg)) continue;
1776 if (!LIS->getInterval(reg).killedAt(DefIdx)) {
1777 MO.setIsKill(false);
1780 // When leaving a kill flag on a physreg, check if any subregs should
1782 if (!TargetRegisterInfo::isPhysicalRegister(reg))
1784 for (const uint16_t *SR = TRI->getSubRegisters(reg);
1785 unsigned S = *SR; ++SR)
1786 if (LIS->hasInterval(S) && LIS->getInterval(S).liveAt(DefIdx))
1787 MI->addRegisterDefined(S, TRI);
1792 // After deleting a lot of copies, register classes may be less constrained.
1793 // Removing sub-register opreands may alow GR32_ABCD -> GR32 and DPR_VFP2 ->
1795 array_pod_sort(InflateRegs.begin(), InflateRegs.end());
1796 InflateRegs.erase(std::unique(InflateRegs.begin(), InflateRegs.end()),
1798 DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size() << " regs.\n");
1799 for (unsigned i = 0, e = InflateRegs.size(); i != e; ++i) {
1800 unsigned Reg = InflateRegs[i];
1801 if (MRI->reg_nodbg_empty(Reg))
1803 if (MRI->recomputeRegClass(Reg, *TM)) {
1804 DEBUG(dbgs() << PrintReg(Reg) << " inflated to "
1805 << MRI->getRegClass(Reg)->getName() << '\n');
1812 if (VerifyCoalescing)
1813 MF->verify(this, "After register coalescing");
1817 /// print - Implement the dump method.
1818 void RegisterCoalescer::print(raw_ostream &O, const Module* m) const {