1 //===- RegisterCoalescer.cpp - Generic Register Coalescing Interface -------==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the generic RegisterCoalescer interface which
11 // is used as the common interface used by all clients and
12 // implementations of register coalescing.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "regalloc"
17 #include "RegisterCoalescer.h"
18 #include "llvm/ADT/OwningPtr.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
24 #include "llvm/CodeGen/LiveRangeEdit.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/CodeGen/RegisterClassInfo.h"
31 #include "llvm/CodeGen/VirtRegMap.h"
32 #include "llvm/IR/Value.h"
33 #include "llvm/Pass.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetSubtargetInfo.h"
46 STATISTIC(numJoins , "Number of interval joins performed");
47 STATISTIC(numCrossRCs , "Number of cross class joins performed");
48 STATISTIC(numCommutes , "Number of instruction commuting performed");
49 STATISTIC(numExtends , "Number of copies extended");
50 STATISTIC(NumReMats , "Number of instructions re-materialized");
51 STATISTIC(NumInflated , "Number of register classes inflated");
52 STATISTIC(NumLaneConflicts, "Number of dead lane conflicts tested");
53 STATISTIC(NumLaneResolves, "Number of dead lane conflicts resolved");
56 EnableJoining("join-liveintervals",
57 cl::desc("Coalesce copies (default=true)"),
60 // Temporary flag to test critical edge unsplitting.
62 EnableJoinSplits("join-splitedges",
63 cl::desc("Coalesce copies on split edges (default=subtarget)"), cl::Hidden);
65 // Temporary flag to test global copy optimization.
66 static cl::opt<cl::boolOrDefault>
67 EnableGlobalCopies("join-globalcopies",
68 cl::desc("Coalesce copies that span blocks (default=subtarget)"),
69 cl::init(cl::BOU_UNSET), cl::Hidden);
72 VerifyCoalescing("verify-coalescing",
73 cl::desc("Verify machine instrs before and after register coalescing"),
77 class RegisterCoalescer : public MachineFunctionPass,
78 private LiveRangeEdit::Delegate {
80 MachineRegisterInfo* MRI;
81 const TargetMachine* TM;
82 const TargetRegisterInfo* TRI;
83 const TargetInstrInfo* TII;
85 const MachineLoopInfo* Loops;
87 RegisterClassInfo RegClassInfo;
89 /// \brief True if the coalescer should aggressively coalesce global copies
90 /// in favor of keeping local copies.
91 bool JoinGlobalCopies;
93 /// \brief True if the coalescer should aggressively coalesce fall-thru
94 /// blocks exclusively containing copies.
97 /// WorkList - Copy instructions yet to be coalesced.
98 SmallVector<MachineInstr*, 8> WorkList;
99 SmallVector<MachineInstr*, 8> LocalWorkList;
101 /// ErasedInstrs - Set of instruction pointers that have been erased, and
102 /// that may be present in WorkList.
103 SmallPtrSet<MachineInstr*, 8> ErasedInstrs;
105 /// Dead instructions that are about to be deleted.
106 SmallVector<MachineInstr*, 8> DeadDefs;
108 /// Virtual registers to be considered for register class inflation.
109 SmallVector<unsigned, 8> InflateRegs;
111 /// Recursively eliminate dead defs in DeadDefs.
112 void eliminateDeadDefs();
114 /// LiveRangeEdit callback.
115 void LRE_WillEraseInstruction(MachineInstr *MI);
117 /// coalesceLocals - coalesce the LocalWorkList.
118 void coalesceLocals();
120 /// joinAllIntervals - join compatible live intervals
121 void joinAllIntervals();
123 /// copyCoalesceInMBB - Coalesce copies in the specified MBB, putting
124 /// copies that cannot yet be coalesced into WorkList.
125 void copyCoalesceInMBB(MachineBasicBlock *MBB);
127 /// copyCoalesceWorkList - Try to coalesce all copies in CurrList. Return
128 /// true if any progress was made.
129 bool copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList);
131 /// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
132 /// which are the src/dst of the copy instruction CopyMI. This returns
133 /// true if the copy was successfully coalesced away. If it is not
134 /// currently possible to coalesce this interval, but it may be possible if
135 /// other things get coalesced, then it returns true by reference in
137 bool joinCopy(MachineInstr *TheCopy, bool &Again);
139 /// joinIntervals - Attempt to join these two intervals. On failure, this
140 /// returns false. The output "SrcInt" will not have been modified, so we
141 /// can use this information below to update aliases.
142 bool joinIntervals(CoalescerPair &CP);
144 /// Attempt joining two virtual registers. Return true on success.
145 bool joinVirtRegs(CoalescerPair &CP);
147 /// Attempt joining with a reserved physreg.
148 bool joinReservedPhysReg(CoalescerPair &CP);
150 /// adjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
151 /// the source value number is defined by a copy from the destination reg
152 /// see if we can merge these two destination reg valno# into a single
153 /// value number, eliminating a copy.
154 bool adjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
156 /// hasOtherReachingDefs - Return true if there are definitions of IntB
157 /// other than BValNo val# that can reach uses of AValno val# of IntA.
158 bool hasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
159 VNInfo *AValNo, VNInfo *BValNo);
161 /// removeCopyByCommutingDef - We found a non-trivially-coalescable copy.
162 /// If the source value number is defined by a commutable instruction and
163 /// its other operand is coalesced to the copy dest register, see if we
164 /// can transform the copy into a noop by commuting the definition.
165 bool removeCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
167 /// reMaterializeTrivialDef - If the source of a copy is defined by a
168 /// trivial computation, replace the copy by rematerialize the definition.
169 bool reMaterializeTrivialDef(CoalescerPair &CP, MachineInstr *CopyMI);
171 /// canJoinPhys - Return true if a physreg copy should be joined.
172 bool canJoinPhys(const CoalescerPair &CP);
174 /// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
175 /// update the subregister number if it is not zero. If DstReg is a
176 /// physical register and the existing subregister number of the def / use
177 /// being updated is not zero, make sure to set it to the correct physical
179 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
181 /// eliminateUndefCopy - Handle copies of undef values.
182 bool eliminateUndefCopy(MachineInstr *CopyMI, const CoalescerPair &CP);
185 static char ID; // Class identification, replacement for typeinfo
186 RegisterCoalescer() : MachineFunctionPass(ID) {
187 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
190 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
192 virtual void releaseMemory();
194 /// runOnMachineFunction - pass entry point
195 virtual bool runOnMachineFunction(MachineFunction&);
197 /// print - Implement the dump method.
198 virtual void print(raw_ostream &O, const Module* = 0) const;
200 } /// end anonymous namespace
202 char &llvm::RegisterCoalescerID = RegisterCoalescer::ID;
204 INITIALIZE_PASS_BEGIN(RegisterCoalescer, "simple-register-coalescing",
205 "Simple Register Coalescing", false, false)
206 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
207 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
208 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
209 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
210 INITIALIZE_PASS_END(RegisterCoalescer, "simple-register-coalescing",
211 "Simple Register Coalescing", false, false)
213 char RegisterCoalescer::ID = 0;
215 static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI,
216 unsigned &Src, unsigned &Dst,
217 unsigned &SrcSub, unsigned &DstSub) {
219 Dst = MI->getOperand(0).getReg();
220 DstSub = MI->getOperand(0).getSubReg();
221 Src = MI->getOperand(1).getReg();
222 SrcSub = MI->getOperand(1).getSubReg();
223 } else if (MI->isSubregToReg()) {
224 Dst = MI->getOperand(0).getReg();
225 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(),
226 MI->getOperand(3).getImm());
227 Src = MI->getOperand(2).getReg();
228 SrcSub = MI->getOperand(2).getSubReg();
234 // Return true if this block should be vacated by the coalescer to eliminate
235 // branches. The important cases to handle in the coalescer are critical edges
236 // split during phi elimination which contain only copies. Simple blocks that
237 // contain non-branches should also be vacated, but this can be handled by an
238 // earlier pass similar to early if-conversion.
239 static bool isSplitEdge(const MachineBasicBlock *MBB) {
240 if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
243 for (MachineBasicBlock::const_iterator MII = MBB->begin(), E = MBB->end();
245 if (!MII->isCopyLike() && !MII->isUnconditionalBranch())
251 bool CoalescerPair::setRegisters(const MachineInstr *MI) {
255 Flipped = CrossClass = false;
257 unsigned Src, Dst, SrcSub, DstSub;
258 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
260 Partial = SrcSub || DstSub;
262 // If one register is a physreg, it must be Dst.
263 if (TargetRegisterInfo::isPhysicalRegister(Src)) {
264 if (TargetRegisterInfo::isPhysicalRegister(Dst))
267 std::swap(SrcSub, DstSub);
271 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
273 if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
274 // Eliminate DstSub on a physreg.
276 Dst = TRI.getSubReg(Dst, DstSub);
277 if (!Dst) return false;
281 // Eliminate SrcSub by picking a corresponding Dst superregister.
283 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
284 if (!Dst) return false;
286 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
290 // Both registers are virtual.
291 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
292 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
294 // Both registers have subreg indices.
295 if (SrcSub && DstSub) {
296 // Copies between different sub-registers are never coalescable.
297 if (Src == Dst && SrcSub != DstSub)
300 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
305 // SrcReg will be merged with a sub-register of DstReg.
307 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
309 // DstReg will be merged with a sub-register of SrcReg.
311 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
313 // This is a straight copy without sub-registers.
314 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
317 // The combined constraint may be impossible to satisfy.
321 // Prefer SrcReg to be a sub-register of DstReg.
322 // FIXME: Coalescer should support subregs symmetrically.
323 if (DstIdx && !SrcIdx) {
325 std::swap(SrcIdx, DstIdx);
329 CrossClass = NewRC != DstRC || NewRC != SrcRC;
331 // Check our invariants
332 assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual");
333 assert(!(TargetRegisterInfo::isPhysicalRegister(Dst) && DstSub) &&
334 "Cannot have a physical SubIdx");
340 bool CoalescerPair::flip() {
341 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
343 std::swap(SrcReg, DstReg);
344 std::swap(SrcIdx, DstIdx);
349 bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
352 unsigned Src, Dst, SrcSub, DstSub;
353 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
356 // Find the virtual register that is SrcReg.
359 std::swap(SrcSub, DstSub);
360 } else if (Src != SrcReg) {
364 // Now check that Dst matches DstReg.
365 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
366 if (!TargetRegisterInfo::isPhysicalRegister(Dst))
368 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.");
369 // DstSub could be set for a physreg from INSERT_SUBREG.
371 Dst = TRI.getSubReg(Dst, DstSub);
374 return DstReg == Dst;
375 // This is a partial register copy. Check that the parts match.
376 return TRI.getSubReg(DstReg, SrcSub) == Dst;
378 // DstReg is virtual.
381 // Registers match, do the subregisters line up?
382 return TRI.composeSubRegIndices(SrcIdx, SrcSub) ==
383 TRI.composeSubRegIndices(DstIdx, DstSub);
387 void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const {
388 AU.setPreservesCFG();
389 AU.addRequired<AliasAnalysis>();
390 AU.addRequired<LiveIntervals>();
391 AU.addPreserved<LiveIntervals>();
392 AU.addPreserved<SlotIndexes>();
393 AU.addRequired<MachineLoopInfo>();
394 AU.addPreserved<MachineLoopInfo>();
395 AU.addPreservedID(MachineDominatorsID);
396 MachineFunctionPass::getAnalysisUsage(AU);
399 void RegisterCoalescer::eliminateDeadDefs() {
400 SmallVector<LiveInterval*, 8> NewRegs;
401 LiveRangeEdit(0, NewRegs, *MF, *LIS, 0, this).eliminateDeadDefs(DeadDefs);
404 // Callback from eliminateDeadDefs().
405 void RegisterCoalescer::LRE_WillEraseInstruction(MachineInstr *MI) {
406 // MI may be in WorkList. Make sure we don't visit it.
407 ErasedInstrs.insert(MI);
410 /// adjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
411 /// being the source and IntB being the dest, thus this defines a value number
412 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
413 /// see if we can merge these two pieces of B into a single value number,
414 /// eliminating a copy. For example:
418 /// B1 = A3 <- this copy
420 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
421 /// value number to be replaced with B0 (which simplifies the B liveinterval).
423 /// This returns true if an interval was modified.
425 bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP,
426 MachineInstr *CopyMI) {
427 assert(!CP.isPartial() && "This doesn't work for partial copies.");
428 assert(!CP.isPhys() && "This doesn't work for physreg copies.");
431 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
433 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
434 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
436 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
437 // the example above.
438 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
439 if (BLR == IntB.end()) return false;
440 VNInfo *BValNo = BLR->valno;
442 // Get the location that B is defined at. Two options: either this value has
443 // an unknown definition point or it is defined at CopyIdx. If unknown, we
445 if (BValNo->def != CopyIdx) return false;
447 // AValNo is the value number in A that defines the copy, A3 in the example.
448 SlotIndex CopyUseIdx = CopyIdx.getRegSlot(true);
449 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
450 // The live range might not exist after fun with physreg coalescing.
451 if (ALR == IntA.end()) return false;
452 VNInfo *AValNo = ALR->valno;
454 // If AValNo is defined as a copy from IntB, we can potentially process this.
455 // Get the instruction that defines this value number.
456 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
457 // Don't allow any partial copies, even if isCoalescable() allows them.
458 if (!CP.isCoalescable(ACopyMI) || !ACopyMI->isFullCopy())
461 // Get the LiveRange in IntB that this value number starts with.
462 LiveInterval::iterator ValLR =
463 IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot());
464 if (ValLR == IntB.end())
467 // Make sure that the end of the live range is inside the same block as
469 MachineInstr *ValLREndInst =
470 LIS->getInstructionFromIndex(ValLR->end.getPrevSlot());
471 if (!ValLREndInst || ValLREndInst->getParent() != CopyMI->getParent())
474 // Okay, we now know that ValLR ends in the same block that the CopyMI
475 // live-range starts. If there are no intervening live ranges between them in
476 // IntB, we can merge them.
477 if (ValLR+1 != BLR) return false;
479 DEBUG(dbgs() << "Extending: " << PrintReg(IntB.reg, TRI));
481 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
482 // We are about to delete CopyMI, so need to remove it as the 'instruction
483 // that defines this value #'. Update the valnum with the new defining
485 BValNo->def = FillerStart;
487 // Okay, we can merge them. We need to insert a new liverange:
488 // [ValLR.end, BLR.begin) of either value number, then we merge the
489 // two value numbers.
490 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
492 // Okay, merge "B1" into the same value number as "B0".
493 if (BValNo != ValLR->valno)
494 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
495 DEBUG(dbgs() << " result = " << IntB << '\n');
497 // If the source instruction was killing the source register before the
498 // merge, unset the isKill marker given the live range has been extended.
499 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
501 ValLREndInst->getOperand(UIdx).setIsKill(false);
504 // Rewrite the copy. If the copy instruction was killing the destination
505 // register before the merge, find the last use and trim the live range. That
506 // will also add the isKill marker.
507 CopyMI->substituteRegister(IntA.reg, IntB.reg, 0, *TRI);
508 if (ALR->end == CopyIdx)
509 LIS->shrinkToUses(&IntA);
515 /// hasOtherReachingDefs - Return true if there are definitions of IntB
516 /// other than BValNo val# that can reach uses of AValno val# of IntA.
517 bool RegisterCoalescer::hasOtherReachingDefs(LiveInterval &IntA,
521 // If AValNo has PHI kills, conservatively assume that IntB defs can reach
523 if (LIS->hasPHIKill(IntA, AValNo))
526 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
528 if (AI->valno != AValNo) continue;
529 LiveInterval::Ranges::iterator BI =
530 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
531 if (BI != IntB.ranges.begin())
533 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
534 if (BI->valno == BValNo)
536 if (BI->start <= AI->start && BI->end > AI->start)
538 if (BI->start > AI->start && BI->start < AI->end)
545 /// removeCopyByCommutingDef - We found a non-trivially-coalescable copy with
546 /// IntA being the source and IntB being the dest, thus this defines a value
547 /// number in IntB. If the source value number (in IntA) is defined by a
548 /// commutable instruction and its other operand is coalesced to the copy dest
549 /// register, see if we can transform the copy into a noop by commuting the
550 /// definition. For example,
552 /// A3 = op A2 B0<kill>
554 /// B1 = A3 <- this copy
556 /// = op A3 <- more uses
560 /// B2 = op B0 A2<kill>
562 /// B1 = B2 <- now an identify copy
564 /// = op B2 <- more uses
566 /// This returns true if an interval was modified.
568 bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
569 MachineInstr *CopyMI) {
570 assert (!CP.isPhys());
572 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
575 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
577 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
579 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
580 // the example above.
581 VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx);
582 if (!BValNo || BValNo->def != CopyIdx)
585 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
587 // AValNo is the value number in A that defines the copy, A3 in the example.
588 VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getRegSlot(true));
589 assert(AValNo && "COPY source not live");
590 if (AValNo->isPHIDef() || AValNo->isUnused())
592 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
595 if (!DefMI->isCommutable())
597 // If DefMI is a two-address instruction then commuting it will change the
598 // destination register.
599 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
600 assert(DefIdx != -1);
602 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
604 unsigned Op1, Op2, NewDstIdx;
605 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
609 else if (Op2 == UseOpIdx)
614 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
615 unsigned NewReg = NewDstMO.getReg();
616 if (NewReg != IntB.reg || !LiveRangeQuery(IntB, AValNo->def).isKill())
619 // Make sure there are no other definitions of IntB that would reach the
620 // uses which the new definition can reach.
621 if (hasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
624 // If some of the uses of IntA.reg is already coalesced away, return false.
625 // It's not possible to determine whether it's safe to perform the coalescing.
626 for (MachineRegisterInfo::use_nodbg_iterator UI =
627 MRI->use_nodbg_begin(IntA.reg),
628 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
629 MachineInstr *UseMI = &*UI;
630 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
631 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
632 if (ULR == IntA.end() || ULR->valno != AValNo)
634 // If this use is tied to a def, we can't rewrite the register.
635 if (UseMI->isRegTiedToDefOperand(UI.getOperandNo()))
639 DEBUG(dbgs() << "\tremoveCopyByCommutingDef: " << AValNo->def << '\t'
642 // At this point we have decided that it is legal to do this
643 // transformation. Start by commuting the instruction.
644 MachineBasicBlock *MBB = DefMI->getParent();
645 MachineInstr *NewMI = TII->commuteInstruction(DefMI);
648 if (TargetRegisterInfo::isVirtualRegister(IntA.reg) &&
649 TargetRegisterInfo::isVirtualRegister(IntB.reg) &&
650 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
652 if (NewMI != DefMI) {
653 LIS->ReplaceMachineInstrInMaps(DefMI, NewMI);
654 MachineBasicBlock::iterator Pos = DefMI;
655 MBB->insert(Pos, NewMI);
658 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
659 NewMI->getOperand(OpIdx).setIsKill();
661 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
670 // Update uses of IntA of the specific Val# with IntB.
671 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg),
672 UE = MRI->use_end(); UI != UE;) {
673 MachineOperand &UseMO = UI.getOperand();
674 MachineInstr *UseMI = &*UI;
676 if (UseMI->isDebugValue()) {
677 // FIXME These don't have an instruction index. Not clear we have enough
678 // info to decide whether to do this replacement or not. For now do it.
679 UseMO.setReg(NewReg);
682 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
683 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
684 if (ULR == IntA.end() || ULR->valno != AValNo)
686 // Kill flags are no longer accurate. They are recomputed after RA.
687 UseMO.setIsKill(false);
688 if (TargetRegisterInfo::isPhysicalRegister(NewReg))
689 UseMO.substPhysReg(NewReg, *TRI);
691 UseMO.setReg(NewReg);
694 if (!UseMI->isCopy())
696 if (UseMI->getOperand(0).getReg() != IntB.reg ||
697 UseMI->getOperand(0).getSubReg())
700 // This copy will become a noop. If it's defining a new val#, merge it into
702 SlotIndex DefIdx = UseIdx.getRegSlot();
703 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
706 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
707 assert(DVNI->def == DefIdx);
708 BValNo = IntB.MergeValueNumberInto(BValNo, DVNI);
709 ErasedInstrs.insert(UseMI);
710 LIS->RemoveMachineInstrFromMaps(UseMI);
711 UseMI->eraseFromParent();
714 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
716 VNInfo *ValNo = BValNo;
717 ValNo->def = AValNo->def;
718 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
720 if (AI->valno != AValNo) continue;
721 IntB.addRange(LiveRange(AI->start, AI->end, ValNo));
723 DEBUG(dbgs() << "\t\textended: " << IntB << '\n');
725 IntA.removeValNo(AValNo);
726 DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n');
731 /// reMaterializeTrivialDef - If the source of a copy is defined by a trivial
732 /// computation, replace the copy by rematerialize the definition.
733 bool RegisterCoalescer::reMaterializeTrivialDef(CoalescerPair &CP,
734 MachineInstr *CopyMI) {
735 unsigned SrcReg = CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg();
736 unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx();
737 unsigned DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
738 unsigned DstIdx = CP.isFlipped() ? CP.getSrcIdx() : CP.getDstIdx();
739 if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
742 LiveInterval &SrcInt = LIS->getInterval(SrcReg);
743 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(true);
744 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
745 assert(SrcLR != SrcInt.end() && "Live range not found!");
746 VNInfo *ValNo = SrcLR->valno;
747 if (ValNo->isPHIDef() || ValNo->isUnused())
749 MachineInstr *DefMI = LIS->getInstructionFromIndex(ValNo->def);
752 assert(DefMI && "Defining instruction disappeared");
753 if (!DefMI->isAsCheapAsAMove())
755 if (!TII->isTriviallyReMaterializable(DefMI, AA))
757 bool SawStore = false;
758 if (!DefMI->isSafeToMove(TII, AA, SawStore))
760 const MCInstrDesc &MCID = DefMI->getDesc();
761 if (MCID.getNumDefs() != 1)
763 // Only support subregister destinations when the def is read-undef.
764 MachineOperand &DstOperand = CopyMI->getOperand(0);
765 unsigned CopyDstReg = DstOperand.getReg();
766 if (DstOperand.getSubReg() && !DstOperand.isUndef())
769 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF);
770 if (!DefMI->isImplicitDef()) {
771 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
772 unsigned NewDstReg = DstReg;
774 unsigned NewDstIdx = TRI->composeSubRegIndices(CP.getSrcIdx(),
775 DefMI->getOperand(0).getSubReg());
777 NewDstReg = TRI->getSubReg(DstReg, NewDstIdx);
779 // Finally, make sure that the physical subregister that will be
780 // constructed later is permitted for the instruction.
781 if (!DefRC->contains(NewDstReg))
784 // Theoretically, some stack frame reference could exist. Just make sure
785 // it hasn't actually happened.
786 assert(TargetRegisterInfo::isVirtualRegister(DstReg) &&
787 "Only expect to deal with virtual or physical registers");
791 MachineBasicBlock *MBB = CopyMI->getParent();
792 MachineBasicBlock::iterator MII =
793 llvm::next(MachineBasicBlock::iterator(CopyMI));
794 TII->reMaterialize(*MBB, MII, DstReg, SrcIdx, DefMI, *TRI);
795 MachineInstr *NewMI = prior(MII);
797 LIS->ReplaceMachineInstrInMaps(CopyMI, NewMI);
798 CopyMI->eraseFromParent();
799 ErasedInstrs.insert(CopyMI);
801 // NewMI may have dead implicit defs (E.g. EFLAGS for MOV<bits>r0 on X86).
802 // We need to remember these so we can add intervals once we insert
803 // NewMI into SlotIndexes.
804 SmallVector<unsigned, 4> NewMIImplDefs;
805 for (unsigned i = NewMI->getDesc().getNumOperands(),
806 e = NewMI->getNumOperands(); i != e; ++i) {
807 MachineOperand &MO = NewMI->getOperand(i);
809 assert(MO.isDef() && MO.isImplicit() && MO.isDead() &&
810 TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
811 NewMIImplDefs.push_back(MO.getReg());
815 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
816 unsigned NewIdx = NewMI->getOperand(0).getSubReg();
817 const TargetRegisterClass *RCForInst;
819 RCForInst = TRI->getMatchingSuperRegClass(MRI->getRegClass(DstReg), DefRC,
822 if (MRI->constrainRegClass(DstReg, DefRC)) {
823 // The materialized instruction is quite capable of setting DstReg
824 // directly, but it may still have a now-trivial subregister index which
826 NewMI->getOperand(0).setSubReg(0);
827 } else if (NewIdx && RCForInst) {
828 // The subreg index on NewMI is essential; we still have to make sure
829 // DstReg:idx is in a class that NewMI can use.
830 MRI->constrainRegClass(DstReg, RCForInst);
832 // DstReg is actually incompatible with NewMI, we have to move to a
833 // super-reg's class. This could come from a sequence like:
835 // GR8 = COPY GR32:sub_8
836 MRI->setRegClass(DstReg, CP.getNewRC());
837 updateRegDefsUses(DstReg, DstReg, DstIdx);
838 NewMI->getOperand(0).setSubReg(
839 TRI->composeSubRegIndices(SrcIdx, DefMI->getOperand(0).getSubReg()));
841 } else if (NewMI->getOperand(0).getReg() != CopyDstReg) {
842 // The New instruction may be defining a sub-register of what's actually
843 // been asked for. If so it must implicitly define the whole thing.
844 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
845 "Only expect virtual or physical registers in remat");
846 NewMI->getOperand(0).setIsDead(true);
847 NewMI->addOperand(MachineOperand::CreateReg(CopyDstReg,
853 if (NewMI->getOperand(0).getSubReg())
854 NewMI->getOperand(0).setIsUndef();
856 // CopyMI may have implicit operands, transfer them over to the newly
857 // rematerialized instruction. And update implicit def interval valnos.
858 for (unsigned i = CopyMI->getDesc().getNumOperands(),
859 e = CopyMI->getNumOperands(); i != e; ++i) {
860 MachineOperand &MO = CopyMI->getOperand(i);
862 assert(MO.isImplicit() && "No explicit operands after implict operands.");
863 // Discard VReg implicit defs.
864 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
865 NewMI->addOperand(MO);
870 SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
871 for (unsigned i = 0, e = NewMIImplDefs.size(); i != e; ++i) {
872 unsigned Reg = NewMIImplDefs[i];
873 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
874 if (LiveInterval *LI = LIS->getCachedRegUnit(*Units))
875 LI->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
878 DEBUG(dbgs() << "Remat: " << *NewMI);
881 // The source interval can become smaller because we removed a use.
882 LIS->shrinkToUses(&SrcInt, &DeadDefs);
883 if (!DeadDefs.empty())
889 /// eliminateUndefCopy - ProcessImpicitDefs may leave some copies of <undef>
890 /// values, it only removes local variables. When we have a copy like:
892 /// %vreg1 = COPY %vreg2<undef>
894 /// We delete the copy and remove the corresponding value number from %vreg1.
895 /// Any uses of that value number are marked as <undef>.
896 bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI,
897 const CoalescerPair &CP) {
898 SlotIndex Idx = LIS->getInstructionIndex(CopyMI);
899 LiveInterval *SrcInt = &LIS->getInterval(CP.getSrcReg());
900 if (SrcInt->liveAt(Idx))
902 LiveInterval *DstInt = &LIS->getInterval(CP.getDstReg());
903 if (DstInt->liveAt(Idx))
906 // No intervals are live-in to CopyMI - it is undef.
911 VNInfo *DeadVNI = DstInt->getVNInfoAt(Idx.getRegSlot());
912 assert(DeadVNI && "No value defined in DstInt");
913 DstInt->removeValNo(DeadVNI);
915 // Find new undef uses.
916 for (MachineRegisterInfo::reg_nodbg_iterator
917 I = MRI->reg_nodbg_begin(DstInt->reg), E = MRI->reg_nodbg_end();
919 MachineOperand &MO = I.getOperand();
920 if (MO.isDef() || MO.isUndef())
922 MachineInstr *MI = MO.getParent();
923 SlotIndex Idx = LIS->getInstructionIndex(MI);
924 if (DstInt->liveAt(Idx))
927 DEBUG(dbgs() << "\tnew undef: " << Idx << '\t' << *MI);
932 /// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
933 /// update the subregister number if it is not zero. If DstReg is a
934 /// physical register and the existing subregister number of the def / use
935 /// being updated is not zero, make sure to set it to the correct physical
937 void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg,
940 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
941 LiveInterval *DstInt = DstIsPhys ? 0 : &LIS->getInterval(DstReg);
943 SmallPtrSet<MachineInstr*, 8> Visited;
944 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg);
945 MachineInstr *UseMI = I.skipInstruction();) {
946 // Each instruction can only be rewritten once because sub-register
947 // composition is not always idempotent. When SrcReg != DstReg, rewriting
948 // the UseMI operands removes them from the SrcReg use-def chain, but when
949 // SrcReg is DstReg we could encounter UseMI twice if it has multiple
950 // operands mentioning the virtual register.
951 if (SrcReg == DstReg && !Visited.insert(UseMI))
954 SmallVector<unsigned,8> Ops;
956 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
958 // If SrcReg wasn't read, it may still be the case that DstReg is live-in
959 // because SrcReg is a sub-register.
960 if (DstInt && !Reads && SubIdx)
961 Reads = DstInt->liveAt(LIS->getInstructionIndex(UseMI));
963 // Replace SrcReg with DstReg in all UseMI operands.
964 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
965 MachineOperand &MO = UseMI->getOperand(Ops[i]);
967 // Adjust <undef> flags in case of sub-register joins. We don't want to
968 // turn a full def into a read-modify-write sub-register def and vice
970 if (SubIdx && MO.isDef())
971 MO.setIsUndef(!Reads);
974 MO.substPhysReg(DstReg, *TRI);
976 MO.substVirtReg(DstReg, SubIdx, *TRI);
980 dbgs() << "\t\tupdated: ";
981 if (!UseMI->isDebugValue())
982 dbgs() << LIS->getInstructionIndex(UseMI) << "\t";
988 /// canJoinPhys - Return true if a copy involving a physreg should be joined.
989 bool RegisterCoalescer::canJoinPhys(const CoalescerPair &CP) {
990 /// Always join simple intervals that are defined by a single copy from a
991 /// reserved register. This doesn't increase register pressure, so it is
992 /// always beneficial.
993 if (!MRI->isReserved(CP.getDstReg())) {
994 DEBUG(dbgs() << "\tCan only merge into reserved registers.\n");
998 LiveInterval &JoinVInt = LIS->getInterval(CP.getSrcReg());
999 if (CP.isFlipped() && JoinVInt.containsOneValue())
1002 DEBUG(dbgs() << "\tCannot join defs into reserved register.\n");
1006 /// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1007 /// which are the src/dst of the copy instruction CopyMI. This returns true
1008 /// if the copy was successfully coalesced away. If it is not currently
1009 /// possible to coalesce this interval, but it may be possible if other
1010 /// things get coalesced, then it returns true by reference in 'Again'.
1011 bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
1014 DEBUG(dbgs() << LIS->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
1016 CoalescerPair CP(*TRI);
1017 if (!CP.setRegisters(CopyMI)) {
1018 DEBUG(dbgs() << "\tNot coalescable.\n");
1022 // Dead code elimination. This really should be handled by MachineDCE, but
1023 // sometimes dead copies slip through, and we can't generate invalid live
1025 if (!CP.isPhys() && CopyMI->allDefsAreDead()) {
1026 DEBUG(dbgs() << "\tCopy is dead.\n");
1027 DeadDefs.push_back(CopyMI);
1028 eliminateDeadDefs();
1032 // Eliminate undefs.
1033 if (!CP.isPhys() && eliminateUndefCopy(CopyMI, CP)) {
1034 DEBUG(dbgs() << "\tEliminated copy of <undef> value.\n");
1035 LIS->RemoveMachineInstrFromMaps(CopyMI);
1036 CopyMI->eraseFromParent();
1037 return false; // Not coalescable.
1040 // Coalesced copies are normally removed immediately, but transformations
1041 // like removeCopyByCommutingDef() can inadvertently create identity copies.
1042 // When that happens, just join the values and remove the copy.
1043 if (CP.getSrcReg() == CP.getDstReg()) {
1044 LiveInterval &LI = LIS->getInterval(CP.getSrcReg());
1045 DEBUG(dbgs() << "\tCopy already coalesced: " << LI << '\n');
1046 LiveRangeQuery LRQ(LI, LIS->getInstructionIndex(CopyMI));
1047 if (VNInfo *DefVNI = LRQ.valueDefined()) {
1048 VNInfo *ReadVNI = LRQ.valueIn();
1049 assert(ReadVNI && "No value before copy and no <undef> flag.");
1050 assert(ReadVNI != DefVNI && "Cannot read and define the same value.");
1051 LI.MergeValueNumberInto(DefVNI, ReadVNI);
1052 DEBUG(dbgs() << "\tMerged values: " << LI << '\n');
1054 LIS->RemoveMachineInstrFromMaps(CopyMI);
1055 CopyMI->eraseFromParent();
1059 // Enforce policies.
1061 DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI)
1062 << " with " << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx())
1064 if (!canJoinPhys(CP)) {
1065 // Before giving up coalescing, if definition of source is defined by
1066 // trivial computation, try rematerializing it.
1067 if (reMaterializeTrivialDef(CP, CopyMI))
1073 dbgs() << "\tConsidering merging to " << CP.getNewRC()->getName()
1075 if (CP.getDstIdx() && CP.getSrcIdx())
1076 dbgs() << PrintReg(CP.getDstReg()) << " in "
1077 << TRI->getSubRegIndexName(CP.getDstIdx()) << " and "
1078 << PrintReg(CP.getSrcReg()) << " in "
1079 << TRI->getSubRegIndexName(CP.getSrcIdx()) << '\n';
1081 dbgs() << PrintReg(CP.getSrcReg(), TRI) << " in "
1082 << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n';
1085 // When possible, let DstReg be the larger interval.
1086 if (!CP.isPartial() && LIS->getInterval(CP.getSrcReg()).ranges.size() >
1087 LIS->getInterval(CP.getDstReg()).ranges.size())
1091 // Okay, attempt to join these two intervals. On failure, this returns false.
1092 // Otherwise, if one of the intervals being joined is a physreg, this method
1093 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1094 // been modified, so we can use this information below to update aliases.
1095 if (!joinIntervals(CP)) {
1096 // Coalescing failed.
1098 // If definition of source is defined by trivial computation, try
1099 // rematerializing it.
1100 if (reMaterializeTrivialDef(CP, CopyMI))
1103 // If we can eliminate the copy without merging the live ranges, do so now.
1104 if (!CP.isPartial() && !CP.isPhys()) {
1105 if (adjustCopiesBackFrom(CP, CopyMI) ||
1106 removeCopyByCommutingDef(CP, CopyMI)) {
1107 LIS->RemoveMachineInstrFromMaps(CopyMI);
1108 CopyMI->eraseFromParent();
1109 DEBUG(dbgs() << "\tTrivial!\n");
1114 // Otherwise, we are unable to join the intervals.
1115 DEBUG(dbgs() << "\tInterference!\n");
1116 Again = true; // May be possible to coalesce later.
1120 // Coalescing to a virtual register that is of a sub-register class of the
1121 // other. Make sure the resulting register is set to the right register class.
1122 if (CP.isCrossClass()) {
1124 MRI->setRegClass(CP.getDstReg(), CP.getNewRC());
1127 // Removing sub-register copies can ease the register class constraints.
1128 // Make sure we attempt to inflate the register class of DstReg.
1129 if (!CP.isPhys() && RegClassInfo.isProperSubClass(CP.getNewRC()))
1130 InflateRegs.push_back(CP.getDstReg());
1132 // CopyMI has been erased by joinIntervals at this point. Remove it from
1133 // ErasedInstrs since copyCoalesceWorkList() won't add a successful join back
1134 // to the work list. This keeps ErasedInstrs from growing needlessly.
1135 ErasedInstrs.erase(CopyMI);
1137 // Rewrite all SrcReg operands to DstReg.
1138 // Also update DstReg operands to include DstIdx if it is set.
1140 updateRegDefsUses(CP.getDstReg(), CP.getDstReg(), CP.getDstIdx());
1141 updateRegDefsUses(CP.getSrcReg(), CP.getDstReg(), CP.getSrcIdx());
1143 // SrcReg is guaranteed to be the register whose live interval that is
1145 LIS->removeInterval(CP.getSrcReg());
1147 // Update regalloc hint.
1148 TRI->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
1151 dbgs() << "\tJoined. Result = " << PrintReg(CP.getDstReg(), TRI);
1153 dbgs() << LIS->getInterval(CP.getDstReg());
1161 /// Attempt joining with a reserved physreg.
1162 bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
1163 assert(CP.isPhys() && "Must be a physreg copy");
1164 assert(MRI->isReserved(CP.getDstReg()) && "Not a reserved register");
1165 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1166 DEBUG(dbgs() << "\t\tRHS = " << PrintReg(CP.getSrcReg()) << ' ' << RHS
1169 assert(CP.isFlipped() && RHS.containsOneValue() &&
1170 "Invalid join with reserved register");
1172 // Optimization for reserved registers like ESP. We can only merge with a
1173 // reserved physreg if RHS has a single value that is a copy of CP.DstReg().
1174 // The live range of the reserved register will look like a set of dead defs
1175 // - we don't properly track the live range of reserved registers.
1177 // Deny any overlapping intervals. This depends on all the reserved
1178 // register live ranges to look like dead defs.
1179 for (MCRegUnitIterator UI(CP.getDstReg(), TRI); UI.isValid(); ++UI)
1180 if (RHS.overlaps(LIS->getRegUnit(*UI))) {
1181 DEBUG(dbgs() << "\t\tInterference: " << PrintRegUnit(*UI, TRI) << '\n');
1185 // Skip any value computations, we are not adding new values to the
1186 // reserved register. Also skip merging the live ranges, the reserved
1187 // register live range doesn't need to be accurate as long as all the
1190 // Delete the identity copy.
1191 MachineInstr *CopyMI = MRI->getVRegDef(RHS.reg);
1192 LIS->RemoveMachineInstrFromMaps(CopyMI);
1193 CopyMI->eraseFromParent();
1195 // We don't track kills for reserved registers.
1196 MRI->clearKillFlags(CP.getSrcReg());
1201 //===----------------------------------------------------------------------===//
1202 // Interference checking and interval joining
1203 //===----------------------------------------------------------------------===//
1205 // In the easiest case, the two live ranges being joined are disjoint, and
1206 // there is no interference to consider. It is quite common, though, to have
1207 // overlapping live ranges, and we need to check if the interference can be
1210 // The live range of a single SSA value forms a sub-tree of the dominator tree.
1211 // This means that two SSA values overlap if and only if the def of one value
1212 // is contained in the live range of the other value. As a special case, the
1213 // overlapping values can be defined at the same index.
1215 // The interference from an overlapping def can be resolved in these cases:
1217 // 1. Coalescable copies. The value is defined by a copy that would become an
1218 // identity copy after joining SrcReg and DstReg. The copy instruction will
1219 // be removed, and the value will be merged with the source value.
1221 // There can be several copies back and forth, causing many values to be
1222 // merged into one. We compute a list of ultimate values in the joined live
1223 // range as well as a mappings from the old value numbers.
1225 // 2. IMPLICIT_DEF. This instruction is only inserted to ensure all PHI
1226 // predecessors have a live out value. It doesn't cause real interference,
1227 // and can be merged into the value it overlaps. Like a coalescable copy, it
1228 // can be erased after joining.
1230 // 3. Copy of external value. The overlapping def may be a copy of a value that
1231 // is already in the other register. This is like a coalescable copy, but
1232 // the live range of the source register must be trimmed after erasing the
1233 // copy instruction:
1236 // %dst = COPY %ext <-- Remove this COPY, trim the live range of %ext.
1238 // 4. Clobbering undefined lanes. Vector registers are sometimes built by
1239 // defining one lane at a time:
1241 // %dst:ssub0<def,read-undef> = FOO
1243 // %dst:ssub1<def> = COPY %src
1245 // The live range of %src overlaps the %dst value defined by FOO, but
1246 // merging %src into %dst:ssub1 is only going to clobber the ssub1 lane
1247 // which was undef anyway.
1249 // The value mapping is more complicated in this case. The final live range
1250 // will have different value numbers for both FOO and BAR, but there is no
1251 // simple mapping from old to new values. It may even be necessary to add
1254 // 5. Clobbering dead lanes. A def may clobber a lane of a vector register that
1255 // is live, but never read. This can happen because we don't compute
1256 // individual live ranges per lane.
1260 // %dst:ssub1<def> = COPY %src
1262 // This kind of interference is only resolved locally. If the clobbered
1263 // lane value escapes the block, the join is aborted.
1266 /// Track information about values in a single virtual register about to be
1267 /// joined. Objects of this class are always created in pairs - one for each
1268 /// side of the CoalescerPair.
1272 // Location of this register in the final joined register.
1273 // Either CP.DstIdx or CP.SrcIdx.
1276 // Values that will be present in the final live range.
1277 SmallVectorImpl<VNInfo*> &NewVNInfo;
1279 const CoalescerPair &CP;
1281 SlotIndexes *Indexes;
1282 const TargetRegisterInfo *TRI;
1284 // Value number assignments. Maps value numbers in LI to entries in NewVNInfo.
1285 // This is suitable for passing to LiveInterval::join().
1286 SmallVector<int, 8> Assignments;
1288 // Conflict resolution for overlapping values.
1289 enum ConflictResolution {
1290 // No overlap, simply keep this value.
1293 // Merge this value into OtherVNI and erase the defining instruction.
1294 // Used for IMPLICIT_DEF, coalescable copies, and copies from external
1298 // Merge this value into OtherVNI but keep the defining instruction.
1299 // This is for the special case where OtherVNI is defined by the same
1303 // Keep this value, and have it replace OtherVNI where possible. This
1304 // complicates value mapping since OtherVNI maps to two different values
1305 // before and after this def.
1306 // Used when clobbering undefined or dead lanes.
1309 // Unresolved conflict. Visit later when all values have been mapped.
1312 // Unresolvable conflict. Abort the join.
1316 // Per-value info for LI. The lane bit masks are all relative to the final
1317 // joined register, so they can be compared directly between SrcReg and
1320 ConflictResolution Resolution;
1322 // Lanes written by this def, 0 for unanalyzed values.
1323 unsigned WriteLanes;
1325 // Lanes with defined values in this register. Other lanes are undef and
1327 unsigned ValidLanes;
1329 // Value in LI being redefined by this def.
1332 // Value in the other live range that overlaps this def, if any.
1335 // Is this value an IMPLICIT_DEF that can be erased?
1337 // IMPLICIT_DEF values should only exist at the end of a basic block that
1338 // is a predecessor to a phi-value. These IMPLICIT_DEF instructions can be
1339 // safely erased if they are overlapping a live value in the other live
1342 // Weird control flow graphs and incomplete PHI handling in
1343 // ProcessImplicitDefs can very rarely create IMPLICIT_DEF values with
1344 // longer live ranges. Such IMPLICIT_DEF values should be treated like
1346 bool ErasableImplicitDef;
1348 // True when the live range of this value will be pruned because of an
1349 // overlapping CR_Replace value in the other live range.
1352 // True once Pruned above has been computed.
1353 bool PrunedComputed;
1355 Val() : Resolution(CR_Keep), WriteLanes(0), ValidLanes(0),
1356 RedefVNI(0), OtherVNI(0), ErasableImplicitDef(false),
1357 Pruned(false), PrunedComputed(false) {}
1359 bool isAnalyzed() const { return WriteLanes != 0; }
1362 // One entry per value number in LI.
1363 SmallVector<Val, 8> Vals;
1365 unsigned computeWriteLanes(const MachineInstr *DefMI, bool &Redef);
1366 VNInfo *stripCopies(VNInfo *VNI);
1367 ConflictResolution analyzeValue(unsigned ValNo, JoinVals &Other);
1368 void computeAssignment(unsigned ValNo, JoinVals &Other);
1369 bool taintExtent(unsigned, unsigned, JoinVals&,
1370 SmallVectorImpl<std::pair<SlotIndex, unsigned> >&);
1371 bool usesLanes(MachineInstr *MI, unsigned, unsigned, unsigned);
1372 bool isPrunedValue(unsigned ValNo, JoinVals &Other);
1375 JoinVals(LiveInterval &li, unsigned subIdx,
1376 SmallVectorImpl<VNInfo*> &newVNInfo,
1377 const CoalescerPair &cp,
1379 const TargetRegisterInfo *tri)
1380 : LI(li), SubIdx(subIdx), NewVNInfo(newVNInfo), CP(cp), LIS(lis),
1381 Indexes(LIS->getSlotIndexes()), TRI(tri),
1382 Assignments(LI.getNumValNums(), -1), Vals(LI.getNumValNums())
1385 /// Analyze defs in LI and compute a value mapping in NewVNInfo.
1386 /// Returns false if any conflicts were impossible to resolve.
1387 bool mapValues(JoinVals &Other);
1389 /// Try to resolve conflicts that require all values to be mapped.
1390 /// Returns false if any conflicts were impossible to resolve.
1391 bool resolveConflicts(JoinVals &Other);
1393 /// Prune the live range of values in Other.LI where they would conflict with
1394 /// CR_Replace values in LI. Collect end points for restoring the live range
1396 void pruneValues(JoinVals &Other, SmallVectorImpl<SlotIndex> &EndPoints);
1398 /// Erase any machine instructions that have been coalesced away.
1399 /// Add erased instructions to ErasedInstrs.
1400 /// Add foreign virtual registers to ShrinkRegs if their live range ended at
1401 /// the erased instrs.
1402 void eraseInstrs(SmallPtrSet<MachineInstr*, 8> &ErasedInstrs,
1403 SmallVectorImpl<unsigned> &ShrinkRegs);
1405 /// Get the value assignments suitable for passing to LiveInterval::join.
1406 const int *getAssignments() const { return Assignments.data(); }
1408 } // end anonymous namespace
1410 /// Compute the bitmask of lanes actually written by DefMI.
1411 /// Set Redef if there are any partial register definitions that depend on the
1412 /// previous value of the register.
1413 unsigned JoinVals::computeWriteLanes(const MachineInstr *DefMI, bool &Redef) {
1415 for (ConstMIOperands MO(DefMI); MO.isValid(); ++MO) {
1416 if (!MO->isReg() || MO->getReg() != LI.reg || !MO->isDef())
1418 L |= TRI->getSubRegIndexLaneMask(
1419 TRI->composeSubRegIndices(SubIdx, MO->getSubReg()));
1426 /// Find the ultimate value that VNI was copied from.
1427 VNInfo *JoinVals::stripCopies(VNInfo *VNI) {
1428 while (!VNI->isPHIDef()) {
1429 MachineInstr *MI = Indexes->getInstructionFromIndex(VNI->def);
1430 assert(MI && "No defining instruction");
1431 if (!MI->isFullCopy())
1433 unsigned Reg = MI->getOperand(1).getReg();
1434 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1436 LiveRangeQuery LRQ(LIS->getInterval(Reg), VNI->def);
1439 VNI = LRQ.valueIn();
1444 /// Analyze ValNo in this live range, and set all fields of Vals[ValNo].
1445 /// Return a conflict resolution when possible, but leave the hard cases as
1447 /// Recursively calls computeAssignment() on this and Other, guaranteeing that
1448 /// both OtherVNI and RedefVNI have been analyzed and mapped before returning.
1449 /// The recursion always goes upwards in the dominator tree, making loops
1451 JoinVals::ConflictResolution
1452 JoinVals::analyzeValue(unsigned ValNo, JoinVals &Other) {
1453 Val &V = Vals[ValNo];
1454 assert(!V.isAnalyzed() && "Value has already been analyzed!");
1455 VNInfo *VNI = LI.getValNumInfo(ValNo);
1456 if (VNI->isUnused()) {
1461 // Get the instruction defining this value, compute the lanes written.
1462 const MachineInstr *DefMI = 0;
1463 if (VNI->isPHIDef()) {
1464 // Conservatively assume that all lanes in a PHI are valid.
1465 V.ValidLanes = V.WriteLanes = TRI->getSubRegIndexLaneMask(SubIdx);
1467 DefMI = Indexes->getInstructionFromIndex(VNI->def);
1469 V.ValidLanes = V.WriteLanes = computeWriteLanes(DefMI, Redef);
1471 // If this is a read-modify-write instruction, there may be more valid
1472 // lanes than the ones written by this instruction.
1473 // This only covers partial redef operands. DefMI may have normal use
1474 // operands reading the register. They don't contribute valid lanes.
1476 // This adds ssub1 to the set of valid lanes in %src:
1478 // %src:ssub1<def> = FOO
1480 // This leaves only ssub1 valid, making any other lanes undef:
1482 // %src:ssub1<def,read-undef> = FOO %src:ssub2
1484 // The <read-undef> flag on the def operand means that old lane values are
1487 V.RedefVNI = LiveRangeQuery(LI, VNI->def).valueIn();
1488 assert(V.RedefVNI && "Instruction is reading nonexistent value");
1489 computeAssignment(V.RedefVNI->id, Other);
1490 V.ValidLanes |= Vals[V.RedefVNI->id].ValidLanes;
1493 // An IMPLICIT_DEF writes undef values.
1494 if (DefMI->isImplicitDef()) {
1495 // We normally expect IMPLICIT_DEF values to be live only until the end
1496 // of their block. If the value is really live longer and gets pruned in
1497 // another block, this flag is cleared again.
1498 V.ErasableImplicitDef = true;
1499 V.ValidLanes &= ~V.WriteLanes;
1503 // Find the value in Other that overlaps VNI->def, if any.
1504 LiveRangeQuery OtherLRQ(Other.LI, VNI->def);
1506 // It is possible that both values are defined by the same instruction, or
1507 // the values are PHIs defined in the same block. When that happens, the two
1508 // values should be merged into one, but not into any preceding value.
1509 // The first value defined or visited gets CR_Keep, the other gets CR_Merge.
1510 if (VNInfo *OtherVNI = OtherLRQ.valueDefined()) {
1511 assert(SlotIndex::isSameInstr(VNI->def, OtherVNI->def) && "Broken LRQ");
1513 // One value stays, the other is merged. Keep the earlier one, or the first
1515 if (OtherVNI->def < VNI->def)
1516 Other.computeAssignment(OtherVNI->id, *this);
1517 else if (VNI->def < OtherVNI->def && OtherLRQ.valueIn()) {
1518 // This is an early-clobber def overlapping a live-in value in the other
1519 // register. Not mergeable.
1520 V.OtherVNI = OtherLRQ.valueIn();
1521 return CR_Impossible;
1523 V.OtherVNI = OtherVNI;
1524 Val &OtherV = Other.Vals[OtherVNI->id];
1525 // Keep this value, check for conflicts when analyzing OtherVNI.
1526 if (!OtherV.isAnalyzed())
1528 // Both sides have been analyzed now.
1529 // Allow overlapping PHI values. Any real interference would show up in a
1530 // predecessor, the PHI itself can't introduce any conflicts.
1531 if (VNI->isPHIDef())
1533 if (V.ValidLanes & OtherV.ValidLanes)
1534 // Overlapping lanes can't be resolved.
1535 return CR_Impossible;
1540 // No simultaneous def. Is Other live at the def?
1541 V.OtherVNI = OtherLRQ.valueIn();
1543 // No overlap, no conflict.
1546 assert(!SlotIndex::isSameInstr(VNI->def, V.OtherVNI->def) && "Broken LRQ");
1548 // We have overlapping values, or possibly a kill of Other.
1549 // Recursively compute assignments up the dominator tree.
1550 Other.computeAssignment(V.OtherVNI->id, *this);
1551 Val &OtherV = Other.Vals[V.OtherVNI->id];
1553 // Check if OtherV is an IMPLICIT_DEF that extends beyond its basic block.
1554 // This shouldn't normally happen, but ProcessImplicitDefs can leave such
1555 // IMPLICIT_DEF instructions behind, and there is nothing wrong with it
1558 // WHen it happens, treat that IMPLICIT_DEF as a normal value, and don't try
1559 // to erase the IMPLICIT_DEF instruction.
1560 if (OtherV.ErasableImplicitDef && DefMI &&
1561 DefMI->getParent() != Indexes->getMBBFromIndex(V.OtherVNI->def)) {
1562 DEBUG(dbgs() << "IMPLICIT_DEF defined at " << V.OtherVNI->def
1563 << " extends into BB#" << DefMI->getParent()->getNumber()
1564 << ", keeping it.\n");
1565 OtherV.ErasableImplicitDef = false;
1568 // Allow overlapping PHI values. Any real interference would show up in a
1569 // predecessor, the PHI itself can't introduce any conflicts.
1570 if (VNI->isPHIDef())
1573 // Check for simple erasable conflicts.
1574 if (DefMI->isImplicitDef())
1577 // Include the non-conflict where DefMI is a coalescable copy that kills
1578 // OtherVNI. We still want the copy erased and value numbers merged.
1579 if (CP.isCoalescable(DefMI)) {
1580 // Some of the lanes copied from OtherVNI may be undef, making them undef
1582 V.ValidLanes &= ~V.WriteLanes | OtherV.ValidLanes;
1586 // This may not be a real conflict if DefMI simply kills Other and defines
1588 if (OtherLRQ.isKill() && OtherLRQ.endPoint() <= VNI->def)
1591 // Handle the case where VNI and OtherVNI can be proven to be identical:
1593 // %other = COPY %ext
1594 // %this = COPY %ext <-- Erase this copy
1596 if (DefMI->isFullCopy() && !CP.isPartial() &&
1597 stripCopies(VNI) == stripCopies(V.OtherVNI))
1600 // If the lanes written by this instruction were all undef in OtherVNI, it is
1601 // still safe to join the live ranges. This can't be done with a simple value
1602 // mapping, though - OtherVNI will map to multiple values:
1604 // 1 %dst:ssub0 = FOO <-- OtherVNI
1605 // 2 %src = BAR <-- VNI
1606 // 3 %dst:ssub1 = COPY %src<kill> <-- Eliminate this copy.
1608 // 5 QUUX %src<kill>
1610 // Here OtherVNI will map to itself in [1;2), but to VNI in [2;5). CR_Replace
1611 // handles this complex value mapping.
1612 if ((V.WriteLanes & OtherV.ValidLanes) == 0)
1615 // If the other live range is killed by DefMI and the live ranges are still
1616 // overlapping, it must be because we're looking at an early clobber def:
1618 // %dst<def,early-clobber> = ASM %src<kill>
1620 // In this case, it is illegal to merge the two live ranges since the early
1621 // clobber def would clobber %src before it was read.
1622 if (OtherLRQ.isKill()) {
1623 // This case where the def doesn't overlap the kill is handled above.
1624 assert(VNI->def.isEarlyClobber() &&
1625 "Only early clobber defs can overlap a kill");
1626 return CR_Impossible;
1629 // VNI is clobbering live lanes in OtherVNI, but there is still the
1630 // possibility that no instructions actually read the clobbered lanes.
1631 // If we're clobbering all the lanes in OtherVNI, at least one must be read.
1632 // Otherwise Other.LI wouldn't be live here.
1633 if ((TRI->getSubRegIndexLaneMask(Other.SubIdx) & ~V.WriteLanes) == 0)
1634 return CR_Impossible;
1636 // We need to verify that no instructions are reading the clobbered lanes. To
1637 // save compile time, we'll only check that locally. Don't allow the tainted
1638 // value to escape the basic block.
1639 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
1640 if (OtherLRQ.endPoint() >= Indexes->getMBBEndIdx(MBB))
1641 return CR_Impossible;
1643 // There are still some things that could go wrong besides clobbered lanes
1644 // being read, for example OtherVNI may be only partially redefined in MBB,
1645 // and some clobbered lanes could escape the block. Save this analysis for
1646 // resolveConflicts() when all values have been mapped. We need to know
1647 // RedefVNI and WriteLanes for any later defs in MBB, and we can't compute
1648 // that now - the recursive analyzeValue() calls must go upwards in the
1650 return CR_Unresolved;
1653 /// Compute the value assignment for ValNo in LI.
1654 /// This may be called recursively by analyzeValue(), but never for a ValNo on
1656 void JoinVals::computeAssignment(unsigned ValNo, JoinVals &Other) {
1657 Val &V = Vals[ValNo];
1658 if (V.isAnalyzed()) {
1659 // Recursion should always move up the dominator tree, so ValNo is not
1660 // supposed to reappear before it has been assigned.
1661 assert(Assignments[ValNo] != -1 && "Bad recursion?");
1664 switch ((V.Resolution = analyzeValue(ValNo, Other))) {
1667 // Merge this ValNo into OtherVNI.
1668 assert(V.OtherVNI && "OtherVNI not assigned, can't merge.");
1669 assert(Other.Vals[V.OtherVNI->id].isAnalyzed() && "Missing recursion");
1670 Assignments[ValNo] = Other.Assignments[V.OtherVNI->id];
1671 DEBUG(dbgs() << "\t\tmerge " << PrintReg(LI.reg) << ':' << ValNo << '@'
1672 << LI.getValNumInfo(ValNo)->def << " into "
1673 << PrintReg(Other.LI.reg) << ':' << V.OtherVNI->id << '@'
1674 << V.OtherVNI->def << " --> @"
1675 << NewVNInfo[Assignments[ValNo]]->def << '\n');
1679 // The other value is going to be pruned if this join is successful.
1680 assert(V.OtherVNI && "OtherVNI not assigned, can't prune");
1681 Other.Vals[V.OtherVNI->id].Pruned = true;
1684 // This value number needs to go in the final joined live range.
1685 Assignments[ValNo] = NewVNInfo.size();
1686 NewVNInfo.push_back(LI.getValNumInfo(ValNo));
1691 bool JoinVals::mapValues(JoinVals &Other) {
1692 for (unsigned i = 0, e = LI.getNumValNums(); i != e; ++i) {
1693 computeAssignment(i, Other);
1694 if (Vals[i].Resolution == CR_Impossible) {
1695 DEBUG(dbgs() << "\t\tinterference at " << PrintReg(LI.reg) << ':' << i
1696 << '@' << LI.getValNumInfo(i)->def << '\n');
1703 /// Assuming ValNo is going to clobber some valid lanes in Other.LI, compute
1704 /// the extent of the tainted lanes in the block.
1706 /// Multiple values in Other.LI can be affected since partial redefinitions can
1707 /// preserve previously tainted lanes.
1709 /// 1 %dst = VLOAD <-- Define all lanes in %dst
1710 /// 2 %src = FOO <-- ValNo to be joined with %dst:ssub0
1711 /// 3 %dst:ssub1 = BAR <-- Partial redef doesn't clear taint in ssub0
1712 /// 4 %dst:ssub0 = COPY %src <-- Conflict resolved, ssub0 wasn't read
1714 /// For each ValNo in Other that is affected, add an (EndIndex, TaintedLanes)
1715 /// entry to TaintedVals.
1717 /// Returns false if the tainted lanes extend beyond the basic block.
1719 taintExtent(unsigned ValNo, unsigned TaintedLanes, JoinVals &Other,
1720 SmallVectorImpl<std::pair<SlotIndex, unsigned> > &TaintExtent) {
1721 VNInfo *VNI = LI.getValNumInfo(ValNo);
1722 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
1723 SlotIndex MBBEnd = Indexes->getMBBEndIdx(MBB);
1725 // Scan Other.LI from VNI.def to MBBEnd.
1726 LiveInterval::iterator OtherI = Other.LI.find(VNI->def);
1727 assert(OtherI != Other.LI.end() && "No conflict?");
1729 // OtherI is pointing to a tainted value. Abort the join if the tainted
1730 // lanes escape the block.
1731 SlotIndex End = OtherI->end;
1732 if (End >= MBBEnd) {
1733 DEBUG(dbgs() << "\t\ttaints global " << PrintReg(Other.LI.reg) << ':'
1734 << OtherI->valno->id << '@' << OtherI->start << '\n');
1737 DEBUG(dbgs() << "\t\ttaints local " << PrintReg(Other.LI.reg) << ':'
1738 << OtherI->valno->id << '@' << OtherI->start
1739 << " to " << End << '\n');
1740 // A dead def is not a problem.
1743 TaintExtent.push_back(std::make_pair(End, TaintedLanes));
1745 // Check for another def in the MBB.
1746 if (++OtherI == Other.LI.end() || OtherI->start >= MBBEnd)
1749 // Lanes written by the new def are no longer tainted.
1750 const Val &OV = Other.Vals[OtherI->valno->id];
1751 TaintedLanes &= ~OV.WriteLanes;
1754 } while (TaintedLanes);
1758 /// Return true if MI uses any of the given Lanes from Reg.
1759 /// This does not include partial redefinitions of Reg.
1760 bool JoinVals::usesLanes(MachineInstr *MI, unsigned Reg, unsigned SubIdx,
1762 if (MI->isDebugValue())
1764 for (ConstMIOperands MO(MI); MO.isValid(); ++MO) {
1765 if (!MO->isReg() || MO->isDef() || MO->getReg() != Reg)
1767 if (!MO->readsReg())
1769 if (Lanes & TRI->getSubRegIndexLaneMask(
1770 TRI->composeSubRegIndices(SubIdx, MO->getSubReg())))
1776 bool JoinVals::resolveConflicts(JoinVals &Other) {
1777 for (unsigned i = 0, e = LI.getNumValNums(); i != e; ++i) {
1779 assert (V.Resolution != CR_Impossible && "Unresolvable conflict");
1780 if (V.Resolution != CR_Unresolved)
1782 DEBUG(dbgs() << "\t\tconflict at " << PrintReg(LI.reg) << ':' << i
1783 << '@' << LI.getValNumInfo(i)->def << '\n');
1785 assert(V.OtherVNI && "Inconsistent conflict resolution.");
1786 VNInfo *VNI = LI.getValNumInfo(i);
1787 const Val &OtherV = Other.Vals[V.OtherVNI->id];
1789 // VNI is known to clobber some lanes in OtherVNI. If we go ahead with the
1790 // join, those lanes will be tainted with a wrong value. Get the extent of
1791 // the tainted lanes.
1792 unsigned TaintedLanes = V.WriteLanes & OtherV.ValidLanes;
1793 SmallVector<std::pair<SlotIndex, unsigned>, 8> TaintExtent;
1794 if (!taintExtent(i, TaintedLanes, Other, TaintExtent))
1795 // Tainted lanes would extend beyond the basic block.
1798 assert(!TaintExtent.empty() && "There should be at least one conflict.");
1800 // Now look at the instructions from VNI->def to TaintExtent (inclusive).
1801 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
1802 MachineBasicBlock::iterator MI = MBB->begin();
1803 if (!VNI->isPHIDef()) {
1804 MI = Indexes->getInstructionFromIndex(VNI->def);
1805 // No need to check the instruction defining VNI for reads.
1808 assert(!SlotIndex::isSameInstr(VNI->def, TaintExtent.front().first) &&
1809 "Interference ends on VNI->def. Should have been handled earlier");
1810 MachineInstr *LastMI =
1811 Indexes->getInstructionFromIndex(TaintExtent.front().first);
1812 assert(LastMI && "Range must end at a proper instruction");
1813 unsigned TaintNum = 0;
1815 assert(MI != MBB->end() && "Bad LastMI");
1816 if (usesLanes(MI, Other.LI.reg, Other.SubIdx, TaintedLanes)) {
1817 DEBUG(dbgs() << "\t\ttainted lanes used by: " << *MI);
1820 // LastMI is the last instruction to use the current value.
1821 if (&*MI == LastMI) {
1822 if (++TaintNum == TaintExtent.size())
1824 LastMI = Indexes->getInstructionFromIndex(TaintExtent[TaintNum].first);
1825 assert(LastMI && "Range must end at a proper instruction");
1826 TaintedLanes = TaintExtent[TaintNum].second;
1831 // The tainted lanes are unused.
1832 V.Resolution = CR_Replace;
1838 // Determine if ValNo is a copy of a value number in LI or Other.LI that will
1842 // %src = COPY %dst <-- This value to be pruned.
1843 // %dst = COPY %src <-- This value is a copy of a pruned value.
1845 bool JoinVals::isPrunedValue(unsigned ValNo, JoinVals &Other) {
1846 Val &V = Vals[ValNo];
1847 if (V.Pruned || V.PrunedComputed)
1850 if (V.Resolution != CR_Erase && V.Resolution != CR_Merge)
1853 // Follow copies up the dominator tree and check if any intermediate value
1855 V.PrunedComputed = true;
1856 V.Pruned = Other.isPrunedValue(V.OtherVNI->id, *this);
1860 void JoinVals::pruneValues(JoinVals &Other,
1861 SmallVectorImpl<SlotIndex> &EndPoints) {
1862 for (unsigned i = 0, e = LI.getNumValNums(); i != e; ++i) {
1863 SlotIndex Def = LI.getValNumInfo(i)->def;
1864 switch (Vals[i].Resolution) {
1868 // This value takes precedence over the value in Other.LI.
1869 LIS->pruneValue(&Other.LI, Def, &EndPoints);
1870 // Check if we're replacing an IMPLICIT_DEF value. The IMPLICIT_DEF
1871 // instructions are only inserted to provide a live-out value for PHI
1872 // predecessors, so the instruction should simply go away once its value
1873 // has been replaced.
1874 Val &OtherV = Other.Vals[Vals[i].OtherVNI->id];
1875 bool EraseImpDef = OtherV.ErasableImplicitDef &&
1876 OtherV.Resolution == CR_Keep;
1877 if (!Def.isBlock()) {
1878 // Remove <def,read-undef> flags. This def is now a partial redef.
1879 // Also remove <def,dead> flags since the joined live range will
1880 // continue past this instruction.
1881 for (MIOperands MO(Indexes->getInstructionFromIndex(Def));
1883 if (MO->isReg() && MO->isDef() && MO->getReg() == LI.reg) {
1884 MO->setIsUndef(EraseImpDef);
1885 MO->setIsDead(false);
1887 // This value will reach instructions below, but we need to make sure
1888 // the live range also reaches the instruction at Def.
1890 EndPoints.push_back(Def);
1892 DEBUG(dbgs() << "\t\tpruned " << PrintReg(Other.LI.reg) << " at " << Def
1893 << ": " << Other.LI << '\n');
1898 if (isPrunedValue(i, Other)) {
1899 // This value is ultimately a copy of a pruned value in LI or Other.LI.
1900 // We can no longer trust the value mapping computed by
1901 // computeAssignment(), the value that was originally copied could have
1903 LIS->pruneValue(&LI, Def, &EndPoints);
1904 DEBUG(dbgs() << "\t\tpruned all of " << PrintReg(LI.reg) << " at "
1905 << Def << ": " << LI << '\n');
1910 llvm_unreachable("Unresolved conflicts");
1915 void JoinVals::eraseInstrs(SmallPtrSet<MachineInstr*, 8> &ErasedInstrs,
1916 SmallVectorImpl<unsigned> &ShrinkRegs) {
1917 for (unsigned i = 0, e = LI.getNumValNums(); i != e; ++i) {
1918 // Get the def location before markUnused() below invalidates it.
1919 SlotIndex Def = LI.getValNumInfo(i)->def;
1920 switch (Vals[i].Resolution) {
1922 // If an IMPLICIT_DEF value is pruned, it doesn't serve a purpose any
1923 // longer. The IMPLICIT_DEF instructions are only inserted by
1924 // PHIElimination to guarantee that all PHI predecessors have a value.
1925 if (!Vals[i].ErasableImplicitDef || !Vals[i].Pruned)
1927 // Remove value number i from LI. Note that this VNInfo is still present
1928 // in NewVNInfo, so it will appear as an unused value number in the final
1930 LI.getValNumInfo(i)->markUnused();
1931 LI.removeValNo(LI.getValNumInfo(i));
1932 DEBUG(dbgs() << "\t\tremoved " << i << '@' << Def << ": " << LI << '\n');
1936 MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
1937 assert(MI && "No instruction to erase");
1939 unsigned Reg = MI->getOperand(1).getReg();
1940 if (TargetRegisterInfo::isVirtualRegister(Reg) &&
1941 Reg != CP.getSrcReg() && Reg != CP.getDstReg())
1942 ShrinkRegs.push_back(Reg);
1944 ErasedInstrs.insert(MI);
1945 DEBUG(dbgs() << "\t\terased:\t" << Def << '\t' << *MI);
1946 LIS->RemoveMachineInstrFromMaps(MI);
1947 MI->eraseFromParent();
1956 bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
1957 SmallVector<VNInfo*, 16> NewVNInfo;
1958 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1959 LiveInterval &LHS = LIS->getInterval(CP.getDstReg());
1960 JoinVals RHSVals(RHS, CP.getSrcIdx(), NewVNInfo, CP, LIS, TRI);
1961 JoinVals LHSVals(LHS, CP.getDstIdx(), NewVNInfo, CP, LIS, TRI);
1963 DEBUG(dbgs() << "\t\tRHS = " << PrintReg(CP.getSrcReg()) << ' ' << RHS
1964 << "\n\t\tLHS = " << PrintReg(CP.getDstReg()) << ' ' << LHS
1967 // First compute NewVNInfo and the simple value mappings.
1968 // Detect impossible conflicts early.
1969 if (!LHSVals.mapValues(RHSVals) || !RHSVals.mapValues(LHSVals))
1972 // Some conflicts can only be resolved after all values have been mapped.
1973 if (!LHSVals.resolveConflicts(RHSVals) || !RHSVals.resolveConflicts(LHSVals))
1976 // All clear, the live ranges can be merged.
1978 // The merging algorithm in LiveInterval::join() can't handle conflicting
1979 // value mappings, so we need to remove any live ranges that overlap a
1980 // CR_Replace resolution. Collect a set of end points that can be used to
1981 // restore the live range after joining.
1982 SmallVector<SlotIndex, 8> EndPoints;
1983 LHSVals.pruneValues(RHSVals, EndPoints);
1984 RHSVals.pruneValues(LHSVals, EndPoints);
1986 // Erase COPY and IMPLICIT_DEF instructions. This may cause some external
1987 // registers to require trimming.
1988 SmallVector<unsigned, 8> ShrinkRegs;
1989 LHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs);
1990 RHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs);
1991 while (!ShrinkRegs.empty())
1992 LIS->shrinkToUses(&LIS->getInterval(ShrinkRegs.pop_back_val()));
1994 // Join RHS into LHS.
1995 LHS.join(RHS, LHSVals.getAssignments(), RHSVals.getAssignments(), NewVNInfo,
1998 // Kill flags are going to be wrong if the live ranges were overlapping.
1999 // Eventually, we should simply clear all kill flags when computing live
2000 // ranges. They are reinserted after register allocation.
2001 MRI->clearKillFlags(LHS.reg);
2002 MRI->clearKillFlags(RHS.reg);
2004 if (EndPoints.empty())
2007 // Recompute the parts of the live range we had to remove because of
2008 // CR_Replace conflicts.
2009 DEBUG(dbgs() << "\t\trestoring liveness to " << EndPoints.size()
2010 << " points: " << LHS << '\n');
2011 LIS->extendToIndices(&LHS, EndPoints);
2015 /// joinIntervals - Attempt to join these two intervals. On failure, this
2017 bool RegisterCoalescer::joinIntervals(CoalescerPair &CP) {
2018 return CP.isPhys() ? joinReservedPhysReg(CP) : joinVirtRegs(CP);
2022 // Information concerning MBB coalescing priority.
2023 struct MBBPriorityInfo {
2024 MachineBasicBlock *MBB;
2028 MBBPriorityInfo(MachineBasicBlock *mbb, unsigned depth, bool issplit)
2029 : MBB(mbb), Depth(depth), IsSplit(issplit) {}
2033 // C-style comparator that sorts first based on the loop depth of the basic
2034 // block (the unsigned), and then on the MBB number.
2036 // EnableGlobalCopies assumes that the primary sort key is loop depth.
2037 static int compareMBBPriority(const void *L, const void *R) {
2038 const MBBPriorityInfo *LHS = static_cast<const MBBPriorityInfo*>(L);
2039 const MBBPriorityInfo *RHS = static_cast<const MBBPriorityInfo*>(R);
2040 // Deeper loops first
2041 if (LHS->Depth != RHS->Depth)
2042 return LHS->Depth > RHS->Depth ? -1 : 1;
2044 // Try to unsplit critical edges next.
2045 if (LHS->IsSplit != RHS->IsSplit)
2046 return LHS->IsSplit ? -1 : 1;
2048 // Prefer blocks that are more connected in the CFG. This takes care of
2049 // the most difficult copies first while intervals are short.
2050 unsigned cl = LHS->MBB->pred_size() + LHS->MBB->succ_size();
2051 unsigned cr = RHS->MBB->pred_size() + RHS->MBB->succ_size();
2053 return cl > cr ? -1 : 1;
2055 // As a last resort, sort by block number.
2056 return LHS->MBB->getNumber() < RHS->MBB->getNumber() ? -1 : 1;
2059 /// \returns true if the given copy uses or defines a local live range.
2060 static bool isLocalCopy(MachineInstr *Copy, const LiveIntervals *LIS) {
2061 if (!Copy->isCopy())
2064 unsigned SrcReg = Copy->getOperand(1).getReg();
2065 unsigned DstReg = Copy->getOperand(0).getReg();
2066 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)
2067 || TargetRegisterInfo::isPhysicalRegister(DstReg))
2070 return LIS->intervalIsInOneMBB(LIS->getInterval(SrcReg))
2071 || LIS->intervalIsInOneMBB(LIS->getInterval(DstReg));
2074 // Try joining WorkList copies starting from index From.
2075 // Null out any successful joins.
2076 bool RegisterCoalescer::
2077 copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList) {
2078 bool Progress = false;
2079 for (unsigned i = 0, e = CurrList.size(); i != e; ++i) {
2082 // Skip instruction pointers that have already been erased, for example by
2083 // dead code elimination.
2084 if (ErasedInstrs.erase(CurrList[i])) {
2089 bool Success = joinCopy(CurrList[i], Again);
2090 Progress |= Success;
2091 if (Success || !Again)
2098 RegisterCoalescer::copyCoalesceInMBB(MachineBasicBlock *MBB) {
2099 DEBUG(dbgs() << MBB->getName() << ":\n");
2101 // Collect all copy-like instructions in MBB. Don't start coalescing anything
2102 // yet, it might invalidate the iterator.
2103 const unsigned PrevSize = WorkList.size();
2104 if (JoinGlobalCopies) {
2105 // Coalesce copies bottom-up to coalesce local defs before local uses. They
2106 // are not inherently easier to resolve, but slightly preferable until we
2107 // have local live range splitting. In particular this is required by
2108 // cmp+jmp macro fusion.
2109 for (MachineBasicBlock::reverse_iterator
2110 MII = MBB->rbegin(), E = MBB->rend(); MII != E; ++MII) {
2111 if (!MII->isCopyLike())
2113 if (isLocalCopy(&(*MII), LIS))
2114 LocalWorkList.push_back(&(*MII));
2116 WorkList.push_back(&(*MII));
2120 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
2122 if (MII->isCopyLike())
2123 WorkList.push_back(MII);
2125 // Try coalescing the collected copies immediately, and remove the nulls.
2126 // This prevents the WorkList from getting too large since most copies are
2127 // joinable on the first attempt.
2128 MutableArrayRef<MachineInstr*>
2129 CurrList(WorkList.begin() + PrevSize, WorkList.end());
2130 if (copyCoalesceWorkList(CurrList))
2131 WorkList.erase(std::remove(WorkList.begin() + PrevSize, WorkList.end(),
2132 (MachineInstr*)0), WorkList.end());
2135 void RegisterCoalescer::coalesceLocals() {
2136 copyCoalesceWorkList(LocalWorkList);
2137 for (unsigned j = 0, je = LocalWorkList.size(); j != je; ++j) {
2138 if (LocalWorkList[j])
2139 WorkList.push_back(LocalWorkList[j]);
2141 LocalWorkList.clear();
2144 void RegisterCoalescer::joinAllIntervals() {
2145 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
2146 assert(WorkList.empty() && LocalWorkList.empty() && "Old data still around.");
2148 std::vector<MBBPriorityInfo> MBBs;
2149 MBBs.reserve(MF->size());
2150 for (MachineFunction::iterator I = MF->begin(), E = MF->end();I != E;++I){
2151 MachineBasicBlock *MBB = I;
2152 MBBs.push_back(MBBPriorityInfo(MBB, Loops->getLoopDepth(MBB),
2153 JoinSplitEdges && isSplitEdge(MBB)));
2155 array_pod_sort(MBBs.begin(), MBBs.end(), compareMBBPriority);
2157 // Coalesce intervals in MBB priority order.
2158 unsigned CurrDepth = UINT_MAX;
2159 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
2160 // Try coalescing the collected local copies for deeper loops.
2161 if (JoinGlobalCopies && MBBs[i].Depth < CurrDepth) {
2163 CurrDepth = MBBs[i].Depth;
2165 copyCoalesceInMBB(MBBs[i].MBB);
2169 // Joining intervals can allow other intervals to be joined. Iteratively join
2170 // until we make no progress.
2171 while (copyCoalesceWorkList(WorkList))
2175 void RegisterCoalescer::releaseMemory() {
2176 ErasedInstrs.clear();
2179 InflateRegs.clear();
2182 bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
2184 MRI = &fn.getRegInfo();
2185 TM = &fn.getTarget();
2186 TRI = TM->getRegisterInfo();
2187 TII = TM->getInstrInfo();
2188 LIS = &getAnalysis<LiveIntervals>();
2189 AA = &getAnalysis<AliasAnalysis>();
2190 Loops = &getAnalysis<MachineLoopInfo>();
2192 const TargetSubtargetInfo &ST = TM->getSubtarget<TargetSubtargetInfo>();
2193 if (EnableGlobalCopies == cl::BOU_UNSET)
2194 JoinGlobalCopies = ST.enableMachineScheduler();
2196 JoinGlobalCopies = (EnableGlobalCopies == cl::BOU_TRUE);
2198 // The MachineScheduler does not currently require JoinSplitEdges. This will
2199 // either be enabled unconditionally or replaced by a more general live range
2200 // splitting optimization.
2201 JoinSplitEdges = EnableJoinSplits;
2203 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
2204 << "********** Function: " << MF->getName() << '\n');
2206 if (VerifyCoalescing)
2207 MF->verify(this, "Before register coalescing");
2209 RegClassInfo.runOnMachineFunction(fn);
2211 // Join (coalesce) intervals if requested.
2215 // After deleting a lot of copies, register classes may be less constrained.
2216 // Removing sub-register operands may allow GR32_ABCD -> GR32 and DPR_VFP2 ->
2218 array_pod_sort(InflateRegs.begin(), InflateRegs.end());
2219 InflateRegs.erase(std::unique(InflateRegs.begin(), InflateRegs.end()),
2221 DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size() << " regs.\n");
2222 for (unsigned i = 0, e = InflateRegs.size(); i != e; ++i) {
2223 unsigned Reg = InflateRegs[i];
2224 if (MRI->reg_nodbg_empty(Reg))
2226 if (MRI->recomputeRegClass(Reg, *TM)) {
2227 DEBUG(dbgs() << PrintReg(Reg) << " inflated to "
2228 << MRI->getRegClass(Reg)->getName() << '\n');
2234 if (VerifyCoalescing)
2235 MF->verify(this, "After register coalescing");
2239 /// print - Implement the dump method.
2240 void RegisterCoalescer::print(raw_ostream &O, const Module* m) const {