1 //===- RegisterCoalescer.cpp - Generic Register Coalescing Interface -------==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the generic RegisterCoalescer interface which
11 // is used as the common interface used by all clients and
12 // implementations of register coalescing.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "regalloc"
17 #include "RegisterCoalescer.h"
18 #include "LiveDebugVariables.h"
19 #include "RegisterClassInfo.h"
20 #include "VirtRegMap.h"
22 #include "llvm/Pass.h"
23 #include "llvm/Value.h"
24 #include "llvm/ADT/OwningPtr.h"
25 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/ADT/SmallSet.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Analysis/AliasAnalysis.h"
29 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
30 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
31 #include "llvm/CodeGen/LiveRangeEdit.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineInstr.h"
34 #include "llvm/CodeGen/MachineInstr.h"
35 #include "llvm/CodeGen/MachineLoopInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/Support/CommandLine.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/ErrorHandling.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Target/TargetRegisterInfo.h"
52 STATISTIC(numJoins , "Number of interval joins performed");
53 STATISTIC(numCrossRCs , "Number of cross class joins performed");
54 STATISTIC(numCommutes , "Number of instruction commuting performed");
55 STATISTIC(numExtends , "Number of copies extended");
56 STATISTIC(NumReMats , "Number of instructions re-materialized");
57 STATISTIC(NumInflated , "Number of register classes inflated");
60 EnableJoining("join-liveintervals",
61 cl::desc("Coalesce copies (default=true)"),
65 VerifyCoalescing("verify-coalescing",
66 cl::desc("Verify machine instrs before and after register coalescing"),
70 class RegisterCoalescer : public MachineFunctionPass,
71 private LiveRangeEdit::Delegate {
73 MachineRegisterInfo* MRI;
74 const TargetMachine* TM;
75 const TargetRegisterInfo* TRI;
76 const TargetInstrInfo* TII;
78 LiveDebugVariables *LDV;
79 const MachineLoopInfo* Loops;
81 RegisterClassInfo RegClassInfo;
83 /// WorkList - Copy instructions yet to be coalesced.
84 SmallVector<MachineInstr*, 8> WorkList;
86 /// ErasedInstrs - Set of instruction pointers that have been erased, and
87 /// that may be present in WorkList.
88 SmallPtrSet<MachineInstr*, 8> ErasedInstrs;
90 /// Dead instructions that are about to be deleted.
91 SmallVector<MachineInstr*, 8> DeadDefs;
93 /// Virtual registers to be considered for register class inflation.
94 SmallVector<unsigned, 8> InflateRegs;
96 /// Recursively eliminate dead defs in DeadDefs.
97 void eliminateDeadDefs();
99 /// LiveRangeEdit callback.
100 void LRE_WillEraseInstruction(MachineInstr *MI);
102 /// joinAllIntervals - join compatible live intervals
103 void joinAllIntervals();
105 /// copyCoalesceInMBB - Coalesce copies in the specified MBB, putting
106 /// copies that cannot yet be coalesced into WorkList.
107 void copyCoalesceInMBB(MachineBasicBlock *MBB);
109 /// copyCoalesceWorkList - Try to coalesce all copies in WorkList after
110 /// position From. Return true if any progress was made.
111 bool copyCoalesceWorkList(unsigned From = 0);
113 /// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
114 /// which are the src/dst of the copy instruction CopyMI. This returns
115 /// true if the copy was successfully coalesced away. If it is not
116 /// currently possible to coalesce this interval, but it may be possible if
117 /// other things get coalesced, then it returns true by reference in
119 bool joinCopy(MachineInstr *TheCopy, bool &Again);
121 /// joinIntervals - Attempt to join these two intervals. On failure, this
122 /// returns false. The output "SrcInt" will not have been modified, so we
123 /// can use this information below to update aliases.
124 bool joinIntervals(CoalescerPair &CP);
126 /// Attempt joining with a reserved physreg.
127 bool joinReservedPhysReg(CoalescerPair &CP);
129 /// adjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
130 /// the source value number is defined by a copy from the destination reg
131 /// see if we can merge these two destination reg valno# into a single
132 /// value number, eliminating a copy.
133 bool adjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
135 /// hasOtherReachingDefs - Return true if there are definitions of IntB
136 /// other than BValNo val# that can reach uses of AValno val# of IntA.
137 bool hasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
138 VNInfo *AValNo, VNInfo *BValNo);
140 /// removeCopyByCommutingDef - We found a non-trivially-coalescable copy.
141 /// If the source value number is defined by a commutable instruction and
142 /// its other operand is coalesced to the copy dest register, see if we
143 /// can transform the copy into a noop by commuting the definition.
144 bool removeCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI);
146 /// reMaterializeTrivialDef - If the source of a copy is defined by a
147 /// trivial computation, replace the copy by rematerialize the definition.
148 bool reMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg,
149 MachineInstr *CopyMI);
151 /// canJoinPhys - Return true if a physreg copy should be joined.
152 bool canJoinPhys(CoalescerPair &CP);
154 /// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
155 /// update the subregister number if it is not zero. If DstReg is a
156 /// physical register and the existing subregister number of the def / use
157 /// being updated is not zero, make sure to set it to the correct physical
159 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
161 /// eliminateUndefCopy - Handle copies of undef values.
162 bool eliminateUndefCopy(MachineInstr *CopyMI, const CoalescerPair &CP);
165 static char ID; // Class identification, replacement for typeinfo
166 RegisterCoalescer() : MachineFunctionPass(ID) {
167 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
170 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
172 virtual void releaseMemory();
174 /// runOnMachineFunction - pass entry point
175 virtual bool runOnMachineFunction(MachineFunction&);
177 /// print - Implement the dump method.
178 virtual void print(raw_ostream &O, const Module* = 0) const;
180 } /// end anonymous namespace
182 char &llvm::RegisterCoalescerID = RegisterCoalescer::ID;
184 INITIALIZE_PASS_BEGIN(RegisterCoalescer, "simple-register-coalescing",
185 "Simple Register Coalescing", false, false)
186 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
187 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
188 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
189 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
190 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
191 INITIALIZE_PASS_END(RegisterCoalescer, "simple-register-coalescing",
192 "Simple Register Coalescing", false, false)
194 char RegisterCoalescer::ID = 0;
196 static unsigned compose(const TargetRegisterInfo &tri, unsigned a, unsigned b) {
199 return tri.composeSubRegIndices(a, b);
202 static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI,
203 unsigned &Src, unsigned &Dst,
204 unsigned &SrcSub, unsigned &DstSub) {
206 Dst = MI->getOperand(0).getReg();
207 DstSub = MI->getOperand(0).getSubReg();
208 Src = MI->getOperand(1).getReg();
209 SrcSub = MI->getOperand(1).getSubReg();
210 } else if (MI->isSubregToReg()) {
211 Dst = MI->getOperand(0).getReg();
212 DstSub = compose(tri, MI->getOperand(0).getSubReg(),
213 MI->getOperand(3).getImm());
214 Src = MI->getOperand(2).getReg();
215 SrcSub = MI->getOperand(2).getSubReg();
221 bool CoalescerPair::setRegisters(const MachineInstr *MI) {
225 Flipped = CrossClass = false;
227 unsigned Src, Dst, SrcSub, DstSub;
228 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
230 Partial = SrcSub || DstSub;
232 // If one register is a physreg, it must be Dst.
233 if (TargetRegisterInfo::isPhysicalRegister(Src)) {
234 if (TargetRegisterInfo::isPhysicalRegister(Dst))
237 std::swap(SrcSub, DstSub);
241 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
243 if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
244 // Eliminate DstSub on a physreg.
246 Dst = TRI.getSubReg(Dst, DstSub);
247 if (!Dst) return false;
251 // Eliminate SrcSub by picking a corresponding Dst superregister.
253 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
254 if (!Dst) return false;
256 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
260 // Both registers are virtual.
261 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
262 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
264 // Both registers have subreg indices.
265 if (SrcSub && DstSub) {
266 // Copies between different sub-registers are never coalescable.
267 if (Src == Dst && SrcSub != DstSub)
270 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
275 // SrcReg will be merged with a sub-register of DstReg.
277 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
279 // DstReg will be merged with a sub-register of SrcReg.
281 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
283 // This is a straight copy without sub-registers.
284 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
287 // The combined constraint may be impossible to satisfy.
291 // Prefer SrcReg to be a sub-register of DstReg.
292 // FIXME: Coalescer should support subregs symmetrically.
293 if (DstIdx && !SrcIdx) {
295 std::swap(SrcIdx, DstIdx);
299 CrossClass = NewRC != DstRC || NewRC != SrcRC;
301 // Check our invariants
302 assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual");
303 assert(!(TargetRegisterInfo::isPhysicalRegister(Dst) && DstSub) &&
304 "Cannot have a physical SubIdx");
310 bool CoalescerPair::flip() {
311 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
313 std::swap(SrcReg, DstReg);
314 std::swap(SrcIdx, DstIdx);
319 bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
322 unsigned Src, Dst, SrcSub, DstSub;
323 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
326 // Find the virtual register that is SrcReg.
329 std::swap(SrcSub, DstSub);
330 } else if (Src != SrcReg) {
334 // Now check that Dst matches DstReg.
335 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
336 if (!TargetRegisterInfo::isPhysicalRegister(Dst))
338 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.");
339 // DstSub could be set for a physreg from INSERT_SUBREG.
341 Dst = TRI.getSubReg(Dst, DstSub);
344 return DstReg == Dst;
345 // This is a partial register copy. Check that the parts match.
346 return TRI.getSubReg(DstReg, SrcSub) == Dst;
348 // DstReg is virtual.
351 // Registers match, do the subregisters line up?
352 return compose(TRI, SrcIdx, SrcSub) == compose(TRI, DstIdx, DstSub);
356 void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const {
357 AU.setPreservesCFG();
358 AU.addRequired<AliasAnalysis>();
359 AU.addRequired<LiveIntervals>();
360 AU.addPreserved<LiveIntervals>();
361 AU.addRequired<LiveDebugVariables>();
362 AU.addPreserved<LiveDebugVariables>();
363 AU.addPreserved<SlotIndexes>();
364 AU.addRequired<MachineLoopInfo>();
365 AU.addPreserved<MachineLoopInfo>();
366 AU.addPreservedID(MachineDominatorsID);
367 MachineFunctionPass::getAnalysisUsage(AU);
370 void RegisterCoalescer::eliminateDeadDefs() {
371 SmallVector<LiveInterval*, 8> NewRegs;
372 LiveRangeEdit(0, NewRegs, *MF, *LIS, 0, this).eliminateDeadDefs(DeadDefs);
375 // Callback from eliminateDeadDefs().
376 void RegisterCoalescer::LRE_WillEraseInstruction(MachineInstr *MI) {
377 // MI may be in WorkList. Make sure we don't visit it.
378 ErasedInstrs.insert(MI);
381 /// adjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
382 /// being the source and IntB being the dest, thus this defines a value number
383 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
384 /// see if we can merge these two pieces of B into a single value number,
385 /// eliminating a copy. For example:
389 /// B1 = A3 <- this copy
391 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
392 /// value number to be replaced with B0 (which simplifies the B liveinterval).
394 /// This returns true if an interval was modified.
396 bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP,
397 MachineInstr *CopyMI) {
398 assert(!CP.isPartial() && "This doesn't work for partial copies.");
400 // Bail if there is no dst interval - can happen when merging physical subreg
402 if (!LIS->hasInterval(CP.getDstReg()))
406 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
408 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
409 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
411 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
412 // the example above.
413 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
414 if (BLR == IntB.end()) return false;
415 VNInfo *BValNo = BLR->valno;
417 // Get the location that B is defined at. Two options: either this value has
418 // an unknown definition point or it is defined at CopyIdx. If unknown, we
420 if (BValNo->def != CopyIdx) return false;
422 // AValNo is the value number in A that defines the copy, A3 in the example.
423 SlotIndex CopyUseIdx = CopyIdx.getRegSlot(true);
424 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
425 // The live range might not exist after fun with physreg coalescing.
426 if (ALR == IntA.end()) return false;
427 VNInfo *AValNo = ALR->valno;
429 // If AValNo is defined as a copy from IntB, we can potentially process this.
430 // Get the instruction that defines this value number.
431 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
432 if (!CP.isCoalescable(ACopyMI))
435 // Get the LiveRange in IntB that this value number starts with.
436 LiveInterval::iterator ValLR =
437 IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot());
438 if (ValLR == IntB.end())
441 // Make sure that the end of the live range is inside the same block as
443 MachineInstr *ValLREndInst =
444 LIS->getInstructionFromIndex(ValLR->end.getPrevSlot());
445 if (!ValLREndInst || ValLREndInst->getParent() != CopyMI->getParent())
448 // Okay, we now know that ValLR ends in the same block that the CopyMI
449 // live-range starts. If there are no intervening live ranges between them in
450 // IntB, we can merge them.
451 if (ValLR+1 != BLR) return false;
453 // If a live interval is a physical register, conservatively check if any
454 // of its aliases is overlapping the live interval of the virtual register.
455 // If so, do not coalesce.
456 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
457 for (const uint16_t *AS = TRI->getAliasSet(IntB.reg); *AS; ++AS)
458 if (LIS->hasInterval(*AS) && IntA.overlaps(LIS->getInterval(*AS))) {
460 dbgs() << "\t\tInterfere with alias ";
461 LIS->getInterval(*AS).print(dbgs(), TRI);
468 dbgs() << "Extending: ";
469 IntB.print(dbgs(), TRI);
472 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
473 // We are about to delete CopyMI, so need to remove it as the 'instruction
474 // that defines this value #'. Update the valnum with the new defining
476 BValNo->def = FillerStart;
478 // Okay, we can merge them. We need to insert a new liverange:
479 // [ValLR.end, BLR.begin) of either value number, then we merge the
480 // two value numbers.
481 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
483 // If the IntB live range is assigned to a physical register, and if that
484 // physreg has sub-registers, update their live intervals as well.
485 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
486 for (const uint16_t *SR = TRI->getSubRegisters(IntB.reg); *SR; ++SR) {
487 if (!LIS->hasInterval(*SR))
489 LiveInterval &SRLI = LIS->getInterval(*SR);
490 SRLI.addRange(LiveRange(FillerStart, FillerEnd,
491 SRLI.getNextValue(FillerStart,
492 LIS->getVNInfoAllocator())));
496 // Okay, merge "B1" into the same value number as "B0".
497 if (BValNo != ValLR->valno) {
498 // If B1 is killed by a PHI, then the merged live range must also be killed
499 // by the same PHI, as B0 and B1 can not overlap.
500 bool HasPHIKill = BValNo->hasPHIKill();
501 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
503 ValLR->valno->setHasPHIKill(true);
506 dbgs() << " result = ";
507 IntB.print(dbgs(), TRI);
511 // If the source instruction was killing the source register before the
512 // merge, unset the isKill marker given the live range has been extended.
513 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
515 ValLREndInst->getOperand(UIdx).setIsKill(false);
518 // Rewrite the copy. If the copy instruction was killing the destination
519 // register before the merge, find the last use and trim the live range. That
520 // will also add the isKill marker.
521 CopyMI->substituteRegister(IntA.reg, IntB.reg, 0, *TRI);
522 if (ALR->end == CopyIdx)
523 LIS->shrinkToUses(&IntA);
529 /// hasOtherReachingDefs - Return true if there are definitions of IntB
530 /// other than BValNo val# that can reach uses of AValno val# of IntA.
531 bool RegisterCoalescer::hasOtherReachingDefs(LiveInterval &IntA,
535 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
537 if (AI->valno != AValNo) continue;
538 LiveInterval::Ranges::iterator BI =
539 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
540 if (BI != IntB.ranges.begin())
542 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
543 if (BI->valno == BValNo)
545 if (BI->start <= AI->start && BI->end > AI->start)
547 if (BI->start > AI->start && BI->start < AI->end)
554 /// removeCopyByCommutingDef - We found a non-trivially-coalescable copy with
555 /// IntA being the source and IntB being the dest, thus this defines a value
556 /// number in IntB. If the source value number (in IntA) is defined by a
557 /// commutable instruction and its other operand is coalesced to the copy dest
558 /// register, see if we can transform the copy into a noop by commuting the
559 /// definition. For example,
561 /// A3 = op A2 B0<kill>
563 /// B1 = A3 <- this copy
565 /// = op A3 <- more uses
569 /// B2 = op B0 A2<kill>
571 /// B1 = B2 <- now an identify copy
573 /// = op B2 <- more uses
575 /// This returns true if an interval was modified.
577 bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
578 MachineInstr *CopyMI) {
579 // FIXME: For now, only eliminate the copy by commuting its def when the
580 // source register is a virtual register. We want to guard against cases
581 // where the copy is a back edge copy and commuting the def lengthen the
582 // live interval of the source register to the entire loop.
583 if (CP.isPhys() && CP.isFlipped())
586 // Bail if there is no dst interval.
587 if (!LIS->hasInterval(CP.getDstReg()))
590 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
593 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
595 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
597 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
598 // the example above.
599 VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx);
600 if (!BValNo || BValNo->def != CopyIdx)
603 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
605 // AValNo is the value number in A that defines the copy, A3 in the example.
606 VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getRegSlot(true));
607 assert(AValNo && "COPY source not live");
609 // If other defs can reach uses of this def, then it's not safe to perform
611 if (AValNo->isPHIDef() || AValNo->isUnused() || AValNo->hasPHIKill())
613 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
616 if (!DefMI->isCommutable())
618 // If DefMI is a two-address instruction then commuting it will change the
619 // destination register.
620 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
621 assert(DefIdx != -1);
623 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
625 unsigned Op1, Op2, NewDstIdx;
626 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
630 else if (Op2 == UseOpIdx)
635 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
636 unsigned NewReg = NewDstMO.getReg();
637 if (NewReg != IntB.reg || !NewDstMO.isKill())
640 // Make sure there are no other definitions of IntB that would reach the
641 // uses which the new definition can reach.
642 if (hasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
645 // Abort if the aliases of IntB.reg have values that are not simply the
646 // clobbers from the superreg.
647 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
648 for (const uint16_t *AS = TRI->getAliasSet(IntB.reg); *AS; ++AS)
649 if (LIS->hasInterval(*AS) &&
650 hasOtherReachingDefs(IntA, LIS->getInterval(*AS), AValNo, 0))
653 // If some of the uses of IntA.reg is already coalesced away, return false.
654 // It's not possible to determine whether it's safe to perform the coalescing.
655 for (MachineRegisterInfo::use_nodbg_iterator UI =
656 MRI->use_nodbg_begin(IntA.reg),
657 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
658 MachineInstr *UseMI = &*UI;
659 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
660 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
661 if (ULR == IntA.end() || ULR->valno != AValNo)
663 // If this use is tied to a def, we can't rewrite the register.
664 if (UseMI->isRegTiedToDefOperand(UI.getOperandNo()))
668 DEBUG(dbgs() << "\tremoveCopyByCommutingDef: " << AValNo->def << '\t'
671 // At this point we have decided that it is legal to do this
672 // transformation. Start by commuting the instruction.
673 MachineBasicBlock *MBB = DefMI->getParent();
674 MachineInstr *NewMI = TII->commuteInstruction(DefMI);
677 if (TargetRegisterInfo::isVirtualRegister(IntA.reg) &&
678 TargetRegisterInfo::isVirtualRegister(IntB.reg) &&
679 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
681 if (NewMI != DefMI) {
682 LIS->ReplaceMachineInstrInMaps(DefMI, NewMI);
683 MachineBasicBlock::iterator Pos = DefMI;
684 MBB->insert(Pos, NewMI);
687 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
688 NewMI->getOperand(OpIdx).setIsKill();
690 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
699 // Update uses of IntA of the specific Val# with IntB.
700 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg),
701 UE = MRI->use_end(); UI != UE;) {
702 MachineOperand &UseMO = UI.getOperand();
703 MachineInstr *UseMI = &*UI;
705 if (UseMI->isDebugValue()) {
706 // FIXME These don't have an instruction index. Not clear we have enough
707 // info to decide whether to do this replacement or not. For now do it.
708 UseMO.setReg(NewReg);
711 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
712 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
713 if (ULR == IntA.end() || ULR->valno != AValNo)
715 if (TargetRegisterInfo::isPhysicalRegister(NewReg))
716 UseMO.substPhysReg(NewReg, *TRI);
718 UseMO.setReg(NewReg);
721 if (!UseMI->isCopy())
723 if (UseMI->getOperand(0).getReg() != IntB.reg ||
724 UseMI->getOperand(0).getSubReg())
727 // This copy will become a noop. If it's defining a new val#, merge it into
729 SlotIndex DefIdx = UseIdx.getRegSlot();
730 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
733 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
734 assert(DVNI->def == DefIdx);
735 BValNo = IntB.MergeValueNumberInto(BValNo, DVNI);
736 ErasedInstrs.insert(UseMI);
737 LIS->RemoveMachineInstrFromMaps(UseMI);
738 UseMI->eraseFromParent();
741 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
743 VNInfo *ValNo = BValNo;
744 ValNo->def = AValNo->def;
745 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
747 if (AI->valno != AValNo) continue;
748 IntB.addRange(LiveRange(AI->start, AI->end, ValNo));
750 DEBUG(dbgs() << "\t\textended: " << IntB << '\n');
752 IntA.removeValNo(AValNo);
753 DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n');
758 /// reMaterializeTrivialDef - If the source of a copy is defined by a trivial
759 /// computation, replace the copy by rematerialize the definition.
760 bool RegisterCoalescer::reMaterializeTrivialDef(LiveInterval &SrcInt,
762 MachineInstr *CopyMI) {
763 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(true);
764 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
765 assert(SrcLR != SrcInt.end() && "Live range not found!");
766 VNInfo *ValNo = SrcLR->valno;
767 if (ValNo->isPHIDef() || ValNo->isUnused())
769 MachineInstr *DefMI = LIS->getInstructionFromIndex(ValNo->def);
772 assert(DefMI && "Defining instruction disappeared");
773 if (!DefMI->isAsCheapAsAMove())
775 if (!TII->isTriviallyReMaterializable(DefMI, AA))
777 bool SawStore = false;
778 if (!DefMI->isSafeToMove(TII, AA, SawStore))
780 const MCInstrDesc &MCID = DefMI->getDesc();
781 if (MCID.getNumDefs() != 1)
783 if (!DefMI->isImplicitDef()) {
784 // Make sure the copy destination register class fits the instruction
785 // definition register class. The mismatch can happen as a result of earlier
786 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
787 const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI, *MF);
788 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
789 if (MRI->getRegClass(DstReg) != RC)
791 } else if (!RC->contains(DstReg))
795 MachineBasicBlock *MBB = CopyMI->getParent();
796 MachineBasicBlock::iterator MII =
797 llvm::next(MachineBasicBlock::iterator(CopyMI));
798 TII->reMaterialize(*MBB, MII, DstReg, 0, DefMI, *TRI);
799 MachineInstr *NewMI = prior(MII);
801 // NewMI may have dead implicit defs (E.g. EFLAGS for MOV<bits>r0 on X86).
802 // We need to remember these so we can add intervals once we insert
803 // NewMI into SlotIndexes.
804 SmallVector<unsigned, 4> NewMIImplDefs;
805 for (unsigned i = NewMI->getDesc().getNumOperands(),
806 e = NewMI->getNumOperands(); i != e; ++i) {
807 MachineOperand &MO = NewMI->getOperand(i);
809 assert(MO.isDef() && MO.isImplicit() && MO.isDead() &&
810 TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
811 NewMIImplDefs.push_back(MO.getReg());
815 // CopyMI may have implicit operands, transfer them over to the newly
816 // rematerialized instruction. And update implicit def interval valnos.
817 for (unsigned i = CopyMI->getDesc().getNumOperands(),
818 e = CopyMI->getNumOperands(); i != e; ++i) {
819 MachineOperand &MO = CopyMI->getOperand(i);
821 assert(MO.isImplicit() && "No explicit operands after implict operands.");
822 // Discard VReg implicit defs.
823 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
824 NewMI->addOperand(MO);
829 LIS->ReplaceMachineInstrInMaps(CopyMI, NewMI);
831 SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
832 for (unsigned i = 0, e = NewMIImplDefs.size(); i != e; ++i) {
833 unsigned reg = NewMIImplDefs[i];
834 LiveInterval &li = LIS->getInterval(reg);
835 VNInfo *DeadDefVN = li.getNextValue(NewMIIdx.getRegSlot(),
836 LIS->getVNInfoAllocator());
837 LiveRange lr(NewMIIdx.getRegSlot(), NewMIIdx.getDeadSlot(), DeadDefVN);
841 CopyMI->eraseFromParent();
842 ErasedInstrs.insert(CopyMI);
843 DEBUG(dbgs() << "Remat: " << *NewMI);
846 // The source interval can become smaller because we removed a use.
847 LIS->shrinkToUses(&SrcInt, &DeadDefs);
848 if (!DeadDefs.empty())
854 /// eliminateUndefCopy - ProcessImpicitDefs may leave some copies of <undef>
855 /// values, it only removes local variables. When we have a copy like:
857 /// %vreg1 = COPY %vreg2<undef>
859 /// We delete the copy and remove the corresponding value number from %vreg1.
860 /// Any uses of that value number are marked as <undef>.
861 bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI,
862 const CoalescerPair &CP) {
863 SlotIndex Idx = LIS->getInstructionIndex(CopyMI);
864 LiveInterval *SrcInt = &LIS->getInterval(CP.getSrcReg());
865 if (SrcInt->liveAt(Idx))
867 LiveInterval *DstInt = &LIS->getInterval(CP.getDstReg());
868 if (DstInt->liveAt(Idx))
871 // No intervals are live-in to CopyMI - it is undef.
876 VNInfo *DeadVNI = DstInt->getVNInfoAt(Idx.getRegSlot());
877 assert(DeadVNI && "No value defined in DstInt");
878 DstInt->removeValNo(DeadVNI);
880 // Find new undef uses.
881 for (MachineRegisterInfo::reg_nodbg_iterator
882 I = MRI->reg_nodbg_begin(DstInt->reg), E = MRI->reg_nodbg_end();
884 MachineOperand &MO = I.getOperand();
885 if (MO.isDef() || MO.isUndef())
887 MachineInstr *MI = MO.getParent();
888 SlotIndex Idx = LIS->getInstructionIndex(MI);
889 if (DstInt->liveAt(Idx))
892 DEBUG(dbgs() << "\tnew undef: " << Idx << '\t' << *MI);
897 /// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
898 /// update the subregister number if it is not zero. If DstReg is a
899 /// physical register and the existing subregister number of the def / use
900 /// being updated is not zero, make sure to set it to the correct physical
902 void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg,
905 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
906 LiveInterval &DstInt = LIS->getInterval(DstReg);
908 // Update LiveDebugVariables.
909 LDV->renameRegister(SrcReg, DstReg, SubIdx);
911 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg);
912 MachineInstr *UseMI = I.skipInstruction();) {
913 SmallVector<unsigned,8> Ops;
915 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
917 // If SrcReg wasn't read, it may still be the case that DstReg is live-in
918 // because SrcReg is a sub-register.
919 if (!Reads && SubIdx)
920 Reads = DstInt.liveAt(LIS->getInstructionIndex(UseMI));
922 // Replace SrcReg with DstReg in all UseMI operands.
923 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
924 MachineOperand &MO = UseMI->getOperand(Ops[i]);
926 // Adjust <undef> flags in case of sub-register joins. We don't want to
927 // turn a full def into a read-modify-write sub-register def and vice
929 if (SubIdx && MO.isDef())
930 MO.setIsUndef(!Reads);
933 MO.substPhysReg(DstReg, *TRI);
935 MO.substVirtReg(DstReg, SubIdx, *TRI);
939 dbgs() << "\t\tupdated: ";
940 if (!UseMI->isDebugValue())
941 dbgs() << LIS->getInstructionIndex(UseMI) << "\t";
947 /// canJoinPhys - Return true if a copy involving a physreg should be joined.
948 bool RegisterCoalescer::canJoinPhys(CoalescerPair &CP) {
949 /// Always join simple intervals that are defined by a single copy from a
950 /// reserved register. This doesn't increase register pressure, so it is
951 /// always beneficial.
952 if (!RegClassInfo.isReserved(CP.getDstReg())) {
953 DEBUG(dbgs() << "\tCan only merge into reserved registers.\n");
957 LiveInterval &JoinVInt = LIS->getInterval(CP.getSrcReg());
958 if (CP.isFlipped() && JoinVInt.containsOneValue())
961 DEBUG(dbgs() << "\tCannot join defs into reserved register.\n");
965 /// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
966 /// which are the src/dst of the copy instruction CopyMI. This returns true
967 /// if the copy was successfully coalesced away. If it is not currently
968 /// possible to coalesce this interval, but it may be possible if other
969 /// things get coalesced, then it returns true by reference in 'Again'.
970 bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
973 DEBUG(dbgs() << LIS->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
975 CoalescerPair CP(*TII, *TRI);
976 if (!CP.setRegisters(CopyMI)) {
977 DEBUG(dbgs() << "\tNot coalescable.\n");
981 // Dead code elimination. This really should be handled by MachineDCE, but
982 // sometimes dead copies slip through, and we can't generate invalid live
984 if (!CP.isPhys() && CopyMI->allDefsAreDead()) {
985 DEBUG(dbgs() << "\tCopy is dead.\n");
986 DeadDefs.push_back(CopyMI);
991 // If they are already joined we continue.
992 if (CP.getSrcReg() == CP.getDstReg()) {
993 DEBUG(dbgs() << "\tCopy already coalesced.\n");
994 LIS->RemoveMachineInstrFromMaps(CopyMI);
995 CopyMI->eraseFromParent();
996 return false; // Not coalescable.
1000 if (!CP.isPhys() && eliminateUndefCopy(CopyMI, CP)) {
1001 DEBUG(dbgs() << "\tEliminated copy of <undef> value.\n");
1002 LIS->RemoveMachineInstrFromMaps(CopyMI);
1003 CopyMI->eraseFromParent();
1004 return false; // Not coalescable.
1007 // Enforce policies.
1009 DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI)
1010 << " with " << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx())
1012 if (!canJoinPhys(CP)) {
1013 // Before giving up coalescing, if definition of source is defined by
1014 // trivial computation, try rematerializing it.
1015 if (!CP.isFlipped() &&
1016 reMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()),
1017 CP.getDstReg(), CopyMI))
1023 dbgs() << "\tConsidering merging to " << CP.getNewRC()->getName()
1025 if (CP.getDstIdx() && CP.getSrcIdx())
1026 dbgs() << PrintReg(CP.getDstReg()) << " in "
1027 << TRI->getSubRegIndexName(CP.getDstIdx()) << " and "
1028 << PrintReg(CP.getSrcReg()) << " in "
1029 << TRI->getSubRegIndexName(CP.getSrcIdx()) << '\n';
1031 dbgs() << PrintReg(CP.getSrcReg(), TRI) << " in "
1032 << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n';
1035 // When possible, let DstReg be the larger interval.
1036 if (!CP.isPartial() && LIS->getInterval(CP.getSrcReg()).ranges.size() >
1037 LIS->getInterval(CP.getDstReg()).ranges.size())
1041 // Okay, attempt to join these two intervals. On failure, this returns false.
1042 // Otherwise, if one of the intervals being joined is a physreg, this method
1043 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1044 // been modified, so we can use this information below to update aliases.
1045 if (!joinIntervals(CP)) {
1046 // Coalescing failed.
1048 // If definition of source is defined by trivial computation, try
1049 // rematerializing it.
1050 if (!CP.isFlipped() &&
1051 reMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()),
1052 CP.getDstReg(), CopyMI))
1055 // If we can eliminate the copy without merging the live ranges, do so now.
1056 if (!CP.isPartial()) {
1057 if (adjustCopiesBackFrom(CP, CopyMI) ||
1058 removeCopyByCommutingDef(CP, CopyMI)) {
1059 LIS->RemoveMachineInstrFromMaps(CopyMI);
1060 CopyMI->eraseFromParent();
1061 DEBUG(dbgs() << "\tTrivial!\n");
1066 // Otherwise, we are unable to join the intervals.
1067 DEBUG(dbgs() << "\tInterference!\n");
1068 Again = true; // May be possible to coalesce later.
1072 // Coalescing to a virtual register that is of a sub-register class of the
1073 // other. Make sure the resulting register is set to the right register class.
1074 if (CP.isCrossClass()) {
1076 MRI->setRegClass(CP.getDstReg(), CP.getNewRC());
1079 // Removing sub-register copies can ease the register class constraints.
1080 // Make sure we attempt to inflate the register class of DstReg.
1081 if (!CP.isPhys() && RegClassInfo.isProperSubClass(CP.getNewRC()))
1082 InflateRegs.push_back(CP.getDstReg());
1084 // Remember to delete the copy instruction.
1085 LIS->RemoveMachineInstrFromMaps(CopyMI);
1086 CopyMI->eraseFromParent();
1088 // Rewrite all SrcReg operands to DstReg.
1089 // Also update DstReg operands to include DstIdx if it is set.
1091 updateRegDefsUses(CP.getDstReg(), CP.getDstReg(), CP.getDstIdx());
1092 updateRegDefsUses(CP.getSrcReg(), CP.getDstReg(), CP.getSrcIdx());
1094 // SrcReg is guaranteed to be the register whose live interval that is
1096 LIS->removeInterval(CP.getSrcReg());
1098 // Update regalloc hint.
1099 TRI->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
1102 LiveInterval &DstInt = LIS->getInterval(CP.getDstReg());
1103 dbgs() << "\tJoined. Result = ";
1104 DstInt.print(dbgs(), TRI);
1112 /// Attempt joining with a reserved physreg.
1113 bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
1114 assert(CP.isPhys() && "Must be a physreg copy");
1115 assert(RegClassInfo.isReserved(CP.getDstReg()) && "Not a reserved register");
1116 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1117 DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), TRI); dbgs() << "\n"; });
1119 assert(CP.isFlipped() && RHS.containsOneValue() &&
1120 "Invalid join with reserved register");
1122 // Optimization for reserved registers like ESP. We can only merge with a
1123 // reserved physreg if RHS has a single value that is a copy of CP.DstReg().
1124 // The live range of the reserved register will look like a set of dead defs
1125 // - we don't properly track the live range of reserved registers.
1127 // Deny any overlapping intervals. This depends on all the reserved
1128 // register live ranges to look like dead defs.
1129 for (const uint16_t *AS = TRI->getOverlaps(CP.getDstReg()); *AS; ++AS) {
1130 if (!LIS->hasInterval(*AS)) {
1131 // Make sure at least DstReg itself exists before attempting a join.
1132 if (*AS == CP.getDstReg())
1133 LIS->getOrCreateInterval(CP.getDstReg());
1136 if (RHS.overlaps(LIS->getInterval(*AS))) {
1137 DEBUG(dbgs() << "\t\tInterference: " << PrintReg(*AS, TRI) << '\n');
1141 // Skip any value computations, we are not adding new values to the
1142 // reserved register. Also skip merging the live ranges, the reserved
1143 // register live range doesn't need to be accurate as long as all the
1148 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1149 /// compute what the resultant value numbers for each value in the input two
1150 /// ranges will be. This is complicated by copies between the two which can
1151 /// and will commonly cause multiple value numbers to be merged into one.
1153 /// VN is the value number that we're trying to resolve. InstDefiningValue
1154 /// keeps track of the new InstDefiningValue assignment for the result
1155 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1156 /// whether a value in this or other is a copy from the opposite set.
1157 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1158 /// already been assigned.
1160 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1161 /// contains the value number the copy is from.
1163 static unsigned ComputeUltimateVN(VNInfo *VNI,
1164 SmallVector<VNInfo*, 16> &NewVNInfo,
1165 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1166 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1167 SmallVector<int, 16> &ThisValNoAssignments,
1168 SmallVector<int, 16> &OtherValNoAssignments) {
1169 unsigned VN = VNI->id;
1171 // If the VN has already been computed, just return it.
1172 if (ThisValNoAssignments[VN] >= 0)
1173 return ThisValNoAssignments[VN];
1174 assert(ThisValNoAssignments[VN] != -2 && "Cyclic value numbers");
1176 // If this val is not a copy from the other val, then it must be a new value
1177 // number in the destination.
1178 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1179 if (I == ThisFromOther.end()) {
1180 NewVNInfo.push_back(VNI);
1181 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1183 VNInfo *OtherValNo = I->second;
1185 // Otherwise, this *is* a copy from the RHS. If the other side has already
1186 // been computed, return it.
1187 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1188 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1190 // Mark this value number as currently being computed, then ask what the
1191 // ultimate value # of the other value is.
1192 ThisValNoAssignments[VN] = -2;
1193 unsigned UltimateVN =
1194 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1195 OtherValNoAssignments, ThisValNoAssignments);
1196 return ThisValNoAssignments[VN] = UltimateVN;
1200 // Find out if we have something like
1203 // if so, we can pretend this is actually
1206 // which allows us to coalesce A and B.
1207 // VNI is the definition of B. LR is the life range of A that includes
1208 // the slot just before B. If we return true, we add "B = X" to DupCopies.
1209 // This implies that A dominates B.
1210 static bool RegistersDefinedFromSameValue(LiveIntervals &li,
1211 const TargetRegisterInfo &tri,
1215 SmallVector<MachineInstr*, 8> &DupCopies) {
1216 // FIXME: This is very conservative. For example, we don't handle
1217 // physical registers.
1219 MachineInstr *MI = li.getInstructionFromIndex(VNI->def);
1221 if (!MI || !MI->isFullCopy() || CP.isPartial() || CP.isPhys())
1224 unsigned Dst = MI->getOperand(0).getReg();
1225 unsigned Src = MI->getOperand(1).getReg();
1227 if (!TargetRegisterInfo::isVirtualRegister(Src) ||
1228 !TargetRegisterInfo::isVirtualRegister(Dst))
1231 unsigned A = CP.getDstReg();
1232 unsigned B = CP.getSrcReg();
1238 VNInfo *Other = LR->valno;
1239 const MachineInstr *OtherMI = li.getInstructionFromIndex(Other->def);
1241 if (!OtherMI || !OtherMI->isFullCopy())
1244 unsigned OtherDst = OtherMI->getOperand(0).getReg();
1245 unsigned OtherSrc = OtherMI->getOperand(1).getReg();
1247 if (!TargetRegisterInfo::isVirtualRegister(OtherSrc) ||
1248 !TargetRegisterInfo::isVirtualRegister(OtherDst))
1251 assert(OtherDst == B);
1253 if (Src != OtherSrc)
1256 // If the copies use two different value numbers of X, we cannot merge
1258 LiveInterval &SrcInt = li.getInterval(Src);
1259 // getVNInfoBefore returns NULL for undef copies. In this case, the
1260 // optimization is still safe.
1261 if (SrcInt.getVNInfoBefore(Other->def) != SrcInt.getVNInfoBefore(VNI->def))
1264 DupCopies.push_back(MI);
1269 /// joinIntervals - Attempt to join these two intervals. On failure, this
1271 bool RegisterCoalescer::joinIntervals(CoalescerPair &CP) {
1272 // Handle physreg joins separately.
1274 return joinReservedPhysReg(CP);
1276 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
1277 DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), TRI); dbgs() << "\n"; });
1279 // Compute the final value assignment, assuming that the live ranges can be
1281 SmallVector<int, 16> LHSValNoAssignments;
1282 SmallVector<int, 16> RHSValNoAssignments;
1283 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
1284 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
1285 SmallVector<VNInfo*, 16> NewVNInfo;
1287 SmallVector<MachineInstr*, 8> DupCopies;
1289 LiveInterval &LHS = LIS->getOrCreateInterval(CP.getDstReg());
1290 DEBUG({ dbgs() << "\t\tLHS = "; LHS.print(dbgs(), TRI); dbgs() << "\n"; });
1292 // Loop over the value numbers of the LHS, seeing if any are defined from
1294 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1297 if (VNI->isUnused() || VNI->isPHIDef())
1299 MachineInstr *MI = LIS->getInstructionFromIndex(VNI->def);
1300 assert(MI && "Missing def");
1301 if (!MI->isCopyLike()) // Src not defined by a copy?
1304 // Figure out the value # from the RHS.
1305 LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1306 // The copy could be to an aliased physreg.
1309 // DstReg is known to be a register in the LHS interval. If the src is
1310 // from the RHS interval, we can use its value #.
1311 if (!CP.isCoalescable(MI) &&
1312 !RegistersDefinedFromSameValue(*LIS, *TRI, CP, VNI, lr, DupCopies))
1315 LHSValsDefinedFromRHS[VNI] = lr->valno;
1318 // Loop over the value numbers of the RHS, seeing if any are defined from
1320 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1323 if (VNI->isUnused() || VNI->isPHIDef())
1325 MachineInstr *MI = LIS->getInstructionFromIndex(VNI->def);
1326 assert(MI && "Missing def");
1327 if (!MI->isCopyLike()) // Src not defined by a copy?
1330 // Figure out the value # from the LHS.
1331 LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
1332 // The copy could be to an aliased physreg.
1335 // DstReg is known to be a register in the RHS interval. If the src is
1336 // from the LHS interval, we can use its value #.
1337 if (!CP.isCoalescable(MI) &&
1338 !RegistersDefinedFromSameValue(*LIS, *TRI, CP, VNI, lr, DupCopies))
1341 RHSValsDefinedFromLHS[VNI] = lr->valno;
1344 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1345 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1346 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1348 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1351 unsigned VN = VNI->id;
1352 if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1354 ComputeUltimateVN(VNI, NewVNInfo,
1355 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1356 LHSValNoAssignments, RHSValNoAssignments);
1358 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1361 unsigned VN = VNI->id;
1362 if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused())
1364 // If this value number isn't a copy from the LHS, it's a new number.
1365 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
1366 NewVNInfo.push_back(VNI);
1367 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
1371 ComputeUltimateVN(VNI, NewVNInfo,
1372 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1373 RHSValNoAssignments, LHSValNoAssignments);
1376 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1377 // interval lists to see if these intervals are coalescable.
1378 LiveInterval::const_iterator I = LHS.begin();
1379 LiveInterval::const_iterator IE = LHS.end();
1380 LiveInterval::const_iterator J = RHS.begin();
1381 LiveInterval::const_iterator JE = RHS.end();
1383 // Skip ahead until the first place of potential sharing.
1384 if (I != IE && J != JE) {
1385 if (I->start < J->start) {
1386 I = std::upper_bound(I, IE, J->start);
1387 if (I != LHS.begin()) --I;
1388 } else if (J->start < I->start) {
1389 J = std::upper_bound(J, JE, I->start);
1390 if (J != RHS.begin()) --J;
1394 while (I != IE && J != JE) {
1395 // Determine if these two live ranges overlap.
1397 if (I->start < J->start) {
1398 Overlaps = I->end > J->start;
1400 Overlaps = J->end > I->start;
1403 // If so, check value # info to determine if they are really different.
1405 // If the live range overlap will map to the same value number in the
1406 // result liverange, we can still coalesce them. If not, we can't.
1407 if (LHSValNoAssignments[I->valno->id] !=
1408 RHSValNoAssignments[J->valno->id])
1412 if (I->end < J->end)
1418 // Update kill info. Some live ranges are extended due to copy coalescing.
1419 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
1420 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
1421 VNInfo *VNI = I->first;
1422 unsigned LHSValID = LHSValNoAssignments[VNI->id];
1423 if (VNI->hasPHIKill())
1424 NewVNInfo[LHSValID]->setHasPHIKill(true);
1427 // Update kill info. Some live ranges are extended due to copy coalescing.
1428 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
1429 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
1430 VNInfo *VNI = I->first;
1431 unsigned RHSValID = RHSValNoAssignments[VNI->id];
1432 if (VNI->hasPHIKill())
1433 NewVNInfo[RHSValID]->setHasPHIKill(true);
1436 if (LHSValNoAssignments.empty())
1437 LHSValNoAssignments.push_back(-1);
1438 if (RHSValNoAssignments.empty())
1439 RHSValNoAssignments.push_back(-1);
1441 SmallVector<unsigned, 8> SourceRegisters;
1442 for (SmallVector<MachineInstr*, 8>::iterator I = DupCopies.begin(),
1443 E = DupCopies.end(); I != E; ++I) {
1444 MachineInstr *MI = *I;
1446 // We have pretended that the assignment to B in
1449 // was actually a copy from A. Now that we decided to coalesce A and B,
1450 // transform the code into
1452 unsigned Src = MI->getOperand(1).getReg();
1453 SourceRegisters.push_back(Src);
1454 ErasedInstrs.insert(MI);
1455 LIS->RemoveMachineInstrFromMaps(MI);
1456 MI->eraseFromParent();
1459 // If B = X was the last use of X in a liverange, we have to shrink it now
1460 // that B = X is gone.
1461 for (SmallVector<unsigned, 8>::iterator I = SourceRegisters.begin(),
1462 E = SourceRegisters.end(); I != E; ++I) {
1463 LIS->shrinkToUses(&LIS->getInterval(*I));
1466 // If we get here, we know that we can coalesce the live ranges. Ask the
1467 // intervals to coalesce themselves now.
1468 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
1474 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1475 // depth of the basic block (the unsigned), and then on the MBB number.
1476 struct DepthMBBCompare {
1477 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1478 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1479 // Deeper loops first
1480 if (LHS.first != RHS.first)
1481 return LHS.first > RHS.first;
1483 // Prefer blocks that are more connected in the CFG. This takes care of
1484 // the most difficult copies first while intervals are short.
1485 unsigned cl = LHS.second->pred_size() + LHS.second->succ_size();
1486 unsigned cr = RHS.second->pred_size() + RHS.second->succ_size();
1490 // As a last resort, sort by block number.
1491 return LHS.second->getNumber() < RHS.second->getNumber();
1496 // Try joining WorkList copies starting from index From.
1497 // Null out any successful joins.
1498 bool RegisterCoalescer::copyCoalesceWorkList(unsigned From) {
1499 assert(From <= WorkList.size() && "Out of range");
1500 bool Progress = false;
1501 for (unsigned i = From, e = WorkList.size(); i != e; ++i) {
1504 // Skip instruction pointers that have already been erased, for example by
1505 // dead code elimination.
1506 if (ErasedInstrs.erase(WorkList[i])) {
1511 bool Success = joinCopy(WorkList[i], Again);
1512 Progress |= Success;
1513 if (Success || !Again)
1520 RegisterCoalescer::copyCoalesceInMBB(MachineBasicBlock *MBB) {
1521 DEBUG(dbgs() << MBB->getName() << ":\n");
1523 // Collect all copy-like instructions in MBB. Don't start coalescing anything
1524 // yet, it might invalidate the iterator.
1525 const unsigned PrevSize = WorkList.size();
1526 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1528 if (MII->isCopyLike())
1529 WorkList.push_back(MII);
1531 // Try coalescing the collected copies immediately, and remove the nulls.
1532 // This prevents the WorkList from getting too large since most copies are
1533 // joinable on the first attempt.
1534 if (copyCoalesceWorkList(PrevSize))
1535 WorkList.erase(std::remove(WorkList.begin() + PrevSize, WorkList.end(),
1536 (MachineInstr*)0), WorkList.end());
1539 void RegisterCoalescer::joinAllIntervals() {
1540 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
1541 assert(WorkList.empty() && "Old data still around.");
1543 if (Loops->empty()) {
1544 // If there are no loops in the function, join intervals in function order.
1545 for (MachineFunction::iterator I = MF->begin(), E = MF->end();
1547 copyCoalesceInMBB(I);
1549 // Otherwise, join intervals in inner loops before other intervals.
1550 // Unfortunately we can't just iterate over loop hierarchy here because
1551 // there may be more MBB's than BB's. Collect MBB's for sorting.
1553 // Join intervals in the function prolog first. We want to join physical
1554 // registers with virtual registers before the intervals got too long.
1555 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1556 for (MachineFunction::iterator I = MF->begin(), E = MF->end();I != E;++I){
1557 MachineBasicBlock *MBB = I;
1558 MBBs.push_back(std::make_pair(Loops->getLoopDepth(MBB), I));
1561 // Sort by loop depth.
1562 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1564 // Finally, join intervals in loop nest order.
1565 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1566 copyCoalesceInMBB(MBBs[i].second);
1569 // Joining intervals can allow other intervals to be joined. Iteratively join
1570 // until we make no progress.
1571 while (copyCoalesceWorkList())
1575 void RegisterCoalescer::releaseMemory() {
1576 ErasedInstrs.clear();
1579 InflateRegs.clear();
1582 bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
1584 MRI = &fn.getRegInfo();
1585 TM = &fn.getTarget();
1586 TRI = TM->getRegisterInfo();
1587 TII = TM->getInstrInfo();
1588 LIS = &getAnalysis<LiveIntervals>();
1589 LDV = &getAnalysis<LiveDebugVariables>();
1590 AA = &getAnalysis<AliasAnalysis>();
1591 Loops = &getAnalysis<MachineLoopInfo>();
1593 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
1594 << "********** Function: "
1595 << ((Value*)MF->getFunction())->getName() << '\n');
1597 if (VerifyCoalescing)
1598 MF->verify(this, "Before register coalescing");
1600 RegClassInfo.runOnMachineFunction(fn);
1602 // Join (coalesce) intervals if requested.
1603 if (EnableJoining) {
1606 dbgs() << "********** INTERVALS POST JOINING **********\n";
1607 for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end();
1609 I->second->print(dbgs(), TRI);
1615 // Perform a final pass over the instructions and compute spill weights
1616 // and remove identity moves.
1617 SmallVector<unsigned, 4> DeadDefs;
1618 for (MachineFunction::iterator mbbi = MF->begin(), mbbe = MF->end();
1619 mbbi != mbbe; ++mbbi) {
1620 MachineBasicBlock* mbb = mbbi;
1621 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
1623 MachineInstr *MI = mii;
1627 // Check for now unnecessary kill flags.
1628 if (LIS->isNotInMIMap(MI)) continue;
1629 SlotIndex DefIdx = LIS->getInstructionIndex(MI).getRegSlot();
1630 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1631 MachineOperand &MO = MI->getOperand(i);
1632 if (!MO.isReg() || !MO.isKill()) continue;
1633 unsigned reg = MO.getReg();
1634 if (!reg || !LIS->hasInterval(reg)) continue;
1635 if (!LIS->getInterval(reg).killedAt(DefIdx)) {
1636 MO.setIsKill(false);
1639 // When leaving a kill flag on a physreg, check if any subregs should
1641 if (!TargetRegisterInfo::isPhysicalRegister(reg))
1643 for (const uint16_t *SR = TRI->getSubRegisters(reg);
1644 unsigned S = *SR; ++SR)
1645 if (LIS->hasInterval(S) && LIS->getInterval(S).liveAt(DefIdx))
1646 MI->addRegisterDefined(S, TRI);
1651 // After deleting a lot of copies, register classes may be less constrained.
1652 // Removing sub-register operands may allow GR32_ABCD -> GR32 and DPR_VFP2 ->
1654 array_pod_sort(InflateRegs.begin(), InflateRegs.end());
1655 InflateRegs.erase(std::unique(InflateRegs.begin(), InflateRegs.end()),
1657 DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size() << " regs.\n");
1658 for (unsigned i = 0, e = InflateRegs.size(); i != e; ++i) {
1659 unsigned Reg = InflateRegs[i];
1660 if (MRI->reg_nodbg_empty(Reg))
1662 if (MRI->recomputeRegClass(Reg, *TM)) {
1663 DEBUG(dbgs() << PrintReg(Reg) << " inflated to "
1664 << MRI->getRegClass(Reg)->getName() << '\n');
1671 if (VerifyCoalescing)
1672 MF->verify(this, "After register coalescing");
1676 /// print - Implement the dump method.
1677 void RegisterCoalescer::print(raw_ostream &O, const Module* m) const {